LM5145-Q1 [TI]
LM25148-Q1 42-V Automotive Synchronous Buck DC/DC Controller with Ultra-Low IQ and Dual Random Spread Spectrum;型号: | LM5145-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | LM25148-Q1 42-V Automotive Synchronous Buck DC/DC Controller with Ultra-Low IQ and Dual Random Spread Spectrum |
文件: | 总53页 (文件大小:5131K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LM25148-Q1
SNVSC03 – JUNE 2021
LM25148-Q1 42-V Automotive Synchronous Buck DC/DC Controller with Ultra-Low IQ
and Dual Random Spread Spectrum
1 Features
2 Applications
•
•
AEC-Q100 qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature
•
•
•
Automotive electronic systems
Advanced driver assistance systems (ADAS)
Infotainment and clusters
Integrated EMI mitigation
3 Description
– Selectable dual random spread spectrum
(DRSS) feature for enhanced EMI performance
across low and high-frequency bands
– Optimized for CISPR 25 Class 5 requirements
Versatile synchronous buck DC/DC controller
– Wide input voltage range of 3.5 V to 42 V
– 1% accurate, fixed 3.3-V, 5-V, 12-V, or
adjustable outputs from 0.8 V to 36 V
The LM25148-Q1 is a 42-V, ultra-low IQ synchronous
buck DC/DC controller for high-current, single-output
applications. The controller uses a peak-current-mode
control architecture for easy loop compensation,
fast transient response, and excellent load and
line regulation. The LM25148-Q1 can be set up in
interleaved mode (paralleled output) with accurate
current sharing for high-current applications. It can
operate at input voltages as low as 3.5 V, at nearly
100% duty cycle if needed.
•
– 150°C maximum junction temperature
– Lossless DCR or shunt current sensing
– Shutdown mode current: 2.2 µA
– No-load standby current: 9 µA
The LM25148-Q1 has a unique EMI reduction
feature known as Dual Random Spread Spectrum
(DRSS). Combining low-frequency triangular and
high-frequency randomized modulations mitigates
EMI across lower and higher radio-frequency bands,
respectively. This hybrid technique aligns with
the multiple resolution bandwidth (RBW) settings
specified in industry-standard EMC tests.
•
•
Switching frequency from 100 kHz to 2.2 MHz
– SYNC in and SYNC out capability
– Selectable PFM or FPWM modes
Inherent protection features for robust design
– Internal hiccup mode overcurrent protection
– ENABLE and PGOOD functions
– VCC, VDDA, and gate-drive UVLO protection
– Internal or external loop compensation
– Thermal shutdown protection with hysteresis
Create a custom design using the LM25148-Q1
with WEBENCH® Power Designer
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
LM25148-Q1
VQFN (24)
3.5 mm × 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet
VIN = 3.5 V...42 V
CIN
CVCC
2.2
F
VCC
VIN
EN
CBOOT
HO
CBOOT
0.1
VOUT = 5 V
IOUT = 8 A
F
Q1
Q2
RS
CNFG
LO
5 m
PGOOD
0.56
H
CO
SW
4 ꢀ 47
F
VDDA
LO
LM25148-Q1
PGND
RFB
PFM/SYNCIN
FB
24.9 k
CS
VOUT
EXTCOMP
* Tie to GND
if not used
VCCX
RT
VDDA
AGND
RT
CVDDA
0.1
* VOUT tracks VIN if VIN < 5.2 V
F
9.52 k
Typical Application Schematic
CISPR 25 EMI Performance, 150 kHz to 30 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
LM25148-Q1
SNVSC03 – JUNE 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 3
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
6.1 Wettable Flanks.......................................................... 5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings ............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 30
10 Power Supply Recommendations..............................42
11 Layout...........................................................................43
11.1 Layout Guidelines................................................... 43
11.2 Layout Example...................................................... 46
12 Device and Documentation Support..........................48
12.1 Device Support....................................................... 48
12.2 Documentation Support.......................................... 49
12.3 Receiving Notification of Documentation Updates..49
12.4 Support Resources................................................. 50
12.5 Trademarks.............................................................50
12.6 Electrostatic Discharge Caution..............................50
12.7 Glossary..................................................................50
13 Mechanical, Packaging, and Orderable
Information.................................................................... 50
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4 Revision History
DATE
REVISION
NOTES
Initial release
June 2021
*
5 Description (continued)
Additional features of the LM25148-Q1 include 150°C maximum junction temperature operation, user-selectable
diode emulation for lower current consumption at light-load conditions, open-drain power-good flag for fault
reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated VCC
bias supply regulator, internal 2.8-ms soft-start time, and thermal shutdown protection with automatic recovery.
The LM25148-Q1 controller comes in a 3.5-mm × 5.5-mm thermally enhanced, 24-pin VQFN package with
wettable flank pins to facilitate optical inspection during manufacturing.
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6 Pin Configuration and Functions
NC
CNFG
RT
2
3
4
5
6
7
8
9
23
NC
22 NC
21 VOUT
20 ISNS+
EXTCOMP
FB
EN
19
18
PFM/SYNC
AGND
VDDA
VCC
17 PG
VCCX
16
15 CBOOT
14 SW
PGND 10
LO 11
Connect the exposed pad to AGND and PGND on the PCB.
Figure 6-1. 24-Pin VQFN RGY Package with Wettable Flanks (Top View)
Table 6-1. Pin Functions
PIN
NAME
I/O(1)
DESCRIPTION
NO.
1
NC
NC
̶
̶
Connect to GND at the exposed pad to improve heat spreading.
Connect to GND at the exposed pad to improve heat spreading.
2
Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved
operation.
3
4
5
CNFG
RT
I
I
Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz
and 2.2 MHz.
The output of the transconduction amplifier. If used, connect the compensation network from EXTCOMP to
AGND.
EXTCOMP
O
Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB through 24.9 kΩ to set the output
voltage to 5 V, or a resistor divider from VOUT to FB to set the output voltage level between 0.8 V to 36 V.
The regulation threshold is 0.8 V.
6
FB
I
7
AGND
VDDA
VCC
PGND
LO
G
O
P
Analog ground connection. Ground return for the internal voltage reference and analog circuits
Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
Power ground connection pin for low-side NMOS gate driver
Low-side gate driver signal
8
9
10
11
12
13
G
O
P
VIN
Supply voltage input source for the VCC regulator
HO
O
High-side gate driver signal
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side MOSFET, and the drain terminal of the low-side MOSFET.
14
15
16
SW
P
P
P
CBOOT
VCCX
High-side driver supply for bootstrap gate drive
Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the
internal VCC regulator is disabled.
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Table 6-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NO.
NAME
17
PG
O
An open-collector output that goes low if VOUT is outside the specified regulation window.
Connect PFM to VDDA to Enable Diode Emulation mode. Connect PFM to AGND to operate the LM25148-
Q1 in Forced PWM (FPWM) mode with continuous conduction at light loads. PFM can also be used as a
synchronization input to synchronize the internal oscillator to an external clock.
18
19
20
21
PFM/SYNC
EN
I
I
I
I
An active-high input (VEN) enables the output. If the output is not enabled, the LM25148-Q1 is in Shutdown
mode.
Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor (or
to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin
connection.
ISNS+
VOUT
Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current
sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
22
23
24
NC
NC
NC
̶
̶
Connect to GND at the exposed pad to improve heat spreading.
Connect to GND at the exposed pad to improve heat spreading.
Connect to GND at the exposed pad to improve heat spreading.
̶
(1) P = Power, G = Ground, I = Input, O = Output
6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet reliability and robustness
standards. Standard quad-flat no-lead (QFN) packages do not have solderable or exposed pins and terminals
that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully
soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue
of side-lead wetting of leadless packaging. The LM25148-Q1 is assembled using a 24-pin VQFN package with
wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing
costs.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40℃ to +150℃ (unless otherwise noted). (1)
MIN
–0.3
–0.3
–5
MAX
UNIT
VIN to PGND
47
SW to PGND
47
SW to PGND, transient < 20 ns
CBOOT to SW
–0.3
–5
6.5
CBOOT to SW, transient < 20 ns
HO to SW
–0.3
–5
VHB + 0.3
Input voltage
HO to SW, transient < 20 ns
LO to PGND
V
–0.3
–1.5
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–55
VVCC + 0.3
0.3
LO to PGND, transient < 20 ns
EN to PGND
47
VCC, VCCX, VDDA, PG, FB, PFM/SYNC, RT, EXTCOMP to AGND
CNFG to AGND
6.5
5.5
VOUT, ISNS+ to AGND
VOUT, ISNS+
36
Output voltage
0.3
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 (1)
Charged device model (CDM), per AEC Q100-011
±2000
Corner pins (1, 2, 11, 12, 13, 14, 23, and
24)
V(ESD)
Electrostatic discharge
±750
±500
V
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the operating junction temperature range of –40℃ to +150℃ (unless otherwise noted). (1)
MIN
NOM
MAX
42
UNIT
VIN
Input supply voltage range
Output voltage range
SW to PGND
3.5
VOUT
0.8
36
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
42
CBOOT to SW
5
5
5.25
5.25
42
FB, EXTCOMP, RT, CNFG to AGND
EN to PGND
V
Pin voltage
VCC, VCCX, VDDA to PGND
VOUT, ISNS+ to PGND
PGND to AGND
5.25
36
0.3
150
TJ
Operating junction temperature
°C
(1) Recommended operating conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
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7.4 Thermal Information
LM25148-Q1
RGY (VQFN)
24 PINS
36.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28
11.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
11.7
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
7.5 Electrical Characteristics
TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY (VIN)
IQ-VIN1
Nonswitching, VEN = 0 V, VFB = VREF + 50
mV
VIN shutdown current
VIN standby current
2.2
3.8
µA
µA
IQ-VIN2
Nonswitching, 0.5 V ≤ VEN ≤ 1 V
104
1.03 ≤ VEN ≤ 42 V, VVOUT = 3.3 V, in
regulation, no-load, not switching, VPFM/SYNC
= 0 V
ISTANDBY1
Sleep current, 3.3 V
Sleep current, 5 V
9.5
9.9
19.7
19.9
µA
µA
VEN = 5 V, VVOUT = 5 V, in regulation, no-
load, not switching, VPFM/SYNC = 0 V
ISTANDBY2
ENABLE (EN)
VSDN
Shutdown to standby threshold
Enable voltage rising threshold
Enable hystersis
VEN rising
0.5
1.0
10
V
V
VEN-HIGH
VEN rising, enable switching
VEN = 1.1 V
0.95
8
1.05
12
IEN-HYS
µA
INTERNAL LDO (VCC)
VVCC-REG
VCC regulation voltage
IVCC = 0 mA to 100 mA
4.7
3.3
5
3.4
5.3
3.5
V
V
VVCC-UVLO
VVCC-HYST
IVCC-REG
VCC UVLO rising threshold
VCC UVLO hysteresis
130
200
mV
mA
Internal LDO short-circuit current limit
140
INTERNAL LDO (VDDA)
VVDDA-REG
VVDDA-UVLO
VVDDA-HYST
RVDDA
VDDA regulation voltage
4.75
3.1
5
3.2
120
5.5
5.25
3.3
V
V
VDDA UVLO rising
VDDA UVLO hysteresis
VDDA resistance
VVCC rising, VVCCX = 0 V
VVCCX = 0 V
mV
Ω
VVCCX = 0 V
EXTERNAL BIAS (VCCX)
VVCCX-ON
VVCCX-HYST
RVCCX
VCCX rising threshold
4.1
4.3
130
2
4.4
V
mV
Ω
VCCX hysteresis voltage
VCCX resistance
VVCCX = 5 V
VVCCX = 5 V
REFERENCE VOLTAGE
VREF
Regulated FB voltage
795
800
808
mV
OUTPUT VOLTAGE (VOUT)
RFB = 0 Ω, VIN = 3.8 V to 42 V, internal
COMP
VOUT-3.3V–INT
VOUT-3.3V–EXT
VOUT-5V–INT
VOUT-5V–EXT
3.3-V output voltage setpoint
3.267
3.267
4.95
3.3
3.3
5.0
5.0
3.333
3.333
5.05
V
V
V
V
RFB = 0 Ω, VIN = 3.8 V to 42 V, external
COMP
3.3-V output voltage setpoint
5-V output voltage setpoint
5-V output voltage setpoint
RFB = 24.9 kΩ, VIN = 5.5 V to 42 V, internal
COMP
RFB = 24.9 kΩ, VIN = 5.5 V to 42 V, external
COMP
4.95
5.05
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TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RFB = 48.7 kΩ, VIN = 24 V to 42 V, internal
COMP COMP
VOUT-12V–INT
VOUT-12V-EXT
12-V output setpoint
11.88
12
12.12
12.12
V
RFB = 48.7 kΩ, VIN = 24 V to 42 V, external
COMP
12-V output setpoint
11.88
12
V
RFB-OPT2
RFB-OPT3
5-V output select
12-V output select
24.3
47.5
24.9
48.7
25.5
49.9
kΩ
kΩ
ERROR AMPLIFIER (COMP)
EA transconductance, external
gm-EXTERNAL
FB to COMP
1020
1200
30
µS
µS
compensation
EA transconductance, internal
compensation
gm-INTERNAL
FB to COMP, EXTCOMP 100 kΩ to VDDA
IFB
Error amplifier input bias current
COMP clamp voltage
EA source current
75
nA
V
VCOMP-CLAMP
ICOMP-SRC
ICOMP-SINK
RCOMP
VFB = 0 V
2.1
180
160
400
50
VCOMP = 1 V, VFB = 0.4 V
VCOMP = 1 V, VFB = 0.8 V
EXTCOMP 100 kΩ to VDDA
EXTCOMP 100 kΩ to VDDA
EXTCOMP 100 kΩ to VDDA
µA
µA
kΩ
pF
pF
EA sink current
Internal compensation
Internal compensation
Internal compensation
CCOMP
CCOMP-HF
1
PULSE FREQUENCY MODULATION (PFM)
VPFM-LO
VPFM-HI
VZC-SW
PFM detection threshold low
PFM decection threshold high
Zero-cross threshold
0.8
V
V
2.0
–5.5
100
mV
PFM = VDDA, 1000 SW cycles after first HO
pulse
VZC-DIS
Zero-cross threshold disable
Frequency sync range
mV
kHz
ns
RRT = 9.53 kΩ, ± 20% of the nominal
oscillator frequency
FSYNCIN3
tSYNC-MIN3
tSYNCIN-HO
tPFM-FILTER
1760
20
2640
250
Minimum pulse-width of external
synchronization signal
Delay from PFM faling edge to HO rising
edge
25
ns
µs
SYNCIN to PFM mode
15
30
21
DUAL RANDOM SPREAD SPECTRUM (DRSS)
Distance from the nominal switching
frequency
ΔfC
fm
7.8%
Modulation frequency
9.7
kHz
SWITCHING FREQUENCY
VRT
RT pin regulation voltage
10 kΩ < RRT < 100 kΩ
RRT = 97.6 kΩ to AGND
VIN = 12 V, RRT = 9.53 kΩ to AGND
RRT = 220 kΩ to AGND
RRT = 9.53 kΩ
0.5
220
2.2
100
500
50
V
kHz
MHz
kHz
mV/µs
mV/µs
ns
FSW1
Switching frequency 1
Switching frequency 2
Switching frequency 3
Internal slope compensation 1
Internal slope compensation 2
Minimum on time
FSW2
1.98
2.42
FSW3
SLOPE1
SLOPE2
tON(min)
RRT = 97.6 kΩ
65
80
85
tOFF(min)
POWER GOOD (PG)
VPG-UV
Minimum off time
60
ns
Power-good UV trip level
Power-good OV trip level
Power Good UV hysteresis
Power Good OV hysteresis
OV filter time
Falling with respect to the regulated voltage
Rising with respect to the regulation voltage
Falling with respect to the regulated output
Rising with respect to the regulation voltage
VOUT rising
90%
92%
110%
3.4%
3.4%
25
94%
VPG-OV
108%
112%
VPG-UV-HYST
VPG-OV-HYST
tOV-DLY
µs
µs
V
tUV-DLY
UV filter time
VOUT falling
25
VPG-OL
PG voltage
Open collector, IPG = 4 mA
0.8
SYNCHRONIZATION OUTPUT (PG/SYNCOUT)
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TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RCNFG = 54.9 kΩ or 71.5 kΩ to VDDA
(primary), ISYNCOUT = 4 mA
VSYNCOUT-LO
VSYNCOUT-HO
tSYNCOUT
SYNCO-LO low-state voltage
0.8
V
RCNFG = 54.9 kΩ or 71.5 kΩ to VDDA
(primary) ISYNCOUT = 4 mA
SYNCO-HO high-state voltage
2.0
V
Delay from HO rising edge to SYNCOUT
(PG pin in primary mode)
VPFM = 0 V, FSW set by RRT = 100 kΩ
2.1
µs
STARTUP (Soft Start)
tSS-INT
Internal fixed soft-start time
Internal diode forward drop
1.9
2.8
0.8
3.6
3.5
ms
BOOT CIRCUIT
VBOOT-DROP
ICBOOT = 20 mA, VCC to CBOOT
VEN = 5 V, VCBOOT-SW = 5 V
0.63
V
CBOOT to SW quiescent current, not
switching
IBOOT
µA
VBOOT-SW-UV-R
VBOOT-SW-UV-F
VBOOT-SW-UV-HYS
VHO-LOW
CBOOT-SW UVLO rising threshold
CBOOT-SW UVLO falling threshold
CBOOT-SW UVLO hysteresis
HO low-state output voltage
VCBOOT-SW rising
VCBOOT-SW falling
2.7
2.5
V
V
V
V
0.25
0.038
IHO = 100 mA
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH
VHO-LOW
tHO-RISE
tHO-FALL
HO high-state output voltage
IHO = –100 mA, VHO-HIGH = VCBOOT – VHO
IHO = 100 mA
0.08
0.05
7
V
V
HO low-state output voltage
HO rise time (10% to 90%)
HO fall time (90% to 10%)
CLOAD = 2.7 nF
ns
ns
CLOAD = 2.7 nF
7
VHO = VSW = 0 V, VCBOOT = 5 V, VVCCX = 5
V
IHO-SRC
IHO-SINK
HO peak source current
HO peak sink current
2.2
3.2
A
A
VVCCX = 5 V
LOW-SIDE GATE DRIVER (LO)
VLO-LOW
VLO-HIGH
tLO-RISE
tLO-FALL
LO low-state output voltage
ILO = 100 mA
ILO = –100 mA
CLOAD = 2.7 nF
CLOAD = 2.7 nF
0.038
0.08
7
V
V
LO high-state output voltage
LO rise time (10% to 90%)
LO fall time (90% to 10%)
ns
ns
7
VHO = VSW = 0 V, VCBOOT = 5 V, VVCCX = 5
V
ILO-SRC
ILO-SINK
LO peak source current
LO peak sink current
2.2
3.2
A
A
VVCCX = 5 V
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime
tDEAD2 LO off to HO on deadtime
INTERNAL HICCUP MODE
12
13
ns
ns
HICDLY
Hiccup mode activation delay
Hiccup mode fault
VISNS+ –VVOUT > 60 mV
VISNS+ –VVOUT > 60 mV
512
cycles
cycles
HICCYCLES
16384
OVERCURRENT PROTECTION
VCS-TH
Current limit threshold
Measured from ISNS+ to VOUT
54
60
45
10
66
mV
ns
tDELAY-ISNS+
GCS
ISNS+ delay to output
CS amplifier gain
9.5
10.5
15
V/V
nA
IBIAS-ISNS+
CONFIGURATION
RCONF-OPT1
RCONF-OPT2
RCONF-OPT3
RCONF-OPT4
RCONF-OPT5
CS amplifier input bias current
Primary, no spread spectrum
Primary, with spread spectrum
Primary, interleaved, no spread spectrum
Primary, interleaved, with spread spectrum
Secondary
28.7
40.2
53.6
69.8
88.7
29.4
41.2
54.9
71.5
90.9
30.1
43.2
57.6
73.2
93.1
kΩ
kΩ
kΩ
kΩ
kΩ
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TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
175
15
°C
°C
TJ-HYS
(1) Specified by design. Not production tested.
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8 Detailed Description
8.1 Overview
The LM25148-Q1 is a switching controller that features all of the functions necessary to implement a high-
efficiency synchronous buck power supply operating over a wide input voltage range from 3.5 V to 42 V. The
LM25148-Q1 is configured to provide a fixed 3.3-V, 5-V, or 12-V output, or an adjustable output between 0.8
V to 36 V. This easy-to-use controller integrates high-side and low-side MOSFET drivers capable of sourcing
2.2-A and sinking 3.2-A peak current. Adaptive dead-time control is designed to minimize body diode conduction
during switching transitions.
Current-mode control using a shunt resistor or inductor DCR current sensing provides inherent line feedforward,
cycle-by-cycle peak current limiting, and easy loop compensation. It also supports a wide duty cycle range for
high input voltage and low-dropout applications as well as when a high step-down conversion ratio (for example,
10-to-1) is required. The oscillator frequency is user-programmable between 100 kHz to 2.2 MHz, and the
frequency can be synchronized as high as 2.5 MHz by applying an external clock to the PFM/SYNC pin.
An external bias supply can be connected to VCCX to maximize efficiency in high input voltage applications.
A user-selectable diode emulation feature enables Discontinuous Conduction mode (DCM) operation to further
improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include
the following:
•
•
•
•
Current limiting
Thermal shutdown
UVLO
Remote shutdown capability
The LM25148-Q1 incorporates features to simplify the compliance with automotive EMI requirements (CISPR
25). Dual Random Spread Spectrum (DRSS) techniques reduce the peak harmonic EMI signature.
The LM25148-Q1 is provided in a 24-pin VQFN package with a wettable flank pinout and an exposed pad to aid
in thermal dissipation.
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8.2 Functional Block Diagram
CLK
SYNCOUT
DEM/FPWM
PLL &
OSCILLATORS
VIN
PFM/SYNC
HICCUP
FAULT TIMER
512 CYCLES
ILIM
BIAS
VREF 0.8 V
VCCX
VCC
HICCUP
RT amp
VDDA
CONTROL
VOUT
VDDA
DUAL RANDOM
SPREAD SPECTURM
(DRSS)
DRSS
ENABLE
800 mV
+
–
RT
CONFG
DECODER
CNFG
SECONDARY
INTERLEAVED
EN
–
+
ILIM
VCC
CURRENT
LIMIT
GAIN = 10
+
–
60 mV
+
–
ISNS+
VOUT
BOOT
UVLO
SLOPE
CBOOT
COMP
RAMP
SECONDARY
3.3 V
5 V
FB
INTERLEAVE
DECODER
/MUX
12 V
DEM/FPWM
HICCUP
HO
SW
DRIVER
COMP/ENABLE
FB
EXTERNAL EA
gm 1200 µS
SYNCOUT
SECONDARY
+
–
PWM
–
+
+
R
S
Q
Q
VREF
CLK
PG/SYNCOUT
–
0.880 V
0.735 V
INTERNAL EA
gm 30 µs
PGO
VCC
+
LEVEL
SHIFT
ADAPTIVE
DEADTIME
PG
–
+
+
PG
DELAY
25 ms
LO
–
+
DRIVER
PGUV
EXTCOMP
AGND
PGND
–
+
SOFT-START
STANDBY
+
–
150 mV
SS
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN)
The LM25148-Q1 operational input voltage range is from 3.5 V to 42 V. The device is intended for step-down
conversions from 12-V, 24-V, and 48-V automotive supply rails. The application circuit in Figure 9-4 shows all the
necessary components to implement an LM25148-Q1 based wide-VIN single-output step-down regulator using
a single supply. The LM25148-Q1 uses an internal LDO to provide a 5-V VCC bias rail for the gate drive and
control circuits (assuming the input voltage is higher than 5 V with additional voltage margin necessary for the
sub-regulator dropout specification).
In high input voltage applications, take extra care to ensure that the VIN and SW pins do not exceed their
absolute maximum voltage rating of 47 V during line or load transient events. Voltage excursions that exceed the
input voltage can damage the IC.
There is an internal ESD diode from the VOUT pin to the VIN pin of the LM25148-Q1. Under VIN transients
that take VIN more than 2 V below VOUT, the output capacitors can discharge through the internal ESD diode.
Typically, the output will discharge through the high-side MOSFET, but if the VIN transient falls too fast, diode
protection must be added to the VIN pin of the controller so the ESD diode will not be damaged. Under these
conditions TI recommends adding a Schottky diode in series with the LM25148-Q1 VIN pin.
8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
The LM25148-Q1 contains an internal high-voltage VCC bias regulator that provides the bias supply for the
PWM controller and the gate drivers for the external MOSFETs. The input voltage pin (VIN) can be connected
directly to an input voltage source up to 42 V. However, when the input voltage is below the VCC setpoint level,
the VCC voltage tracks VIN minus a small voltage drop.
The VCC regulator output current limit is 110 mA (minimum). At power up, the controller sources current into the
capacitor connected at the VCC pin. When the VCC voltage exceeds 3.3 V and the EN pin is connected to a
voltage greater than 1 V, the soft-start sequence begins. The output remains active unless the VCC voltage falls
below the VCC UVLO falling threshold of 3.1 V (typical) or EN is switched to a low state. Connect a ceramic
capacitor from VCC to PGND. The recommended range of the VCC capacitor is from 2.2 µF to 10 µF.
An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or greater ceramic
capacitor to achieve a low-noise internal bias rail. Normally, VDDA is 5 V. However, there is one condition where
VDDA regulates at 3.3-V. This is in PFM mode with a light or no-load on the output.
Minimize the internal power dissipation of the VCC regulator by connecting VCCX to a 5-V output or to an
external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. Tie VCCX to PGND if it is unused. Never connect VCCX to a voltage greater than 6.5
V. If an external supply is connected to VCCX to power the LM25148-Q1 VIN must be greater than the external
bias voltage during all conditions to avoid damage to the controller.
8.3.3 Enable (EN)
The EN pin can be connected to a voltage as high as 42 V. The LM25148-Q1 has a precision enable. When
the EN voltage is greater than 1 V, VOUT is enabled. If the EN pin is pulled below 0.5 V, the LM25148-Q1 is in
shutdown with an IQ of 2.2 μA (typical) current draw from VIN. When the enable voltage is between 0.5 V and
1 V, the LM25148-Q1 is in Standby mode. When the controller is in Standby mode, the VCC regulator is active,
and the controller is not switching. Under these conditions, the IQ current is 100 μA typical. The LM25148-Q1 is
enabled with a logic level voltage greater then 2.0 V, and a voltage less than 0.4 V disables the LM25148-Q1.
However, many applications benefit from using a resistor divider RUV1 and RUV2, as shown in Figure 8-3, to
establish a precision UVLO level. TI does not recommend leaving the EN pin floating.
When using precision enable and a VCCX supply, a diode must be placed with the cathode connected to the
LM25148-Q1 VCCX node.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off
voltages.
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V
- V
(
IN on
(
IN off
)
)
RUV1
=
IHYS
(1)
(2)
VEN-HIGH
- VEN
RUV2 = RUV1
ì
V
IN on
VDDA
VIN
10 µA
RUV1
EN
19
+
1 V
Enable
comparator
RUV2
Figure 8-1. Programmable Input Voltage UVLO Turn-on
8.3.4 Power Good Monitor (PG)
The LM25148-Q1 includes an output voltage monitoring signal for VOUT to simplify sequencing and supervision.
The Power Good signal is used for start-up sequencing of downstream converters, fault protection, and output
monitoring. The power-good output (PG) switches to a high impedance open-drain state when the output voltage
is in regulation. The PG switches low when the output voltage drops below the lower power-good threshold
(92% typical) or rises above the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false
tripping of the power-good signal during transients. TI recommends a pullup resistor of 100 kΩ (typical) from PG
to the relevant logic rail. PG is asserted low during soft start and when the buck regulator is disabled.
When the LM25148-Q1 is configured as a primary controller, the PG pin is becomes a synchronization clock
output for the secondary controller. The synchronization signal is a logic level, 180° out-of-phase with the
primary HO driver output.
8.3.5 Switching Frequency (RT)
The LM25148-Q1 oscillator is programmed by a resistor between RT and AGND to set an oscillator frequency
between 100 kHz to 2.2 MHz. Calculate the RT resistance for a given switching frequency using Equation 3.
106
- 53
FSW (kHz)
RT (kW) =
45
(3)
Under low VIN conditions when the on time of the high-side MOSFET exceeds the programmed oscillator period,
the LM25148-Q1 extends the switching period until the PWM latch is reset by the current sense ramp exceeding
the controller compensation voltage.
The approximate input voltage level at which this occurs is given by Equation 4.
tSW
V
= VOUT ∂
IN(min)
tSW - tOFF(min)
(4)
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where
•
•
tSW is the switching period
tOFF(min) is the minimum off time of 60 ns
8.3.6 Dual Random Spread Spectrum (DRSS)
The LM25148-Q1 provides a digital spread spectrum, which reduces the EMI of the power supply over a
wide frequency range. DRSS combines a low-frequency triangular modulation profile with a high frequency
cycle-by-cycle random modulation profile. The low-frequency triangular modulation improves performance in
lower radio frequency bands, while the high-frequency random modulation improves performance in higher radio
frequency bands.
Spread spectrum works by converting a narrowband signal into a wideband signal that spreads the energy
over multiple frequencies. Since industry standards require different EMI receiver resolution bandwidth (RBW)
settings for different frequency bands, the RBW has an impact on the spread spectrum performance. For
example, the CISPR 25 spectrum analyzer RBW in the frequency band from 150 kHz to 30 MHz is 9 kHz.
For frequencies greater than 30 MHz, the RBW is 120 kHz. DRSS is able to simultaneously improve the EMI
performance in the high and low RBWs with its low-frequency triangular modulation profile and high frequency
cycle-by-cycle random modulation. DRSS can reduce conducted emissions up to 15 dBμV in the low-frequency
band (150 kHz to 30 MHz) and 5 dBμV in the high-frequency band (30 MHz to 108 MHz).
To enable DRSS, connect either a 41.2-kΩ or 71.5-kΩ resistor from CNFG to AGND. DRSS is disabled when an
external clock is applied to the PFM/SYNC pin.
Frequency
(a) Low-frequency
triangular modulation
(b) High-frequency
randomized modulation
(c) Low-frequency triangular + high-
frequency
randomized modulations
fs(t)
2∆fs
Low RBW
High RBW
t
Spread spectrum OFF
Spread spectrum ON
Figure 8-2. Dual Random Spread Spectrum Implementation
8.3.7 Soft Start
The LM25148-Q1 has an internal 2.8-ms soft-start timer (typical). The soft start feature allows the regulator to
gradually reach the steady-state operating point, thus reducing start-up stresses and surges.
8.3.8 Output Voltage Setpoint (FB)
The LM25148-Q1 output can be independently configured for one of three fixed output voltages without external
feedback resistors, or adjusted to the desired voltage using an external resistor divider. Set the output to 3.3-V
by connecting FB directly to VDDA. Alternatively, set the output to either 5-V or 12-V by installing a 24.9-kΩ or
49.9 kΩ resistor between FB and VDDA, respectively. See Table 8-1.
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Table 8-1. Feedback Configuration Resistors
PULLUP RESISTOR TO VDDA
VOUT
0 Ω
24.9 kΩ
49 kΩ
NA
3.3 V
5 V
12 V
External FB divider
The configuration settings are latched and cannot be changed until the LM25148-Q1 is powered down (with the
VCC voltage decreasing below its falling UVLO threshold) and then powered up again (VCC rises above the 3.4
V typical). Alternatively, set the output voltage with an external resistive divider from the output to the FB pin. The
output voltage adjustment range is between 0.8 V to 36 V. The regulation threshold at FB is 0.8 V (VREF). Use
Equation 5 to calculate the upper and lower feedback resistors, designated RFB1 and RFB2
.
≈
∆
«
’
VOUT
VREF
RFB1
=
-1 ∂R
÷
FB2
◊
(5)
The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ.
If a low IQ mode is required, take care when selecting the external resistors. The extra current drawn from the
external divider is added to the LM25148-Q1 ISTANDBY current (9 µA typical). The divider current reflected to VIN
is divided down by the ratio of VOUT / VIN.
8.3.9 Minimum Controllable On Time
There are two limitations to the minimum output voltage adjustment range: the LM25148-Q1 voltage reference of
0.8 V and the minimum controllable switch-node pulse width, tON(min)
.
tON(min) effectively limits the voltage step-down conversion ratio VOUT / VIN at a given switching frequency. For
fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 6.
VOUT
> tON(min) ∂FSW
V
IN
(6)
where
•
•
tON(min) is 65 ns (typical)
FSW is the switching frequency
If the desired voltage conversion ratio does not meet the above condition, the LM25148-Q1 transitions from fixed
switching frequency operation to a pulse-skipping mode to maintain output voltage regulation. For example, if
the desired output voltage is 5 V with an input voltage of 24 V and switching frequency of 2.1 MHz, the voltage
conversion ratio test in Equation 7 is satisfied.
5V
> 59ns ∂2.1MHz
24V
0.208 > 0.124
(7)
For wide VIN applications and low output voltages, an alternative is to reduce the LM25148-Q1 switching
frequency to meet the requirement of Equation 6.
8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
The LM25148-Q1 has a high-gain transconductance amplifier that generates an error current proportional to
the difference between the feedback voltage and an internal precision reference (0.8 V). The control loop
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compensation is configured two ways. The first is using the internal compensation amplifier, which has a
transconductance of 30 µS. Internal compensation is configured by connecting the EXTCOMP pin through a
100-kΩ resistance to VDDA. If a 100-kΩ resistor is not detected, the LM25148-Q1 defaults to the external loop
compensation network. The transconductance of the amplifier for external compensation is 1200 µS. This is
latched and cannot be re-configured on the fly. Use an external compensation network if higher performance is
required to meet a stringent transient response. To re-configure the compensation (internal or external), remove
power and allow VCC to drop below its VCCUVLO threshold, which is 3.3 V typical.
A type-II compensation network is generally recommended for peak current-mode control.
8.3.11 Slope Compensation
The LM25148-Q1 provides internal slope compensation for stable operation with peak current-mode control and
a duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution
equal to one times the inductor downslope using Equation 8.
VOUT (V)∂RS(mW)
LO-IDEAL (ꢀH) =
24 ∂FSW (MHz)
(8)
•
•
A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and
cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses
and peak currents.
A higher inductance value generally decreases the peak-to-peak inductor current, reducing switch peak and
RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.
8.3.12 Inductor Current Sense (ISNS+, VOUT)
There are two methods to sense the inductor current of the buck power stage. The first uses a current sense
resistor (also known as a shunt) in series with the inductor, and the second avails of the DC resistance of the
inductor (DCR current sensing).
When the switch-node voltage rises faster than 3 V/ns, noise may be injected between PGND and VOUT. If
the output current is operating close to current limit, the noise can prematurely trip the current limit comparator
causing the HO to turn off immediately. This issue is more apparent at higher VIN where the switch node rises
very quickly, which will be fixed in the final silicon.
8.3.12.1 Shunt Current Sensing
Figure 8-3 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the
inductor current to provide accurate overcurrent protection across the operating temperature range. For optimal
current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between
the inductor and the output, with a Kelvin connection to the LM25148-Q1 current sense amplifier.
If the peak voltage signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 60 mV, the
current limit comparator immediately terminates HO output for cycle-by-cycle current limiting. Calculate the shunt
resistance using Equation 9.
VCS-TH
RS
=
DIL
2
IOUT(CL)
+
(9)
where
•
•
VCS-TH is current sense threshold of 60 mV
IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the
overcurrent comparator during load transients
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•
ΔIL is the peak-to-peak inductor ripple current
VIN
LO
RS
VOUT
CO
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
Figure 8-3. Shunt Current Sensing Implementation
The SS voltage is clamped 150 mV above FB during an overcurrent condition. Sixteen overcurrent events must
occur before the SS clamp is enabled. This ensures that SS can be pulled low during brief overcurrent events,
preventing output voltage overshoot during recovery.
8.3.12.2 Inductor DCR Current Sensing
For high-power applications that do not require accurate current-limit protection, inductor DCR current sensing
is preferable. This technique provides lossless and continuous monitoring of the inductor current using an RC
sense network in parallel with the inductor. Select an inductor with a low DCR tolerance to achieve a typical
current limit accuracy within the range of 10% to 15% at room temperature. Components RCS and CCS in Figure
8-4 create a low-pass filter across the inductor to enable differential sensing of the voltage across the inductor
DCR.
VIN
LO
RDCR
VOUT
CO
RCS
CCS
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
Figure 8-4. Inductor DCR Current Sensing Implementation
The voltage drop across the sense capacitor in the s-domain is given by Equation 10. When the RCSCCS time
constant is equal to LO/RDCR, the voltage developed across the sense capacitor, CCS, is a replica of the inductor
DCR voltage and accurate current sensing is achieved. If the RCSCCS time constant is not equal to the LO/RDCR
time constant, there is a sensing error as follows:
•
•
RCSCCS > LO/RDCR → the DC level is correct, but the AC amplitude is attenuated.
RCSCCS < LO/RDCR → the DC level is correct, but the AC amplitude is amplified.
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LO
1+ s∂
RDCR
DIL
2
≈
’
VCS(s) =
∂RDCR ∂∆IOUT(CL) +
÷
◊
1+ s∂RCS ∂CCS
«
(10)
Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network, thus
reducing the susceptibility of noise pickup from the switch node. Carefully observe Section 11.1 to make sure
that noise and DC errors do not corrupt the current sense signals applied between the ISNS+ and VOUT pins.
8.3.13 Hiccup Mode Current Limiting
The LM25148-Q1 includes an internal Hiccup mode protection function. After an overload is detected, 512 cycles
of cycle-by-cycle current limiting occurs. The 512-cycle counter is reset if four consecutive switching cycles
occur without exceeding the current limit threshold. Once the 512-cycle counter has expired, the internal soft
start is pulled low, the HO and LO driver outputs are disabled, and the 16384 counter is enabled. After the
counter reaches 16384, the internal soft start is enabled and the output restarts. The Hiccup mode current limit is
disabled during soft start until the FB voltage exceeds 0.4 V.
8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
The LM25148-Q1 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive
the external N-channel MOSFET. The high-side gate driver works in conjunction with an internal bootstrap diode
DBOOT and bootstrap capacitor CBOOT. During the conduction interval of the low-side MOSFET, the SW voltage
is approximately 0 V and CBOOT charges from VCC through the internal DBOOT. TI recommends a 0.1-μF
ceramic capacitor connected with short traces between the CBOOT and SW pins.
The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and
LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn
on, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2.0 V typical.
LO is allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turnon is delayed until
the LO voltage has dropped below 2.0 V. This technique ensures adequate dead-time for any size N-channel
MOSFET component or parallel MOSFET configurations.
Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected
N-channel high-side MOSFET determines the appropriate bootstrap capacitance value CBOOT in according to
Equation 11.
QG
CBOOT
=
DVCBOOT
(11)
where
•
•
QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage
ΔVBOOT is the voltage variation of the high-side MOSFET driver after turn-on
To determine CBOOT, choose ΔVBOOT so that the available gate drive voltage is not significantly impacted. An
acceptable range of ΔVBST is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor,
typically 0.1 µF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.
If zero-cross detection is just above 20% load (typical) such that LO turns off early, use an external low-leakage
boot diode. Place a footprint for a diode on the PCB layout. Final silicon will not require an external boot diode.
8.3.15 Output Configurations (CNFG)
The LM25148-Q1 can be configured as a primary controller (interleaved mode) or as a secondary controller for
paralleling the outputs for high-current applications with a resistor RCNFG. This resistor also configures if spread
spectrum is enabled or disabled. See Table 8-2. Once the VCC voltage is above 3.3 V (typical), the CNFG pin
voltage is monitored and latched. To change the configuration mode the LM25148-Q1 must be powered down,
and VCC must drop below 3.3 V. Figure 8-5 shows the configuration timing diagram.
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When the LM25148-Q1 is configured with spread spectrum enabled, or as a primary controller with spread
spectrum (RCNFG 41.2 kΩ or 71.5 kΩ), the LM25148-Q1 cannot be synchronized to an external clock.
Table 8-2. Configuration Modes
PRIMARY/
SECONDARY
RCNFG
SPREAD SPECTRUM
DUAL PHASE
29.9 kΩ
41.2 kΩ
54.9 kΩ
71.5 kΩ
90.9 kΩ
Primary
OFF
ON
Disabled
Disabled
Enabled
Enabled
Enabled
Primary
Primary
OFF
ON
Primary
Secondary
N/A
EN
VCC
VVDDA-UVLO
VDDA
CONFIG_START
CONFIG_DONE
50 µs
CONFIGURATION
TIME
SS(internal)
Figure 8-5. Configuration Timing
8.3.16 Single-Output Two-phase Operation
To configure for two-phase operation, two LM25148-Q1 controllers are required. The LM25148-Q1 can only
be configured in a single or dual-phase configuration where both outputs are tied together. Additional phases
cannot be added. Refer to Figure 8-6. Configure the first controller (CNTRL1) as a primary controller and the
second controller (CNTRL2) as a secondary. To configure CNTRL1 as a primary controller, install a 54-kΩ or
a 71.5-kΩ resistor from CNFG to AGND. To configure the CNTRL2 as a secondary controller, install a 90.9-kΩ
resistor from CNFG to AGND. This disables the error amplifier of CNTRL2, placing it into a high-impedance
state. Connect the EXTCOMP pins of the primary and secondary controllers together. The internal compensation
amplifier feature is not supported when the controller is in Dual-phase mode. In Dual-phase mode the PG pin of
the primary controller becomes a SYNCOUT. Refer to Electrical Characteristics for voltage levels. Connect PG
of the primary to PFM/SYNC (SYNCIN) of the secondary controller. The PG SYNCOUT signal of the primary
controller is 180° out-of-phase and facilitates interleaved operation. RT is not used for the oscillator when the
LM25148-Q1 is in Secondary Controller mode, but instead is used for slope compensation. Therefore, select
the RT resistance to be the same as that of the primary controller. The oscillator is derived from the primary
controller. When in primary/secondary mode, enable both controllers simultaneously for start-up. After the power
supply has started, pull the secondary EN pin low (< 0.8 V) for phase shedding if needed at light load to reduce
the IQ current.
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If an external SYNCIN signal is applied after start-up while in primary/secondary mode, there is a two-clock cycle
delay before the LM25148-Q1 locks on to the external synchronization signal.
VOUT
RPGOOD
20 kꢀ
SYNCOUT
System
PGOOD
VDDA
PFM/SYNC
EN
PG
PG
PFM/SYNC
EN
VOUT
EN CH1
EN CH2
Primary
Controller
Secondary
Controller
RFB1
VDDA
FB
CNFG
CNFG
FB
RCNFG1
RCNFG2
EXTCOMP
EXTCOMP
RFB2
54.9 kꢀ
90.9 kꢀ
Figure 8-6. Schematic Configured for Single-Output Multi-Phase Operation
In PFM mode, the controller enters pulse skipping to reduce the IQ current. When this occurs, the primary
controller disables its synchronization clock output, so phase shedding is not supported. In PFM modex connect
the two enable pins together. Phase shedding is supported in FPWM only. In FPWM, enable or disable the
secondary controller as needed to support higher load current or better light-load efficency, respectively. When
the secondary controller is disabled and then re-enabled, its internal soft start is pulled low and the LM25148-Q1
goes through a normal soft-start turn-on. When the LM25148-Q1 is configured for a single-output two-phase
operation using the internal 3.3 V feedback resistor divider, the internal bootstrap UV circuit can source current
out of the SW pin, charging up the output capacitors approximatly to 3.6 V. If this behavior is undesirable, you
can add a 100-kΩ resistor from VOUT to GND to bleed off the charge on the output capacitors.
For more information, see the Benefits of a Multiphase Buck Converter Technical Brief and Multiphase Buck
Design From Start to Finish Application Report.
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8.4 Device Functional Modes
8.4.1 Standby Modes
The LM25148-Q1 operates with peak current-mode control such that the compensation voltage is proportional to
the peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As
a result, the compensation voltage does not demand the driver output pulses on a cycle-by-cycle basis. When
the LM25148-Q1 controller detects 16 missed switching cycles, it enters Standby mode and switches to a low IQ
state to reduce the current drawn from the input. For the LM25148-Q1 to go into Standby mode, the controller
must be programmed for diode emulation (tie PFM/SYNC to VDDA).
In Standby mode and normal mode, the typical low IQ is 9 μA with a 3.3-V output.
8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
A synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode has the
capability to sink negative current from the output during light-load, overvoltage, and pre-bias start-up conditions.
The LM25148-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source)
current flow in the low-side MOSFET. When configured for Diode Emulation mode, the low-side MOSFET is
switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator.
The benefit of this configuration is lower power loss during light-load conditions. The disadvantage of Diode
Emulation mode is slower light-load transient response.
The PFM/SYNC pin configures diode emulation. To enable diode emulation and thus achieve low-IQ current at
light loads, connect PFM/SYNC to VDDA. If FPWM or Continuous Conduction mode (CCM) operation is desired,
tie PFM/SYNC to AGND. Note that diode emulation is automatically engaged to prevent reverse current flow
during a prebias start-up in PFM. A gradual change from DCM to CCM operation provides monotonic start-up
performance.
To synchronize the LM25148-Q1 to an external source, apply a logic-level clock to the PFM/SYNC pin. The
LM25148-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there
is an RT resistor and a synchronization signal, the LM25148-Q1 ignores the RT resistor and synchronizes to the
external clock. Under low VIN conditions when the minimum off time is reached, the synchronization signal is
ignored, allowing the switching frequency to reduce to maintain output voltage regulation.
8.4.3 Thermal Shutdown
The LM25148-Q1 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs. When entering thermal shutdown, the device:
1. Turns off the high-side and low-side MOSFETs.
2. Pulls SS and PG/SYNC low.
3. Turns off the VCC regulator.
4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
15°C (typical).
This is a non-latching protection, and, as such, the device cycles into and out of thermal shutdown if the fault
persists.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Power Train Components
A comprehensive understanding of the buck regulator power train components is critical to successfully
completing a synchronous buck regulator design. The following section discuss the output inductor, input and
output capacitors, power MOSFETs, and EMI input filter.
9.1.1.1 Buck Inductor
For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to
50% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 12
based on a peak inductor current given by Equation 13.
≈
’
÷
◊
VOUT
VOUT
LO
=
∂ 1-
∆
DIL ∂FSW
V
IN
«
(12)
(13)
DIL
2
IL(peak) = IOUT
+
Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current and higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.1.2 Output Capacitors
Ordinarily, the output capacitor energy storage of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics – equivalent series
resistance (ESR) and equivalent series inductance (ESL) – take greater precedence in shaping the load
transient response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 14.
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DIL
2
COUT
í
2
8 ∂FSW DVOUT - RESR ∂ DIL
(14)
Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps
to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of
charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up
transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds
to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL
dt
VOUT
LF
= -
inductor current, iL(t)
DIOUT
DQC
IOUT2
load current,
iOUT(t)
diOUT DIOUT
=
dt
tramp
inductor current, iL(t)
IOUT2
DQC
diL
dt
VIN - VOUT
LF
DIOUT
=
load current, iOUT(t)
IOUT1
tramp
Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 12-V input to low output voltage (for example, 3.3 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT / L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger
than:
2
LO ∂ DIOUT
COUT
í
2
2
V
+ DVOVERSHOOT - VOUT
(
)
OUT
(15)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic
capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces
contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have
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low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates.
However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop
quite significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 14 gives a quick estimation of the minimum ceramic capacitance necessary
to meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
common choice for a 5-V output. Use Equation 15 to determine if additional capacitance is necessary to meet
the load-off transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.1.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-
frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance
in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET
and the source of the low-side MOSFET. The input capacitor RMS current for a single-channel buck regulator is
given by Equation 16.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(16)
The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the input
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT
−
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 17.
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(17)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 18.
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
(18)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating
with high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic
decoupling capacitors are usually sufficient for 12-V battery automotive applications. Select the input bulk
capacitor based on its ripple current rating and operating temperature range.
Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple
current cancellation and reduced input capacitor current stress. The above equations represent valid calculations
when one output is disabled and the other output is fully loaded.
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9.1.1.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with
low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster
transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate
charge and output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and
QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package ensures that
the MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM25148-Q1 application are as follows:
•
•
•
•
•
•
RDS(on) at VGS = 5 V
Drain-source voltage rating, BVDSS, typically 40 V or 60 V, depending on the maximum input voltage
Gate charge parameters at VGS = 5 V
Output charge, QOSS, at the relevant input voltage
Body diode reverse recovery charge, QRR
Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive
amplitude of the LM25148-Q1 provides an adequately-enhanced MOSFET when on and a margin against
Cdv/dt shoot-through when off.
The MOSFET-related power losses for one channel are summarized by the equations presented in Table 9-1,
where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the
influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic
inductances and SW node ringing, are not included. Consult the Quickstart Calculator, available for download
from the LM25148-Q1 product folder, to assist with power loss calculations.
Table 9-1. MOSFET Power Losses
POWER LOSS MODE
HIGH-SIDE MOSFET
LOW-SIDE MOSFET
DIL2
12
DIL2
12
≈
’
≈
’
MOSFET conduction(2)
2
2
∆
÷
÷
◊
Å ∆
÷
÷
◊
P
= D∂ IOUT
+
∂RDS(on)1
P
= D ∂ IOUT
+
∂RDS(on)2
cond1
cond2
(3)
∆
«
∆
«
»
…
ÿ
F Ÿ
⁄
V
IN ∂FSW
2
DIL
2
DIL
2
≈
’
≈
’
P
=
I
-
∂ tR + I
+
∂ t
MOSFET switching
Negligible
PGate2 = VCC ∂FSW ∂QG2
sw1
∆ OUT
÷
◊
∆ OUT
÷
◊
«
«
MOSFET gate drive(1)
PGate1 = VCC ∂FSW ∂QG1
MOSFET output
charge(4)
PCoss = FSW ∂ VIN ∂Qoss2 + Eoss1 -Eoss2
»
…
ÿ
dt2 Ÿ
⁄
DIL
2
DIL
2
≈
’
≈
’
Body diode
conduction
P
= VF ∂FSW
I
+
∂ tdt1 + I
∆ OUT
-
∂ t
N/A
condBD
∆ OUT
÷
◊
÷
◊
«
«
Body diode
PRR = VIN ∂FSW ∂QRR2
reverse recovery(5)
(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the
relevant driver resistance of the LM25148-Q1.
(2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
(3) D' = 1–D is the duty cycle complement.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by
the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output
capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turnon, but this is offset by the stored energy Eoss2 on
Coss2
.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed, and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is, therefore, imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
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the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition deadtimes. LM25148-Q1, with
its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses
scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM25148-Q1 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.
9.1.1.5 EMI Filter
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability,
the filter output impedance must be less than the absolute value of the converter input impedance.
2
V
IN(min)
ZIN = -
P
IN
(19)
The passive EMI filter design steps are as follows:
•
•
•
Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter.
Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a
high-current design.
Calculate input filter capacitor CF.
Figure 9-2. Passive π-Stage EMI Filter for Buck Regulator
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 20.
≈
’
IL(PEAK)
1
∆
∆
«
÷
÷
◊
Attn = 20log
∂sin
p
∂DMAX
∂
- VMAX
(
)
1ꢀV
p
2 ∂FSW ∂CIN
(20)
where
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•
VMAX is the allowed dBμV noise level for the applicable conducted EMI specification, for example CISPR 25
Class 5
•
•
•
CIN is the existing input capacitance of the buck regulator
DMAX is the maximum duty cycle
IPEAK is the peak inductor current
For filter design purposes, the current at the input can be modeled as a square-wave. Determine the passive
EMI filter capacitance CF from Equation 21.
2
Attn
≈
∆
∆
’
÷
÷
40
1
10
CF =
LIN
2p
∂FSW
∆
∆
«
÷
÷
◊
(21)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small so that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
passive filter is given by Equation 22.
1
fres
=
2
p ∂ LIN ∂CF
(22)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD should
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added input damping
is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for input damping with a value given by Equation 23.
CD í 4 ∂CIN
(23)
Select the input damping resistor RD using Equation 24.
LIN
RD
=
CIN
(24)
9.1.2 Error Amplifier and Compensation
A Type-ll compensator using a transconductance error amplifier (EA) is shown in Figure 9-3. The dominant pole
of the EA open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance,
CBW, as shown by Equation 25.
g ∂RO-EA
m
GEA(openloop)(s) = -
1+ s∂RO-EA ∂CBW
(25)
The EA high-frequency pole is neglected in the above expression. The compensator transfer function from
output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor
network, is calculated in Equation 26.
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≈
’
÷
◊
s
gm ∂RO-EA ∂ 1+
∆
Ù
vc (s)
w
z1
VREF
VOUT
«
Gc (s) =
= -
∂
Ù
vout (s)
≈
’ ≈
’
s
s
1+
∂ 1+
∆
∆
«
÷ ∆
÷ ∆
◊ «
÷
÷
◊
wp1
wp2
(26)
where
•
•
•
VREF is the feedback voltage reference of 0.8 V
gm is the EA gain transconductance of 1200 µS
RO-EA is the error amplifier output impedance of 64 MΩ
1
wZ1
wp1
wp2
=
=
=
RCOMP ∂CCOMP
(27)
(28)
1
1
@
RO-EA ∂ C
+ CHF + CBW
RO-EA ∂CCOMP
(
)
COMP
1
1
@
RCOMP ∂CHF
RCOMP ∂ C
C
+ CBW
(
)
COMP
HF
(29)
The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically,
RCOMP << RO-EA and CCOMP >> CBW and CHF, so the approximations are valid.
VOUT
Error Amplifier Model
RFB1
FB
COMP
œ
gm
VREF
+
wp2
RCOMP
wz1
RO-EA
wp1
RFB2
CHF
CBW
CCOMP
AGND
Figure 9-3. Error Amplifier and Compensation Network
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9.2 Typical Applications
9.2.1 Design 1 – High Efficiency 2.1-MHz Buck Regulator
Figure 9-4 shows the schematic diagram of a single-output synchronous buck regulator with output voltage of 5
V and a rated load current of 8 A. In this example, the target half-load and full-load efficiencies are 93.5% and
92.5%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 36 V. The switching
frequency is set at 2.1 MHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA.
LIN
1 µH
CIN
2 ꢀꢁ10 µF
VIN = 3.5 V...36 V
CF
CDAMP
10
F
47
F
CVCC
2.2
F
VCC
VIN
EN
CBOOT
HO
CBOOT
0.1
VDDA
Q1
F
VOUT = 5 V
IOUT = 8 A
RFB
RS
5 m
LO
0.68
Q2
FB
24.9 k
CCOMP
H
SW
CO
RCOMP
10 k
4 ꢀ 47
F
EXTCOMP
LO
LM25148-Q1
2.7 nF
PGND
CHF
N/A
ISNS+
VOUT
PGOOD
Tie to VOUT
or GND
VCCX
PFM/SYNC
AGND
Tie to VDDA
or GND
RT
VDDA
CNFG
* VOUT tracks VIN if VIN < 5.2 V
RCNFG
41.2 k
RT
9.52 k
CVDDA
0.1
F
Figure 9-4. Application Circuit 1 With LM25148-Q1 Buck Regulator at 2.1 MHz
Note
This and subsequent design examples are provided herein to showcase the LM25148-Q1 controller
in several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Power Supply Recommendations for more details.
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9.2.1.1 Design Requirements
Table 9-2 shows the intended input, output, and performance parameters for this automotive design example.
Table 9-2. Design Parameters
DESIGN PARAMETER
Input voltage range (steady state)
Min transient input voltage (cold crank)
Max transient input voltage (load dump)
Output voltage
VALUE
8 V to 18 V
5.5 V
36 V
5 V
Output current
8 A
Switching frequency
2.1 MHz
±1%
Output voltage regulation
Standby current, no-load
Shutdown current
10 µA
2.2 µA
2.8 ms
Soft-start time
The switching frequency is set at 2.1 MHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 60 kHz with a phase margin greater than 50°.
The selected buck regulator powertrain components are cited in Table 9-3, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for lowest total conduction and switching
power loss, as discussed in detail in Section 9.1.1.4. This design uses a low-DCR, composite inductor, and
ceramic output capacitor implementation.
Table 9-3. List of Materials for Application Circuit 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
Taiyo Yuden
Murata
UMJ325KB7106KMHT
GCM32EC71H106KA03
CGA6P3X7S1H106K250AB
GCM32ER70J476KE19L
JMK325B7476KMHTR
CGA6P1X7S1A476M250AC
744373490056
CIN
2
10 µF, 50 V, X7S, 1210, ceramic, AEC-Q200
TDK
Murata
47 µF, 6.3 V, X7R, 1210, ceramic, AEC-Q200
CO
4
1
Taiyo Yuden
TDK
47 µF, 10 V, X7S, 1210, ceramic, AEC-Q200
0.56 μH, 3.6 mΩ, 13 A, 6.6 × 6.6 × 4.8 mm, AEC-Q200
0.68 µH, 4.5 mΩ, 22 A, 6.95 × 6.6 × 2.8 mm, AEC-Q200
40 V, 4.6 mΩ, 7 nC, SON 5 × 6, AEC-Q101
Shunt, 5 mΩ, 0508, 1 W, AEC-Q200
Würth Electronik
Colicraft
LO
XGL6030-681
Q1, Q2
RS
2
1
1
Infineon
IAUC60N04S6L039
Susumu
KRL2012E-M-R005-F-T5
LM25148QRGYRQ1
U1
LM25148-Q1 42-V buck controller, AEC-Q100
Texas Instruments
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25148-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Buck Inductor
1. Use Equation 30 to calculate the required buck inductance based on a 30% inductor ripple current at
nominal input voltages.
≈
’
VOUT
VOUT
≈
’
5V
5V
∆
÷
÷
◊
LO
=
∂ 1 -
=
∂ 1-
= 0.58ꢀH
∆
÷
◊
∆
«
DILO ∂F
V
2.4A ∂2.1MHz
12V
«
SW
IN nom
(
)
(30)
2. Select a standard inductor value of 0.56 µH or use a 0.68 µH to account for effective inductance derating of
molded inductors. Use Equation 31 to calculate the peak inductor currents at maximum steady-state input
voltage. Subharmonic oscillation occurs with a duty cycle greater than 50% for peak current-mode control.
For design simplification, the LM25148-Q1 has an internal slope compensation ramp proportional to the
switching frequency that is added to the current sense signal to damp any tendency toward subharmonic
oscillation.
≈
∆
«
’
DILO
2
VOUT
VOUT
≈
’
÷
◊
5V
5V
ILO(PK) = IOUT
+
= IOUT
+
∂ 1-
= 8A +
∂ 1-
= 9.53A
∆
÷
÷
◊
∆
2∂LO ∂FSW
V
0.56ꢀH∂ 2.1MHz
18V
«
IN(max)
(31)
3. Based on Equation 8, use Equation 32 to cross-check the inductance to set a slope compensation close to
the ideal one times the inductor current downslope.
VOUT ∂RS
24 ∂FSW
5V ∂5mW
24 ∂2.1MHz
LO(sc)
=
=
= 0.5ꢀH
(32)
9.2.1.2.3 Current-Sense Resistance
1. Calculate the current-sense resistance based on a maximum peak current capability of at least 25% higher
than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients.
Calculate the current sense resistances using Equation 33.
VCS-TH
1.25 ∂ILO(PK) 1.25 ∂9.53A
60mV
RS
=
=
= 5.04mW
(33)
where
•
VCS-TH is the 60-mV current limit threshold
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2. Select a standard resistance value of 5 mΩ for the shunt. An 0508 footprint component with wide aspect
ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB
layout. Carefully adhere to the layout guidelines in Section 11.1 to make sure that noise and DC errors do
not corrupt the differential current-sense voltages measured at the ISNS+ and VOUT pins.
3. Place the shunt resistor close to the inductor.
4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM25148-Q1.
5. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power
MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold.
For a total propagation delay tDELAY-ISNS+ of 40 ns, use Equation 34 to calculate the worst-case peak inductor
current with the output shorted.
V
IN(max) ∂ tDELAY-ISNS+
VCS-TH
RS
60mV 18V ∂ 45ns
ILO-PK(SC)
=
+
=
+
= 13.5A
LO
5mW
0.56ꢀH
(34)
6. Based on this result, select an inductor with saturation current greater than 16 A across the full operating
temperature range.
9.2.1.2.4 Output Capacitors
1. Use Equation 35 to estimate the output capacitance required to manage the output voltage overshoot during
a load-off transient (from full load to no load) assuming a load transient deviation specification of 1.5% (75
mV for a 5-V output).
2
2
0.56ꢀH∂ 8A
(
)
(
LO ∂ DIOUT
COUT
í
=
= 47.4ꢀF
2
2
2
2
V
+ DVOVERSHOOT - VOUT
5V + 75mV - 5V
(
)
(
)
)
OUT
(35)
2. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly
with applied voltage, select four 47-µF, 10-V, X7S, 1210 ceramic output capacitors. Generally, when
sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot
during a no-load to full-load transient is also satisfactory.
3. Use Equation 36 to estimate the peak-peak output voltage ripple at nominal input voltage.
2
2
≈
∆
«
’
÷
◊
DILO
8 ∂FSW ∂COUT
≈
∆
«
’
÷
◊
2.54A
2
2
DVOUT
=
+ RESR ∂ DILO
(
=
+ 1mW ∂ 2.54A = 4.3mV
)
(
)
8 ∂ 2.1MHz ∂ 44ꢀF
(36)
where
•
•
RESR is the effective equivalent series resistance (ESR) of the output capacitors
44 µF is the total effective (derated) ceramic output capacitance at 5 V
4. Use Equation 37 to calculate the output capacitor RMS ripple current using and verify that the ripple current
is within the capacitor ripple current rating.
DILO
2.54A
12
ICO(RMS)
=
=
= 0.73A
12
(37)
9.2.1.2.5 Input Capacitors
A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality
input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved
operation significantly reduces the input ripple amplitude. In general, the ripple current splits between the input
capacitors based on the relative impedance of the capacitors at the switching frequency.
1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
2. Use Equation 38 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle
operating point of 50%.
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ICIN(RMS) = IOUT ∂ D∂ 1-D = 8A ∂ 0.5 ∂ 1- 0.5 = 4A
(
)
(
)
(38)
3. Use Equation 39 to find the required input capacitance.
D∂ 1-D ∂I 0.5∂ 1- 0.5 ∂8A
(
)
(
)
OUT
CIN
í
=
= 9.2 ꢀF
FSW ∂ DV -RESR ∂IOUT
2.1MHz∂ 120mV - 2mW∂8A
(
)
(
)
IN
(39)
where
•
•
ΔVIN is the input peak-to-peak ripple voltage specification
RESR is the input capacitor ESR
4. Recognizing the voltage coefficient of ceramic capacitors, select two 10-µF, 50-V, X7R, 1210 ceramic input
capacitors. Place these capacitors adjacent to the power MOSFETs. See Section 11.1.1 for more details.
5. Use four 10-nF, 50-V, X7R, 0603 ceramic capacitors near the high-side MOSFET to supply the high di/dt
current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF)
and low effective impedance above 100 MHz. The result is lower power loop parasitic inductance, thus
minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature. Refer
to Section 11.1 for more details.
9.2.1.2.6 Frequency Set Resistor
Calculate the RT resistance for a switching frequency of 2.1 MHz using Equation 40. Choose a standard E96
value of 9.53 kΩ.
106
FSW (kHz)
45
106
2100kHz
45
- 53
- 53
RT (kW) =
=
= 9.4kW
(40)
9.2.1.2.7 Feedback Resistors
If an output voltage setpoint other than 3.3 V or 5 V is required (or to measure a bode plot when using either of
the fixed output voltage options), determine the feedback resistances using Equation 41.
≈
∆
«
’
VOUT1
≈
∆
«
’
5V
RFB1 = RFB2
∂
-1 = 15kW ∂
-1 = 47.5kW
÷
÷
VREF
1.2V
◊
◊
(41)
9.2.1.2.8 Compensation Components
Choose compensation components for a stable control loop using the procedure outlined as follows:
1. Based on a specified loop gain crossover frequency, fC, of 60 kHz, use Equation 42 to calculate RCOMP
assuming an effective output capacitance of 100 µF. Choose a standard value for RCOMP of 10 kΩ.
,
VOUT RS ∂GCS
5V 5mW∂10
0.8V 1200ꢀS
RCOMP = 2
p
∂ fC ∂
∂
∂COUT = 2
p
∂60kHz ∂
∂
∂100ꢀF = 9.82kW
VREF
gm
(42)
2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line
transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the
load pole. Choose a standard value for CCOMP of 2.7 nF.
10
10
CCOMP
=
=
= 2.65 nF
2
p
∂ fC ∂RCOMP
2
p
∂60kHz ∂10 kW
(43)
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Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout
(when the input voltage is less than the output voltage setpoint and VCOMP is railed high).
3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. CBW is the
bandwidth-limiting capacitance of the error amplifier. CHF may not be significant enough to be necessary in
some designs, like this one. CHF can be unpopulated, or used with a small 22 pF for more noise filtering.
1
1
CHF
=
- CBW
=
- 31 pF = 0.8 pF
2
p
∂ fESR ∂RCOMP
2
p
∂500kHz ∂10 kW
(44)
Note
Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from
operation in dropout.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to
TI's technical articles.
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9.2.1.3 Application Curves
5-V output
5-V output
Figure 9-5. Efficiency vs IOUT
Figure 9-6. Efficiency vs IOUT, Log Scale
8-A resistive load
No load
Figure 9-7. Full load Switching
Figure 9-8. PFM Switching
VIN falls to 3.8 V
5-A load
VIN ramps from 12 V to 36 V
5-A load
Figure 9-10. Cold-Crank Response to VIN = 3.8 V
Figure 9-9. Line Transient
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VIN step to 12 V
8-A resistive load
VIN = 12 V
8-A resistive load
Figure 9-11. Start-Up Characteristic
Figure 9-12. ENABLE ON and OFF Characteristic
VIN = 12 V
FPWM
VIN = 12 V
FPWM
Figure 9-14. Load Transient, 4 A to 8 A
Figure 9-13. Load Transient, 0 A to 8 A
VIN = 12 V
8-A resistive load
VIN = 13.8 V
150 kHz to 30 MHz
7-A resistive load
Figure 9-15. Bode Plot, 5-V Output
Figure 9-16. CISPR 25 Class 5 Conducted EMI
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9.2.2 Design 2 – High Efficiency 440-kHz Buck Regulator
Figure 9-17 shows the schematic diagram of a single-output synchronous buck regulator with output voltage of
5 V and a rated load current of 10 A. In this example, the target half-load and full-load efficiencies are 97%
and 95%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 36 V. The switching
frequency is set at 440 kHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA
(tie VCCX to GND in this case).
LIN
2.2 µH
CIN
4 ꢀ 10 µF
VIN = 3.5 V...36 V
CDAMP
CF
10
F
120 F
CVCC
2.2
F
VCC
VIN
EN
CBOOT
HO
CBOOT
0.1
VDDA
Q1
F
VOUT = 5 V
IOUT = 10 A
RFB
RS
4 m
LO
FB
24.9 k
CCOMP
2.2
Q2
H
SW
CO
4 ꢀ 47
RCOMP
4.22 k
F
EXTCOMP
LO
LM25148-Q1
15 nF
PGND
CHF
150 pF
ISNS+
VOUT
PGOOD
Tie to VOUT
or GND
VCCX
PFM/SYNC
AGND
Tie to VDDA
or GND
RT
VDDA
CNFG
* VOUT tracks VIN if VIN < 5.2 V
RT
49.9 k
CVDDA
0.1
RCNFG
41.2 k
F
Figure 9-17. Application Circuit 1 With LM25148-Q1 Buck Regulator at 440 kHz
Note
This and subsequent design examples are provided herein to showcase the LM25148-Q1 controller
in several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Power Supply Recommendations for more detail.
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9.2.2.1 Design Requirements
Table 9-4 shows the intended input, output, and performance parameters for this automotive design example.
Table 9-4. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Min transient input voltage (cold crank)
Max transient input voltage (load dump)
Output voltage
VALUE
8 V to 36 V
5.5 V
40 V
5 V
Output current
10 A
Switching frequency
440 kHz
±1%
Output voltage regulation
Standby current, no-load
Shutdown current
12 µA
2.2 µA
2.8 ms
Soft-start time
The switching frequency is set at 440 kHz by resistor RRT. The selected buck regulator powertrain components
are cited in Table 9-5, and many of the components are available from multiple vendors. The MOSFETs in
particular are chosen for both lowest conduction and switching power loss, as discussed in detail in Section
9.1.1.4.
Table 9-5. List of Materials for Application Circuit 2
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
AVX
TDK
12105C106K4Z2A
C3225X7R1H106K250AC
GRM32ER71H106KA12L
GCM32ER70J476KE19L
JMK325B7476KMHTR
CGA6P1X7S1A476M250AC
XGL6060-222MEC
CIN
4
10 µF, 50 V, X7R, 1210, ceramic, AEC-Q200
Murata
Murata
47 µF, 6.3 V, X7R, 1210, ceramic, AEC-Q200
CO
4
1
Taiyo Yuden
TDK
47 µF, 10 V, X7S, 1210, ceramic, AEC-Q200
2.2 μH, 4.3 mΩ, 12.5 A, 6.71 × 6.51 × 6.1 mm, AEC-Q200
2.2 µH, 6.5 mΩ, 10 A, 10 × 11 × 3.8 mm, AEC-Q200
40 V, 4.7 mΩ, 7 nC, SON 5 × 6, AEC-Q101
Coilcraft
Würth Electronik
Infineon
LO
74437368022
Q1, Q2
RS
2
1
1
IAUC60N04S6L039
Shunt, 4 mΩ, 0508, 1 W, AEC-Q200
Susumu
KRL2012E-M-R004-F-T5
LM25148QRGYRQ1
U1
LM25148-Q1 42-V buck controller, AEC-Q100
Texas Instruments
9.2.2.2 Detailed Design Procedure
See Section 9.2.1.2.
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9.2.2.3 Application Curves
100
95
90
85
80
75
70
100
95
90
85
80
75
70
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 8V
VIN = 12V
VIN = 18V
0
1
2
3
4
5
6
7
8
9
10
0.001
0.01
0.1
Load (A)
1
10
Load (A)
5-V output
5-V output
Figure 9-18. Efficiency vs IOUT
Figure 9-19. Efficiency vs IOUT, Log Scale
VOUT 20mV/DIV
VOUT 50mV/DIV
SW 5V/DIV
SW 5V/DIV
100 ms/DIV
1 µs/DIV
No load
10-A resistive load
Figure 9-21. PFM Switching
Figure 9-20. Full load Switching
VIN 1 V/DIV
VOUT 1 V/DIV
VIN 10 V/DIV
VOUT 50 mV/DIV
IOUT 1 A/DIV
PG 5 V/DIV
IOUT 5A/DIV
5 ms/DIV
20 ms/DIV
VIN ramps from 12 to 40 V
5-A load
VIN falls to 4 V
1-A load
Figure 9-22. Line Transient Response to VIN = 40 V
Figure 9-23. Line Transient Response to VIN = 4 V
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EN 2V/DIV
VIN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 5A/DIV
IOUT 5A/DIV
1 ms/DIV
1 ms/DIV
VIN = 12 V
10-A resistive load
VIN step to 12 V
10-A resistive load
Figure 9-25. ENABLE ON and OFF Characteristic
Figure 9-24. Start-Up Characteristic
VOUT 500 mV/DIV
VOUT 500 mV/DIV
IOUT 5 A/DIV
IOUT 5 A/DIV
100 µs/DIV
100 µs/DIV
VIN = 12 V
FPWM
VIN = 12 V
FPWM
Figure 9-26. Load Transient, 0 A to 10 A
Figure 9-27. Load Transient, 5 A to 10 A
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10 Power Supply Recommendations
The LM25148-Q1 buck controller is designed to operate from a wide input voltage range of 3.5 V to 42 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the
fully-loaded regulator. Estimate the average input current with Equation 45.
POUT
I
=
IN
V ∂
h
IN
(45)
where
η is the efficiency
•
If the regulator is connected to an input supply through long wires or PCB traces with a large impedance,
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables
can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply
to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate
ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. A
capacitance in the range of 10 µF to 47 µF is usually sufficient to provide parallel input damping and helps to
hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability
as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI
for DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.
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11 Layout
11.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuit (with high current and voltage
slew rates) to achieve a robust and reliable design. As expected, certain issues must be considered before
designing a PCB layout using the LM25148-Q1. The high-frequency power loop of a buck regulator power stage
is denoted by loop 1 in the shaded area of Figure 11-1. The topological architecture of a buck regulator means
that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the
parasitic inductance of this loop by minimizing its effective loop area. Also important are the gate drive loops of
the high-side and low-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.
VIN
CIN
#1
CBOOT
High frequency
power loop
VCC
CBOOT
Q1
HO
High-side
gate driver
LO
#2
SW
VOUT
VCC
CVCC
COUT
Q2
LO
Low-side
gate driver
#3
PGND
GND
Figure 11-1. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
11.1.1 Power Stage Layout
1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). Insert at least one inner
plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
2. The DC/DC regulator has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and optimize switching performance.
•
Loop 1: The most important loop area to minimize is the path from the input capacitor or capacitors
through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the ground
connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-
side MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close to
the drain of the high-side MOSFET (at VIN). Refer to loop 1 of Figure 11-1.
•
Another loop, not as critical as loop 1, is the path from the low-side MOSFET through the inductor and
output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the
source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as
close as possible.
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3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,
including pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 11-1 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz)
ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than
the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating
limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate-Drive Layout
The LM5148 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control, and low-impedance output stages capable of delivering large peak currents with very fast rise and
fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the
gate drive command, thereby increasing MOSFET switching times. The following loops are important:
•
Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop 2 of Figure 11-1.
•
Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop 3 of Figure 11-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
1. Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side
MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive
currents can be as high as 3.3 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at
least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from
the LM5148 to the high-side MOSFET, taking advantage of flux cancellation.
2. Minimize the current loop path from the VCC and HB pins through their respective capacitors as these
provide the high instantaneous current, up to 3.3 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the CBOOT and SW pins of the LM5148 to minimize the area
of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC
and PGND pins of the LM5148 to minimize the area of loop 3 associated with the low-side driver.
11.1.3 PWM Controller Layout
With the proviso to locate the controller as close as possible to the power MOSFETs to minimize gate driver
trace runs, the components related to the analog and feedback signals as well as current sensing are considered
in the following:
1. Separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components related to COMP, FB, ISNS+, and RT away from high-
voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or
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layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense
(ISNS+ and VOUT) traces from power traces and components.
3. Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short
as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at
the load.
4. Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin
connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if
inductor DCR current sensing is used).
5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
PGND pin. Locate these capacitors as close as possible to the LM25148-Q1.
11.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by the following:
•
•
•
•
Average gate drive current requirements of the power MOSFETs
Switching frequency
Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the
efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM5148
controller is available in a small 4-mm × 4-mm 24-pin VQFN PowerPAD package to cover a range of application
requirements. Section 11.1.4 summarizes the thermal metrics of this package.
The 24-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM5148 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5148 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed
on the PCB layer below the power components. Not only does this provide a plane for the power stage currents
to flow but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are
normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW
plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.
11.1.5 Ground Plane Design
As mentioned previously, TI recommends using one or more of the inner PCB layers as a solid ground plane. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components
is essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output
capacitors to this ground plane. Connect the PGND and AGND pins of the controller at the DAP and then
connect to the system ground plane using an array of vias under the DAP. The PGND nets contain noise at the
switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and
SW can be restricted to one side of the ground plane, for example on the top layer. The other side of the ground
plane contains much less noise and is ideal for sensitive analog trace routes.
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11.2 Layout Example
Figure 11-2 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and
Q2, in SON 5-mm × 6-mm case size. The power stage is surrounded by a GND pad geometry to connect an
EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the
top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic
inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.
The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane
on layer 2, and back to VIN through the 0603 ceramic capacitors C15 through C18. The currents flowing in
opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance.
Figure 11-4 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer
PCB structure. The layer-2 GND plane layer, shown in Figure 11-3, provides a tightly-coupled current return path
directly under the MOSFETs to the source terminals of Q2.
Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain
of Q1. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small
footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are
connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic
loop inductance.
Locate controller close
to the power stage
Place PGND vias close to the
source of the low-side FET
Output Caps
PGND
G
S
SW
HO
VOUT
VIN
GND
Low-side
FET
Inductor
SW
LO
VCC
Input Caps
VIN
Shunt
G S
AGND
High-side
FET
GND
GND
Optional shield
GND connection
Copper island
connected to AGND pin
Use paralleled 0603 input capacitors close to
the FETs for VIN to PGND decoupling
Figure 11-2. PCB Top Layer – High Density, Single-sided Design
Additional guidelines to improve noise immunity and reduce EMI are as follows:
•
Make the ground connections to the LM25148 controller as shown in Figure 11-2. Create a power
ground directly connected to all high-power components and an analog ground plane for sensitive analog
components. The analog ground plane for AGND and power ground plane for PGND must be connected at a
single point directly under the IC – at the die attach pad (DAP).
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•
Connect the MOSFETs (switch node) directly to the inductor terminal with short copper connections (without
vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node
connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This
avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper
pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI
signature.
•
Place the EMI filter components on the bottom side of the PCB so that they are shielded from the power
stage components on the top side.
Figure 11-3. Layer 2 Full Ground Plane Directly Under the Power Components
Tightly-coupled return path
minimizes power loop impedance
Cin1-4
Q2
Q1
SW
VIN
GND
GND
L1
L2
0.15mm
L3
L4
0.3mm
vias
Figure 11-4. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing 1
1
See Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout for more detail.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
With an input operating voltage as low as 3.5 V and up to 100 V as specified in Table 12-1, the LM(2)514x-Q1
family of automotive synchronous buck controllers from TI provides flexibility, scalability and optimized solution
size for a range of applications. These controllers enable DC/DC solutions with high density, low EMI and
increased flexibility. Available EMI mitigation features include dual-random spread spectrum (DRSS) or triangular
spread spectrum (TRSS), split gate driver outputs for slew rate (SR) control, and integrated active EMI filtering
(AEF). All controllers are rated for a maximum operating junction temperature of 150°C, have AEC-Q100 grade
1 qualification, and are functional safety capable.
Table 12-1. Automotive Synchronous Buck DC/DC Controller Family
DC/DC
CONTROLLER
SINGLE or
DUAL
GATE DRIVE
VOLTAGE
VIN RANGE
CONTROL METHOD
SYNC OUTPUT
EMI MITIGATION
LM25148-Q1
LM25149-Q1
LM25141-Q1
LM5141-Q1
LM5143-Q1
LM5145-Q1
LM5146-Q1
Single
Single
Single
Single
Dual
3.5 V to 42 V
3.5 V to 42 V
3.8 V to 42 V
3.8 V to 65 V
3.5 V to 65 V
5.5 V to 75 V
5.5 V to 100 V
Peak current mode
Peak current mode
Peak current mode
Peak current mode
Peak current mode
Voltage mode
5 V
180° phase shift
180° phase shift
N/A
DRSS
5 V
AEF, DRSS
SR control, TRSS
SR control, TRSS
SR control, TRSS
N/A
5 V
5 V
N/A
5 V
90° phase shift
180° phase shift
180° phase shift
Single
Single
7.5 V
7.5 V
Voltage mode
N/A
For development support see the following:
•
•
•
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
TI Designs:
– ADAS 8-Channel Sensor Fusion Hub Reference Design with Two 4-Gbps Quad Deserializers
– Automotive EMI and Thermally Optimized Synchronous Buck Converter Reference Design
– Automotive High Current, Wide VIN Synchronous Buck Controller Reference Design Featuring LM5141-
Q1
– 25W Automotive Start-Stop Reference Design Operating at 2.2 MHz
– Synchronous Buck Converter for Automotive Cluster Reference Design
– 137W Holdup Converter for Storage Server Reference Design
– Automotive Synchronous Buck With 3.3V @ 12.0A Reference Design
– Automotive Synchronous Buck Reference Design
– Wide Input Synchronous Buck Converter Reference Design With Frequency Spread Spectrum
– Automotive Wide VIN Front-end Reference Design for Digital Cockpit Processing Units
Technical Articles:
– High-Density PCB Layout of DC/DC Converters
– Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility
– How to Use Slew Rate for EMI Control
•
•
To view a related device of this product, see the LM5141-Q1
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25148-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
User's Guides:
– LM25149-Q1 Synchronous Buck Controller High Density EVM
– LM5141-Q1 Synchronous Buck Controller EVM
– LM5143-Q1 Synchronous Buck Controller EVM
– LM5146-Q1 EVM User's Guide
– LM5145 EVM User's Guide
•
Application Reports:
– Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
Application Report
– AN-2162 Simple Success with Conducted EMI from DC-DC Converters
– Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140-Q1 Dual Synchronous
Buck Controller
•
•
Technical Briefs:
– Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
White Papers:
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
– Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications
12.2.1.1 PCB Layout Resources
•
Application Reports:
– Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
– AN-1149 Layout Guidelines for Switching Power Supplies
– AN-1229 Simple Switcher PCB Layout Guidelines
– Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
Seminars:
•
– Constructing Your Power Supply – Layout Considerations
12.2.1.2 Thermal Design Resources
•
Application Reports:
– AN-2020 Thermal Design by Insight, Not Hindsight
– AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
– Semiconductor and IC Package Thermal Metrics
– Thermal Design Made Simple with LM43603 and LM43602
– PowerPAD™Thermally Enhanced Package
– PowerPAD Made Easy
– Using New Thermal Metrics
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
NexFET™ and TI E2E™ are trademarks of Texas Instruments.
PowerPAD™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
is a registered trademark of TI.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages show mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLM25148QRGYRQ1
ACTIVE
VQFN
RGY
24
3000
Non-RoHS &
Non-Green
Call TI
Call TI
-40 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RGY 24
5.5 x 3.5 mm, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4203539-5/J
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Copyright © 2021, Texas Instruments Incorporated
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