LM5170PHPR [TI]
多相双向电流控制器 | PHP | 48 | -40 to 125;型号: | LM5170PHPR |
厂家: | TEXAS INSTRUMENTS |
描述: | 多相双向电流控制器 | PHP | 48 | -40 to 125 控制器 |
文件: | 总74页 (文件大小:3821K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LM5170
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
LM5170 多相双向电流控制器
1 特性
2 应用
• 提供功能安全
• 电池测试仪
• 双向电池管理系统
• 备用电池供电型转换器
• 可堆叠降压或升压转换器
• 负/正电压转换器
– 可帮助进行功能安全系统设计的文档
• 适用于大功率工业双电池系统
– 高压(HV) 端口和低压(LV) 端口的最高额定电压
分别为100V 和65V
– 1% 精密双向电流调节
– 1% 精密通道电流监测
3 说明
LM5170 控制器提供双通道双向转换器必不可少的高压
和精密元件。该器件可按照 DIR 输入信号指定的方向
调节高压和低压端口间的平均电流。电流调节水平可通
过模拟或数字PWM 输入以编程方式设定。
– 5A 峰值半桥栅极驱动器
– 借助可堆叠功能支持多相操作
– 二极管仿真可防止负电流
• 可编程性和灵活性
– 可编程或自适应死区时间控制
– 可选择与外部时钟同步的可编程振荡器频率
– 双通道使能控制输入
– 模拟和PWM 电流控制
– 可编程峰值电流限制
双通道差分电流感测传感器和专用通道电流监测计可实
现 1% 的典型电流精度。稳定的 5A 半桥栅极驱动器能
够驱动功率不低于 500W/通道的并联金属氧化物半导
体场效应晶体管 (MOSFET) 开关。同步整流器的二极
管仿真模式可避免出现负向电流,但也支持通过非连续
操作模式提升轻载效率。通用保护特性包括逐周期电流
限制、HV 和 LV 端口过压保护、MOSFET 故障检测和
过热保护。
– 可编程软启动计时器
– 使用EN2 进行增相或减相
• 集成保护特性
– HV 和LV 端口过压保护
– 启动时执行MOSFET 故障检测以及断路器控制
– 热关断
器件信息(1)
封装尺寸(标称值)
器件型号
封装
LM5170
TQFP (48)
7.00mm × 7.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
LV-Port
(12 V)
HV-Port
(48 V)
+10
V Bias
HO1 SW1 LO1
PGND
VCC
CSA1
CSB1
VIN
VINX
IOUT1
IOUT2
RAMP1
OVPA
IPK
OSC
RAMP2
SYNCOUT
AGND
OVPB
ISETD
SYNCIN
ISETA
DIR
EN1
CSB2
CSA2
EN2
HO2
SW2 LO2
GND
简化版应用电路
通道电流跟踪ISETA 命令
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSBJ0
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Table of Contents
8.5 Programming............................................................ 36
9 Application and Implementation..................................39
9.1 Application Information............................................. 39
9.2 Typical Application.................................................... 47
10 Power Supply Recommendations..............................59
11 Layout...........................................................................60
11.1 Layout Guidelines................................................... 60
11.2 Layout Examples.....................................................61
12 Device and Documentation Support..........................64
12.1 Device Support....................................................... 64
12.2 接收文档更新通知................................................... 64
12.3 支持资源..................................................................64
12.4 Trademarks.............................................................64
12.5 Electrostatic Discharge Caution..............................64
12.6 术语表..................................................................... 64
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics.............................................. 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................32
Information.................................................................... 64
4 Revision History
Changes from Revision A (June 2020) to Revision B (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
Changes from Revision * (November 2019) to Revision A (June 2020)
Page
• 向节1 添加了功能安全要点................................................................................................................................ 1
5 说明(续)
创新型平均电流模式控制方案可维持恒定环路增益,因此允许使用单一 R-C 网络来补偿升压和降压转换。振荡器
频率最高可调节至500kHz,能够与外部时钟同步。连接两个LM5170 控制器执行三相或四相操作,或者将多个控
制器与相移时钟同步来实现相位更多的操作,进而实现多相并行操作。UVLO 引脚的低电平状态可禁用处于低电
流关断模式下的LM5170。
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
6 Pin Configuration and Functions
CSA2
CSB2
NC
1
2
36
35
34
33
32
31
30
29
28
27
26
25
CSA1
CSB1
BRKG
BRKS
NC
3
VINX
NC
4
5
VIN
NC
6
VCCA
IPK
7
8
RAMP2
OVPA
OPT
RAMP1
9
UVLO
COMP2
SS
10
11
12
nFAULT
COMP1
OVPB
图6-1. 48-Pin TQFP, PHP Package (Top View)
表6-1. Pin Functions
PIN
NAME
I/O(1)
DESCRIPTION
NO.
1
CSA2
CSB2
NC
I
I
CH-2 differential current sense inputs. The CSA2 pin connects to the CH-2 power inductor. The CSB2 pin
connects to the circuit breaker or directly to the LV-Port if the circuit breaker is not used. The CH-2 current sense
resistor is placed between these two pins.
2
3
No connect
—
Internally connected to VIN the pin through a cutoff switch. When the controller is shut down, VINX is
disconnected from VIN, opening the current leakage path. When the controller is enabled, VINX is connected to
VIN and serves as the pullup supply for the RC ramp generators at the RAMP1 and RAMP2 pins. VINX also
pulls up the OVPA pin through an internal 3-MΩresistor.
4
VINX
O
5
6
7
NC
VIN
NC
No connect
—
The input pin connecting to the HV-Port line voltage. It supplies the BRKG pin through an internal 330-µA
current source.
I
No connect
—
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
表6-1. Pin Functions (continued)
PIN
NAME
I/O(1)
DESCRIPTION
NO.
The inverting input of the CH-2 PWM comparator. An external RC circuit tied between VINX, RAMP2, and
AGND forms the ramp generator, producing a ramp signal proportional to the HV-Port voltage, thus achieving a
voltage feedforward function. The RAMP2 capacitor voltage is reset to AGND at the end of every switching
cycle.
8
RAMP2
OVPA
I
Connected to the non-inverting input of the HV-Port overvoltage comparator. An internal 3-MΩpullup resistor
and an external resistor across the OVPA and AGND pins form a divider that senses the HV-Port voltage. When
the OVPA pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the
overvoltage condition is removed.
9
I
I
The UVLO pin serves as the master enable pin. When UVLO is pulled below 1.25 V, the entire LM5170 is in a
low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the LM5170 enters
the initialization stage where the nFAULT pin is first pulled up to 5 V, while the rest of the LM5170 is kept in the
OFF state. When UVLO is pulled above the 2.5 V, the LM5170 enters a MOSFET failure detection stage. If no
failure is detected, the circuit breaker gate driver (BRKS and BRKG) turns on, and the LM5170 enables the
oscillator and RAMP generator, and stands by until the EN1 and EN2 commands enable the channel.
10
ULVO
The output of the CH-2 transconductance (gm) error amplifier and the non-inverting input of the CH-2 PWM
comparator. A loop compensation network must be connected to this pin.
11
12
13
COMP2
SS
O
I
The soft-start programming pin. An external capacitor and an internal 25-μA current source set the ramp rate of
the COMP pins voltage during soft start. If CH-2 is enabled after CH-1 completes soft start, the CH-2 turnon is
not controlled by the SS pin.
CH-2 switch node. Connect to the CH-2 high-side MOSFET source, the low-side MOSFET drain, and the
bootstrap capacitor return terminal.
SW2
I
14
15
16
17
18
HB2
HO2
NC
P
CH-2 high-side gate driver bootstrap supply input
I/O CH-2 high-side gate driver output
No connect
I/O CH-2 low-side gate driver output
—
LO2
PGND
G
Power ground connection pin for the low-side gate drivers and external VCC bias supply
VCC bias supply pin, powering the drivers. An external bias supply between 9 V to 12 V must be applied across
the VCC and PGND pins.
19
VCC
I/P
20
21
22
23
LO1
NC
I/O CH-1 low-side gate driver output
No connect
I/O CH-1 high-side gate driver output
—
HO1
HB1
P
I
CH-1 high-side gate driver bootstrap supply input
CH-1 switch node. Connect to the CH-1 high-side MOSFET source, the low-side MOSFET drain, and the
bootstrap capacitor return terminal.
24
25
26
27
SW1
Connected to the non-inverting input of the LV-Port overvoltage comparator. An internal 1-MΩ pullup resistor
and an external resistor across the OVPB and AGND pins form the divider that senses the LV-Port voltage.
When the converter operates in boost mode, the OVPB pin status is ignored. In buck mode, when the OVPB pin
voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage
condition is removed.
OVPB
I
Output of the CH-1 transconductance (gm) error amplifier and the non-inverting input of the CH-1 PWM
comparator. A loop compensation network must be connected to this pin.
COMP1
nFAULT
O
Fault flag pin or external shutdown pin. When a MOSFET drain-to-source short circuit failure is detected before
start-up, the nFAULT pin is internally pulled low to report the short-circuit failure. The LM5170 remains in a
I/O disabled state. The nFAULT pin can also be externally pulled low to shut down the LM5170, serving as a forced
shutdown pin. In forced shutdown, all gate drivers turn off and nFAULT is latched low until the UVLO pin is
pulled below 1.25 V to release the latch and initiate a new start-up.
The inverting input of the CH-1 PWM comparator. An external RC circuit tied between VINX, RAMP1, and
AGND forms the ramp generator, producing a ramp signal proportional to the HV-Port voltage. This achieves a
voltage feedforward function. The RAMP1 capacitor voltage is reset to AGND at the end of every switching
28
RAMP1
I
cycle.
Multiphase configuration pin. Tied to either VCCA or AGND, the OPT pin sets the phase lag of the SYNCOUT
signal corresponding to 4-phase or 3-phase operation, respectively.
29
30
OPT
IPK
I
I
A resistor connected between IPK and AGND sets the threshold for the cycle-by-cycle current limit comparator.
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
PIN
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
表6-1. Pin Functions (continued)
I/O(1)
DESCRIPTION
NO.
NAME
VCCA
NC
Analog bias supply pin. Connect VCCA to VCC through an external 25-Ω resistor. A low-pass filter capacitor is
31
I/P
required from the VCCA pin to AGND.
32
No connect
—
Connect to the common source of the circuit breaker MOSFET pair. When the circuit breaker function is
disabled, simply connect to AGND through a 20-kΩresistor.
33
BRKS
O
Connect to the gate pins of the circuit breaker MOSFET pair. Once the LM5170 is enabled, an internal 330-µA
current source starts to charge the circuit breaker MOSFET gates. The BRKG to BRKS voltage is internally
clamped at 12 V.
34
35
BRKG
CSB1
O
I
CH-1 differential current sense inputs. The CSA1 pin connects to the CH-1 power inductor. The CSB1 pin
connects to the circuit breaker or directly to the LV-Port if the circuit breaker is not used. The CH-1 current sense
resistor is placed between these two current sense pins. An internal 1-MΩ resistor is connected between the
CSB1 and OVPB pins through an internal cutoff switch. During operation, the cutoff switch is closed and this
internal resistor pulls up the OVPB pins. In shutdown mode, the internal resistor is disconnected by the cutoff
switch.
36
CSA1
I
CH-1 inductor current monitor pin. A current source proportional to the CH-1 inductor current flows out of this
pin. Placing a terminating resistor and filter capacitor from IOUT1 to AGND produces a DC voltage representing
the CH-1 DC current level. An internal 25-µA offset DC current source at the IOUT1 pin raises the active signal
to be above the ground noise, thus improving the monitor noise immunity.
37
38
IOUT1
IOUT2
O
O
CH-2 inductor current monitor pin. A current proportional to the CH-2 inductor current flows out of this pin.
Placing a terminating resistor and filter capacitor from IOUT2 to AGND produces a DC voltage representing the
CH-2 DC current level. An internal 25-µA offset DC current source at the IOUT2 pin raises the active signal
above the ground noise, thus improving the monitor noise immunity.
CH-1 enable pin. Pulling EN1 above 2.4 V turns off the SS pulldown and allows CH-1 to begin a soft-start
sequence. Pulling EN1 below 1 V discharges the SS capacitor and holds it low. The high- and low-side gate
drivers of both channels are held in the low state when SS is discharged.
39
40
EN1
I
I
Input for an external clock that overrides the free-running internal oscillator. The SYNCIN pin can be left open or
grounded when it is not used.
SYNCIN
Clock output pin and fault check mode selector. SYNCOUT is connected to the downstream LM5170 in a 3- or
4-phase configuration. It also functions as a circuit breaker selection pin during start-up. Placing a 10-kΩ resistor
from the SYNCOUT to AGND pin disables the fault check feature. If no resistor is connected from SYNCOUT to
AGND, the fault check is enabled.
41
SYNCOUT
O
The PWM current programming pin. The inductor DC current level is proportional to the PWM duty cycle. Use
either ISETA or ISETD but not both for channel current programming. When ISETD is not used, short ISETD to
AGND.
42
43
ISETD
EN2
I
I
CH-2 enable pin. Pulling EN2 above 2.4 V enables CH-2. Pulling EN2 below 1 V shuts down the HO2 and LO2
drivers.
Direction command input. Pulling DIR above 2 V sets the converter to buck mode, which commands the current
to flow from the HV-Port to LV-Port. Pulling DIR below 1 V sets the converter to boost mode, which commands
the current to flow from the LV-Port to HV-Port. If the DIR pin is left open, the LM5170 detects an invalid
command and disables both channels with the MOSFET gate drivers in the low state.
44
45
DIR
I
The analog current programming pin. The inductor DC current is proportional to the ISETA voltage. Use either
I, O ISETA or ISETD but not both for channel current programming. When ISETA is not used, connect a 100-pF to
0.1-µF capacitor from ISETA to AGND.
ISETA
Analog ground reference. AGND must connect to PGND externally through a single point connection to improve
the LM5170 noise immunity.
46
47
48
AGND
OSC
DT
G
I
I
The internal oscillator frequency is programmed by a resistor between OSC and AGND.
A resistor connected between DT and AGND sets the dead time between the high-side and low-side driver
outputs. Tie the DT pin to VCCA to activate the internal adaptive dead time control.
Exposed pad of the package. No internal electrical connections. Must be soldered to the large ground plane to
reduce thermal resistance.
EP
—
—
(1) Note: G = Ground, I = Input, O = Output, P = Power
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
VIN, VINX, to AGND
95
100
95
–0.3
VIN, VINX, to AGND 50-ns Transient
VIN to VINX
–0.3
–5
VIN to VINX 50-ns Transient
SW1, SW2 to PGND
100
95
SW1, SW2 to PGND (20-ns Transient)
SW1, SW2 to PGND (50-ns Transient)
HB1 to SW1, HB2 to SW2
100
–16
–0.3
–0.3
–1.5
–0.3
–1.5
–0.3
–5
14
HO1 to SW1, HO2 to SW2
HO1 to SW1, HO2 to SW2 (20-ns Transient)
HB + 0.3
Voltage
V
LO1, LO2 to PGND
VCC + 0.3
LO1, LO2 to PGND (20-ns Transient)
BRKG, BRKS, to PGND
65
65
0.3
14
CSA1, CSB1, CSA2, CSB2 to PGND
CSA1 to CSB1, CSA2 to CSB2
BRKG to BRKS
–0.3
–0.3
EN1, EN2, DIR, IOUT1, IOUT2, IPK, ISETA, ISETD, nFAULT,
OSC, OVPA, OVPB, SYNCIN, SYNCOUT, UVLO, to AGND
7
–0.3
–0.3
–0.3
PGND to AGND
0.3
14
VCC to PGND, VCCA, DT, OPT, COMP1, COMP2, RAMP1,
RAMP2, SS, to AGND
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
–40
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) For soldering specs, see www.ti.com/packaging.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
6
NOM
MAX
85
UNIT
Buck mode
Boost mode
Buck mode
Boost mode
VIN, HV-Port
LV-Port
V
V
6
85
0
60
3(2)
60
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
12
UNIT
V
VVCC
TJ
External voltage applied to VCC
Operating junction temperature
Oscillator frequency
9
125
°C
–40
FOSC
FEX_CLK
tDT
50
500
kHz
kHz
ns
Synchronization to external clock frequency (minimal 50 kHz)
Programmable dead time
0.8 × FOSC
1.2 × FOSC
200
15
1
ISETD PWM frequency
1000
500
kHz
ns
SYNCIN pulse width
100
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
(2) Minimum input voltage in boost mode can be lower than 3 V after start-up, but is limited by the minimum off-time.
7.4 Thermal Information
LM5170
THERMAL METRIC(1)
PHP (TQFP)
48 PINS
25.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.6
8.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
8.5
ψJB
RθJC(bot)
1.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETER
VIN SUPPLY (VIN, VINX)
ISHUTDOWN VIN pin current in shutdown mode
TEST CONDITIONS
MIN(3)
TYP(2)
MAX(3)
UNIT
VUVLO = 0 V
20
µA
VVCC > 9 V, VUVLO > 2.5 V, VEN1 = VEN2
= 0 V
ISTANDBY
VIN pin current, no switching
1
mA
VIN to VINX disconnect switch
VIN to VINX disconnect switch
VUVLO < 1 V or VVCC < 7.5 V
VUVLO > 2.6 V, VVCC > 9 V
5
MΩ
100
Ω
VCC AND VCCA BIAS SUPPLIES
VCCUVLO
VCCHYS
IVCC_SD
IVCC_SB
VCC undervoltage detection
VVCC falling
7.6
8.1
8
8.3
8.9
30
V
V
VCC UVLO hysteresis
VVCC rising
8.5
VCC sink current in shutdown mode
VCC sink current in standby: no switching
VUVLO = 0 V
µA
mA
VUVLO > 2.6 V, VEN1 = VEN2 = 0 V
10
MASTER ON/OFF CONTROL (UVLO)
VUVLO_TH
IHYS
UVLO release threshold
UVLO hysteresis current
UVLO voltage rising
2.4
21
2.5
25
2.6
29
V
UVLO source current when VUVLO > 2.6
V
µA
VSD
UVLO shutdown threshold (IC shutdown)
UVLO shutdown release
UVLO voltage falling
1
1.25
0.25
2.5
1
1.5
V
V
UVLO voltage rising above VSD
UVLO voltage falling
0.15
0.35
tUVLO
UVLO glitch filter time
µs
µA
UVLO internal pulldown current
CHANNEL ENABLE INPUTS EN1 AND EN2
VIL
VIH
Enable input low state
Enable input high state
Disabled the driver outputs
Enable the driver outputs
1
V
V
2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETER
TEST CONDITIONS
MIN(3)
TYP(2)
100
2
MAX(3)
UNIT
kΩ
Internal pulldown impedance
EN1, EN2 internal pulldown resistor
EN glitch filter time (the rising and falling edges)
µs
DIRECTION COMMAND (DIR)
Command for current flowing from LV-Port to
HV-Port (boost mode 12 V to 48 V)
VDIR
Actively pulled low by external circuit
Actively pulled high by external circuit
1
V
V
Command for current flowing from HV-Port to
LV-Port (buck mode 48 V to 12 V)
2
Standby (invalid DIR command)
DIR glitch filter
DIR neither active high nor active low
Both rising and falling edges
1.5
10
V
µs
ISET INPUT (ISETA, ISETD)
Regulated DC current sense voltage to ISETA
GISETA
19.7
20
170
20.3
mV/V
kΩ
|VCSA –VCSB| = 50 mV
voltage
ISETA internal pulldown resistor
Conversion ratio of ISETA voltage to ISETD
duty cycle
ISETD frequency = 10 kHz, Duty =
100%
GISETD
30.63
2
31.25
31.88
1
mV / %
VISETD _LO
VISETD _HI
ISETD PWM signal low-state voltage
ISETD PWM signal high-state voltage
ISETD internal pulldown resistor
V
V
100
100
kΩ
ISETD internal decoder filter resistor (tied to
ISETA pin)
kΩ
OUTPUT CURRENT MONITOR (IOUT1, IOUT2)
IOUT1 and IOUT2 versus channel current sense
voltage, in buck mode
GIOUT_BK1
GIOUT_BST1
GIOUT_BK2
GIOUT_BST2
4.9
4.9
5
5
5.1
5.1
|VCSA –VCSB| = 50 mV, VDIR > 2 V
|VCSA –VCSB| = 50 mV, VDIR < 1 V
μA/mV
μA/mV
μA/mV
IOUT1 and IOUT2 versus channel current sense
voltage, in boost mode
IOUT1 and IOUT2 versus channel current sense
voltage, in buck mode
|VCSA –VCSB| = 10 mV, VDIR > 2 V, TJ =
25°C
4.91
5.18
5.43
IOUT1 and IOUT2 versus channel current sense
voltage, in boost mode
|VCSA –VCSB| = 10 mV, VDIR < 1 V, TJ =
25°C
4.47
22
4.77
25
5.1
28
μA/mV
IOUT1 and IOUT2 DC offset currents
µA
|VCSA –VCSB| = 0 mV
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
Amplifier output to current sense voltage in buck
GCS_BK1
mode
49.25
49.25
49
50
50
52
50.75
50.75
55
V/V
V/V
V/V
|VCSA –VCSB| = 50 mV, VDIR > 2 V
|VCSA –VCSB| = 50 mV, VDIR < 1 V
Amplifier output to current sense voltage in
boost mode
GCS_BST1
Amplifier output to current sense voltage in buck
|VCSA –VCSB| = 10 mV, VDIR > 2 V, TJ =
25°C
GCS_BK2
mode
Amplifier output to current sense voltage in
boost mode
|VCSA –VCSB| = 10 mV, VDIR < 1 V, TJ =
25°C
GCS_BST2
45
48
10
51
V/V
BWCS
Amplifier bandwidth
MHz
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
Gm
Transconductance
1
2
mA/V
mA
ICOMP
Output source current limit
Output sink current limit
Amplifier bandwidth
VISETA = 2.5 V, |VCSA –VCSB| = 10 mV
VISETA = 0 V, |VCSA –VCSB| = 50 mV
mA
–2
BWgm
4
MHz
PWM COMPARATOR
COMP to output delay
50
1
ns
V
COMP to PWM offset
Minimum OFF time
TOFF(min)
150
200
250
15
ns
RAMP GENERATOR (RAMP1 AND RAMP2)
RAMP discharge device RDS(on)
Threshold voltage for valid ramp signal
PEAK CURRENT LIMIT (IPK)
Ω
0.6
V
IPK internal current source
24.375
25
25.625
µA
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETER
TEST CONDITIONS
MIN(3)
TYP(2)
MAX(3)
UNIT
Current sense voltage versus cycle-by-cycle
limit threshold voltage given at IPK pin, in buck
mode
IPKBuck
35.8
46
58.9
mV/V
RIPK = 40 kΩ, VDIR > 2 V
Current sense voltage versus cycle-by-cycle
limit threshold voltage given at IPK pin, in boost
mode
IPKBoost
38.5
1.15
48
62.25
1.22
mV/V
RIPK = 40 kΩ, VDIR < 1 V
OVERVOLTAGE PROTECTION (OVPA, OVPB)
OVP threshold
OVP voltage rising
1.185
100
5
V
OVPHYS
OVP hysteresis (falling edge)
OVPA and OVPB glitch filter
Internal OVPA pullup resistor
mV
µs
ROVPA
ROVPB
VINX to OVPA impedance
3
MΩ
CSB1 to OVPB impedance, VUVLO > 2.6
V
Internal OVPB pullup resistor
1
MΩ
OSCILLATOR (OSC)
Oscillator frequency 1
90
100
375
110
410
kHz
kHz
V
ROSC = 40 kΩ, SYNCIN open
ROSC = 10 kΩ, SYNCIN open
Oscillator frequency 2
OSC pin DC voltage
335
VOSC
1.25
SYNCIN
VSYNIH
SYNCIN input threshold for high state
2
V
V
VSYNIL SYNC SYNCIN input threshold for low state
Internal pulldown impedance
Delay to establish synchronization
SYNCOUT
1
VSYNCIN = 2.5 V
100
200
kΩ
µs
0.8 × FOSC < FSYNCIN < 1.2 × FOSC
VSYNOH
VSYNOL
SYNCOUT high state
SYNCOUT low state
2.5
V
V
0.4
Sourcing current when SYNCOUT in high state VSYNCOUT = 2.5 V
SYNCOUT pulse width
1
300
90
mA
ns
240
370
VOPT > 2 V
SYNCOUT phase delay configurations
VOPT < 1 V
Degree
120
Use circuit breaker function and fault
detection at start-up
OPEN
10
RSYNCOUT
Circuit breaker signature
kΩ
Do not use circuit breaker function or
disable fault detection at start-up
BOOTSTRAP (HB1, HB2)
VHB-UV
Bootstrap undervoltage threshold
5.7
6.5
0.5
7.3
50
V
V
(VHB –VSW) voltage rising
VHB-UV-HYS Hysteresis
IHB-LK
Bootstrap quiescent current
µA
V
HB –VSW = 10 V, VHO –VSW = 0 V
HIGH-SIDE GATE DRIVERS (HO1, HO2)
VOLH
VOHH
HO low-state output voltage
IHO = 100 mA
0.1
0.15
5
V
V
HO high-state output voltage
HO rise time (10% to 90% pulse magnitude)
HO fall time (90% to 10% pulse magnitude)
HO peak source current
IHO = –100 mA, VOHH = VHB –VHO
CLD = 1000 pF
ns
ns
A
CLD = 1000 pF
4
IOHH
IOLH
4
V
V
HB –VSW = 10 V
HB –VSW = 10 V
HO peak sink current
5
A
LOW-SIDE GATE DRIVERS (LO1, LO2)
VOLL
VOHL
LO low-state output voltage
ILO = 100 mA
0.1
0.15
5
V
V
LO high-state output voltage
LO rise time (10% to 90% pulse magnitude)
LO fall time (90% to 10% pulse magnitude)
LO peak source current
ILO = –100 mA, VOHL = VVCC –VLO
CLD = 1000 pF
ns
ns
A
CLD = 1000 pF
4
IOHL
IOLL
4
LO peak sink current
5
A
INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETER
TEST CONDITIONS
MIN(3)
TYP(2)
MAX(3)
UNIT
V
VOPTL
VOPTH
OPT input low state
1
OPT input high state
2
V
HO2 on-time rising edge versus HO1 on-time
rising edge, or LO2 on-time rising edge versus
LO1 on-time rising edge
VOPT > 2 V for 2, 4, 6, and 8 phases
VOPT < 1 V for 3 phases
175
180
240
1
185
245
Degrees
235
Internal pulldown impedance
MΩ
DEAD TIME (DT)
tDT
LO falling edge to HO rising edge delay
40
40
ns
ns
V
RDT = 7.5 kΩ
RDT = 7.5 kΩ
tDT
HO falling edge to LO rising edge delay
DC voltage level for programming
VDT
1.25
DC voltage for adaptive dead time scheme only
(short DT to VCCA)
VDT
VCCA
1.5
V
V
HO-SW or LO-GND voltage threshold to enable
cross output for adaptive dead time scheme
VVCC > 9 V, (VHB –VSW) > 8 V, HO or
LO voltage falling
VADPT
tADPT
tADPT
LO falling edge to HO rising edge delay
HO falling edge to LO rising edge delay
VDT = VVCC
VDT = VVCC
36
41
ns
ns
SOFT START (SS)
ISS
SS charging current source
VSS = 0 V
25
1
µA
V
SS –PWM comparator noninverting
input
VSS-OFFS
SS to PWM comparator offset
RSS
SS discharge device RDS(on)
VSS = 2 V
30
Ω
VSS_LOW
SS discharge completion threshold
Once it is discharged by internal logic
0.23
V
DIODE EMULATION
Current zero cross threshold
CKT BREAKER CONTROL (BRKG, BRKS)
Current sense voltage
0
mV
nFAULT = 5 V, VVIN = 24 V, VBRKS = 12
V
IBRKG
Sourcing current
275
9
330
375
µA
VBRK-CLP
RBRK-SINK
Voltage clamp
nFAULT= 5 V, VVIN = 48 V, VBRKS = 12 V
nFAULT = 0 V
14.5
V
Sinking capability
20
Ω
BRKG to BRKS voltage threshold to indicate
readiness for operation
VREADY
Rising edge
6.5
8.5
V
nFAULT= 5 V, VVIN –VBRKS = 0 V,
IBRKG-LEAK BRKG leakage current
20
µA
V
BRKG –VBRKS = 10 V
FAULT ALARM (nFAULT)
In normal operation, no fault
4
5
V
Internal pull-up impedance for normal operation
30
kΩ
Internal pull-down FET RDS(on) after fault
detected
125
1
Ω
External pull-down voltage threshold for IC
shutdown
V
tFAULT
External pul-ldown glitch filter
2
µs
µs
ms
Delay time of nFAULT pull-down below 1 V to
(VBRKG –VBRKS) < 1.5 V
td1_FAULT
td2_FAULT
5
3
Start-up fault detection duration
VUVLO > 2.6 V, VVCC > 9 V
THERMAL SHUTDOWN
TSD
Thermal shutdown
Thermal shutdown hysteresis
175
25
°C
°C
TSD-HYS
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) Typical values correspond to TJ = 25°C.
(3) Minimum and maximum limits apply over the –40°C to 125°C junction temperature range.
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
7.6 Typical Characteristics
VVIN = 48 V, VVCC = 10 V, VUVLO = 3.3 V, TJ = 25°C, unless otherwise stated.
20
15
10
5
18
16
14
12
10
8
œ40°C
25°C
70
150°C
œ40°C
25°C
150°C
0
6
0
10
20
30
40
50
60
Input Voltage (V)
80
90 100
4
6
8 10
VCCA Voltage (V)
12
14
VUVLO = 0 V
VUVLO = 0 V
图7-1. VIN Shutdown IQ
图7-2. VCCA Shutdown IQ
7.95
7.9
8.8
8.6
8.4
8.2
8
7.85
7.8
7.75
7.7
7.8
7.6
Falling
Rising
7.65
-50
-25
0
25
Junction Temperature (°C)
50
75
100
125
150
-50
-25
0
25
Junction Temperature (°C)
50
75
100
125
150
图7-3. VCCA Standby Current vs Temperature
图7-4. VCC UVLO Threshold vs Temperature
105
6
IOUT1 Gain
IOUT2 Gain
5.8
104
103
102
101
100
99
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
98
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
0
10
20
30
40
50
60
Current Sense Voltage (mV)
70
80
90 100
D001
ROSC = 40.2 kΩ
图7-5. Oscillator Frequency vs Temperature
图7-6. IOUT1 and IOUT2 Current Monitor Accuracy
vs VCS
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
100
80
60
40
20
0
50.75
50.5
50.25
50
49.75
49.5
49.25
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
0
1
2
3
Current Setting, VISETA (V)
4
5
VISETA = 2.5 V
图7-8. Regulated VCS Voltage vs Temperature
图7-7. Regulated VCS Voltage vs ISETA Voltage
600
280
500
400
300
200
278
276
274
272
100
IOUT1 (mA)
IOUT2 (mA)
IOUT1
IOUT2
0
270
-50
0
20
40 60
Current Sense Voltage (mV)
80
100
-25
0
25
50
75
Junction Temperature (°C)
100
125 150
D001
VCS = 50 mV
图7-9. IOUT1 and IOUT2 Current Monitor vs VCS
Voltage
图7-10. IOUT1 and IOUT2 Current Monitor vs
Temperature
25.2
25.1
25
1.19
1.188
1.186
1.184
1.182
1.18
24.9
24.8
24.7
24.6
24.5
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
图7-12. OVP Reference Voltage vs Temperature
图7-11. IPK Current Source vs Temperature
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
3.1
1.01
1.005
1
3.05
3
0.995
2.95
0.99
2.9
-50
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
-25
0
25
50
75
Junction Temperature (°C)
100
125
150
图7-14. OVPB Pullup Resistance vs Temperature
图7-13. OVPA Pullup Resistance vs Temperature
140
80
120
100
80
60
40
20
60
40
20
RDT = 25 kW
HO to LO
LO to HO
RDT = 7.5 kW
0
-50
0
-50
-25
0
25
Junction Temperature (°C)
50
75
100
125
150
-25
0
25
Junction Temperature (°C)
50
75
100
125 150
VDT = VVCC
FSW = 100 kΩ
图7-16. Adaptive Dead Time vs Temperature
图7-15. Programmed Dead Time vs Temperature
14
450
12
10
8
390
330
270
210
6
4
2
0
0
10
20
30
40
50
-50
-25
0
25
50
Junction Temperature (°C)
75
100
125
150
VVIN - VCS1B (V)
图7-17. [VBRKG –VBRKS] vs [VVIN –VBRKG] Voltage
图7-18. Circuit Breaker Gate Current vs
Temperature
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8 Detailed Description
8.1 Overview
The LM5170 is a high-performance, dual-channel bidirectional current controller intended to manage current
transfer between a Higher Voltage Port (HV-Port) and Lower Voltage Port (LV-Port). It integrates essential analog
functions that enable the design of high-power converters with a minimal number of external components. The
device regulates DC current in the direction designated by the DIR pin input signal. The current regulation level
is programmed by the analog signal applied at the ISETA pin or the digital PWM signal at the ISETD pin.
Independent enable signals activate each channel of the dual controller.
The dual-channel differential current sense amplifiers and dedicated channel current monitors achieve typical
accuracy of 1%. The robust 5-A half-bridge gate drivers are capable of controlling parallel MOSFET switches,
delivering 500 W or more per channel. The diode emulation mode of the buck or boost synchronous rectifiers
enables discontinuous mode operation for improved efficiency under light load conditions and prevents negative
current. Versatile protection features include:
• Cycle-by-cycle peak current limit
• Overvoltage protection of both 48-V and 12-V battery rails
• Detection and protection of MOSFET switch failures
• Overtemperature protection
The LM5170 uses average current mode control, simplifying compensation by eliminating the right-half plane
zero in boost operating mode and maintaining a constant loop gain regardless of the operating voltages and load
level. The free-running oscillator is adjustable up to 500 kHz and can be synchronized to an external clock within
±20% of the free running oscillator frequency. Stackable multiphase parallel operation is achieved by connecting
two LM5170 controllers in parallel for 3- or 4-phase operation. It can also be done by synchronizing multiple
LM5170 controllers to external multiphase clocks for a higher number of phases. The UVLO pin provides master
ON and OFF control that disables the LM5170 in a low-quiescent current shutdown state when the pin is held
low.
Definition of IC Operation Modes:
• Shutdown Mode: When the UVLO pin is < 1.25 V, VCC < 8 V, or nFAULT < 1.25 V, the LM5170 is in
shutdown mode with all gate drivers in the low state, all internal logic reset, and the VINX pin disconnected
from the VIN pin. When UVLO < 1.25 V, the IC draws < 20 µA through the VIN and VCC pins.
• Initialization Mode: When the UVLO pin is > 1.5 V but < 2.5 V, VCC > 8.5 V, and nFAULT > 2 V, the LM5170
establishes proper internal logic states and prepares for circuit operation.
• Standby Mode: When the UVLO pin is > 2.5 V, VCC > 8.5 V, and nFAULT > 2 V, the LM5170 first performs
fault detection for 2 to 3 ms. During this time, the external power MOSFETs are each checked for drain-to-
source short-circuit conditions. If a fault is detected, the LM5170 returns to shutdown mode and is latched in
shutdown until reset through the UVLO or VCC pins. If no failure is detected, the LM5170 is ready to operate.
The circuit breaker MOSFETs are turned on and the oscillator and ramp generators are activated, but the four
gate drive outputs remain off until the EN1 or EN2 initiate the power delivery mode.
• Power Delivery Mode: When the UVLO pin > 2.5 V, VCC > 8.5 V, nFAULT > 2 V, EN1 or EN2 > 2 V, DIR is
valid (> 2 V or < 1 V), and ISETA > 0 V, the SS capacitor is released and the LM5170 regulates the DC
current at the level set at the ISETA pin.
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.2 Functional Block Diagram
SYNCOUT
OPT
OSC
SYNCIN
VIN
3.125V
VIN
VINX
CLK1
CLK2
VCCA
OSCILLATOR AND
PHASE SPLITTER
2.5V
1.5V
BIAS
REGULATORS
SD
VINX
1.185V
25µA
VCCUV
ENABLE
+
-
UVLO
nFAULT
2.5V
1.5V
CONTROL
LOGIC
RESET
+
-
SD
300uA
DIR_GOOD
CIRCUIT
BREAKER
CONTROL
BRKG
BRKS
DIR
VALIDATION
DIR
12V
DIR
VIN
FLIP
DETECT
ISETA
ISET
SD
3.125V
25uA
SS1
100K
FAILURE
DETECT
SS
ISETD
SS2
DISABLE1
100K
FLIP
DETECT
OVER
TEMP
DIR
DEAD TIME
CONTROL
VDT
DT
SD
CSB1
DIR
3 MEG
0
OVP
VINX
1 MEG
-
-
OVPA
OVPB
IPK
+
+
1
1.185V
1.185V
VCC
8.5V
PK LIMIT
PROGRAM
25uA
+
-
VCC
VIPK
VCC_UV
COMMON CONTROL
AGND
PGND
DIR
CSB1
CH-1 CONTROL
100uA/V
25uA
CSB1
Gm=1 mA/V
IOUT1
+
-
-
+
ISET
SS1
CS AMP
A=50
CSA1
HB1
ERR AMP
1V
+
-
COMP1
RAMP1
-
+
VIPK
PEAK
LIMIT
PWM
COMP
CLK1
DISABLE1
VDT
PEAK
HOLD
ZERO
CROSS
DELAY
LOGIC
HO1
SW1
+
-
OVP
0.6V
LEVEL
SHIFT
DIR
ADPT
LOGIC
SD
EN1
CLK1
S
Q
VCC
1-D1
D1
DISABLE1
EN1
VDT
DISABLE1
DELAY
LOGIC
LO1
R
Q
DIR
CH-2 CONTROL
100uA/V
25uA
CSB2
Gm=1 mA/V
IOUT2
+
-
-
+
ISET
SS2
CS AMP
A=50
CSA2
HB2
ERR AMP
1V
+
-
COMP2
RAMP2
-
+
VIPK
PEAK
LIMIT
PWM
COMP
CLK2
DISABLE2
VDT
PEAK
HOLD
ZERO
CROSS
DELAY
LOGIC
HO2
SW2
+
-
OVP
SD
0.6V
LEVEL
SHIFT
DIR
ADPT
EN1
LOGIC
CLK2
S
Q
VCC
1-D2
D2
DISABLE2
VDT
DISABLE2
DELAY
LOGIC
EN2
LO2
R
Q
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.3 Feature Description
8.3.1 Bias Supply (VCC, VCCA)
The LM5170 requires an external bias supply of 9 V to 12 V at the VCC and VCCA pins to function. If an
external supply voltage is greater than 12 V, a 10-V LDO or switching regulator must be used to produce 10 V for
VCC and VCCA. 图 8-1 shows typical connections of the bias supply. The VCC voltage is directly fed to the low-
side MOSFET drivers. A 1-µF to 2.2-µF ceramic capacitor must be placed between the VCC and PGND pins to
bypass the driver switching currents. The VCCA pin serves as the bias supply input for the internal logic and
analog circuits for which the ground reference is the AGND pin. VCCA must be connected to VCC through a 25-
Ω to 50-Ω external resistor. A 0.1-µF to 1-µF bypass capacitor must be placed between the VCCA and AGND
pins to filter out possible switching noise.
The internal VCC undervoltage (UV) detection circuit monitors the VCC voltage. When the VCC voltage falls
below 8 V on the falling edge, the LM5170 is held in shutdown state. For normal operation, the VCC and VCCA
voltages must be greater than 8.5 V on a rising edge.
25 ꢀ
Ext > 12 Vdc
Ext
9~12 Vdc
Driver
10 V
LDO
VCCA
AGND
VCC
Analog
Circuit
VCC
UV
CVCCA
CVCC
PGND
图8-1. VCC Bias Supply Connections
8.3.2 Undervoltage Lockout (UVLO) and Master Enable or Disable
The UVLO pin serves as the master enable or disable pin. To use the UVLO pin to program undervoltage lockout
control for the HV-port, LV-port, or VCC rail, see 节8.5.2.
There are two UVLO voltage thresholds. When the pin voltage is externally pulled below 1.25 V, the LM5170 is
in shutdown mode, where the following occurs:
• All gate drivers are in the OFF state
• All internal logic resets
• The VINX pin is disconnected from the VIN pin
• The IC draws less than 20 µA through the VIN, VCC, and VCCA pins
When the VCC voltage is above the 8.5 V and the UVLO pin voltage is pulled higher than 1.5 V but lower than
2.5 V, the LM5170 is in initialization mode where the nFAULT pin is pulled up to approximately 5 V, but the rest of
the LM5170 remain off.
When the UVLO pin is pulled higher than 2.5 V, which is the UVLO release threshold and the master enable
threshold, the LM5170 starts the MOSFET failure detection in a period of 2 to 3 ms (see 节 8.3.16). If no failure
is detected, the BRKG pin starts to source a 330-µA current to charge the gates of the breaker MOSFETs.
When the BRKG to BRKS voltage is above 8.5 V, the LM5170 enters standby mode. In standby mode, the VINX
pin is internally connected to the VIN pin through an internal cutoff switch (see 图 8-2). Additionally, the internal
1-MΩ OVPB pullup resistor is connected to the CSB1 pin through another internal cutoff switch (see 图 8-18).
The oscillator and the RAMP1 and RAMP2 generators start to operate, the SYNCOUT pin starts to send clock
pulses at the oscillator frequency, and the LM5170 is ready to operate. The LO1, LO2, HO1, and HO2 drivers
remain off until the EN1, EN2, and DIR inputs command them to operate.
When a MOSFET gate-to-source short-circuit failure is detected, the LM5170 is latched off. The latch can only
be reset by pulling the VCC pin below 8 V or by pulling the UVLO pin below 1.25 V. For details, see 节8.3.16.
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.3.3 High Voltage Input (VIN, VINX)
图 8-2 shows the external and internal configuration for the VIN and VINX pins. Both are rated at 100 Vdc. The
VIN pin must be directly connected either to the voltage rail of the HV-Port, or through a small RC filter consisting
of 10- to 20-Ω resistor and 0.1-µF to 1-µF bypass capacitor. The VIN pin supplies the internal 330-µA current
source supplying the BRKG pin.
A cutoff switch connects and disconnects the VIN and VINX pins. When the UVLO pin voltage is greater than 2.5
V, and when the VCC voltage is greater than 8.5 V, the switch is closed and the VINX and VIN pins are
connected.
The VINX pin serves as the supply pin for the RAMP generators (see 图 8-2 and 节 8.3.9 for details). It is also
the high-side terminal of the internal 3-MegΩ pullup resistor for the OVPA pin (see 节 8.3.17 for details).
Moreover, it serves as the HV-Port voltage sense for internal circuit use during operation.
HV-Port (48 V)
VIN
VINX
VINX
3 Meg
RAMP1
RAMP2
OVPA
+
OVP
COMP
1.185 V
œ
AGND
图8-2. VIN and VINX Pins Configuration
8.3.4 Current Sense Amplifier
Each channel of the LM5170 has an independent bidirectional, high accuracy, and high-speed differential current
sense amplifier. The differential current sense polarity is determined by the DIR command. The amplifier gain is
50, so that a smaller current sense resistor can be used to reduce power dissipation. The amplified current
sense signal is used to perform the following functions:
• Applied to the inverting input of the error amplifier for current loop regulation
• Used to reconstruct the channel current monitor signal at the IOUT1 and IOUT2 pins
• Monitored by the cycle-by-cycle peak current limit comparator for instantaneous overcurrent protection
• Sensed by the current zero cross detector to operate the synchronous rectifiers in diode emulation mode
The current sense resistor Rcs must be selected for 50-mV current sense voltage when the channel DC current
reaches the rated level. The CS1A, CS1B, CS2A, and CS2B pins must be Kelvin connected for accurate
sensing.
It is very important that the current sense resistors are non-inductive. Otherwise, the sensed current signals are
distorted even if the parasitic inductance is only a few nH. Such inductance may not affect the current regulation
during continuous conduction mode, but it does affect current zero cross detection, hence the performance of
diode emulation mode under light load. As a consequence, the synchronous rectifier gate pulse is truncated
much earlier than the inductor current zero crossing. This causes the body diode of the synchronous rectifier to
conduct unnecessarily for a longer time. See 节8.3.15 for details.
If the selected current sense resistor has parasitic inductance. See 节 9.1 for methods to compensate for this
condition and achieve optimal performance.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.3.5 Control Commands
8.3.5.1 Channel Enable Commands (EN1, EN2)
These pins are two-state function pins. Always use CH-1 if only single-channel operation is required. Note that
CH-2 can only be enabled when CH-1 is also enabled.
1. When the EN1 pin voltage is pulled above 2 V (logic state of 1), the HO1 and LO1 outputs are enabled
through soft start.
2. When the EN1 pin voltage is pulled below 1 V (logic state of 0), CH-1 controller is disabled and both HO1
and LO1 outputs are turned off.
3. Similar behaviors for EN2, HO2, and LO2 of CH-2, except that the EN2 pin does not affect the SS pin. Refer
to 节8.3.10 for details.
4. When the EN1 and EN2 pins are left open, an internal 100-kΩ pulldown resistor sets them to the low state.
5. The built-in 2-µs glitch filters prevent errant operation due to the noise on the EN1 and EN2 signals.
8.3.5.2 Direction Command (DIR)
This pin is a triple function pin.
1. When the DIR pin is actively pulled above 2 V (logic state of 1), the LM5170 operates in buck mode, and
current flows from the HV-Port to the LV-Port.
2. When the DIR pin is actively pulled below 1 V (logic state of 0), the LM5170 operates in boost mode, and
current flows from the LV-Port to the HV-Port.
3. When the DIR pin is in the third state that is different from the previous two, it is considered an invalid
command and the LM5170 remains in standby mode regardless of the EN1 and EN2 states. This tri-state
function prevents faulty operation when losing the DIR signal connection to the MCU.
4. When DIR changes state between 1 and 0 dynamically during operation, the transition causes the SS pin to
discharge first to below 0.23 V. Then, the SS pin pulldown is released and the LM5170 goes through a new
soft-start process to produce the current in the new direction. This eliminates surge current during the
direction change.
5. The built-in 10-µs glitch filter prevents errant operation by noise on the DIR signal.
8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
The LM5170 accepts the current setting command in the form of either an analog voltage or a PWM signal. The
analog voltage uses the ISETA pin, and the PWM signal uses the ISETD pin. There is an internal ISETD
decoder that converts the PWM duty ratio at the ISETD pin to an analog voltage at the ISETA pin. Owing to
possible ground noise impact, TI recommends to remove EN1 signal to achieve no load (0 A).
图 8-3 and 图 8-4 show the pin configurations for current programming with an analog voltage or a PWM signal.
The channel DC current is expressed in terms of resulted differential current sense voltage VCS_dc. When ISETA
is used, the ISETD pin can be left open or connected to AGND. When ISETD is used, place ceramic capacitor
CISETA between the ISETA pin and AGND. CISETA and the internal 100 kΩ at the output of the ISETD decoder
forms a low-pass RC filter to attenuate the ripple voltage on ISETA. However, the RC filter delays the ISETD
dynamic change to be reflected on ISETA. To limit the delay to not exceed Tdelay_ISETD, the time constant of the
RC filter must satisfy 方程式1.
Tdelay_ISETD
100 kWìCISETA
Ç
4
(1)
Therefore, the maximum CISETA must be determined by 方程式2:
Tdelay_ISETD
CISETA
Ç
4ì100 kW
(2)
On the other hand, the time constant of the RC filter must be big enough for effective filtering. To attenuate the
ripple by 40 dB, the RC filter corner frequency must be at least two decade below FISETD, that is, 方程式3
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
1
Ç 0.01ìF
ISETD
2pì100 kWìCISETA
(3)
Therefore the minimum ISETD signal frequency must be determined by 方程式4:
1
400
F
í
í
ISETD
2pì1 kWìCISETA 2pì Tdelay_ISETD
(4)
For instance, if ISETA is required to settle down to the steady-state in 1 ms following an ISETD duty ratio step
change, namely Tdelay_ISETD < 1 ms, select CISETA < 2.5 nF, and FISETD > 64 kHz. If Tdelay_ISETD < 0.1 ms, then
CISETA < 250 pF and FISETD > 640 kHz. Note that the feedback loop property causes additional delay for the
actual current to settle to the new regulation level.
Current Level
Command
60.0
50.0
ISETA
+
ISETD
œ
AGND
0
2.5 3.0
0
ISETA (V)
图8-3. Pin Configurations for Current Setting Using an Analog Voltage Signal
Current Level
Command
62.5
50.0
ISETD
FISETD=1~1000 kHz
ISETA
AGND
CISETA
100 pF~100 nF
0
80% 100%
ISETD Duty (%)
0%
图8-4. Pin Configurations for Current Setting Using a PWM Signal
The ISETA pin is directly connected to the non-inverting input of the error amplifier. By ISETA programming, the
channel DC current is determined by 方程式5:
VCS dc = 0.02ì V
ISETA
(5)
Or by 方程式6:
VCS_dc_
I_channel_dc =
Rcs
(6)
(7)
Or by 方程式7:
I_channel_dc =
where
0.02ì V
Rcs
ISETA
• Rcs is the channel current sensing resistor value
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
When using ISETD, the produced VISETA by the internal decoder is equal to the product of the effective duty ratio
of the ISETD PWM signal (DISETD) and the 3.125-V internal reference voltage. The channel current is
determined by 方程式8:
IV
= 3.125 V ìDISETD
ISETA
(8)
Or by 方程式9:
VCS dc = 0.0625 VìDISETD
(9)
Or by 方程式10:
I_channel_dc =
0.0625 V ìDISETD
Rcs
(10)
8.3.6 Channel Current Monitor (IOUT1, IOUT2)
The LM5170 monitors the real time inductor current in each channel at the IOUT1 and IOUT2 pins. The channel
current is converted to a small current source scaled by the factors seen in 方程式11 and 方程式12:
VCSI
IOUT1=
IOUT2 =
+ 25 mA
+ 25 mA
200 W
(11)
(12)
VCS2
200 W
where
• VCS1 and VCS2 are the real time current sense voltage of CH-1 and CH-2, respectively
• 25 µA is a DC offset current superimposed on to the IOUT signals (refer to 图8-5)
The DC offset current is introduced to raise the no-load signal above the possible ground noise floor. Since the
monitor signal is in the form of current, an accurate reading can be obtained across a termination resistor even if
the resistor is located far from the LM5170 but close to the MCU, thus rejecting potential ground differences
between the LM5170 and the MCU. 图 8-6 shows a typical channel current monitor through a 9.09-KΩ
termination resistor and a 10-nF to 100-nF ceramic capacitor in parallel. The RC network converts the current
monitor signal into a DC voltage proportional to the channel DC current. For example, when the current sense
voltage DC component is 50 mVdc, namely VCS_dc = 50 mV, the termination RC network produces a DC voltage
of 2.5 V. Note that the maximum IOUT pin voltage is internally clamped to approximately 4 V.
275
25
0
50
0
V_CS (mV)
图8-5. Channel Monitor Current Source Versus Current Sense Voltage
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
To MCU
Monitor
IOUT2
IOUT1
10 ~100 nF
9.09 k
9.09 k
10 ~100 nF
AGND
Ground
Impedance
图8-6. Channel Current Monitor
8.3.7 Cycle-by-Cycle Peak Current Limit (IPK)
The internal 25-µA current source and a single external resistor RIPK establish a voltage at the IPK pin to
program the cycle-by-cycle current limit threshold. To set the inductor peak current limit value to IPK, RIPK must
satisfy 方程式13:
RcsìIPK
1.1mA
RIPK
=
(13)
IPK must be greater than the inductor peak current at full load, and lower than the rated saturation current of the
inductor, Isat
.
When the IPK pin voltage is greater than 4.5 V, either from a very large RIPK value or the pin being open or some
other reason, an internal monitor circuit shuts down the switching. This prevents the LM5170 from operating with
erroneous peak current limit threshold.
8.3.8 Error Amplifier
Each channel of the LM5170 has an independent gm error amplifier. The output of the error amplifier is
connected to the COMP pin, allowing the loop compensation network to be applied between the COMP pins and
AGND.
The LM5170 control loop is the inner current loop of the bidirectional converter system, of which the outer
voltage loop can either be controlled by an MCU, a DSP, an FPGA, and so forth, or by an analog circuit. Since
the LM5170 employs the averaged current mode control scheme, the inner loop is basically a first order system.
As seen in 图8-7, a Type-II compensation network consisting of RCOMP, CCOMP, and CHF is adequate to stabilize
the LM5170 inner current loop. Refer to 节9.1 for details of the compensation network selection criteria.
8.3.9 Ramp Generator
Refer to 图8-7 for the following:
• Circuit block diagram for the ramp generator
• gm error amplifier
• PWM comparator
• Soft-start control circuit
The VINX pin serves as the supply pin for the ramp generator. Each ramp generator consists of an external RC
circuit (RRAMP and CRAMP) and an internal pulldown switch controlled by the clock signal.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
HV-Port (48 V)
VIN
Shutdown
VINX
RRAMP1
RAMP1
CLK1
CRAMP1
œ
PWM
1 V
To Driver Logic
COMP1
+
RCOMP1
25 µA
Gm AMP
SS
From Current
Sense Amp
CHF1
œ
CCOMP1
Gm
CSS
ISET
+
AGND
COMP2
RRAMP2
To CH2 PWM
CLK2
RAMP2
CRAMP2
图8-7. Error Amplifier, Ramp Generator, Soft Start, and PWM Comparator
When the LM5170 is enabled, CRAMP1/2 is charged by the VINX pin through RRAMP1/2 at the beginning of each
switching cycle. The internal pulldown FET discharges CRAMP1/2 at the end of the cycle within a 200-ns internal.
Then the pulldown is released, and CRAMP1/2 repeats the charging and discharging cycles. In general, the RAMP
RC time constant is much greater than the period of a switching cycle. Therefore, the RAMP pin voltages are
sawtooth signals with a slope proportional to the HV-Port voltage. This way, the RAMP signals convey the line
voltage info. Being directly used by the PWM comparators to determine the instantaneous switching duty cycles,
the RAMP signals fulfill the line voltage feedforward function and enable the LM5170 to have a fast response to
line transients.
Note
TI recommends you to select appropriate RRAMP and CRAMP values by the following equation such that
the RAMP pins reach the peak value of approximately 5 V each cycle when VIN is at 48 V.
9.6
RRAMP
=
F
sw ìCRAMP
(14)
For instance, if Fsw = 100 kHz and CRAMP1 = CRAMP2 = 1 nF, a resistor of approximately 96 kΩmust be selected
for RRAMP1 and RRAMP2
.
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Because CRAMP1/2 must be fully discharged every cycle through the 15-Ω channel resistor of the pulldown FET
within the 150-ns minimum discharging interval, CRAMP1/2 must be limited to be less than 2.5 nF nominal at room
temperature.
There is also a valid RAMP signal detection circuit for each channel to prevent the channel from errantly running
into the maximum duty cycle if RAMP goes away. It detects the peak voltage of the RAMP signal. If the peak
voltage is less than 0.6 V in consecutive cycles, it is considered an invalid RAMP and the channel stops
switching by turning both HO and LO off until the RAMP signal recovers. This 0.6-V voltage threshold defines the
minimum operating voltage of the HV-Port to be approximately 5.76 V.
8.3.10 Soft Start
The soft-start feature helps the converter to gradually reach the steady-state operating point, thus reducing start-
up stresses and surge currents. With the LM5170, there are two ways to implement the soft start.
8.3.10.1 Soft-Start Control by the SS Pin
Place a ceramic capacitor CSS between the SS pin and AGND to program the soft-start time. When the EN1
voltage is < 1 V, an internal pulldown switch holds the SS pin at AGND. When the EN1 pin voltage is > 2 V, the
SS pulldown is released, and CSS is charged up slowly by the internal 25-µA current source. See 图 8-7. The
slow ramping SS voltage clamps the COMP1 and COMP2 pins through two separate clamp circuits. Once the
SS voltage exceeds the 1-V offset voltage, the PWM duty cycle starts to increase gradually from zero.
When EN1 is pulled below 1 V, CSS is discharged by the internal pulldown FET. Once this pulldown FET is
turned on, it remains on until the SS voltage falls below 0.23 V, which is the threshold voltage indicating the
completion of SS discharge.
Note that the EN2 pin does not affect the SS pin. When EN1 and EN2 are enabled together, the CH-2 output
follows CH-1 by going through the same soft-start process. If EN2 is enabled at a later time and CH-1 has
already completed soft start, CH-2 is not affected by the SS pin. This allows the CH-2 current to ramp up quickly
to supply the increased load current. However, when SS is pulled low, both CH-1 and CH-2 are affected at the
same time.
8.3.10.2 Soft Start by MCU Through the ISET Pin
The MCU can control the soft start by gradually ramping up the ISETA voltage or the ISETD PWM duty ratio,
whichever is applicable. When ISETA or ISETD is used to control the soft start, CSS must be properly selected to
a value such that it does not interfere with the ISETA/D soft start.
8.3.10.3 The SS Pin as the Restart Timer
The SS pin also fulfills the function of a restart timer in an OVP event or following a DIR command change:
1. Restart timer in OVP: When OVPA or OVPB catches an overvoltage event (refer to 节8.3.17), CSS is
discharged immediately by the internal pulldown FET. This FET remains ON as long as the overvoltage
condition persists. When the overvoltage condition is removed and after the SS voltage is discharged to
below 0.23 V, the SS pulldown is released, setting off a new soft-start cycle. The circuit can run in retry or
hiccup mode if the overvoltage condition reappears. The retry frequency is determined by the SS capacitor
as well as the nature of the overvoltage condition.
2. Restart timer: When DIR dynamically flips its state from 0 to 1, or 1 to 0 during operation, CSS is first
discharged to 0.23 V by the internal pulldown FET. Then, the pulldown is released to set off a new soft-start
cycle to gradually build up the channel current in the new direction. In this way, the channel current
overshoot is eliminated.
8.3.11 Gate Drive Outputs, Dead Time Programming, and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
Each channel of the LM5170 has a robust 5-A (peak) half bridge driver to drive external N-channel power
MOSFETs. As shown in 图 8-8, the low-side drive is directly powered by VCC, and the high-side driver by the
bootstrap capacitor CBT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and CBT
is charged by VCC through the boot diode DBT. TI recommends selecting a 0.1-µF or larger ceramic capacitor
for CBT, and an ultra-fast diode of 1 A and 100-V ratings for DBT. TI also strongly recommends you add a 2-Ωto
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
5-Ω resistor (RBT) in series with DBT to limit the surge charging current and improve the noise immunity of the
high-side driver.
DBT
RBT
2 Ω
HB
VCC
CBT
HO
Driver
SW
External
10-V Supply
VCCA
AGND
Internal
Logic
Circuit
LO
Driver
PGND
图8-8. Bootstrap Circuit for High-Side Bias Supply
During start-up in buck mode, CBT may not be charged initially. The LM5170 then holds off the high-side driver
outputs (HO1 and HO2) and sends LO pulses of 200-ns width in consecutive cycles to pre-charge CBT. When
the boot voltage is greater than the 6.5-V boot UV threshold, the high-side drivers output PWM signals at the
HO1 and HO2 pins for normal switching action.
During start-up in boost mode, CBT is naturally charged by the normal turnon of the low-side MOSFET, therefore,
there is no such 200-ns pre-charge pulse at the LO pins.
To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two
types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive
dead time.
To program dead time, place a resistor RDT across the DT and AGND pins as shown in 图8-9.
The dead time tDT as depicted in 图8-10 is determined by 方程式15:
ns
tDT = RDT ì 4
+16 ns
kW
(15)
Note that this equation is valid for programming tDT between 20 ns and 250 ns. When the power MOSFET is
connected to the gate drive, its gate input capacitance CISS becomes a load of the gate drive output. Additionally,
the HO and LO slew rate are reduced, leading to a reduced effective tDT between the high- and low-side
MOSFETs. Evaluate the effective tDT to make sure it is adequate to prevent shoot-through between the high- and
low-side MOSFETs.
When the DT programmability is not used, simply connect the DT pin to VCC as shown in 图 8-11 to activate the
built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of the output of a
driver (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in 图 8-11
and 图 8-12. Only when the output voltage of the driver falls below 1.25 V, the other driver starts turnon. The
effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the
gate drive have excessive impedance due to poor layout design.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
HV-Port (48 V)
DBT1/2
RBT1/2
VCC
HB1/2
CBT1/2
HO1/2
SW1/2
DLY
Logic
Driver
Adapt Logic
Level Shift
Level
Shift
FROM
PWM
VCC
LO1/2
DLY
Logic
Driver
DT
PGND
AGND
RDT
图8-9. Dead Time Programming With DT Pin (Only One Channel is Shown)
HO
tDT
tDT
LO
图8-10. Gate Drive Dead Time (Only One Channel is Shown)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
HV-Port (48 V)
DBT1/2
RBT1/2
VCC
HB1/2
CBT1/2
HO1/2
SW1/2
DLY
Logic
Driver
Adapt Logic
Level Shift
Level
Shift
FROM
PWM
VCC
LO1/2
DLY
Logic
Driver
AGND
DT
PGND
图8-11. Dead Time Programming With DT Pin (Only One Channel is Shown)
1.5 V
HO
Adaptive
tDT
LO
1.5 V
图8-12. Adaptive Dead Time (Only One Channel is Shown)
8.3.12 PWM Comparator
Each channel of the LM5170 has a pulse width modulator (PWM) employing a high-speed comparator. It
compares the RAMP pin signal and the COMP pin signal to produce the PWM duty cycle. Note that the COMP
signal passes through a 1-V DC offset before it is applied to the PWM comparator, as shown in 图 8-7. Due to
this DC offset, the duty cycle can reduce to zero when the COMP pin or SS pin is pulled lower than 1 V. The
maximum duty cycle is limited by the 200-ns minimum off-time. Note that the programmed dead time can reduce
the maximum duty cycle because it is additional to the minimum off-time. Therefore, the available maximum duty
cycle, for both buck and boost mode operation, is determined by 方程式16.
DMAX = 1- (200 ns + tDT )ìFsw
(16)
where
• tDT is the dead time given by (15) or the adaptive dead time, whichever is applicable
This maximum duty cycle limits the minimum voltage step-down ratio in buck mode operation and the maximum
step-up ratio in boost mode operation.
Note that the maximum COMP voltage is clamped at approximately 1.5 V higher than the RAMP peak voltage.
This prevents the COMP voltage from moving too far above the RAMP voltage which can cause longer recovery
time during a large scale upward step load response.
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.3.13 Oscillator (OSC)
The LM5170 oscillator frequency is set by the external resistor ROSC connected between the OSC pin and
AGND, as shown in 图 8-13. The OSC pin must never be left open whether or not an external clock is present.
To set a desired oscillator frequency FOSC, ROSC is approximately determined by 方程式17:
40 kW ì100 kHz
FOSC
ROSC
=
(17)
ROSC must be placed as close as possible to the OSC and AGND pins. Take the tolerance of the external
resistor and the frequency tolerance indicated in the Electrical Characteristics into account when determining the
worst case operating frequency.
The LM5170 also includes a Phase-Locked Loop (PLL) circuit to manage multiphase interleaving phase angle
and synchronization to the external clock applied at the SYNCIN pin. When no external clock is present, the
converter operates at the oscillator frequency given by 方程式 17. If an external clock signal of a frequency
within ± 20% of FSW is applied (see 节 8.3.14), the converter switches at the frequency of the external clock
FEX_CLK, namely 方程式18:
FOSC
(in Standalone)
À
Œ
FSW
=
Ã
F
(in Synchronization)
EX_CLK
Œ
Õ
(18)
Two internal clock signals CLK1 and CLK2 are produced to control the interleaving operation of CH-1 and CH-2,
respectively. The third clock signal is output at the SYNCOUT pin. All these three clock signals run at the same
frequency of FSW. The phase angles among these three clock signals are controlled by the state of the OPT pin.
See 节8.4.1 for details.
SYNCIN
CLK1
SYNCOUT
SYNCOUT
CLK2
10 k
CLK1
OSC
OSC and
Phase Splitter
CLK2
ENABLE
AGND
OPT
Interleaving
Control
图8-13. Oscillator and Interleaving Clock Programming
8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
The LM5170 can synchronize to an external clock if FEX_CLK is within ±20% of FOSC. The SYNCIN clock pulse
width must be between 100 ns to 500 ns, with a high voltage level > 2 V and low voltage level < 1 V.
FEX_CLK can be adjusted dynamically. However, the LM5170 PLL takes approximately 500 µs to settle down to
the newly asserted frequency. During the PLL transient, the instantaneous FSW can temporarily drop by 25%. To
avoid overstress during the transient, TI recommends you reduce the load current to less than 50% by lowering
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
the ISETA voltage or ISETD duty, or simply turn off the dual-channels by setting EN1 = EN2 = 0 when making an
the external clock change.
8.3.15 Diode Emulation
The LM5170 has a built-in diode emulation function. Each channel has a real time current zero crossing detector
to monitor instantaneous VCS. When VCS is detected to cross zero, the LM5170 turns off the gate drive of the
synchronous rectifier to prevent negative current. This way, the negative current is prevented and the light load
efficiency is improved. 图8-14 shows key waveforms of a typical operation transiting into diode emulation mode.
CLK
Main FET
Turn-ON
Sync FET
Turn-ON
Diode Emulation
Inductor
Current
0 A
图8-14. Diode Emulation Operation
To obtain optimal diode emulation performance, it requires the VCS signal to be accurate in real time. Any signal
distortion caused by parasitic inductances in the current sense resistor or sensing traces can lead to erroneous
zero crossing detection and cause non-optimal diode emulation operation. The sync FET can be turned off while
the current is still high in the positive direction. See 节 9.1 for coping with current sense parasitic inductances for
optimal diode emulation operation.
8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
The LM5170 includes a circuit to detect a MOSFET switch short-circuit failure during start-up. If a MOSFET drain
and source are found shorted, the LM5170 pulls down the nFAULT pin to flag the fault, and the controller
remains in an OFF state. This feature prevents the LM5170 from starting with a short-circuit-failed MOSFET,
thereby preventing catastrophic failures.
The LM5170 also integrates a control circuit to control the circuit breaker. As shown in 图 8-15, the circuit
breaker consists of a pair of back-to-back MOSFETs. When the breaker is off, the current path between the HV-
Port and LV-Port is cut-off so as to prevent possible catastrophic failures.
Note
The failure detection function must be deactivated if the circuit breaker is not present, or if the circuit
breaker FETs are not controlled by the LM5170.
8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
Depending on application preference, the failure detection function can be activated or deactivated by the
SYNCOUT pin. During start-up, the LM5170 first detects the external resistor attached to the SYNCOUT pin. To
enable the failure detection function, do not place resistor between the SYNCOUT and AGND pins (refer to 图
8-15 or 图8-16).
To disable the failure detection function, place a 10-kΩ resistor between the SYNCOUT and AGND pins, as
shown in 图8-17, and the LM5170 skips the 2- to 3-ms interval of MOSFET failure detection. Instead, it activates
standby mode in approximately 300 µs after VCC is above 8.5 V and UVLO is greater than 2.5 V. If the circuit
breaker is not present or not controlled by the LM5170, do not leave the BRKG and BRKS pins floating, but
terminate the BRKG and BRKS pins with 20-kΩ resistors as shown in 图8-17.
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.3.16.2 Nominal Circuit Breaker Function
If the failure detection function is enabled, which also implies the circuit breaker being controlled by the LM5170,
the LM5170 performs a MOSFET failure detection during start-up. The detection starts after the UVLO is pulled
higher than 2.5 V and VCC above 8.5 V. The detection operation lasts for 2 to 3 ms. During the detection, the
LM5170 checks the high-side and low-side MOSFETs of both channels as well as the circuit breaker MOSFETs
to see if any of them has drain-to-source shorted. If no failure is detected, a 330-µA current source at the BRKG
pin is turned on to charge up the breaker MOSFET gates. When the BRKG to BRKS voltage rises above 8.5 V,
the LM5170 enters standby mode, waiting for the EN1 and EN2 commands to operate in power delivery mode.
The voltage across BRKG and BRKS is internally clamped to 12 V, preventing overvoltage stress on the breaker
MOSFET gates.
If a failure of any MOSFET is detected, the LM5170 immediately pulls the nFAULT pin low, and keeps the
LM5170 in a latched shutdown mode, thereby preventing catastrophic failure.
The nFAULT pin can also be externally pulled low during normal operation and the LM5170 immediately turns off
the circuit breaker and stays in a latched shutdown. There is a 2-µs glitch filter at the nFAULT pin to prevent
errant shutdown by possible noises at the nFAULT pin.
To release the nFAULT shutdown latch, it requires the UVLO pin to be externally forced below 1.25 V, or VCC is
below 8 V.
图 8-15 and 图 8-16 show two ways to use the circuit breaker function. A TVS is recommended to prevent surge
voltage when the circuit breaker is turned off during operation.
The BRKG 330-µA current source is powered by the VIN pin or the HV-Port. Therefore, the differential voltage
between the HV-Port and LV-Port must be greater than 10 V to ensure that BRKG to BRKS voltage can establish
> 8.5 V and allow the LM5170 to enter power delivery mode. The BRKG to BRKS voltage is internally clamped
to 12 V if the differential voltage of the two ports is greater.
The load dump transient at the LV-Port can raise the rail voltage and reduce the differential voltage of the two
ports to below 10 V. To maintain the circuit breaker to be closed during the transient, TI recommends adding a 1-
nF to 10-nF capacitor across BRKG and BRKS to hold the gate voltage during the transient.
Note that the BRKG 330-µA current source always turns on once the LM5170 starts up. If failure detection mode
is deactivated, the LM5170 also skips checking the BRKG to BRKS voltage condition. Therefore, the circuit
breaker can still be controlled by the LM5170 even if the failure detection is deactivated. If the steady-state
differential voltage between the HV-Port and LV-Port is less than 10 V during power up, TI does not recommend
you activate the failure detection function. Also, if the differential voltage is less than 8 V, TI recommends not to
use the circuit breaker function of the LM5170 at all.
HV-Port
LV-Port
Lm
Rcs
VIN
HO
SW
LO
BRKG BRKS
nFAULT
CSA
CSB
To MCU or
System
Monitor
SYNCOUT
OPEN
图8-15. Controlling Dual-Channel Circuit Breaker for MOSFET Failure Protection
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
HV-Port
LV-Port
Rcs
Lm
GND
To SYNCIN of
The Next
Controller
VIN
HO SW
LO
CSA
CSB
BRKG
SYNCOUT
BRKS
OPEN
To MCU or
System
Monitor
nFAULT
图8-16. Controlling System Level Circuit Breaker for MOSFET Failure Protection
HV-Port
LV-Port
Lm
Rcs
20 k
20 k
VIN
HO
SW
LO
BRKG BRKS
nFAULT
CSA
CSB
From MCU
or System
Monitor
SYNCOUT
10 k
图8-17. Circuit Breaker Function Disabled
8.3.17 Overvoltage Protection (OVPA, OVPB)
As shown in 图 8-18 and 图 8-19, the LM5170 includes the overvoltage protection function for both HV-Port and
LV-Port. Use the OVPA pin for the HV-Port protection, and the OVPB pin for the LV-Port protection. Note that the
OVPB protection function is disabled during boost operation mode, while the OVPA function is always enabled in
both buck or boost operation modes.
8.3.17.1 HV-V- Port OVP (OVPA)
A dedicated comparator monitors the HV-Port voltage through a resistor divider. The divider consists of an
internal 3-MegΩ pullup resistor between the VINX and OVPA pins, and an external pulldown resistor between
the OVPA pin and AGND. When the OVPA pin voltage exceeds the 1.185-V threshold, both HOs and LOs are
turned off. At the same time, CSS is discharged, preparing for the restart through soft start when the OV alarm is
removed. See 节8.3.10 for details.
8.3.17.2 LV-Port OVP (OVPB)
A dedicated comparator monitors the LV-Port voltage through a resistor divider. The divider consists of the
internal 1-MegΩ pullup resistor between the CSB1 and OVPB pins, and an external pulldown resistor between
the OVPB pin and AGND. When the OVPB pin voltage exceeds the 1.185-V threshold, both HOs and LOs are
turned off. At the same time the SS capacitor is discharged, preparing to restart through soft start when the OV
alarm is removed. See 节8.3.10 for details.
Note the hysteresis voltage of both OVPA and OVPB comparators is approximately 100 mV. There are 5-µs
built-in glitch filters for both OVPA and OVPB comparators. In addition, a small capacitor can be considered to
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
place from the OVP pins to AGND. All of these help prevent errant operation by possible noises on the OVPA
and OVPB signals.
HV-Port (48 V)
LV-Port (12 V)
Converter Stage
CSA1
CSB1
VIN
20 k
BRKG
BRKS
20 k
Current
Sense
VINX
To Ramp
Generator
3 Meg
DIR
0
1
OVPA
1 Meg
HV Sense,
To MCU
+
+
OVP
OVPB
ROVPB
LV Sense,
To MCU
ROVPA
COMP
COMP
COVPA
AGND
COVPB
1.185 V
1.185 V
œ
œ
SYNCOUT
10 k
SS
SS
CSS
图8-18. Overvoltage Protection: When Circuit Breaker Function is Not Used
HV-Port
LV-Port
Converter Stage
CSA1
CSB1
VIN
BRKG
BRKS
Current
Sense
VINX
To Ramp
Generator
3 Meg
OVPA
1 Meg
HV Sense,
To MCU
+
+
OVP
OVPB
ROVPB
LV Sense,
To MCU
1
ROVPA
COMP
COMP
COVPA
AGND
COVPB
1.185 V
1.185 V
œ
œ
SYNCOUT
Open
SS
SS
CSS
图8-19. Overvoltage Protection: When Circuit Breaker Function is Used
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.4 Device Functional Modes
8.4.1 Multiphase Configurations (SYNCOUT, OPT)
There are various options to make multiphase configurations.
8.4.1.1 Multiphase in Star Configuration
Each LM5170 synchronizes to an external clock, and the clock signals should have appropriate phase delays
among them for proper multiphase interleaving operation. The interleave angle between the two phases of each
LM5170 can be programmed to 180° or 240° by the OPT pin. 表 8-1 summarizes the settings of the external
clocks and the OPT pin state for multiphase configurations.
表8-1. Multiphase Configurations With Individual External Clock
PHASE SHIFT
BETWEEN EXTERNAL
CLOCKS FOR
NUMBER OF LM5170
CONTROLLERS
NEEDED
NUMBER
OF PHASES
OPT LOGIC
STATE(1)
CH-2 PHASE
LAGGING VS CH-1
NUMBER OF EXTERNAL
CLOCKS NEEDED
MULTIPHASE
INTERLEAVING
2
3
180°
120°
1
0
1
1
1
1
180°
240°
180°
180°
180°
180°
1
2
2
3
4
N
1 or 0
2
2
3
4
N
4
90°
6
60° or 120°
45°
8
2xN
(180° / N)
(1) OPT State = 0 when the pin connects to AGND, and 1 when the pin voltage is > 2.5 V.
EN1 EN2
VCCA
EN1 EN2
VCCA
OPT
0 Deg
SYNCIN
120 Deg
SYNCOUT
SYNCIN
OPT
240 Deg
SYNCOUT
U1
U2
DIR
OSC
OSC
DIR
ISETD
AGND
AGND
ISETD
MCU
EN1 EN2
SYNCIN
VCCA
OPT
SYNCOUT
U3
DIR
OSC
ISETD
AGND
图8-20. Example of Six Phase Star Configuration
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
This can be used to achieve 1, 2, 3, or 4 phases without using an external clock. 表 8-2 summarizes the OPT
settings for the daisy-chain multiphase configurations. 图8-21 shows the daisy-chain connections for multiphase
configurations.
表8-2. Multiphase Configurations With Built-In Daisy-Chain Master-Slave Configuration
NUMBER OF LM5170
CONTROLLERS
NEEDED
NUMBER
OF PHASES
CH-2 PHASE
LAGGING VS CH-1 LAGGING VS CH-1
SYNCOUT PHASE
NUMBER OF EXTERNAL
CLOCKS NEEDED
OPT LOGIC STATE(1)
2
3
4
1
0
1
180°
240°
180°
90°
120°
90°
1
2
2
0 or 1
0 or 1
0 or 1
(1) OPT State = 0 when the pin connects to AGND, and 1 when the pin voltage is > 2.5 V.
MCU
EN1 EN2
SYNCIN
EN1 EN2
SYNCIN
VCCA
OPT
VCCA
OPT
SYNCOUT
AGND
OSC
SYNCOUT
AGND
OSC
U1
U2
OPT=“1" 90 Degree Phase Delay
OPT=“0" 120 Degree Phase Delay
图8-21. Three or Four Phases Interchangeable Configuration
8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
To configure 6 or 8 phases, it requires two daisy chains shown in 图 8-22 through 图 8-25. Note that two phase-
shifted external clock signals are required for proper interleaving operation. When external clock signals are not
available, the 6-phase can be configured in 120° interleaving, and 8-phase in 90° interleaving by daisy chain
(refer to 图8-23 and 图8-25), in which two phases of the system are synchronized in phase.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
EN1 EN2
EN1 EN2
SYNCIN
VCCA
OPT
VCCA
OPT
0 Deg
SYNCIN
SYNCOUT
OSC
SYNCOUT
AGND
OSC
AGND
U1
U2
MCU
120 Degree Phase Delay
Channel
U1-CH1
U3-CH2
U2-CH1
U3-CH1
U1-CH2
U2-CH2
Phase Angle
0 deg
60 (420) deg
120 deg
180 deg
EN1 EN2
VCCA
SYNCIN
OPT
OSC
240 deg
300 deg
SYNCOUT
AGND
U3
图8-22. Six Phases 60° Interleaving Configuration
EN1 EN2
SYNCIN
EN1 EN2
SYNCIN
VCCA
OPT
VCCA
OPT
0 Deg
OSC
SYNCOUT
AGND
OSC
SYNCOUT
AGND
U1
U2
MCU
120 Degree Phase Delay
Channel
U1-CH1
U2-CH1
U3-CH1
U1-CH2
U2-CH2
U3-CH2
Phase Angle
0 deg
120 deg
240 deg
240 deg
0 deg
EN1 EN2
VCCA
SYNCIN
OPT
OSC
SYNCOUT
120 deg
AGND
U3
图8-23. Six Phases 120° Interleaving Configuration
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
EN1 EN2
SYNCIN
EN1 EN2
VCCA
VCCA
OPT
0 Deg
SYNCIN
OPT
OSC
OSC
SYNCOUT
SYNCOUT
AGND
AGND
U1
U2
MCU
90 Degree Phase Delay
EN1 EN2
VCCA
EN1 EN2
VCCA
OPT
SYNCIN
OPT
OSC
SYNCIN
SYNCOUT
SYNCOUT
AGND
OSC
AGND
U3
135 Degree Phase Delay
图8-24. Eight Phases 45° Interleaving Configuration
EN1 EN2
SYNCIN
EN1 EN2
SYNCIN
VCCA
OPT
VCCA
OPT
0 Deg
OSC
SYNCOUT
AGND
OSC
SYNCOUT
AGND
U1
U2
MCU
90 Degree Phase Delay
EN1 EN2
VCCA
EN1 EN2
SYNCIN
VCCA
OPT
SYNCIN
OPT
OSC
SYNCOUT
SYNCOUT
AGND
OSC
AGND
U3
U4
270 Degree Phase Delay
图8-25. Eight Phases 90° Interleaving Configuration
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
8.4.2 Multiphase Total Current Monitoring
To minimize the number to signal lines, multichannel monitors can be combined into a total current monitor. 图
8-26 shows an example of total current monitor of a three phase system in which the unused fourth phase
monitor (U2-IOUT2) is grounded.
IOUT1
IOUT2
U2
AGND
3-Phase
Total Current
Monitor
IOUT1
No Load : 0.23 V
Max Load : 2.48 V
IOUT2
10 ~ 100 n
F
3.01 kΩ
U1
AGND
MCU Local
GND
Ground
Impedance
图8-26. 3-Phase Total Current Monitor
8.5 Programming
8.5.1 Dynamic Dead Time Adjustment
In addition to a fixed dead time programming by RDT, the dead time can be dynamically adjusted either by
applying an analog voltage or a PWM signal as shown in 图 8-27. Varying the analog voltage or the duty ratio of
the PWM signal will adjust the DT programming. For analog adjustment, a single stage RC filter is recommended
to filter out any possible noise. For PWM adjustment, a two-stage RC filter is recommended to minimize the
ripple voltage resulted on the DT pin.
RADJ2
10 k
RADJ1
10 k
DT Adjust by
Analog Voltage
DT
VADJ
CADJ1
0.1 µF
AGND
RDT
Time
(a) Adjustment by Analog Voltage
RADJ3
4.99 k
RADJ2
4.99 k
RADJ1
10 k
DT Adjust by
PWM
DT
VHI
CADJ2
0.1 µF
CADJ1
0.1 µF
VLO
AGND
RDT
DADJ
FADJ=10~100 kHz
(b) Dynamic Dead Time Adjustment
图8-27. Dynamic Dead Time Adjustment
When an analog voltage is applied, the resulted dead time is determined by 方程式19:
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
-1
≈
∆
«
’
÷
0.8ì VADJ
RDT RADJ1 +RAJD2 RADJ1 +RADJ2 ◊
1
1
ns
tDT(VADJ) =
+
-
ì 4
+16 ns
kW
(19)
where
• VADJ is the analog voltage used to adjust the dead time
When a PWM signal is applied, the resulted dead time is determined by 方程式20:
-1
≈
’
0.8ì » VHI - VLO ìDADJ + VLO
ÿ
(
)
1
1
ns
⁄
∆
∆
«
÷
÷
◊
tDT(DADJ) =
+
-
ì 4
+16 ns
RDT RADJ1 + RAJD2 + RAJD3
RADJ1 + RADJ2 + RADJ3
kW
(20)
where
• VHI and VLO are the high and low voltage levels of the PWM signal, respectively,
• DADJ is the duty factor of the PWM signal.
8.5.2 Optional UVLO Programming
The UVLO pin is the master enable pin of the LM5170. It can be directly controlled by an external control unit like
an MCU.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Nevertheless, the UVLO pin can also fulfill the undervoltage lockout function of a particular power rail. The rail
can be either the HV-Port, the LV-Port, or VCC. Use a resistor divider to set the UVLO threshold, as shown in 图
8-28. The divider must satisfy 方程式21:
RUVLO2
ì VUVLO = 2.5 V
RUVLO1 + RUVLO2
(21)
The UVLO hysteresis is accomplished with an internal 25-μA current source. When UVLO > 2.5 V, the current
source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the
2.5-V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO
hysteresis is determined by 方程式22:
VHYS = RUVLO1 ì 25 mA
(22)
An optional ceramic capacitor CUVLO can be placed in parallel with RUVLO2 to improve the noise immunity. CUVLO
is usually between 1 nF to 10 nF. Large CUVLO can cause excessive delay to respond to a real UVLO event.
If 方程式 22 does not provide adequate hysteresis voltage, you can add RUVLO3 as shown in 图 8-29. The
hysteresis voltage is thus given by 方程式23:
»
ÿ
Ÿ
≈
’
÷
RUVLO1
VHYS = RUVLO1 + RUVLO3 ì 1+
ì 25 mA
…
…
∆
«
RUVLO2 ◊
Ÿ
⁄
(23)
HV-Port,
or LV-Port,
or VCC
25 µA
RUVLO1
MASTER
ENABLE
UVLO
AGND
+
ENABLE
RESET
œ
RUVLO2
2.5 V
CUVLO
+
œ
1.5 V
图8-28. UVLO Programming
HV-Port,
or LV-Port,
or VCC
25 µA
RUVLO1
MASTER
ENABLE
RUVLO3
UVLO
AGND
+
ENABLE
RESET
œ
RUVLO2
2.5 V
CUVLO
+
œ
1.5 V
图8-29. UVLO With Additional Hysteresis Programming
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The LM5170 is suitable for the bidirectional DC-DC converters for 48-V and 12-V dual battery systems and
battery backup systems. It can also create stackable, high power, unidirectional buck or boost converters with
balanced power sharing among multiphases.
9.1.1 Typical Key Waveforms
The following describes the typical power-up sequence of the LM5170 bidirectional converter in a 48-V to 12-V
dual battery system.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.1.1.1 Typical Power-Up Sequence
图9-1 shows key waveforms of power-up sequence.
Initializ
-ation
Shutdown
Standby
Power Delivery
MODE
10 V
VCC
0 V
UVLO=2.5 V
UVLO
UVLO=1.5 V
Fault Detection Interval
nFAULT
I(BRKG)
8.5 V
VGS_BRK
0 V
INTERNAL(PWR_GD)
VIN
0 V
VINX
OSCILLATOR
DIR
ISET
EN1,2
1.0 V
SS
••••••
••••••
••••••
••••••
HO1
LO1
HO2
LO2
图9-1. Typical Turnon Sequence Key Waveforms
9.1.1.2 One to Eight Phase Programming
图 9-2 and 表 9-1 show a typical logic control signals and external clock requirements to run an eight phase
system.
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
表9-1. Multiphase Programming
1Φ
0
2Φ
0
3Φ
4Φ
6Φ
0
8Φ
1
A7
A6
0
0
0
0
0
0
0
1
A5
0
0
0
0
1
1
A4
0
0
0
0
1
1
A3
0
0
0
1
1
1
A2
0
0
1
1
1
1
A1
0
1
1
1
1
1
A0
1
1
1
1
1
1
OPT (B0)
1
1
0
1
1
1
SYNC
(C0)
0°
0°
—
—
—
—
—
—
—
—
C1
60°
45°
B0
A3
A2
A1
A0
EN1 EN2
SYNCIN
EN1 EN2
0 Deg
VCCA
OPT
VCCA
OPT
C0
SYNCIN
SYNCOUT
SYNCOUT
DIR
ISETD
DIR
OSC
OSC
ISETD
AGND
AGND
MCU
A7
A6
A5
A4
C1
EN1 EN2
SYNCIN
EN1 EN2
SYNCIN
VCCA
OPT
VCCA
OPT
SYNCOUT
SYNCOUT
DIR
DIR
OSC
OSC
ISETD
ISETD
AGND
AGND
图9-2. Eight-Phase Configuration
9.1.2 Inner Current Loop Small Signal Models
The following describes the inner current loop that is controlled by the LM5170. The outer voltage loop must be
managed by the MCU or by an external analog circuit. The interface signals between the inner current loop and
outer voltage loop are basically the DIR and ISET signals, of which the DIR signal controls the current direction,
and the ISET signal carries the error information of the outer voltage loop.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.1.2.1 Small Signal Model
图 9-3 shows the current loop block diagram. The power plant transfer function from the error voltage (Vea) to
the channel inductor current (iLm) is determined by the following, regardless the current flow direction.
ILm
HV-Port
LV-Port
Lm
Rcs
V12
V48
DIR
1
50X
1
DIR
0
0
D
(1-D)
D
Vea
PWM
œ
Gm
+
ISETA
+
COMP
œ
Ramp
Generator
RCOMP
CCOMP
CHF
RAMP
Type II Compensator
Vramp
KFFV48
图9-3. Control Loop Block Diagram
Ù
i
1
1
Lm
H(s) =
=
ì
Ù
Vea
Lm
KFF ì(RCS + RS )
sì
+1
RCS + RS
(24)
where
• Lm is the power inductor,
• RCS is the current sense resistor
• RS is the equivalent total resistance along the current path excluding RCS
• KFF is the ramp generator coefficient. When the RAMP signal is generated per 方程式14 , KFF = 0.104
9.1.2.2 Inner Current Loop Compensation
方程式 24 indicates that the power plant is basically a first-order system. A Type-II compensator as shown in 图
9-3 is adequate to stabilize the loop for both buck and boost mode operations.
Assuming the output impedance of the gm amplifier is RGM, the gain from the inductor to the output of gm
amplifier is determined by 方程式25:
Ù
Vea
G(s) =
= 50ìRCS ìGmì R
II ZCOMP(s)
[
]
GM
Ù
i
Lm
(25)
where
• the coefficient 50 is the current sense amplifier gain
• Gm is the transconductance of the gm error amplifier, which is 1 mA/V
• ZCOMP(s) is the equivalent impedance of the compensation network seen at the COMP pin (see 方程式26)
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
1+ sìRCOMP ìCCOMP
1
ZCOMP(s) =
ì
CHF + CCOMP
≈
’
÷
CHF ìCCOMP
sì 1+ sìRCOMP ì
∆
CHF + CCOMP ◊
«
(26)
Usually CHF is << CCOMP. Thus, 方程式26 can be simplified to 方程式27:
1+ sìRCOMP ìCCOMP
1
ZCOMP(s) =
ì
CCOMP sì 1+ sìRCOMP ìCHF
(27)
Because RGM is > 5 MegΩ and the frequency range for loop compensation is usually above a few kHz, the
effects of RGM on the loop gain in the interested frequency range becomes negligible. Therefore, substituting 方
程式28 into 方程式25, and neglecting RGM, you can get the following:
Ù
Vea 50ìRCS ìGm 1+ sìRCOMP ìCCOMP
G(s) =
=
ì
Ù
CCOMP
sì(1+ sìRCOMP ìCHF )
i
Lm
(28)
(29)
The total open-loop gain of the inner current loop is the product of H(s) and G(s):
Gtotal(s) = H(s)ì G(s)
Or
50ìRCS ìGm
Lm
1+ sìRCOMP ìCCOMP
sì(1+ sìRCOMP ìCHF
1
Gtotal(s) =
ì
ì
KFF ì(RCS + RS )ìCCOMP
)
sì
+1
RCS + RS
(30)
The poles and zeros of the total loop transfer function are determined by:
fp1 = 0
(31)
(32)
(33)
(34)
(RCS + RS )
fp2
=
2pìLm
1
fp3
=
2pìRCOMP ìCHF
1
fz =
2pìRCOMP ìCCOMP
To tailor the total inner current loop gain to cross over at fCO, select the components of the compensation
network according to the following guidelines, then fine tune the network for optimal loop performance.
1. The zero fz is placed at the power stage pole fp2
2. The pole fp3 is placed at approximately two decade higher then fCO
3. The total open-loop gain is set to unity at fCO, namely
H(2iì pì fCO )ìG(2iì pì fCO ) = 1
(35)
Therefore, the compensation components can be derived from the above equations, as shown in 方程式36.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
À
Œ
Œ
KFF
1
R
=
=
ì 2i ì p ì fCO ì Lm + (RCS + RS )
Œ
Œ
Ã
Œ
Œ
Œ
Œ
Õ
COMP
50 ì RCS ì Gm ì H(2i ì p ì fCO
)
50 ì RCS ì Gm
Lm
CCOMP
=
(RCS + RS ) ì RCOMP
CCOMP
CHF
=
100
(36)
9.1.3 Compensating for the Non-Ideal Current Sense Resistor
TI strongly recommends employing a non-inductive resistor for RCS. Even a few nH of inductance cause the
current sense signal to be remarkably distorted, as shown in 图 9-4. The adversary consequences include
reduced peak current limit than actually programmed and false current zero-crossing detection well above 0 A.
The former can reduce the available maximum current to be delivered. The latter terminates the sync FET gate
early and the body diode is used to conduct the remaining current, thereby reducing the efficiency as well as the
accuracies of the channel DC current regulation and IOUT monitors under light load.
When the current sense resistor has some parasitic inductance, it is necessary to compensate the effects of
inductance with an RC circuit, as shown in 图 9-5. Place a 1-Ω resistor in each of the current sense signal path.
The selection of CCS must satisfy 方程式37, assuming the inductance of the current sense resistor is LCS
:
LCS
CCS
=
2 WìRCS
(37)
For instance, if RCS =1 mΩ and LCS = 1 nH, the required compensation capacitor CCS must be approximately
0.5 µF.
Note that selecting CCS greater than the value given by 方程式 37 overcompensates the inductance and
consequently defers the current zero crossing detection point to a negative current. Excessively larger capacitor
must not be used to prevent malfunction of the controller.
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Main FET
Vgs
0
IL
Inductor Current
0
dIL
dt
LCS
False 0-
Crossing
VCS
0
Sync FET
Vgs
0
time
Body Diode Used
图9-4. Effects of Parasitic Inductance on the Current Sense Signal and Zero Crossing Detection
Lcs1
Rcs1
ILm1
LV-Port
V12
Lm1
+
œ
1 ꢀ
1 ꢀ
CCS1
CSA1 CSB1
CSA2 CSB2
CCS2
1 ꢀ
1 ꢀ
Lm2
ILm2
Lcs2
Rcs2
图9-5. Compensation Network to Compensate the Current Sense Resistor’s Parasitic Inductance
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.1.4 Outer Voltage Loop Control
The LM5170 serves as a current regulator that regulates the DC component of the power inductor current to the
value programmed at the ISETA pin. To regulate the output voltage, an outer voltage loop should be employed.
The outer voltage loop can be implemented with an analog circuit (see 图 9-6) or a digital circuit like an MCU
(see 图 9-7). The error voltage signal of the output voltage loop is the ISET command for the inner current loop.
TI advises that the outer voltage loop crossover frequency must be one decade below that of the inner current
loop crossover frequency fCO. Refer to the LM5170 Design Calculator for the loop compensation guidance.
HV-Port
(48 V)
LV-Port
(12 V)
ILm
Rcs
Lm
DIR
1
1
DIR
0
0
D
(1-D)
D
Gm
Vea
PWM
œ
+
+
ISETA
œ
Vramp
COMP
kFF
FF Ramp
Generator
ISET
œ
œ
REF
+
+
REF
DIR
48 V Error Amp
12 V Error Amp
DIR
EN
EN
BST SS
BK SS
图9-6. Analog Outer Voltage Loop Control
HV-Port
(48 V)
LV-Port
(12 V)
ILm
Rcs
Lm
DIR
1
1
DIR
0
0
D
(1-D)
D
Gm
Vea
PWM
œ
+
+
ISETA
œ
Vramp
COMP
kFF
FF Ramp
Generator
DIR
ISET
ADC
œ
PID
Vout Set
ꢀ
+
Microcontroller
图9-7. Digital Outer Voltage Loop Control
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.2 Typical Application
9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
A typical application example is a 60-A, dual-phase bidirectional converter as shown in 图 9-8. The HV-Port
voltage range is 32 V to 70 V and the LV-Port 0 V to 23 V. Each phase is able to deliver 30-Adc current through
the inductor.
Lm1
RCS1
+
4.7 µH
QL2
+
1 mΩ
QH1
CHB1
0.22 µF
C1
100 µF
C2
470 µF
LV-Port
œ
HV-Port
œ
VCC
RHB1
RVIN
10 Ω
2 ꢀ
PGND
PGND
PGND
22
24
23
20
18
36
35
CVIN
1 µF
6
VIN
BRKG 34
BRKS 33
RBRKS
10 kΩ
RBRKS
10 kΩ
PGND
19 VCC
+
RVCCA
24.9 Ω
CVCC
2.2 µF
+10Vdc
œ
31 VCCA
29 OPT
VINX
4
RRAMP
95.3
1
PGND
C5
1 µF
kΩ
RAMP1 28
46 AGND
47 OSC
CRAMP1
1 nF
RRAMP2
95.3 kΩ
ROSC
RAMP2
COMP1
8
40.2 kꢀ
CRAMP2
1 nF
42 ISETD
40 SYNCIN
CCOMP2
RCOMP1
CHF1
PGND
AGND
RSYNCO
26
41 SYNCOUT
15 nF
10 kꢀ
CCOMP2
RCOMP2
CHF2
10 UVLO
39 EN1
CMMD AND
MONITOR
COMP2 11
AGND
15 nF
43 EN2
ENABLE
DIR
1 nF
RDT 10 kΩ
44 DIR
48
DT
CSS 10 nF
45 ISETA
27 nFAULT
37 IOUT1
ISETA
SS 12
ROVPA 51.1 kΩ
ROVB 54.9 kΩ
OVPA
9
IOUT1
IOUT2
CIOUT1
10 nF
RIOUT1
9.09 kΩ
OVPB 25
R
IPK 40.2 kΩ
38 IOUT2
CIOUT2
10 nF
RIOUT1
9.09 kΩ
30
IPK
AGND
15
13 14
17
1
2
AGND
RHB2
2 Ω
VCC
DHB2
CHB2
0.22 µF
QH2
Lm2
RCS2
1 mΩ
QL2
4.7 µH
C8
100 µF
C10
470 µF
PGND
PGND
PGND
图9-8. Schematic of the Example Dual-Phase Bidirectional Converter
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.2.1.1 Design Requirements
表9-2 lists the design parameters for this example.
表9-2. Design Parameters
PARAMETER
VLV_min
VLV_reg
VLV_max
VHV_min
VHV_reg
VHV_max
FSW
EXAMPLE VALUE
NOTE
6 V
14 V
LV-Port minimum operating voltage
LV-Port nominal voltage
23 V
LV-Port maximum operating voltage
HV-Port minimum operating voltage
HV-Port nominal operating voltage
HV-Port maximum operating voltage
Switching frequency
32 V
50 V
70 V
100 kHz
30 A
Imax
Maximum channel DC current, bidirectional
Total bidirectional DC at the LV-Port
Itotal
60 A
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Determining the Duty Cycle
Obviously, the duty cycles are determined by 方程式38 through 方程式41:
VLV_reg
14 V
DBK_min
=
=
= 0.2
VHV max 70 V
(38)
(39)
(40)
(41)
VLV_reg
14 V
DBK_max
=
=
= 0.438
VHV min 32 V
VHV_reg - VLV_max
50 V - 23 V
50 V
DBST_min
=
=
= 0.54
VHV_reg
VHV_reg - VLV_min
50 V - 6 V
50 V
DBST_max
=
=
= 0.88
VHV_reg
9.2.1.2.2 Oscillator Programming
To operate the converter at the desired switching frequency FSW, select the ROSC by satisfying 方程式 17,
namely,
40 kW ì100 kHz
100 kHz
ROSC
=
= 40 kW
(42)
Choose the closest standard resistor, that is, ROSC = 40.2 kΩ.
9.2.1.2.3 Power Inductor, RMS and Peak Currents
The inductor current has a triangle waveform, as shown in 图 9-4. TI recommends selecting an inductor such
that its peak-to-peak ripple current is less than 80% of the channel inductor full load DC current. Therefore, the
inductor must satisfy 方程式43:
VLV_reg ì 1-D
(
)
BK _min
14 V ì(1- 0.2)
0.8ì30 A ì100 kHz
Lm
í
=
= 4.67 mH
80%ìImaxìF
sw
(43)
Select Lm = 4.7 µH.
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Then, the actual inductor peak to peak inductor current is determined by 方程式44:
VLV_reg ì(1- DBK_min
)
14 V ì(1- 0.2)
4.7 mHì100 kHz
Ipk-pk
=
=
= 23.83 A
Lm ìF
sw
(44)
(45)
The peak inductor current is determined by 方程式45:
Ipk-pk
23.83
2
Ipeak = Imax
+
= 30 A +
= 41.9 A
2
Select an inductor that has a saturation current Isat at least 20% greater than Ipeak to ensure full power with
adequate margin. In this example, TI recommends selecting an inductor of Isat > 49 A.
The full load Root Mean Square (RMS) current of the power inductor, ILM_RMS, determines its conduction losses.
The RMS current is given by 方程式46:
1
ILm_RMS = Im2 ax
+
ìIp2k-pk = 30.8 A
12
(46)
9.2.1.2.4 Current Sense (RCS
)
To achieve the highest regulation accuracy over wider load range, target to create 50 mV of VCS at full current.
Therefore, RCS must be selected as 方程式47:
50 mV 50 mV
=
RCS
Ç
= 1.667 mW
Imax
30 A
(47)
Ideally, a 1.5-mΩ current sense resistor is chosen for this example. However, due to availability, a standard non-
inductive 1-mΩ current sense resistor is selected, namely,
RCS = 1.0 mW
(48)
Because RCS conducts the same current as the power inductor, its power dissipation is also determined by
ILm_RMS
.
If the selected RCS has parasitic inductance (assuming it is 1 nH), it must be compensated, and the
compensation capacitor CCS must satisfy 方程式37.
LCS
2 WìRCS 2 Wì1 mW
1 nH
CCS
=
=
= 0.5 mF
(49)
Select the closest standard capacitor, CCS = 0.47 µF.
For optimal performance, it is good practice to add a 100-pF ceramic capacitor at each current sense pin to filter
out common-mode noise, as shown in 图9-9.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Lcs1
Rcs1
ILm1
LV-Port
V12
Lm1
+
œ
1 ꢀ
1 ꢀ
CCS1
100 pF
100 pF
CSA1 CSB1
CSA2 CSB2
100 pF
100 pF
CCS2
1 ꢀ
1 ꢀ
Lm2
ILm2
Lcs2
Rcs2
图9-9. Current Sense With Compensation to Cancel the Effects of Parasitic Inductances
9.2.1.2.5 Current Setting Limits (ISETA or ISETD)
TI recommends setting a hard limit of the maximum current programming signal such that the converter cannot
be over driven by an errant current programming signal. Assume the converter is allowed up to 10% overloading
current. Refer to 方程式7, the analog current setting signal ISETA must be limited by the following voltage level:
110%ìImaxìRCS
0.02
110%ì30 Aì1mW
0.02
V
Ç
=
= 1.65 V
ISETA_max
(50)
Refer to 方程式10, the PWM current setting signal ISETD must be limited by the following duty cycle:
110%ìImaxìRCS
0.0625 V
110%ì30 Aì1mW
0.0625 V
D
Ç
=
= 52.8%
ISETD_max
(51)
9.2.1.2.6 Peak Current Limit
One purpose of the peak current limit is to protect the power inductor from saturation. Select RIPK such that the
peak current limit threshold is 5~10% greater than Ipeak. According to 方程式13, one gets:
RCS ì105%ìIpeak
1.1mA
1 mWì105%ì 41.9 A
1.1 mA
RIPK
=
=
= 40 kW
(52)
Select RIPK = 40.2 kΩ, which results in a nominal inductor peak current limit of 44.2 A per channel.
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.2.1.2.7 Power MOSFETS
The power MOSFETs must be chosen with a VDS rating capable of withstanding the maximum HV-port voltage
plus transient spikes (ringing). In this example, the maximum HV-rail voltage is 70 V. Selecting the 80-V rated
MOSFETs allows 10-V transient spikes.
When the voltage rating is determined, select the MOSFETs by making tradeoffs between the MOSFET Rds(ON)
and total gate charge Qg to balance the conduction and switching losses. For high-power applications, parallel
MOSFETs to share total power and reduce the dissipation on any individual MOSFET, hence relieving the
thermal stress. The conduction losses in each MOSFET is determined by 方程式53.
1.8ìRds(ON)
PQ_cond
=
ìIQ2 _RMS
N
(53)
where
• N is the number of MOSFETs in parallel
• 1.8 is the approximate temperature coefficient of the Rds(ON) at 125 °C
• Total RMS switch current IQ_RMS is approximately determined by 方程式54
IQ_RMS
ö Dmax ìImax = Dmax ìImax
(54)
where
• Dmax is the maximum duty cycle, either in the buck mode or boost mode
The switching transient rise and fall times are approximately determined by:
Nì Qg
Dtrise
ö
4 A
(55)
(56)
NìQg
Dtfall
ö
5 A
And the switching losses of each of the paralleled MOSFETs are approximately determined by:
Ipeak
N
1
2
1
2
PQ_sw
=
ìCoss ì VH2V ìF
+
ì
ì VHV ì(Dtrise + Dtfall)ìF
sw
sw
(57)
where
• Coss is the output capacitance of the MOSFET
The power MOSFET usually requires a gate-to-source resistor of 10 kΩ to 100 kΩ to mitigate the effects of a
failed gate drive. When using parallel MOSFETs, a good practice is to use 1- to 2-Ω gate resistor for each
MOSFET, as shown in 图9-10.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
To Inductor
HV-Port
100 kꢀ
100 K
100 K
100 kꢀ
1 ꢀ
1 ꢀ
1 ꢀ
1 ꢀ
HO
SW
LO
PGND
图9-10. Paralleled MOSFET Configuration
If the dead time is not optimal, the body diode of the power synchronous rectifier MOSFET causes losses in
reverse recovery. Assuming the reverse recovery charge of the power MOSFET is Qrr, the reverse recovery
losses are thus determined by 方程式58:
PQ_rr = Qrr ì VHV_max ìF
sw
(58)
To reduce the reverse recovery losses, an optional Schottky diode can be placed in parallel with the power
MOSFETs. The diode should have the same voltage rating as the MOSFET, and it must be placed directly
across the MOSFETs drain and source. The peak repetitive forward current rating must be greater than Ipeak
,
and the continuous forward current rating must be greater than the following 方程式59:
ISD_avg = Ipeak ì tDT ìF
sw
(59)
9.2.1.2.8 Bias Supply
The LM5170 requires an external 10- to 12-V VCC bias supply to operate. If not available in the system, you can
generate it from the LV-Port using a buck-boost or SEPIC converter, or from the HV-Port using a buck converter.
Refer to the Texas Instruments LM25118-Q1 and LM5118-Q1 to implement a buck-boost converter, the LM5001-
Q1 to implement a SEPIC converter, or the LM5160-Q1 and LM5161-Q1 to implement a buck converter.
The total load current of the bias supply is mainly determined by the total MOSFET gate charge Qg. Assume the
system employs multiple LM5170s to implement M number of phases, and each phase uses N number of
MOSFETs in parallel as one switch. There are 2× N MOSFETs per phase to drive. Then the total current to drive
these MOSFETs through VCC bias supply is determined by 方程式60.
IVCC = 2ìMìNìQg ìF + Mì5 mA
sw
(60)
where
• 5 mA is the worst case maximum current used by the control logic circuit of each phase
In an example of a four-phase system employing two parallelled MOSFETs for one switch, where M = 4, N = 2,
Qg = 100 nC, and Fsw = 100 KHz, the bias supply must be able to support at least the following total load
current:
IVCC í 2ì 4ì 2ì100 nCì100 kHz + 4ì5 mA = 180 mA
(61)
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
In an example of an eight-phase system employing the same parallel MOSFETs for one switch, the bias supply
must be able to support the following total load current:
IVCC_8ph = 2ì8ì2ì100 nCì100 kHz + 8ì5 mA = 360 mA
(62)
The VCC AC bypass ceramic capacitor CVCC = 1 to approximately 2.2 µF, rated at least 16 V, must be placed
close to the VCC and PGND pins. Similarly, a ceramic capacitor CVCCA = 1 µF, rated at least 16 V, must be
placed close to the VCCA and AGND pins. Place a 24-Ωresistor between VCC and VCCA pins.
9.2.1.2.9 Bootstrap
Select a ceramic capacitor CHB1 = CHB2 = 0.1 to approximately 0.22 µF, placed close to the HB and SW pins.
The fast switching diode of the forward current rated at 1-A and reverse voltage not lower than VHV_max must be
selected as the bootstrap diode, through which the boot capacitor CHB1 or CHB2 is charged by VCC. To reduce
the noise caused by the fast charging current, a 2-Ω to 5-Ω current limiting resistor must be placed in series
with each boot diode.
9.2.1.2.10 RAMP Generators
According to 方程式 14, the ramp generator must be selected such that a peak voltage of 5 V is produced each
cycle when the HV-Port voltage is 48 V.
Select CRAMP1 = CRAMP2 = 1 nF. Therefore,
9.6
9.6
RRAMP
=
=
= 96 kW
F
ì CRAMP 100 kHzì1 nF
sw
(63)
Choose the closest standard resistor value, namely:
RRAMP1 = RRAMP2 = 95.3 kΩ.
For optimal performance, CRAMP1 and CRAMP2 must be ceramic capacitors with tolerance not greater than 10%.
Capacitors of the 5% or 1% C0G and NPO types are preferred.
9.2.1.2.11 OVP
As shown in 图 8-18 and 图 8-19, the HV-Port and LV-Port overvoltage protection thresholds can be
programmed by ROVPA and ROVPB, respectively. These resistor values are determined by 方程式 64 and 方程式
65.
1.185 V
1.185 V
ROVPA
=
ì3000 kW =
ì1000 kW =
ì3000 kW = 51.66 kW
ì1000 kW = 54.3 kW
VHV_max -1.185 V
70 V -1.185 V
(64)
(65)
1.185 V
1.185 V
ROVPB
=
VLV_max -1.185 V
23 V -1.185 V
Select the closest standard resistor values. In this example, ROVPA = 51.1 kΩ, and ROVPB = 54.9 kΩ.
9.2.1.2.12 Dead Time
To use the built-in adaptive dead time, the DT pin must be connected to VCCA pin.
To program the dead time, follow 方程式 15 to select the resistor RDT. To dynamically adjust the dead time with
an external analog voltage signal, follow 方程式 19. To dynamically adjust the dead time with an external PWM
signal, follow 方程式20.
In the example circuit, the nominal dead time is selected to be 55 ns. According to 方程式 15, the programming
resistor should be:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: LM5170
LM5170
www.ti.com.cn
(66)
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
ns
tDT = RDT ì 4
+16 ns
kW
tDT -16 ns
kW 55 ns -16 ns
kW
ns
RDT
=
ì1
=
ì1
= 9.75 kW
4
ns
4
(67)
Select the standard value, RDT = 10 kΩ.
9.2.1.2.13 IOUT Monitors
TI recommends making the following selections:
RIOUT1 = RIOUT2 = 9.09 kΩ
(68)
(69)
CIOUT1 = CIOUT2 = 0.01 µF
Then the monitors' delay is determined by the following time constant:
tIOUT = RIOUT1ìCCIOUT1 = 9.09 kWì0.01mF = 90.9 ms
(70)
At full load, the DC component of the monitor voltage is determined by:
I
maxìRCS
200 W
30 Aì1mW
200 W
≈
’
≈
’
V
IOUT1 = V
=
+ 25 mA ìRIOUT1
=
+ 25 mA ì9.09 kW = 1.591V
IOUT2
∆
«
÷
∆
«
÷
◊
◊
(71)
Because the inductor ripple current is 23.8 A, according to 方程式11, the IOUT peak to peak ripple current is:
Ipk-pk ìRCS
200 W
23.8 Aì1mW
200 W
DIOUT1=
=
= 119 mA
(72)
(73)
The RC filter corner frequency is thus given by:
1
1
F
=
=
= 1.75 kHz
IOUT
6.28ìRIOUT ìCIOUT 6.28ì9.09 kWì10 nF
The resulting peak-to-peak monitor ripple voltage is approximately determined by:
≈
∆
«
’
÷
F
100kHz
1.75kHz
≈
’
sw
-log
-log
∆
«
÷
◊
F
IOUT ◊
DV
= DIOUT1ìRIOUT ì10
= 119 mA ì9.09 kW ì10
= 19 mV
IOUT
(74)
Which is approximately 1.1% peak-to-peak ripple on top of the full load DC monitor voltage. Increasing CIOUT
value further attenuate the ripple voltage, but also causes longer monitor delays.
9.2.1.2.14 UVLO Pin Usage
The example circuit uses the UVLO pin as the master enable pin of the LM5170. However, the UVLO pin can
also fulfill the function of undervoltage lockout, either the 48-V rail UVLO, 12-V rail UVLO, or VCC UVLO.
Assume you implement the 48-V rail UVLO and the low-side resistor RUVLO2 = 10 kΩ, the 48-V UVLO release
threshold VUVLO = 24 V, and UVLO hysteresis is VHYS =2.4 V. Referring to 图 8-29 and 方程式 21, you can find
that RUVLO1 is given by:
VUVLO- 2.5 V
2.5 V
24 V - 2.5 V
2.5 V
RUVLO1
=
ìRUVLO2
=
ì10 kW = 86 kW
(75)
The final selection must select the closest standard resistor of RUVLO1 = 86.6 kΩ.
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
And RUVLO3 must satisfy 方程式23, namely,
VHYS
2.4 V
-RUVLO1
- 86.6 kW
25 mA
25 mA
RUVLO3
=
=
= 0.973 kW
RUVLO1
86.6 kW
1+
1+
10 kW
RUVLO2
(76)
Select the closest standard resistor, RUVLO1 = 976 Ω.
If you choose to add the capacitor CUVLO = 1 nF, it leads to a delay time constant of 10 µs to filter possible noise
at the at the UVLO pin.
9.2.1.2.15 VIN Pin Configuration
The VIN pin must always be connected to the HV voltage rail. It is good practice to add a small RC filter to
improve the VIN noise immunity, as shown in 图 9-11. Usually the filter resistor selection is 10 to 20 Ω, and the
bypass capacitor is 0.1 µF to 1.0 µF.
HV-Port
RVIN
10 ꢀ
VIN
CVIN
0.1 ~ 1.0 µF
AGND
图9-11. VIN Pin Configuration
9.2.1.2.16 Loop Compensation
Assuming the total resistance along the current path including the external power cables, PCB current tracks,
and battery internal impedances is 50 mΩ, according to 方程式 36, the compensation network for the inner
current loop is determined by:
À
Œ
Œ
KFF
0.104
Œ
RCOMP
=
ì 2i ì p ì fCO ì Lm + (RCS + RS )=
ì 2i ì p ì10 kHz ì 4.7 ꢀH + 51 mꢁ = 0.623 kꢁ
= 147 nF
50 ì Rcs ì Gm
50 ì 1 mꢁ ì 1 mA/V
Œ
Œ
Ã
Œ
Œ
Œ
Œ
Lm
4.7 ꢀH
CCOMP
=
=
(RCS + RS ) ì RCOMP
(50 mꢁ + 1 mꢁ) ì 0.623 kꢁ
CCOMP
CHF
=
= 1.47 nF
100
Œ
Õ
(77)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
Selecting the closest standard values for the compensation network, namely,
RCOMP1 = RCOMP2 = 634 Ω
CCOMP1 = CCOMP2 = 150 nF
CHF1 = CHF2 = 1 nF
These initial component selections produce a total loop phase margin of 90°, which is larger than necessary.
Fine tune the loop compensation by reselecting CCOMP1 = CCOMP2 = 15 nF, then the phase margin is 45° for an
optimal dynamic performance.
图9-12 shows the Bode Plots of the power plant, the compensation gain, and the resulting total open loop.
60
Power Plant
40
Compensation
Total Loop
20
0
- 20
- 40
3
4
5
6
100
1ì10
1ì10
1ì10
1ì10
180
150
120
90
60
30
0
3
4
5
6
100
1ì10
1ì10
Frequency (Hz)
图9-12. Bode Plots of the Example Converter
1ì10
1ì10
9.2.1.2.17 Soft Start
Soft start can be programmed with a ceramic capacitor CSS. Note that CSS also determines the retry frequency
when the converter is an under overvoltage condition (OVPA or OVPB). Because the soft start completes when
the SS pin voltage reaches approximately 5 V, the capacitor CSS can be chosen by 方程式78 to limit the full load
start-up time within ΔTSS = 2 ms:
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
25 mA ì DTSS
5 V
25 mA ì 2 ms
5 V
CSS
=
=
= 10 nF
(78)
Select the closest standard ceramic capacitor, that is, CSS = 10 nF.
9.2.1.2.18 ISET Pins
To control the current setting by an analog voltage, ground the ISETD pin. To control the current setting by a
PWM signal, there are two options to choose.
The first option is to use the built-in ISETD-to-ISETA decoder as shown in 图 8-4. The PWM duty cycle to ISETA
voltage conversion ratio satisfies 方程式 8. The selection of CISETA and FISETD must be constrained by 方程式 1
and 方程式 4. The advantages of this option include convenience and current control accuracy. The drawback is
the delay it can cause.
Another option is to use an external two-stage RC filter to convert the PWM ISETD signal to a DC voltage
feeding the ISETA pin as shown in 图 9-13. To achieve the same ISETA ripple voltage, this option only requires
CISETA =1.5 nF, and the delay time of this two-stage filter is only 10% of the built-in decoder, or 15 µs versus the
built-in 150 µs of the decoder. The drawback of this option is the conversion errors if the PWM signal voltage
levels are not well regulated. This option is more suitable for operation under a closed digital outer voltage loop
because the ISETD to ISETA conversion error can be readily compensated by the closed outer voltage loop.
ISETD
10 kꢀ
10 kꢀ
PWM
ISETA
ISETD
1.5 nF
1.5 nF
AGND
图9-13. Two-Stage RC Filter to Convert the PWM into an Analog Voltage at the ISETA Pin
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
9.2.1.3 Application Curves
图9-14. Channel Inductor Current and IOUT
图9-15. Diode Emulation Prevents Negative
Tracking ISETA Command
Current
图9-16. Channel Inductor Current and Monitor
图9-17. Start-Up Sequence Following UVLO
Responses to Dynamic DIR Change
Enable
图9-18. nFAULT Shutdown Latch
图9-19. Boot Capacitor Pre-Charge During Start-
Up in Buck Mode
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
图9-20. Dual-Channel Interleaving Operation: Buck
图9-21. Dual-Channel Interleaving Operation:
Mode
Boost Mode
图9-22. LV-Port OVP: Buck Mode
图9-23. HV-Port OVP: Boost Mode
10 Power Supply Recommendations
The LM5170-based converter is designed to operate with two differential voltage rails like the 48-V and 12-V
dual battery system, or a storage system having a battery on one end and the Super-Cap on the other end.
When operating with bench power supplies, each supply should be capable of sourcing and sinking the
maximum operating current. This can require to parallel an Electronic load (E-Load) with the bench power supply
(PS) to emulate the batteries, as shown in 图10-1.
It can also be used with a voltage source on one end and a load on the other end if the outer voltage control loop
is closed. The outer voltage loop can be implemented either with digital means like an MCU or with analog
circuit, as shown in 图9-6 and 图9-7.
V12
V48
+
+
Bi-Directional
Converter
œ
œ
RTN
RTN
E-Load
E-Load
PS
PS
图10-1. Emulated Dual Battery System With Bench Power Supplies and E-Loads
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
11 Layout
11.1 Layout Guidelines
Careful PCB layout is critical to achieve low EMI and stable power supply operation as well as optimal efficiency.
Make the high frequency current loops as small as possible, and follow these guidelines of good layout
practices:
1. For high-power board design, use at least a 4-layer PCB of 2-oz or thicker copper planes. Make the first
inner layer a ground plane that is adjacent to the top layer on which the power components are installed, and
use the second inner layer for the critical control signals including the current sense, gate drive, commands,
and so forth. The ground plane between the signal and top layers helps shield switching noises on the top
layer away from affecting the control signals.
2. Optimize the component placements and orientations before routing any traces. Place the power
components such that the power flow from port to port is direct, straight and short. Avoid making the power
flow path zigzag on the board.
3. Identify the high frequency AC current loops. In the bidirectional converter, the AC current loop of each
channel is along the path of the HV-port rail capacitors, high-side MOSFET, low-side MOSFET, and back to
the return of the HV-port rail capacitors. Place these components such that the current flow path is short,
direct and the special area enclosed by the loop is minimized.
4. Place the power circuit symmetrically between CH-1 and CH-2. Split the HV-port rail capacitors and LV-port
rail capacitors evenly between CH-1 and CH-2.
5. If more than one LM5170 is used on the same PCB for multi phases, place the circuits of each LM5170 in
the similar pattern.
6. Use adequate copper for the power circuit, so as to minimize the conductions losses on high-current PCB
tracks. Adequate copper can also help dissipate the heat generated by the power components, especially
the power inductors, power MOSFETs, and current sense resistors. However, pay attention to the polygon of
the switch node, which connects the high-side MOSFET source, low-side MOSFET drain, power inductor,
and the controller SW pin. The switch node polygon sees high dv/dt during switching operation. To minimize
the EMI emission by the switch node polygon, make its size sufficient but not excessive to conduct the
switched current.
7. Use appropriate number of via holes to conduct current to, and heat through, the inner layers.
8. Always separate the power ground from the analog ground, and make a single point connection of the power
ground, analog ground, and the EP pad, at the location of the PGND pin.
9. Minimize current-sensing errors by routing each pair of CSA and CSB traces using a kelvin-sensing directly
across the current sense resistors. The pair of traces must be routed closely side by side for good noise
immunity.
10. Route sensitive analog signals of the CS, IOUT, COMP, OVPA, and OVPB pins away from the high-speed
switching nodes (HB, HO, LO, and SW).
11. Route the paired gate drive traces, namely the pairs of HO1 and SW1, HO2 and SW2, LO1 and return, and
LO2 and return, closely side by side. Route CH-1 gate drive traces in symmetry with CH-2’s.
12. Place the IC setting, programming and controlling components as close as possible to the corresponding
pins, including the following component: ROSC, RDT, RIPK, CRAMP1, CRAMP2, ROVPA, ROVPB, CISETA, CCOMP1
,
RCOMP2, CCOMP1, CCOPM2, CHF1, and CHF2
.
13. Place the bypass capacitors as close as possible to the corresponding pins, including CVIN, CVCC, CVCCA
CHB1, CHB2, COPVA, COVPB, as well as the 100-pF current sense common-mode bypassing capacitors.
14. Flood each layer with copper to take up the empty areas for optimal thermal performance.
15. Apply heat sink to components as necessary according to the system requirements.
,
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
11.2 Layout Examples
The following figures are some examples illustrating these layout guidelines. For the detailed PCB layout artwork
of the LM5170-Q1 Evaluation Module (LM5170EVM-BIDIR), please refer to the LM5170-Q1 EVM User's Guide
(SNVU543).
GND
S
GND
D
CH-1 AC
Loop
L
G
LV(+12 V)
HV(+48 V)
G
S
RCS
LV(+12 V)
LV(+12 V)
D
D
D
Circuit
Breaker
D
D
S
G
TVS
S
G
G
GND
GND
G
S
S
S
G
D
RCS
GND
HV(+48 V)
CH-2 AC
Loop
D
S
Controller
L
G
图11-1. A Layout Example of Dual-Channel Power Circuit Placement
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
S
D
L
CH-1
G
HV(+48 V)
D
HO1
SW1
LO1
S
G
GND
GND
PGND
PGND
LO2
G
S
SW2
HO2
D
HV(+48 V)
S
D
L
CH-2
G
图11-2. A Layout Example of MOSFET Gate Drive Routing
To Controller
RCS
(a) Kelvin Contact of Resistor without Sense Pins
To Controller
RCS
(b) Kelvin Contact of Resistor with Sense Pins
图11-3. A Layout Example of Current Sense Routing
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
To AGND
From VCC
To CH-1
Current
Sense
From OPT
From nFAULT
From UVLO
SW1
HB1
HO1
NC
IOUT1
IOUT2
EN1
To CH-1
MOSFETs
SYNCIN
SYNCOUT
ISETD
EN2
LO1
VCC
PGND
LO2
NC
EP
To +10V Supply
DIR
To CH-2
MOSFETs
ISETA
AGND
OSC
HO2
HB2
SW2
DT
Single Point
Ground
Connection
To CH-2
Current
Sense
To AGND
图11-4. A Layout Example of LM5170 Critical Signal Routing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: LM5170
LM5170
www.ti.com.cn
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, see the following:
• LM25118-Q1
• LM5118-Q1
• LM5001-Q1
• LM5160-Q1
• LM5161-Q1
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: LM5170
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5170PHPR
LM5170PHPT
ACTIVE
ACTIVE
HTQFP
HTQFP
PHP
PHP
48
48
1000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LM5170
LM5170
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2021
OTHER QUALIFIED VERSIONS OF LM5170 :
Automotive : LM5170-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5170PHPR
LM5170PHPT
HTQFP
HTQFP
PHP
PHP
48
48
1000
250
330.0
330.0
16.4
16.4
9.6
9.6
9.6
9.6
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5170PHPR
LM5170PHPT
HTQFP
HTQFP
PHP
PHP
48
48
1000
250
336.6
336.6
336.6
336.6
31.8
31.8
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PHP 48
7 x 7, 0.5 mm pitch
TQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
PACKAGE OUTLINE
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
7.2
6.8
B
NOTE 3
37
48
PIN 1 ID
1
36
7.2
6.8
9.2
TYP
8.8
NOTE 3
12
25
13
24
A
0.27
48X
44X 0.5
0.17
0.08
C A B
4X 5.5
1.2 MAX
C
SEATING PLANE
SEE DETAIL A
0.08
(0.13)
TYP
13
24
12
25
0.25
(1)
GAGE PLANE
4.6
3.6
49
0.75
0.45
0.15
0.05
0 -7
A
16
36
DETAIL A
TYPICAL
1
48
37
4X (0.115)NOTE5
4.6
3.6
4226381/A 11/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
5. Feature may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
6.5)
NOTE 10
(4.6)
SYMM
48
37
SOLDER MASK
DEFINED PAD
48X (1.6)
1
36
48X (0.3)
SYMM
49
(4.6)
(1.1 TYP)
(8.5)
44X (0.5)
12
25
(R0.05) TYP
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
13
24
(1.1 TYP)
SEE DETAILS
(8.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226381/A 11/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(4.6)
BASED ON
0.125 THICK STENCIL
SEE TABLE FOR
SYMM
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
48
37
48X (1.6)
1
36
48X (0.3)
(8.5)
(4.6)
SYMM
49
BASED ON
0.125 THICK
STENCIL
44X (0.5)
12
25
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
24
13
(8.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
5.14 X 5.14
4.6 X 4.6 (SHOWN)
4.2 X 4.2
0.125
0.150
0.175
3.89 X 3.89
4226381/A 11/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2021 德州仪器半导体技术(上海)有限公司
相关型号:
©2020 ICPDF网 联系我们和版权申明