LM5181QNGURQ1 [TI]
具有 100V、0.75A 集成式 MOSFET 的汽车类 65V 输入电压非光电反激式直流/直流转换器 | NGU | 8 | -40 to 150;
| 型号： | LM5181QNGURQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 100V、0.75A 集成式 MOSFET 的汽车类 65V 输入电压非光电反激式直流/直流转换器 | NGU | 8 | -40 to 150 光电 转换器 |
| 文件： | 总33页 (文件大小：2113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5181-Q1
ZHCSL48 –APRIL 2020
具有 100V、0.75A 集成 MOSFET 的 LM5181-Q1 65VIN PSR 反激式直流/
直流转换器
1 特性
•
超低的 EMI 传导和辐射信号
–
–
软开关可避免二极管反向恢复
1
•
符合面向汽车 应用的 AEC-Q100 标准
根据标准要求进行了优化CISPR 25 5 类
–
器件温度等级 1：-40℃ 至 125℃ 的环境温度范
围
2 应用
•
•
提供功能安全
可帮助进行功能安全系统设计的可用文档
专为可靠耐用的应用 设计
•
•
•
•
AM 以下波段汽车车身电子装置
–
汽车 HEV/EV 动力总成系统
牵引逆变器：IGBT 和 SiC 栅极驱动器
隔离式偏置电源
–
4.5V 至 65V 的宽输入电压范围，启动后的工作
电压低至 3.5V
–
–
–
–
–
–
–
稳定可靠的解决方案，只有一个组件穿过隔离层
±1.5% 的总输出稳压精度
3 说明
LM5181-Q1 是一款初级侧稳压 (PSR) 反激式转换器，
在 4.5V 至 65V 的宽输入范围内具有高效率。隔离输
出电压采样自初级侧反激式电压，因此，无需使用光耦
合器、电压基准或变压器的第三绕组进行输出电压稳
压。
可选 VOUT 温度补偿
6ms 内部或可编程软启动
输入 UVLO 和热关断保护
断续模式过流故障保护
具有 –40°C 至 +150°C 的结温范围
•
•
通过集成技术减小解决方案尺寸，降低成本
凭借高度的集成性，可实现简单可靠的高密度设计，其
中只有一个组件穿过隔离层。通过采用边界导电模式
(BCM) 开关，可实现紧凑的磁解决方案以及优于
±1.5% 的负载和线路调节性能。集成的 100V 功率
MOSFET 能够提供高达 4W 的输出功率并提高应对线
路瞬变的余量。
–
–
集成 100V、0.4Ω 功率 MOSFET
无需光耦合器或变压器辅助绕组即可进行 VOUT
稳压
–
内部环路补偿
高效率 PSR 反激运行
–
–
–
–
MOSFET 在 BCM 模式下实现准谐振关断
低输入静态电流
LM5181-Q1 转换器符合汽车 AEC-Q100 1 级标准，并
且采用引脚间距为 0.8mm 且具有可湿性侧面的 8 引脚
WSON 封装。
具有用于提升效率的外部偏置选项
具有单输出和多输出实施手段
使用 WEBENCH® 电源设计器创建定制稳压器设计
器件信息(1)
•
器件型号
LM5181-Q1
封装
WSON (8)
封装尺寸（标称值）
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
典型效率 (VOUT = 5V)
90
DFLY
VIN = 4.5 V...65 V
VOUT = 5 V
T1
85
80
75
DZ
COUT
100 ꢀF
3 : 1
CIN
DF
VIN
EN/UVLO
2.2 ꢀF
SW
RFB
LM5181-Q1
158 kW
70
GND
FB
VIN = 12V
VIN = 24V
RSET
TC
VIN = 36V
VIN = 48V
VIN = 65V
65
60
RSET
SS/BIAS
12.1 kW
0
100
200
300 400
Output Current (mA)
500
600
700
D002
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBN6
LM5181-Q1
ZHCSL48 –APRIL 2020
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Applications ................................................ 16
1
2
3
4
5
6
7
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Examples................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 器件支持................................................................ 25
12.2 文档支持 ............................................................... 26
12.3 接收文档更新通知 ................................................. 26
12.4 支持资源................................................................ 26
12.5 商标....................................................................... 26
12.6 静电放电警告......................................................... 27
12.7 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2020 年 4 月
*
初始发行版
5 说明 （续）
LM5181-Q1 反激式转换器简化了隔离式直流/直流电源的实现，且可通过可选 功能 优化目标终端设备的性能。该
器件通过一个电阻器来设置输出电压，同时使用可选的电阻器通过抵消反激式二极管的压降热系数来提高输出电压
精度。其他 功能 包括内部固定或外部可编程软启动、可实现更高效率的可选偏置电源连接、用于可调节线路
UVLO 的精密使能输入（带迟滞功能）、间断模式过载保护和带自动恢复功能的热关断保护。
2
Copyright © 2020, Texas Instruments Incorporated
LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
6 Pin Configuration and Functions
NGU Package
8-Pin WSON With Wettable Flanks
Top View
8
7
6
5
GND
SW
FB
1
RSET
TC
2
3
4
VIN
EN/UVLO
SS/BIAS
Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
Switch node that is internally connected to the drain of the N-channel power MOSFET. Connect
to the primary-side switching terminal of the flyback transformer.
1
SW
P
I
Primary-side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to the
resistor at the RSET pin sets the output voltage.
2
3
FB
Input supply connection. Source for internal bias regulators and input voltage sensing pin.
Connect directly to the input supply of the converter with short, low impedance paths.
VIN
P/I
Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO
voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
4
5
EN/UVLO
SS/BIAS
I
I
Soft start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up
time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is
activated. Connect an external supply to SS/BIAS to supply bias to the internal voltage regulator
and enable internal soft start.
Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the
temperature coefficient of the forward voltage drop of the secondary diode, thus improving
regulation at the secondary-side output.
6
7
TC
I
I
Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor
from RSET to GND.
RSET
8
-
GND
DAP
G
G
Analog and power ground. Ground connection of internal control circuits and power MOSFET.
Die attach pad. Connect to PCB ground plane.
(1) P = Power, G = Ground, I = Input, O = Output.
Copyright © 2020, Texas Instruments Incorporated
3
LM5181-Q1
ZHCSL48 –APRIL 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1.5
–3
MAX
70
UNIT
VIN to GND
EN/UVLO to GND
TC to GND
70
6
Input voltage
SS/BIAS to GND
FB to GND
14
V
70.3
0.3
3
FB to VIN
RSET to GND
SW to GND
100
Output voltage
V
SW to GND (20-ns transient)
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002
HBM ESD Classification Level 2
±2000
(1)
V(ESD)
Electrostatic discharge
V
All pins except 1,
4, 5, and 8
Charged device model (CDM), per
AEC Q100-011
CDM ESD Classification Level C4B
±500
±750
Pins 1, 4, 5, and 8
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
NOM
MAX
65
UNIT
V
VIN
Input voltage
4.5
VSW
SW voltage
95
V
VEN/UVLO
VSS/BIAS
TJ
EN/UVLO voltage
SS/BIAS voltage
Operating junction temperature
65
V
13
V
–40
150
°C
7.4 Thermal Information
LM5181-Q1
THERMAL METRIC(1)
NGU (WSON)
8 PINS
41.3
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
34.7
19.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJB
19.2
RΘJC(bot)
3.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2020, Texas Instruments Incorporated
LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
7.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISHUTDOWN
IACTIVE
IACTIVE-BIAS
VSD-FALLING
VIN shutdown current
VIN active current
VEN/UVLO = 0 V
3
260
25
µA
µA
µA
V
VEN/UVLO = 2.5 V, VRSET = 1.8 V
VSS/BIAS = 6 V
350
40
VIN current with BIAS connected
Shutdown threshold
VEN/UVLO falling
0.3
ENABLE AND INPUT UVLO
VSD-RISING
VUV-RISING
Standby threshold
Enable threshold
VEN/UVLO rising
VEN/UVLO rising
VEN/UVLO falling
0.8
1.5
1
V
V
1.45
0.04
4.2
1.53
VUV-HYST
Enable voltage hysteresis
Enable current hysteresis
0.05
5
V
IUV-HYST
FEEDBACK
IRSET
VEN/UVLO = 1.6 V
5.5
µA
RSET current
RRSET = 12.1 kΩ
RRSET = 12.1 kΩ
IFB = 80 µA
100
µA
V
VRSET
RSET regulation voltage
FB to VIN voltage
FB to VIN voltage
1.191
–40
1.21
1.224
40
VFB-VIN1
VFB-VIN2
mV
mV
IFB = 120 µA
SWITCHING FREQUENCY
FSW-MIN
FSW-MAX
tON-MIN
Minimum switching frequency
12
350
140
kHz
kHz
ns
Maximum switching frequency
Minimum switch on-time
DIODE THERMAL COMPENSATION
VTC TC voltage
POWER SWITCHES
ITC = ±10 µA, TJ = 25°C
ISW = 100 mA
1.2
0.4
1.27
V
RDS(on)
MOSFET on-state resistance
Ω
SOFT-START AND BIAS
ISS
tSS
SS ext capacitor charging current
5
6
µA
ms
Internal SS time
VBIAS-UVLO-
RISE
BIAS enable voltage
VSS/BIAS rising
VSS/BIAS falling
5.5
5.75
0.88
V
VBIAS-UVLO-
HYST
BIAS UVLO hysteresis
190
mV
CURRENT LIMIT
ISW-PEAK
Peak current limit threshold
0.62
0.75
A
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
6
°C
°C
TSD-HYS
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5
LM5181-Q1
ZHCSL48 –APRIL 2020
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7.6 Typical Characteristics
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
90
85
80
75
70
5.2
5.15
5.1
5.05
5
4.95
4.9
VIN = 12V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
65
60
4.85
4.8
0
100
200
300 400
Output Current (mA)
500
600
700
0
100
200
300 400
Output Current (mA)
500
600
700
D002
D003
See 图 21
See 图 21
图 1. Efficiency versus Load
图 2. Output Voltage versus Load
18
15
12
9
VIN = 12 V
VIN = 24 V
VIN = 48 V
SW 20V/DIV
6
3
0
-50
1 ms/DIV
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D001
See 图 21
IOUT = 0.5 A
图 3. Primary-side Switching Waveform in BCM
图 4. Shutdown Quiescent Current versus Temperature
290
280
270
260
250
240
35
30
25
20
15
VIN = 12 V
VIN = 24 V
VIN = 48 V
VIN = 12 V
VIN = 24 V
VIN = 48 V
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D002
D003
VSS/BIAS = 6 V
图 5. Active Quiescent Current versus Temperature
图 6. Active Quiescent Current with BIAS versus
Temperature
6
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LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
Typical Characteristics (接下页)
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
102
104
102
100
98
101
100
99
98
96
0
10
20
30 40
Input Voltage (V)
50
60
70
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D004
D005
图 7. RSET Current versus Input Voltage
图 8. RSET Current versus Temperature
1.8
1.6
1.4
1.2
1
1.54
1.52
1.5
1.48
1.46
1.44
1.42
1.4
VEN/UVLO Rising
VEN/UVLO Falling
0.8
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D006
D007
图 9. TC Voltage versus Temperature
图 10. EN/UVLO Threshold Voltages versus Temperature
5.3
0.8
5.2
5.1
5
0.7
0.6
0.5
0.4
0.3
0.2
4.9
4.8
4.7
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D008
D009
图 11. EN/UVLO Hysteresis Current versus Temperature
图 12. MOSFET RDS(on) versus Temperature
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ZHCSL48 –APRIL 2020
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Typical Characteristics (接下页)
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
1
160
155
150
145
140
135
130
0.8
0.6
BCM / DCM
FFM
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D010
D011
图 13. Switch Peak Current Limits versus Temperature
图 14. Minimum Switch On-Time versus Temperature
380
13
370
360
350
340
330
320
12.5
12
11.5
11
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D012
D013
图 15. Minimum Switching Frequency versus Temperature
图 16. Maximum Switching Frequency versus Temperature
8
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LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
8 Detailed Description
8.1 Overview
The LM5181-Q1 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for
automotive and industrial systems requiring less than 4 W of isolated DC/DC power. This compact, easy-to-use
flyback converter with low IQ can be applied over a wide input voltage range from 4.5 V to 65 V, with operation
down to 3.5 V after start-up. Innovative frequency and current amplitude modulation enables high conversion
efficiency across the entire load and line range. Primary-side regulation of the isolated output voltage using
sampled values of the primary winding voltage eliminates the need for an opto-coupler or an auxiliary transformer
winding for feedback. Regulation performance that rivals that of traditional opto-coupler solutions is achieved
without the associated cost, solution size, and reliability concerns. The LM5181-Q1 converter services a wide
range of applications including IGBT-based motor drives, factory automation, and medical equipment.
8.2 Functional Block Diagram
VOUT
VIN
DFLY
NP : NS
DZ
COUT
5 mA
LM5181-Q1
SS/BIAS
BIAS
REGULATOR
CIN
EN/UVLO
Standby
1.5 V
1.45 V
VDD
VIN
DF
VDD UVLO
Shutdown
VIN
SAMPLED
FEEDBACK
THERMAL
SHUTDOWN
1.1 V
100-V Power
MOSFET
FB
SW
RSET
COMP
VDD
gm
VREF
TRIMMED
REFERENCE
CONTROL
LOGIC
RTC
RSET
FB
ILIM
TC
0.75 A
TC
REGULATION
VDD
RFB
SS/BIAS
GND
Internal SS
CSS
8.3 Feature Description
8.3.1 Integrated Power MOSFET
The LM5181-Q1 is a flyback dc/dc converter with integrated 100-V, 0.75-A N-channel power MOSFET. During
the MOSFET on-time, the transformer primary current increases from zero with a slope of VIN / LMAG (where LMAG
is the transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current.
When the MOSFET is turned off by the control logic, the SW voltage VSW swings up to approximately VIN + (NPS
× VOUT), where NPS = NP / NS is the primary-to-secondary turns ratio of the transformer. The magnetizing current
flows in the secondary side through the flyback diode, charging the output capacitor and supplying current to the
load. Duty cycle D is defined as tON / tSW, where tON is the MOSFET conduction time and tSW is the switching
period.
图 17 shows a typical schematic of the LM5181-Q1 PSR flyback circuit. Components denoted in red are optional
depending on the application requirements.
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ZHCSL48 –APRIL 2020
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Feature Description (接下页)
DFLY
T1
VIN
VOUT
DCLAMP
COUT
DOUT
RUV1
NP : NS
DF
CIN
VIN
EN/UVLO
SW
RUV2
RFB
LM5181
GND
FB
RSET
TC
SS/BIAS
RTC
RSET
CSS
图 17. LM5181-Q1 Flyback Converter Schematic (Optional Components in Red)
8.3.2 PSR Flyback Modes of Operation
The LM5181-Q1 uses a variable-frequency, peak current-mode (VFPCM) control architecture with three possible
modes of operation as illustrated in 图 18.
Frequency
foldback mode
(FFM)
Discontinuous conduction mode (DCM)
Boundary conduction mode (BCM)
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
% Total Rated Output Power
图 18. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load
The LM5181-Q1 operates in boundary conduction mode (BCM) at heavy loads. The power MOSFET turns on
when the current in the secondary winding reaches zero, and the MOSFET turns off when the peak primary
current reaches the level dictated by the output of the internal error amplifier. As the load is decreased, the
frequency increases to maintain BCM operation. The duty cycle of the flyback converter is given 公式 1.
10
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Feature Description (接下页)
V
+ VD ∂N
(
)
OUT
PS
D =
V
+ V
+ VD ∂N
(
)
IN
OUT
PS
where
•
VD is the forward voltage drop of the flyback diode as its current approaches zero
(1)
The output power in BCM is given by 公式 2, where the applicable switching frequency and peak primary current
in BCM are specified by 公式 3 and 公式 4, respectively.
2
LMAG ∂IPRI-PK(BCM)
POUT(BCM)
=
∂FSW(BCM)
2
(2)
1
FSW(BCM)
=
≈
’
LMAG
LMAG
NPS ∂ V
IPRI-PK(BCM)
∂
+
∆
∆
÷
÷
V
+ VD
OUT
(
)
IN
«
◊
(3)
(4)
2∂ V
(
+ VD ∂I
OUT
)
OUT
IPRI-PK(BCM)
=
V ∂D
IN
As the load decreases, the LM5181-Q1 clamps the maximum switching frequency to 350 kHz, and the converter
enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is proportional to the
peak primary current squared as given by 公式 5 and 公式 6. Thus, as the load decreases, the peak current
reduces to maintain regulation at 350-kHz switching frequency.
2
LMAG ∂IPRI-PK(DCM)
POUT(DCM)
=
∂FSW(DCM)
2
(5)
2∂IOUT ∂ V
+ VD
(
)
OUT
IPRI-PK(DCM)
=
LMAG ∂FSW(DCM)
(6)
(7)
LMAG ∂IPRI-PK(DCM) ∂FSW(DCM)
DDCM
=
V
IN
At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum
level of 0.15 A, or 20% of its 0.75-A peak value, and the MOSFET off-time extends to maintain the output load
requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases as
the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM5181-Q1 is
12 kHz, which sets a minimum load requirement of approximately 0.5% full load.
8.3.3 Setting the Output Voltage
To minimize output voltage regulation error, the LM5181-Q1 senses the reflected secondary voltage when the
secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB as shown
in 图 17, is determined using 公式 8.
RSET
RFB = V
+ VD ∂N
∂
(
)
OUT
PS
VREF
where
•
RSET is nominally 12.1 kΩ
(8)
11
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Feature Description (接下页)
8.3.3.1 Diode Thermal Compensation
The LM5181-Q1 employs a unique thermal compensation circuit that adjusts the feedback setpoint based on the
thermal coefficient of the forward voltage drop of the flyback diode. Even though the output voltage is measured
when the secondary current is effectively zero, there is still a non-zero forward voltage drop associated with the
flyback diode. Select the thermal compensation resistor using 公式 9.
RFB kW
»
ÿ
⁄
3
RTC kW =
∂
»
ÿ
⁄
NPS
TCDiode mV èC
» ÿ
⁄
(9)
The temperature coefficient of the diode voltage drop may not be explicitly provided in the diode data sheet, so
the effective value can be estimated based on the measured output voltage shift overtemperature when the TC
resistor is not installed.
8.3.4 Control Loop Error Amplifier
The inputs of the error amplifier include a level-shifted version of the FB voltage and an internal 1.21-V reference
set by the resistor at RSET. A type-2 internal compensation network stabilizes the converter. In BCM operation
when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.
The power MOSFET is subsequently turned off when an amplified version of the peak primary current exceeds
the error amplifier output.
8.3.5 Precision Enable
The precision EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis for
application specific power-up and power-down requirements. EN/UVLO connects to a comparator with a 1.5-V
reference voltage and 50-mV hysteresis. An external logic signal can be used to drive the EN/UVLO input to
toggle the output on and off for system sequencing or protection. The simplest way to enable the LM5181-Q1 is
to connect EN/UVLO directly to VIN. This allows the LM5181-Q1 to start up when VIN is within its valid operating
range. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in 图 19 to
establish a precision UVLO level.
LM5181
VCC
VIN
5 ꢀA
RUV1
EN/UVLO
+
RUV2
UVLO
Comparator
1.5 V
1.45 V
图 19. Programmable Input Voltage UVLO With Hysteresis
Use 公式 10 and 公式 11 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.
12
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Feature Description (接下页)
≈
’
÷
◊
RUV1
RUV2
V
= VUV-RISING 1+
∆
IN(on)
«
where
•
•
VUV-RISING and VUV-FALLING are the UVLO comparator thresholds
IUV-HYST is the hysteresis current
(10)
(11)
≈
’
÷
◊
RUV1
RUV2
V
= VUV-FALLING 1+
-IUV-HYST ∂RUV1
∆
IN(off)
«
where
•
•
VUV-RISING and VUV-FALLING are the UVLO comparator thresholds
IUV-HYST is the hysteresis current
The LM5181-Q1 also provides a low-IQ shutdown mode when the EN/UVLO voltage is pulled below a base-
emitter voltage drop (approximately 0.6 V at room temperature). If the EN/UVLO voltage is below this hard
shutdown threshold, the internal LDO regulator powers off, and the internal bias-supply rail collapses, shutting
down the bias currents of the LM5181-Q1. The LM5181-Q1 operates in standby mode when the EN/UVLO
voltage is between the hard shutdown and precision-enable thresholds.
8.3.6 Configurable Soft Start
The LM5181-Q1 has a flexible and easy-to-use soft-start control pin, SS/BIAS. The soft-start feature prevents
inrush current impacting the LM5181-Q1 and the input supply when power is first applied. This is achieved by
controlling the voltage at the output of the internal error amplifier. Soft start is achieved by slowly ramping up the
target regulation voltage when the device is first enabled or powered up. Selectable and adjustable start-up
timing options include a 6-ms internally-fixed soft start and an externally-programmable soft start.
The simplest way to use the LM5181-Q1 is to leave SS/BIAS open. The LM5181-Q1 employs an internal soft-
start control ramp and starts up to the regulated output voltage in 6 ms.
However, in applications with a large amount of output capacitance, higher VOUT or other special requirements,
the soft-start time can be extended by connecting an external capacitor CSS from SS/BIAS to GND. A longer soft-
start time further reduces the supply current needed to charge the output capacitors while sourcing the required
load current. When the EN/UVLO voltage exceeds the UVLO rising threshold and a delay of 20 µs expires, an
internal current source ISS of 5 µA charges CSS and generates a ramp to control the primary current amplitude.
Calculate the soft-start capacitance for a desired soft-start time, tSS, using 公式 12.
CSS nF = 5 ∂ t
ms
»
»
ÿ
ÿ
⁄
SS
⁄
(12)
CSS is discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.
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Feature Description (接下页)
8.3.7 External Bias Supply
DFLY
T1
VIN
VOUT
DCLAMP
COUT
DOUT
RUV1
NP : NS
DF
CIN
VIN
EN/UVLO
SW
RUV2
RFB
LM5181
GND
FB
DBIAS1
RSET
TC
SS/BIAS
DBIAS2
12 V
CBIAS
22 nF
RSET
NP : NAUX
图 20. External Bias Supply Using Transformer Auxiliary Winding
The LM5181-Q1 has an external bias supply feature that reduces input quiescent current and increases
efficiency. When the voltage at SS/BIAS exceeds a rising threshold of 5.5 V, bias power for the internal LDO
regulator can be derived from an external voltage source or from a transformer auxiliary winding as shown in 图
20. With a bias supply connected, the LM5181-Q1 then uses its internal soft-start ramp to control the primary
current during start-up.
When using a transformer auxiliary winding for bias power, the total leakage current related to diodes DBIAS1 and
DBIAS2 in 图 20 should be less than 1 µA across the full operating temperature range.
8.3.8 Minimum On-Time and Off-Time
When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the
SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage
inductance and can corrupt the secondary zero-current detection. To prevent such a situation, a minimum switch
off-time, designated as tOFF-MIN, of a maximum of 360 ns is set internally to ensure proper functionality. This sets
a lower limit for the transformer magnetizing inductance as discussed in Detailed Design Procedure.
Furthermore, noise effects as a result of power MOSFET turnon can impact the internal current sense circuit
measurement. To mitigate this effect, the LM5181-Q1 provides a blanking time after the MOSFET turns on. This
blanking time forces a minimum on-time, tON-MIN, of 140 ns.
8.3.9 Overcurrent Protection
In case of an overcurrent condition on the isolated output or outputs, the output voltage drops lower than the
regulation level since the maximum power delivered is limited by the peak current capability on the primary side.
The peak primary current is maintained at 0.75 A (plus an amount related to the 100-ns propagation delay of the
current limit comparator) until the output decreases to the secondary diode voltage drop to impact the reflected
signal on the primary side. At this point, the LM5181-Q1 assumes the output cannot be recovered and re-
calibrates its switching frequency to 9 kHz until the overload condition is removed. The LM5181-Q1 responds
with similar behavior to an output short circuit condition.
For a given input voltage, 公式 13 gives the maximum output current prior to the engagement of overcurrent
protection, where η is the efficiency. The typical threshold value for ISW-PEAK from the Specifications is 0.75 A.
14
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LM5181-Q1
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Feature Description (接下页)
ISW-PEAK
h
2
IOUT(max)
=
∂
≈
∆
«
’
÷
◊
VOUT
1
+
V
NPS
IN
(13)
A failsafe current limit set at 1.2 A, or 1.6 times the nominal peak current limit, provides redundant fault protection
in case of transformer short circuit or saturation effects. This initiates a 7.5-ms hiccup interval after eight
overcurrent events.
8.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to
overheating. Thermal shutdown turns off the device when the junction temperature exceeds 175°C to prevent
further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
LM5181-Q1 restarts when the junction temperature falls to 169°C.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
EN/UVLO facilitates ON and OFF control for the LM5181-Q1. When VEN/UVLO is below approximately 0.6 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 3 μA at VIN = 24 V. The LM5181-Q1 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.
8.4.2 Standby Mode
The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is
above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating.
The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action
and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.
8.4.3 Active Mode
The LM5181-Q1 is in active mode when VEN/UVLO is above the precision-enable threshold and the internal bias
rail is above its UV threshold. The LM5181-Q1 operates in one of three modes depending on the load current
requirement:
1. Boundary conduction mode (BCM) at heavy loads
2. Discontinuous conduction mode (DCM) at medium loads
3. Frequency foldback mode (FFM) at light loads
Refer to the PSR Flyback Modes of Operation section for more details.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM5181-Q1 requires only a few external components to convert from a wide range of supply voltages to one
or more isolated output rails. To expedite and streamline the process of designing of a LM5181-Q1-based
converter, a comprehensive LM5181-Q1 quick-start calculator is available for download to assist the designer
with component selection for a given application. WEBENCH® online software is also available to generate
complete designs, leveraging iterative design procedures and access to comprehensive component databases.
The following sections discuss the design procedure for both single- and dual-output implementations using
specific circuit design examples.
As mentioned previously, the LM5181-Q1 also integrates several optional features to meet system design
requirements, including precision enable, input UVLO, programmable soft start, output voltage thermal
compensation, and external bias supply connection. Each application incorporates these features as needed for
a more comprehensive design.
The application circuits detailed in the Typical Applications show LM5181-Q1 configuration options suitable for
several application use cases.
9.2 Typical Applications
For step-by-step design procedures, circuit schematics, bill of materials, PCB files, simulation and test results of LM5181-powered
implementations, refer to the TI reference designs library.
9.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 5 V, 0.5 A
The schematic diagram of a 5-V, 0.5-A PSR flyback converter is given in 图 21.
DFLY
VIN = 10 V...65 V
T1
VOUT = 5 V
IOUT = 0.5 A
DCLAMP
24 V
COUT
DOUT
RUV1
5.6 V
47 ꢀF
536 kW
3 : 1
CIN
DF
VIN
EN/UVLO
44 mH
2.2 ꢀF
SW
FB
RUV2
RFB
LM5181
100 kW
158 kW
GND
RSET
TC
SS/BIAS
RTC
RSET
CSS
130 kW
12.1 kW
47 nF
图 21. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 5 V, IOUT = 0.5 A
16
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LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
9.2.1.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in 表 1.
表 1. Design Parameters
DESIGN PARAMETER
Input voltage range
VALUE
10 V to 65 V
9.5 V on, 6.5 V off
5 V
Input UVLO thresholds
Output voltage
Rated load current, VIN = 24 V
Output voltage regulation
Output voltage ripple
0.5 A
±1.5%
< 100 mV
The target full-load efficiency is 87.5% based on a nominal input voltage of 24 V and an isolated output voltage
of 5 V. The LM5181-Q1 is chosen to deliver a fixed 5-V output voltage set by resistor RFB connected between the
SW and FB pins. The input voltage turnon and turnoff thresholds are established by RUV1 and RUV2. The required
components are listed in 表 2. Transformers for other designs are listed in 表 3.
表 2. List of Components for Design 1
REF DES QTY SPECIFICATION
VENDOR
AVX
PART NUMBER
12061C225K4T2A
CGA6N3X7R2A225K230AB
GCJ32DR72A225KA01L
HMK325B7225KMHP
CGA6P1X7S1A476M250AC
GRM32ER71A476KE15L
LMK325B7476MM-TR
Std
2.2 µF, 100 V, X7R, 1206, ceramic
TDK
CIN
1
2.2 µF, 100 V, X7R, 1210, ceramic, AEC-Q200
Murata
Taiyo Yuden
TDK
47 µF, 10 V, X7S, 1210, ceramic, AEC-Q200
47 µF, 10 V, X7R, 1210, ceramic
COUT
1
Murata
Taiyo Yuden
Std
CSS
1
1
1
1
1
1
1
1
1
1
1
1
47 nF, 16 V, X7R, 0402
DCLAMP
DF
Zener, 24 V, 1 W, PowerDI-123, AEC-Q101
Switching diode, 75 V, 0.25 A, SOD-323
Schottky diode, 40 V, 2 A, SOD-123
Zener, 5.6 V, 5%, SOD-523, AEC-Q101
158 kΩ, 1%, 0402
DFLZ24Q-7
CMDD4448
FSV340FP
BZX585-C5V6
Std
Diodes Inc.
Central Semi
Onsemi
DFLY
DOUT
RFB
Nexperia
Std
RSET
RTC
RUV1
RUV2
T1
12.1 kΩ, 1%, 0402
Std
Std
130 kΩ, 1%, 0402
Std
Std
536 kΩ, 1%, 0603
Std
Std
100 kΩ, 1%, 0402
Std
Std
44 µH, 1.4 A, 3 : 1, 8.2 × 8.6 × 9.6 mm
LM5181-Q1 PSR flyback converter, AEC-Q100, VSON-8
Würth Electronik
Texas Instruments
750318633
U1
LM5181QNGURQ1
表 3. Magnetic Components for Various Output Voltages
OUTPUT VOLTAGE (RANGE) TURNS RATIO
LMAG, ISAT
DIMENSIONS
VENDOR
PART NUMBER
750319117
3.3 V (up to 4 V)
4 : 1
40 µH, 1 A
5 V (4 V to 5.5 V)
12 V (5.5 V to 16 V)
24 V (16 V to 32 V)
48 V (32 V to 50 V)
15 V and –7.5 V dual
3 : 1
750318633
1 : 1
750318737
44 µH, 1 A
30 µH, 1 A
8.6 × 8.26 × 9.65 mm Würth Electronik
1 : 2
750318738
750319118
750319119
1 : 3
1 : 1.5 : 0.8
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5181-Q1 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the converter specifications using the LM5181-Q1 quick-start calculator.
9.2.1.2.3 Flyback Transformer – T1
Choose a turns ratio based on an approximate 60% max duty cycle at minimum input voltage using 公式 14,
rounding up or down as needed.
V
DMAX
0.6
10V
IN(min)
NPS
=
∂
=
∂
= 3
1-DMAX VOUT + VD 1- 0.6 5V + 0.3V
(14)
Select a magnetizing inductance based on the minimum off-time constraint using 公式 15. Choose a value of 44
µH and a saturation current of minimum 1 A for this application.
V
+ VD ∂NPS ∂ tOFF-MIN
)
ISW-PEAK(FFM)
5V + 0.3V ∂3∂360ns
(
(
)
0.15A
OUT
LMAG
í
=
= 38ꢀH
(15)
Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage
inductance can increase based on a higher number of primary turns, NP. The primary and secondary winding
RMS currents are given by 公式 16 and 公式 17, respectively.
D
IPRI-RMS
=
∂IPRI-PK
3
(16)
2∂IOUT ∂IPRI-PK ∂NPS
ISEC-RMS
=
3
(17)
Find the maximum output current for a given turns ratio using 公式 18, where the typical value for ISW-PEAK is the
0.75-A switch current peak threshold. Iterate by increasing the turns ratio if the output current capability is too low
at minimum input voltage.
0.42A at V = 12V
À
IN
ISW-PEAK
h
2
0.85 0.75A
Œ
IOUT(max)
=
∂
=
∂
=
Ã
2
≈
∆
«
’
÷
◊
≈
’
÷
◊
VOUT
1
5V
1
0.6A at V = 24V
Œ
Õ
IN
+
+
∆
«
V
NPS
V
3
IN
IN
(18)
18
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9.2.1.2.4 Flyback Diode – DFLY
The flyback diode reverse voltage is given by 公式 19.
V
65V
3
IN(max)
VD-REV
í
+ VOUT
=
+ 5V ö 27V
NPS
(19)
Select a 40-V, 3-A Schottky diode for this application to account for inevitable diode voltage overshoot and
ringing related to the resonance of transformer leakage inductance and diode parasitic capacitance. Connect an
appropriate RC snubber circuit (for example, 100 Ω and 22 pF) across the flyback diode if needed.
In general, choose a flyback diode with current rating greater than the maximum peak secondary winding current
of NPS × ISW-PEAK. As mentioned in the Layout section, place adequate copper at the cathode of the diode to
improve its thermal performance and prevent overheating during high ambient temperature or overload
conditions. Beware of the high leakage current typical of a Schottky diode at elevated operating temperatures.
9.2.1.2.5 Zener Clamp Circuit – DF, DCLAMP
Connect a diode-Zener clamping circuit across the primary winding to limit the peak switch-node voltage after
MOSFET turnoff below the maximum level of 95 V, as given by 公式 20.
VDZ(clamp) < VSW(max) - V
IN(max)
(20)
Choosing the zener, DCLAMP, with clamp voltage of approximately 1.5 times the reflected output voltage, as
specified by 公式 21, provides a balance between the maximum SW voltage excursion and the leakage
inductance demagnetization time.
VDZ(clamp) = 1.5∂NPS ∂ V
+ VD = 1.5∂3∂ 5V + 0.3V ö 24V
(
)
(
)
OUT
(21)
Select an ultra-fast switching diode or Schottky diode for DF with rated voltage greater than the maximum input
voltage and with low forward recovery voltage drop.
9.2.1.2.6 Output Capacitor – COUT
The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during a
load transient, and sets the dominant pole of the converter's small-signal response. For a flyback converter
specifically, the output capacitor supplies the load current when the main switch is on, therefore, the output
voltage ripple is a function of load current and duty cycle.
Select an output capacitance using 公式 22 to limit the ripple voltage amplitude to less than 1% of the output
voltage at minimum input voltage.
2
2
2
2
44ꢀH∂ 0.75A
LMAG ∂ISW-PEAK
(
)
1+ D
2
1+ 0.6
≈
’
≈
’
COUT
í
∂
=
∂
= 32ꢀF
∆
«
÷
◊
∆
«
÷
◊
2∂ DVOUT ∂ VOUT
2∂50mV ∂5V
2
(22)
Mindful of the voltage coefficient of ceramic capacitors, select a 47-µF, 10-V capacitor in 1210 case size with
X7S or better dielectric. 公式 23 gives the output capacitor RMS ripple current.
2∂NPS ∂IPRI-PK
ICOUT-RMS = IOUT
∂
-1
3 ∂IOUT
(23)
9.2.1.2.7 Input Capacitor – CIN
Select an input capacitance using 公式 24 to limit the ripple voltage amplitude to less than 5% of the input
voltage when operating at nominal input voltage.
2
D
≈
’
IPRI-PK ∂D∂ 1-
∆
÷
◊
2
«
CIN
í
2∂FSW ∂ DV
IN
(24)
19
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Substituting the input current at full load, switching frequency, peak primary current, and peak-to-peak ripple
specification gives CIN greater than 1 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 2.2-µF,
100-V ceramic input capacitor with X7R dielectric in 1210 case size. 公式 25 gives the input capacitor RMS ripple
current.
D ∂IPRI-PK
4
ICIN-RMS
=
∂
-1
2
3 ∂D
(25)
9.2.1.2.8 Feedback Resistor – RFB
Select a feedback resistor, designated RFB, of 158 kΩ based on the secondary winding voltage at the end of the
flyback conduction interval (the sum of the 5-V output voltage and the Schottky diode forward voltage drop)
reflected by the transformer turns ratio of 3 : 1. The forward voltage drop of the flyback diode is 0.3 V as its
current approaches zero.
V
+ VD ∂N
5V + 0.3V ∂3
(
)
0.1mA
(
)
OUT
PS
RFB
=
=
= 158 kW
0.1mA
(26)
9.2.1.2.9 Thermal Compensation Resistor – RTC
Select a resistor for output voltage thermal compensation, designated RTC, based on 公式 27.
RFB kW
»
ÿ
⁄
3
158
3
3
RTC kW =
∂
=
∂
= 130 kW
»
ÿ
⁄
NPS
TCDiode mV èC
1.2
»
ÿ
⁄
(27)
9.2.1.2.10 UVLO Resistors – RUV1, RUV2
Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds of 9.5 V and 6.5 V, respectively,
select the upper and lower UVLO resistors using the following expressions:
VUV-FALLING
VUV-RISING
IUV-HYST
1.45 V
1.5 V
5 ꢀA
V
∂
- V
IN(off)
9.5 V ∂
- 6.5 V
IN(on)
RUV1
=
=
= 536kW
(28)
(29)
VUV-RISING
1.5 V
9.5 V -1.5 V
RUV2 = RUV1
∂
= 536 kW ∂
= 100 kW
V
- VUV-RISING
IN(on)
Calculate the actual input turn-on and turn-off voltage thresholds as follows:
≈
’
÷
◊
RUV1
RUV2
≈
’
÷
◊
536 kW
100kW
V
= VUV-RISING 1+
= 1.5V 1+
= 9.54V
∆
∆
IN(on)
«
«
(30)
(31)
≈
’
RUV1
RUV2
≈
’
÷
◊
536kW
100kW
V
= VUV-FALLING 1+
-IUV-HYST ∂RUV1 = 1.45V 1+
- 5ꢀA ∂536kW = 6.54V
∆
÷
◊
∆
IN(off)
«
«
9.2.1.2.11 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on 公式 12 to achieve a soft-start time of 8 ms.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power Management
technical articles.
20
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LM5181-Q1
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ZHCSL48 –APRIL 2020
9.2.2 Application Curves
Unless otherwise stated, application performance curves were taken at TA = 25°C.
5.2
5.15
5.1
90
85
80
75
70
65
60
5.05
5
4.95
4.9
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
4.85
4.8
0
100
200
300 400
Output Current (mA)
500
600
700
0
100
200
300 400
Output Current (mA)
500
600
700
D003
D002
图 23. Load Regulation (Linear Scale)
图 22. Efficiency (Linear Scale)
SW 20V/DIV
VDFLY 5V/DIV
1 ms/DIV
1 ms/DIV
VIN = 24 V
IOUT = 0.5 A
VIN = 24 V
IOUT = 0.5 A
图 25. Flyback Diode Voltage
图 24. Switch Node Voltage
Average detector
Peak detector
Peak detector
Average detector
Start 150 kHz
Stop 30 MHz
Start 30 MHz
Stop 108 MHz
VIN = 24 V
IOUT = 0.5 A
LIN = 4.7 µH
CIN = 10 µF
VIN = 24 V
IOUT = 0.5 A
LIN = 4.7 µH
CIN = 10 µF
150 kHz to 30 MHz
30 MHz to 108 MHz
图 26. CISPR 25 Class 5 Conducted EMI Plot
图 27. CISPR 25 Class 5 Conducted EMI Plot
版权 © 2020, Texas Instruments Incorporated
21
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www.ti.com.cn
10 Power Supply Recommendations
The LM5181-Q1 PSR flyback DC/DC converter operates over a wide input voltage range from 4.5 V to 65 V. The
characteristics of the input supply must be compatible with the Specifications. In addition, the input supply must
be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input
current with 公式 32.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
where
•
η is the efficiency
(32)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special
care is required to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the
input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients. A typical ESR of 0.25 Ω provides enough damping
for most input circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.
22
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LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
11 Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI. 图 28 and 图 29 provide layout
examples for single-output and dual-output designs, respectively.
11.1 Layout Guidelines
PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate
noise and EMI or degrade the performance of the power supply.
1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place CIN
as close as possible to the LM5181-Q1 VIN and GND pins. Ground return paths for the input capacitor or
capacitors must consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
e-field or capacitive coupling.
4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding
terminals of the transformer.
5. Minimize the loop area formed by the flyback rectifying diode, output capacitor, and the secondary winding
terminals of the transformer.
6. Connect adequate copper at the cathode of the flyback diode to prevent overheating during overload or high
ambient temperature conditions.
7. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
8. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
9. Have a single-point ground connection to the plane. Route the return connections for the reference resistor,
soft-start, and enable components directly to the GND pin. This prevents any switched or load currents from
flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation
or erratic output voltage ripple behavior.
10. Make VIN+, VOUT+, and ground bus connections short and wide. This reduces any voltage drops on the input
or output paths of the converter and maximizes efficiency.
11. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin.
12. Locate components RSET, RTC, and CSS as close as possible to their respective pins. Route with minimal
trace lengths.
13. Place a capacitor between input and output return connections to route common-mode noise currents
directly back to their source.
14. Provide adequate heatsinking for the LM5181-Q1 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper
layers, connect these thermal vias to inner-layer ground planes. The connection to VOUT+ provides
heatsinking for the flyback diode.
版权 © 2020, Texas Instruments Incorporated
23
LM5181-Q1
ZHCSL48 –APRIL 2020
www.ti.com.cn
11.2 Layout Examples
Place the input capacitor close
to the VIN pin and connect to
the GND plane under the IC
Keep the DZ clamp and RC snubber
components close to the primary winding pins
Use adequate heatsinking
copper connected to the
cathode of the flyback
diode (VOUT)
Locate the converter IC close
to the transformer and connect
to the GND plane as shown
Keep the secondary
winding, flyback diode
and output capacitor
loop as tight as possible
Locate the RSET, TC and FB resistors and
the SS capacitor close to their respective pins
Place the Y-cap close to the transformer so that common-mode
currents from the secondary to the primary side return in a tight loop
图 28. Single-Output PCB Layout
Place the ceramic input
capacitor close to the IC to
minimize the switching loop area
Locate the converter IC close
to the transformer and connect
to the GND plane as shown
Minimize the area of the
secondary winding,
flyback diode and output
capacitor switching loops
Maintain the appropriate primary-
to-secondary clearance distance
Place the RSET, TC, FB and SS small-signal
components near their respective pins
图 29. Dual-Output PCB Layout
24
版权 © 2020, Texas Instruments Incorporated
LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.1.2 开发支持
凭借表 4 中的输入电压范围和电流特性，TI 的 PSR 反激式直流/直流转换器系列器件可提供灵活性、可扩展性和经
优化的解决方案尺寸，适用于各种 这些领域的严格功耗要求。通过采用尺寸为 4mm × 4mm、引脚间距为 0.8mm
的 8 引脚 WSON 封装，此类转换器可提供具有高功率密度、较少组件数的隔离式直流/直流解决方案。
表 4. PSR 反激式直流/直流转换器系列
最高负载电流（VOUT = 12V、NPS = 1）
PSR 反激式
直流/直流转换器
输入电压范围
峰值开关电流
VIN = 4.5V
90mA
VIN = 13.5V
180mA
360mA
360mA
600mA
1A
VIN = 24V
225mA
450mA
450mA
750mA
1.25A
LM5181-Q1
LM5180-Q1
LM25180-Q1
LM25183-Q1
LM25184-Q1
4.5V 至 65V
4.5V 至 65V
4.5V 至 42V
4.5V 至 42V
4.5V 至 42V
0.75A
1.5A
1.5A
2.5A
4.1A
180mA
180mA
300mA
500mA
有关开发支持，请参阅以下文档：
•
•
•
•
•
•
LM5181-Q1 快速入门计算器
LM5181-Q1 仿真模型
有关 TI 的参考设计库，请访问 TIDesigns
有关 TI 的 WEBENCH 设计环境，请访问 WEBENCH® 设计中心。
如需查看该产品的相关器件，请参阅 LM5180-Q1 产品页面。
TI Designs：
–
–
–
–
–
–
–
–
–
具有集成开关 PSR 反激式控制器的隔离式 IGBT 栅极驱动电源参考设计
适用于伺服驱动器的紧凑型、高效、24V 输入辅助电源参考设计
适用于电源隔离型超紧凑模拟输出模块的参考设计
具有 3 种 IGBT/SiC 偏置电源解决方案的 HEV/EV 牵引逆变器功率级参考设计
用于 IGBT/SiC 栅极驱动器且具有功率级的 4.5V 至 65V 输入、紧凑型偏置电源参考设计
通道至通道隔离式模拟输入模块参考设计
具有热敏二极管和感应 FET 的 SiC/IGBT 隔离式栅极驱动器参考设计
适用于 5G 电信整流器且效率超过 95% 的 1kW 模拟控制交流/直流参考设计
3.5W 汽车类双路输出 PSR 反激式稳压器参考设计
•
TI 技术文章：
–
–
–
《反激式转换器：双路输出优于单路输出》
《为服务器 PSU 选择辅助电源的常见挑战》
《在节省费用的同时最大程度地提高 PoE PD 效率》
版权 © 2020, Texas Instruments Incorporated
25
LM5181-Q1
ZHCSL48 –APRIL 2020
www.ti.com.cn
12.1.3 使用 WEBENCH® 工具创建定制设计方案
单击此处，使用 LM5181-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
《LM5180EVM-S05 EVM 用户指南》(SNVU592)
《LM5180EVM-DUAL EVM 用户指南》(SNVU609)
《LM25184EVM-S12 EVM 用户指南》 (SNVU680)
《无辅助 PSR 反激式转换器如何提高 PLC 可靠性和密度》 (SLYT779)
《为何在双电池 mHEV 系统中使用 PSR 反激式隔离转换器》 (SLYT791)
《IC 封装 特性 可提高严苛汽车和通信设备系统的可靠性》 (SNVA804)
《适用于 mHEV 应用的 PSR 反激式直流/直流转换器变压器设计 》 (SNVA805)
《反激式变压器设计在效率和 EMI 方面的注意事项》 (SLUP338)
《反激式 SMPS 设计内幕揭秘》 (SLUP261)
白皮书：
–
–
–
《评估适用于成本驱动型严苛应用的宽 VIN、低 EMI 同步降压 电路》 (SLYY104)
《电源的传导 EMI 规格概述》 (SLYY136)
《电源的辐射 EMI 规格概述》 (SLYY142)
•
《汽车启动仿真器用户指南》 (SLVU984)
12.3 接收文档更新通知
要接收文档更新通知，请转至 TI.com.cn 上的器件产品文件夹进行设置。单击右上角的通知我 进行注册，即可接收
产品信息更改每周摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
26
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LM5181-Q1
www.ti.com.cn
ZHCSL48 –APRIL 2020
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面具有机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2020, Texas Instruments Incorporated
27
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5181QNGURQ1
ACTIVE
WSON
NGU
8
4500 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
LM5181Q
NGUQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5181QNGURQ1
WSON
NGU
8
4500
330.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON NGU
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
LM5181QNGURQ1
8
4500
Pack Materials-Page 2
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
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