LM536005QDSXRQ1_技术文档

LM53600-Q1, LM53601-Q1

SNAS660D – JUNE 2015 – REVISED MAY 2021

LM53600/01-Q1 0.65-A/1-A, 36-V Synchronous, 2.1-MHz

Automotive Step-Down DC/DC Converter

1 Features

3 Description

•

Qualified for automotive applications

The LM53600-Q1 and LM53601-Q1 synchronous

buck regulator devices are optimized for automotive

applications, providing an output voltage of 5 V, 3.3 V,

or an adjustable output. Load current up to 650 mA

is supported by the LM53600-Q1, while the LM53601-

Q1 supports up to 1000 mA. Advanced high-speed

circuitry allows the LM53600-Q1 and LM53601-Q1

devices to regulate from an input of 18 V to an output

of 3.3 V at a fixed frequency of 2.1 MHz. Innovative

architecture allows the device to regulate a 3.3-V

output from an input voltage of only 3.8 V. The input

voltage range up to 36 V, with transient tolerance of

up to 42 V, eases input surge protection design. An

open drain reset output, with filtering and delayed

release, provides a true indication of system status.

This feature negates the requirement for an additional

supervisory component, saving cost and board space.

Seamless transitions between PWM and PFM modes,

along with a quiescent current of only 23 µA, ensures

high efficiency and superior transient response at all

loads. Few external components are needed allowing

the generation of compact PCB layout. While the

LM53600-Q1 and LM53601-Q1 devices are Q1 rated,

electrical characteristics are ensured across a junction

temperature range of –40°C up to 150°C.

AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to 125°C

ambient operating temperature range

– Device HBM classification level 2

– Device CDM classification level C5

–40°C to 150°C junction temperature range

(available)

Wide operating input voltage: 3.55 V to 36 V (with

transient to 42 V)

Spread spectrum option available

2.1-MHz fixed switching frequency

Low quiescent current: 23 μA

Shutdown current: 1.8 µA

Adjustable, 3.3-V, or 5-V output

Maximum current load: 650 mA for LM53600-Q1,

1000 mA for LM53601-Q1

Pin-selectable forced PWM mode

RESET output with filter and delay release

External frequency synchronization

Internal compensation, soft start, current limit, and

UVLO

•

10-lead, 3-mm × 3-mm SON package with

wettable and non-wettable flanks

2 Applications

Device Information

•

Automotive camera applications

Automotive driver assistance systems

Automotive body applications

PART NUMBER

LM53600-Q1

PACKAGE⁽¹⁾

BODY SIZE (NOM)

WSON (10)

3.00 mm x 3.00 mm

LM53601-Q1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

V_PU

R_PU

RESET

EN

AGND

FB

V_SUPPLY

LM53600

LM53601

VIN

VCC

C_VCC

SYNC/

MODE

BOOT

SW

C_BOOT

C_IN

L1

GND

C_OUT

(DAP)

Simplified Schematic – Fixed Output

Automotive 11.2-mm x 12.7-mm Layout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM53600-Q1, LM53601-Q1

SNAS660D – JUNE 2015 – REVISED MAY 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................6

7.6 System Characteristics............................................... 8

7.7 Timing Requirements..................................................9

7.8 Typical Characteristics..............................................10

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram......................................... 11

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................17

9 Applications and Implementation................................18

9.1 Application Information............................................. 18

9.2 Typical Applications.................................................. 19

9.3 Do's and Don't's........................................................ 26

10 Power Supply Recommendations..............................28

11 Layout...........................................................................29

11.1 Layout Guidelines................................................... 29

11.2 Layout Example...................................................... 31

12 Device and Documentation Support..........................32

12.1 Documentation Support.......................................... 32

12.2 Receiving Notification of Documentation Updates..32

12.3 Support Resources................................................. 32

12.4 Trademarks.............................................................32

12.5 Electrostatic Discharge Caution..............................32

12.6 Glossary..................................................................32

13 Mechanical, Packaging, and Orderable

Information.................................................................... 33

4 Revision History

Changes from Revision C (April 2021) to Revision D (May 2021)

Page

•

Added non-wettable flank options.......................................................................................................................1

Changes from Revision B (February 2016) to Revision C (April 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document. ................1

Changes from Revision A (December 2015) to Revision B (February 2016)

Page

•

Updated tables in the Device Comparison Table ...............................................................................................3

Removed last sentence in SYNC/MODE description in Pin Functions table in Pin Configuration and Functions

............................................................................................................................................................................4

Updated I_BParameter in Section 7.5 table.........................................................................................................6

Changed R_RESETMAX from "80" to "120" in Section 7.5 table...........................................................................6

Changed V_outto V_{out_3_3V}, V_{out_5V}, and V_{out_ADJ}for 3.3-V, 5-V, and ADJ output voltage options in Section 7.6

table....................................................................................................................................................................8

Corrected references for SNAU190 and SNAU191 in Section 12.1.1 .............................................................32

•

Changes from Revision * (June 2015) to Revision A (December 2015)

Page

•

Changed device status from product preview to production data.......................................................................1

2

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5 Device Comparison

LM53600-Q1 Devices

Spread

Part Number⁽¹⁾

Output Voltage

Package Qty ⁽²⁾

Wettable (WF)/Non-Wettable Flanks (non-

WF)

Spectrum

LM53600AQDSXRQ1

LM53600AQDSXTQ1

LM536003QDSXRQ1

LM536003QDSXTQ1

LM536005QDSXRQ1

LM536005QDSXTQ1

LM53600MQDSXRQ1

LM53600MQDSXTQ1

LM53600NQDSXRQ1

LM53600NQDSXTQ1

LM53600LQDSXRQ1

LM53600LQDSXTQ1

Adjustable

3.3 V

No

3000

250

WF

No

WF

No

3000

250

WF

3.3 V

No

WF

5.0 V

No

3000

250

WF

5.0 V

No

WF

Adjustable

3.3 V

Yes

3000

250

WF

3000

250

WF

3.3 V

WF

5.0 V

3000

250

WF

5.0 V

WF

LM53600MQUDSXRQ1 Adjustable

3000

Non-WF

(1) LM53600-Q1 devices have maximum recommended operating current of 650 mA.

(2) See Package Option Addendum for tape and reel details as well as links used to order parts.

LM53601-Q1 Devices

Spread

Part Number⁽¹⁾

Output Voltage

Package Qty ⁽²⁾

Wettable (WF)/Non-Wettable Flanks (non-WF)

Spectrum

LM53601AQDSXRQ1

LM53601AQDSXTQ1

LM536013QDSXRQ1

LM536013QDSXTQ1

LM536015QDSXRQ1

LM536015QDSXTQ1

LM53601MQDSXRQ1

LM53601MQDSXTQ1

LM53601NQDSXRQ1

LM53601NQDSXTQ1

LM53601LQDSXRQ1

LM53601LQDSXTQ1

Adjustable

3.3 V

No

3000

250

WF

No

WF

No

3000

250

WF

3.3 V

No

WF

5.0 V

No

3000

250

WF

5.0 V

No

WF

Adjustable

3.3 V

Yes

No

3000

250

WF

3000

250

WF

3.3 V

WF

5.0 V

3000

250

WF

5.0 V

WF

LM536015QUDSXRQ1 5.0 V

LM536013QUDSXRQ1 3.3 V

LM53601MQUDSXRQ1 Adjustable

3000

Non-WF

No

Yes

(1) LM53601-Q1 devices have maximum recommended operating current of 1000 mA.

(2) See Package Option Addendum for tape and reel details as well as links used to order parts.

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6 Pin Configuration and Functions

1

2

3

4

5

SW

GND 10

1

2

3

4

5

SW

GND 10

SYNC/

9

SYNC/

MODE

BOOT

VCC

FB

BOOT

VCC

FB

9

8

7

6

MODE

DAP

VIN

EN

8

7

6

DAP

VIN

EN

RESET

AGND

BIAS

Fixed Version

Adjustable Version

Figure 6-1. DSX Package 10-Pin WSON Top View

Table 6-1. Pin Functions

NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

1

SW

P

I

Regulator switch node. Connect to output inductor.

High side gate driver upper supply rail. Connect a 100-nF capacitor from SW pin to BOOT. An internal

diode charges the capacitor while SW node is low.

2

3

BOOT

Internal 3-V regulator output. Used as supply to internal control circuits. Connect a high quality 1.0-μF

capacitor from this pin to AGND for fixed versions or to GND for adjustable versions.

VCC

P

I/P

I

FB (Fixed

Versions)

Fixed version only, this pin serves as feedback for output voltage as well as power source for VCC’s

regulator. Connect to output node. Place 10-nF bypass capacitor immediately adjacent to this pin.

4

FB (ADJ

Version)

ADJ version only, this pin serves as feedback for output voltage only. Connect to output through a

voltage divider which determines output voltage set point.

AGND (Fixed

Version)

G

P

Fixed versions only, this is the ground to which input signals and FB are compared.

5

6

BIAS (ADJ

Version)

Power source for VCC’s regulator. Connect to output node. Place 10-nF bypass capacitor immediately

adjacent to this pin.

Open drain reset output. Connect to suitable voltage supply through a current limiting pull up resistor.

High = regulator OK, Low = regulator fault. Will go low when EN = low. See Detailed Description.

RESET

O

7

8

EN

I

Enable input to regulator. High = on, Low = off. Can be connected to Vin. Do not float.

Input supply to regulator. Connect input bypass capacitors directly between this pin and GND.

VIN

This is a multifunction mode control input which is tolerant of voltages up to input voltage. With a valid

synchronization signal at this pin, the device will switch in forced PWM mode at the external clock

frequency and synchronize with it at the rising edge of the clock. See the Electrical Characteristics

for synchronization signal specifications. With this input tied high, the device will switch at the internal

clock frequency in forced PWM mode. With this input tied low, the device will switch at the internal

clock frequency in AUTO mode with diode emulation at light load. Spread spectrum is disabled if there

is a valid synchronization signal. Do not float.

9

SYNC/MODE

GND

I

10

G

Bypass to VIN immediately adjacent to this pin.

DAP

(EXPO

SED

Connect to ground – The sole function of the DAP interface is the thermal improvement of the device,

Thermal a direct thermal connection to a ground plane is required. The DAP is not meant as an electrical

interconnect. Electrical characteristics are not ensured.

Thermal,

GND

PAD)

(1) G = Ground, I = Input, O = Output, P = Power

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)

MIN

–0.3

MAX

UNIT

VIN to GND⁽¹⁾

42

SW to GND⁽²⁾

VIN+0.3

3.6

42

BOOT to SW

EN to GND ⁽¹⁾

V

BIAS to GND: LM53600-Q1/LM53601-Q1-ADJ

FB to GND : LM53600-Q1/LM53601-Q1 - 3.3 V, LM53600-Q1/LM53601-Q1 - 5.0 V

FB to GND : LM53600-Q1/LM53601-Q1-ADJ

RESET to GND

16

5.5

8

RESET sink current⁽³⁾

8

mA

V

SYNC/MODE to GND⁽¹⁾

–0.3

–1

42

VCC

3.6

2

GND⁽⁴⁾to AGND (Fixed version only)

Storage temperature, T_stg

–40

150

°C

(1) A maximum of 42 V can be sustained at this pin for a duration of ≤100 ms at a duty cycle of ≤1%.

(2) A voltage of 2-V below GND and 2-V above VIN can appear on this pin for ≤200 ns with a duty cycle of ≤ 0.01%.

(3) Do not exceed pin’s voltage rating.

(4) This specification applies to voltage durations of 1 µs or less. The maximum D.C. voltage should not exceed ±0.3 V.

7.2 ESD Ratings

VALUE

±2000

UNIT

VIN, SW, CBOOT

Human body model (HBM), per AEC Q100-002⁽¹⁾

EN, BIAS, RESET, FB, SYNC,

PWM, VCC

V_(ESD)

Electrostatic discharge

V

Other pins

±750

Charged device model (CDM), per AEC Q100-011

Corner pins (1, 5, 6, and 10)

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)

MIN

3.8

0

NOM

MAX

36

UNIT

Input voltage range after startup⁽¹⁾

Output voltage range

V

5 V⁽²⁾

5.5

V

3.3 V⁽²⁾

0

3.63

6

Output adjustment range⁽³⁾for LM53600-Q1-ADJ ⁽²⁾, LM53601-Q1-ADJ⁽²⁾

3.3

0

LM53600-Q1

650

1000

150

Load current range

LM53601-Q1

mA

°C

0

Operating junction temperature⁽⁴⁾

–40

(1) An extended input voltage range to 3.55 V is possible; see Section 7.6. See input UVLO in Section 7.5 for startup conditions.

(2) Output voltage should not be allowed to fall below 0 V during normal operation.

(3) The LM53600-Q1 and LM53601-Q1 devices can operate outside of the listed range output voltage range. For output voltage outside of

the listed range, contact Texas Instruments concerning alternate application circuit BOM and additional operational limitations such as

higher I_Q.

(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

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7.4 Thermal Information

LM53600-Q1,

LM53601-Q1

THERMAL METRIC⁽¹⁾

UNIT

DSX (WSON)

10 PINS

46.2

R_{θ JA}

R_{θ JC}

R_{θ JB}

φ_JT

Junction -to-ambient thermal resistance

Junction -to-case (top) thermal resistance

°C/W

31.5

Junction -to-board thermal resistance

20.9

Junction- to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

φ_JB

21.0

R_{θ JC(bot)}

4.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

7.5 Electrical Characteristics

Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: V_in= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_FB

Initial output voltage accuracy V_in= 3.8 V to 36 V T_j=25°C, Open

Loop

–1%

1%

V_in= 3.8 V to 36 V, Open Loop

–1.5%

1.5%

I_Q

Operating quiescent current;

measured at V_INpin

V_in= 13.5 V, Not switching V_bias= 5 V

6.5

V_in= 13.5 V, Not switching V_bias= 5 V,

T_j= 85°C

16

80

µA

I_B

Bias current into BIAS pin for V_in= 13.5 V, Not switching V_bias= 5 V,

adjustable versions and FB pin Mode = 0 V

for fixed versions

46

1.8

3.6

I_SD

Shutdown quiescent current;

measured at V_INpin

EN = 0, VIN = 13.5 V T_j= 25°C

EN = 0, VIN = 13.5 V T_j= 85°C

Rising

3

V_{in_UVLO}

Minimum input voltage to

operate

3.2

3.75

V

V_{in_UVLO _hyst}

V_{reset_OV}

Minimum input voltage

hysteresis

Hysteresis

0.2

0.3

0.35

RESET upper threshold

voltage

Rising, % of Vout

Falling, % Vout

105%

106.5%

110%

V_{reset_UV}

RESET lower threshold

voltage

92%

94%

1%

97%

V_{reset_guard}

Magnitude of RESET lower

threshold difference from

steady state output voltage

Steady state output voltage and

RESET threshold read at the same

T_J, and V_IN

3.9%

V_{reset_hyst}

RESET hysteresis as a

percent of output voltage set

point

V_{reset_valid}

Minimum input voltage for

proper RESET function

50 µA pull-up to RESET pin, EN = 0

V, T_j= 25°C

1.5

0.4

V

50 µA pull-up to RESET pin, Vin =

1.5 V, EN = 0 V, T_j= 25°C

Low level RESET function

output voltage

0.5mA pull-up to RESET pin, Vin =

13.5 V, EN = 0 V

V_OL

1mA pull-up to RESET pin, Vin =

13.5 V, EN = 3.3 V

6

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Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: V_in= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= 13.5 V, Center frequency with

spread spectrum, PWM operation

1.89

2.1

2.4

V_IN= 13.5 V, Without spread

spectrum, PWM operation

1.89

2.1

1.0

2.4

F_sw

Switching frequency

MHz

V_IN= 36 V, 3.3-V fixed output device

and adjustable devices regardless of

output voltage

V_IN= 36 V, 5-V fixed output device

Output setting + 1 V < V_IN< 18 V

High state input < 5.5 V and > 2.3 V

1.5

2.1

F_SYNC

D_SYNC

Sync frequency range

1.9

25%

1.5

2.3

MHz

Sync input duty cycle range

75%

SYNC/MODE input high

(MODE=FPWM)

SYNC/MODE input threshold

voltage

V_SYNC/MODE

SYNC/MODE input low (MODE =

AUTO with diode emulation)

0.4

1

V

SYNC/MODE input hysteresis

0.185

F_SSS

F_PSS

Frequency span of spread

spectrum operation⁽²⁾

±4%

Spread spectrum pattern

frequency⁽²⁾

30

Hz

Vin = 13.5 V, V_SYNC/MODE= 3.3 V

V_IN= V_SYNC/MODE= 13.5 V

1

5

I_SYNC/MODE

SYNC/MODE leakage current

µA

µs

To FPWM Mode 20 mA load, V_IN

13.5 V

=

100

Mode change transition time

t_MODE

(2)

To AUTO Mode 20-mA load, V_IN

13.5 V

=

60

1.35

1.83

LM53600-Q1 Duty cycle approaches

0%

1.0

1.5

1.65

2.1

High side switch current limit

I_{L_HS}

A

(1)

LM53601-Q1 Duty cycle approaches

0%

LM53600-Q1

LM53601-Q1

0.65

1.0

0.78

1.2

0.93

1.43

I_{L_LS}

I_{L_ZC}

Low side switch current limit

A

Zero-cross current limit

MODE/SYNC = Low

–0.01

LM53600-Q1

–0.7

220

200

-

Negative current limit MODE/

SYNC = High

I_{L_NEG}

A

LM53601-Q1

High side MOSFET Rdson

Low side MOSFET Rdson

mΩ

R_dson

V_EN

Power switch on-resistance

Enable input threshold voltage Enable rising

- rising

1.7

2.0

V

V_{EN_HYST}

V_{EN_WAKE}

I_EN

Enable threshold hysteresis

Enable Wake-up threshold

0.40

0.4

-

0.55

V

Enable pin input current

V_IN= V_EN= 13.5 V

2.7

3.05

3.15

2.7

µA

V_IN= 13.5 V, V_bias= 0 V

V_IN= 13.5 V, V_bias= 3.3 V

VCC rising

V_cc

Internal Vcc voltage

V

V_{cc_UVLO}

Internal Vcc input under

voltage lock-out

V_{cc_UVLO_hyst}

Input under voltage lock-out

hysteresis

Hysteresis below V_{cc_uvlo}

190

mV

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Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: V_in= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_FB

Input current from FB to

AGND

LM53600-Q1-ADJ, FB = 1 V

20

nA

T_j= 25°C

0.993

0.985

1

1.007

1.015

120

Reference voltage for ADJ

option only

V_ref

V

R_RESET

T_SD

Rdson of RESET output

50

Ω

Thermal shutdown rising

threshold⁽²⁾

151

140

167

185

T_SDF

Thermal shutdown falling

threshold⁽²⁾

157

10

°C

T_{SD_hyst}

Thermal shutdown

hysteresis⁽²⁾

Fsw = 2.1 MHz

76%

D_max

Maximum switch duty cycle⁽²⁾

While in frequency fold back

96%

(1) High side current limit is a function of duty factor. Current limit value is highest at small duty factor and less at higher duty factors.

(2) Ensured by design, statistical analysis and production testing of correlated parameters; not tested in production.

7.6 System Characteristics

The following specifications are ensured by design provided that the component values in the typical application circuit

are used. These parameters are not ensured by production testing. Limits apply to the recommended operating junction

temperature range of –40°C to 150°C, unless otherwise noted. Minimum and Maximum limits are ensured through test,

design or statistical correlation. Typical values represent the most likely parametric norm at Tj = 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: Vin = 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

3.55

3.8

UNIT

Minimum input voltage for full

functionality at 500-mA load, after

start-up

V_OUT= 3.3 V

V_{in_min}

V

Minimum input voltage for full

functionality at 100% of max rated

load, after start-up

V_OUT= 3.3 V

V

V_IN= 4.0 V to 36 V, I_OUT= Maximum

recommended load current

3.23

4.9

3.3

3.33

5

3.37

3.39

V_{out_3_3V}

Output voltage for 3.3-V option

Output voltage for 5-V option

V_IN= 3.8 V to 36 V, I_OUT=100 µA to

100 mA, typical value in Auto Mode

V_IN= 5.8 V to 36 V, I_OUT= Maximum

recommended load current

5.1

V_{out_5V}

V

V_IN= 5.5 V to 36 V, I_OUT=100 µA to

100 mA, typical value in Auto Mode

4.9

5.05

5.125

+2%

V_IN= V_OUT+ 0.6 V to 36 V, I_OUT

100 mA, FPWM mode

=

–2%

V_{out_ADJ}

Output voltage ADJ option

V_IN= V_OUT+ 0.6 V to 36 V, I_OUT=100

µA to 100 mA, Auto mode

+2.5%

V_IN= V_OUT+ 1 V to 36 V, I_OUT= 0 A

to 1 A, T_J= 125°C, FPWM mode

Load regulation for ADJ option⁽¹⁾

–1%

(2)

I_{Q_VIN}

Input current to V_INnode of DC/DC

utilizing the LM53600-Q1/LM53601-

Q1

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 0

A

23

30

µA

V

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 0 A

Minimum input to output voltage

differential to maintain regulation

accuracy, without inductor DCR drop

V_OUT=3.3 V, I_OUT=1000 mA, +2/–3%

output accuracy

V_DROP1

0.6

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The following specifications are ensured by design provided that the component values in the typical application circuit

are used. These parameters are not ensured by production testing. Limits apply to the recommended operating junction

temperature range of –40°C to 150°C, unless otherwise noted. Minimum and Maximum limits are ensured through test,

design or statistical correlation. Typical values represent the most likely parametric norm at Tj = 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: Vin = 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum input to output voltage

differential to maintain F_SW≥ 1.85

MHz, without inductor DCR drop

V_OUT= 3.3 V, I_OUT=1000 mA, F_SW

1.85 MHz, 2% regulation accuracy

=

V_DROP2

2.0

V

V_IN= 13.5 V, V_OUT= 5.0 V, I_OUT= 1

A

85%

80%

86%

83%

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 1

A

Typical Efficiency without inductor

loss

Efficiency

V_IN= 13.5 V, V_OUT= 5.0 V, I_OUT

0.65 A

=

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT

0.65 A

=

(1) 125°C is worst case temperature for load regulation. Layout is critical since adjustable option does not have an AGND terminal.

(2) See Section 8.3.7 in Section 8 for the meaning of this specification and how it can be calculated.

7.7 Timing Requirements

Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: V_in= 13.5 V.

MIN

NOM

50

90

6

MAX

80.5

125

8

UNIT

t_on

Minimum switch on time⁽¹⁾

Minimum switch off time⁽¹⁾

Delay time to RESET high signal

V_IN= 18 V, I_OUT= 500 mA

I_OUT= 500 mA

ns

t_off

t_{reset_act}

4

ms

µs

t_{reset_filter}Glitch filter time constant for RESET function

24

3

t_SS

t_EN

t_W

Soft-start time

Time from first SW node

pulse to Vref at 90%, V_IN

≥4.2 V

1.3

4.5

ms

Turn-on delay⁽²⁾

Time from EN high until first

SW node pulse. V_IN= 13.5,

Cvcc = 1 µF

0.7

4.5

ms

Short circuit wait time (Hiccup time)

(1) See Section 8

(2) Ensured by design, statistical analysis and production testing of correlated parameters; not tested in production.

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7.8 Typical Characteristics

V_IN= 13.5 V, T_A= 25°C (unless otherwise noted). Specified temperatures are ambient.

75

72

69

66

63

60

57

54

51

48

45

95

93

91

89

87

85

83

81

79

77

75

-40 -20

0

20

40

60

80 100 120 140

-40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D013

D014

Device Type = 3.3-V Fixed Output

Input Voltage = 20 V

Device Type = 1 A

Output = 4.85 V

5-V Fixed Output In Dropout

Load = 500 mA

Figure 7-1. Minimum On-Time vs Temperature

Figure 7-2. Minimum Off-Time vs Temperature

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

Rising

Falling

Margin

93

92

Rising

Falling

-40 -20

0

20

40

60

80 100 120 140

-40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D015

D016

Margin is the difference between the falling RESET threshold

and actual regulation voltage which includes the effects of

temperature.

Figure 7-3. Upper RESET Threshold

Figure 7-4. Lower Reset Threshold

101

100.8

100.6

100.4

100.2

100

1.9

1.8

1.7

Rising

Falling

1.6

99.8

99.6

99.4

99.2

99

1.5

1.4

1.3

-40 -20

0

20

40

60

80 100 120 140

-40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D017

D018

Figure 7-5. Normalized V_FBvs Temperature

Figure 7-6. EN Threshold vs Temperature

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8 Detailed Description

8.1 Overview

The LM53600-Q1 and LM53601-Q1 devices are wide-input voltage range, low quiescent current, high-

performance regulators with internal compensation designed specifically for the automotive market. These

devices are designed to minimize end product cost and size while operating in demanding automotive

environments. Normal operating frequency is 2.1 MHz allowing the use of small passive components. State

of the art current limit allows the use of inductors that are smaller than those typically used in a 650mA or

1000mA regulator. 2.1MHz is above the AM band, allowing significant saving in input filtering. This part has a

low unloaded current consumption eliminating the need for an external back-up LDO. The low shutdown current

and high maximum operating voltage of the LM53600-Q1 and LM53601-Q1 devices also allows the elimination

of an external load switch. To further reduce system cost, an advanced reset output is provided, which can often

eliminate the use of an external reset or supervisory device.

The LM53600-Q1 and LM53601-Q1 devices are AEC Q1 qualified, and also have electrical characteristics

ensured up to a maximum junction temperature of 150°C.

8.2 Functional Block Diagram

VCC

VIN

Int. Reg.

Bias

EN

BOOT

HS Current

Sense

Voltage

Reference

Error

Amplifier

FB

COMP

Control Logic

Driver

SW

+

-

+

-

LS Current

Sense

RESET

OSC

Control

SYNC/MODE

AGND

GND

Figure 8-1. Fixed Versions

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BIAS VCC

VIN

Int. Reg.

Bias

EN

BOOT

HS Current

Sense

Voltage

Reference

Error

Amplifier

COMP

Control Logic

Driver

SW

+

-

+

-

FB

LS Current

Sense

RESET

OSC

Control

SYNC/MODE

GND

Figure 8-2. Adjustable Versions

8.3 Feature Description

8.3.1 Control Scheme

The control scheme of the LM53600-Q1 and LM53601-Q1 devices allows this part to operate under a wide

range of conditions with a low number of external components. Peak current mode control allows a wide

range of input voltages and output capacitance values, while maintaining a constant switching frequency. Stable

operation is maintained while output capacitance is changed during operation as well. This allows use in

systems that require high performance during load transients and which have load switches which remove loads

as system operating state changes. Short minimum on- and off-times ensure constant frequency regulation over

a wide range of conversion ratios. These on- and off- times allow for a duty factor window of 13% to 77% at

2.1-MHz switching frequency.

This architecture uses frequency foldback in order to achieve low dropout voltage maintaining output regulation

as the input voltage falls close to output voltage. The frequency foldback is smooth and continuous, and

activated as off-time approaches its minimum. Under these conditions, the LM53600-Q1 and LM53601-Q1

devices operate much like a constant off-time converter allowing maximum duty cycle to reach 97%, which

allows output voltage regulation with 600-mV dropout.

If input voltage exceeds approximately 21 V, frequency is reduced smoothly as a function of input voltage.

This frequency reduction allows output voltage regulation and current mode control to operate with duty factor

below 13%. Since current mode control continues at high input voltage insensitivity to output capacitance is

maintained. This form of fold back will not be active if input voltage is below 18 V, insuring constant frequency

operation over normal automotive operating conditions.

High input voltage foldback has two settings; see F_SWunder 36-V input conditions for detail. Since adjustable

output voltage versions fold back under high input voltage conditions as though output voltage were 3.3 V, larger

inductance and output capacitance is required if an adjustable device is used with output voltage above 4.2

V. If a 4.7-µH inductor is used in system with greater 4.2-V output using an adjustable device, the converter

remains stable but may not achieve full output current when operating at high input voltages, such as 36 V, due

to excessive inductor current ripple.

As load current is reduced, the LM53600-Q1 and LM53601-Q1 devices transition to light load mode if SYNC/

MODE is low. In this mode, diode emulation is used to reduce RMS inductor current and switching frequency is

reduced. Also, fixed voltage versions do not need a voltage divider connected to FB saving additional power. As

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a result, only 23 µA (typical, while converting 13.5 V to 3.3 V) is consumed to regulate output voltage if output is

unloaded. Average output voltage increases slightly while lightly loaded.

8.3.2 Soft-Start Function

Soft-start time is fixed internally at about 3.0 ms. Soft-start is achieved by ramping the internal reference. The

LM53600-Q1 and LM53601-Q1 devices operate correctly even if there is a voltage present on output before

activation of the LM53600-Q1 or LM53601-Q1.

8.3.3 Current Limit

The LM53600-Q1 and LM53601-Q1 devices use two current limits which allow the use of smaller inductors than

systems utilizing a single current limit. A coarse high side or peak current limit is provided to protect against

faults and saturated inductors. High side current limit limits the duration of high sides FET's on period during

a given clock cycle. A precision valley current limit prevents excessive average output current from the Buck

converter of the LM53600-Q1 and LM53601-Q1 devices. A new switching cycle is not initiated until inductor

current drops below the valley current limit. This scheme allows use of inductors with saturation current rated

less than twice the rated operating current of the LM53600-Q1 or LM53601-Q1.

Vout

Peak

Valley

Figure 8-3. Current Limit Operation

Figure 8-3 shows the response of the LM53600-Q1 or LM53601-Q1 device to a short circuit: Peak current limit

prevents excessive peak current while valley current limit prevents excessive average inductor current. After a

small number of cycles, hiccup mode is activated.

8.3.4 Hiccup Mode

In order to prevent excessive heating and power consumption under sustained short circuit conditions, a hiccup

mode is included. If an over current condition is maintained, the LM53600-Q1 or LM53601-Q1 device shuts

off its output and waits for t_W(approximately 4.5 ms), after which the LM53600-Q1 or LM53601-Q1 restarts

operation beginning by activating soft start.

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Vout

Figure 8-4. Hiccup Operation

Figure 8-4 shows hiccup mode operation: The switch node of the LM53600-Q1 LM53601-Q1 is high impedance

after a short circuit or over current persists for a short duration. Periodically, the LM53600-Q1 or LM53601-Q1

attempts to restart. If the short has been removed before one of these restart attempts, the LM53600-Q1 or

LM53601-Q1 operates normally.

8.3.5 RESET Function

While the reset function of the LM53600-Q1 and LM53601-Q1 devices resembles a standard power good

function, its functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major

differences between the reset function and the normal power good function seen in most regulators:

•

A delay has been added for release of reset. See waveforms below.

RESET output signals a fault (pulls its output to ground) while the part is disabled.

RESET continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET output may

be high impedance.

Input Voltage

Output Voltage

Input Voltage

t_{reset_filter}

tt_{reset_act}

t

tt_{reset_act}

t

t_{reset_filter}

tt_{reset_act}

t

V_{reset_OV}

V_{reset_hyst}

t_{reset_filter}

V_{reset_UV}

V_{in_UVLO}(rising)

V_{in_UVLO}œ V_{in_UVLO_hyst}

V_{reset_valid}

GND

3.3 V

LM53600/01

RESET

RESET may not

be valid if input is

below V_{reset_valid}

Small glitches

do not reset

timer

Small glitches do not

cause RESET to

signal a fault

RESET may not

be valid if input is

below V_{reset_valid}

Startup

delay

Soft start

complete

OV activates

RESET

RESET continues to

operate below V_{in_UVLO}

Figure 8-5. Reset Output Function Operation

The following table summarizes conditions that cause a fault to be flagged by RESET . Once a fault is flagged,

RESET will not be released (become high impedance) until either there is no fault for t_{reset_act}or VIN drops

below V_{reset_valid}

.

Table showing conditions that cause RESET to signal a fault (pull low).

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FAULT CONDITION ENDS (AFTER WHICH T_{reset_act}MUST PASS

BEFORE RESET OUTPUT IS RELEASED)

FAULT CONDITION INITIATED

FB below V_{reset_UV}for longer than t_{reset_filt}

FB above V_{reset_OV}for longer than t_{reset_filt}

Junction temperature exceeds T_SD

EN low

FB above V_{reset_UV}+ V_{reset_hyst}for longer than t_{reset_filt}

FB below V_{reset_OV}- V_{reset_hyst}for longer than t_{reset_filt}

Junction temperature falls below T_SD– T_{SD_hyst}

t_ENpasses after EN becomes high⁽¹⁾

VIN falls below V_{in_UVLO}- V_{in_UVLO _hyst}or VCC pin falls below

V_{cc_UVLO}- V_{cc_UVLO_hyst}

Voltage on V_INexceeds V_{in_UVLO}and VCC exceed V_{cc_UVLO}

(1) As an additional safety feature, RESET remains low until approximately 1ms after soft start ends even if all other conditions in this

table are met and t_{reset_act}has passed. Lockout during soft start does not require t_{reset_act}to pass before RESET is released.

The threshold voltage for the RESET function is specified taking advantage of the availability of the LM53600-Q1

internal feedback threshold to the RESET circuit. This allows a maximum threshold of 97% of selected output

voltage to be specified at the same time as 95.7% of actual operating point. The net result is a more accurate

reset function while expanding the system allowance for transient response without the need for extremely

accurate internal circuitry. See output voltage error stack up comparison, below.

System with

external reset IC

System using the LM53600/01's

internal reset function

SMPS upper limit

+5%

LM53600/01 max

reference value

-1.5%

1.5%

SMPS nominal

output voltage

0%

1.5% LM53600/01

-1.5%

accuracy

LM53600/01 min

reference value

-1.5%

-3.5%

Available margin for ripple

and transient response

-4.5%

Available margin for ripple

and transient response

Offset between

reference voltage

and nominal

SMPS lower limit,

RESET should not trip

above this voltage

-5.5%

-7%

-5%

-6.5%

-8%

threshold voltage

1.5%

Nominal external

reset IC threshold

1%

1% Reset threshold accuracy with

respect to LM53600/01 reference voltage

-1%

Nominal threshold

setting if reference

is 1.5% low

1.5% Reset IC

-1.5%

accuracy

RESET must trip

Figure 8-6. Reset Threshold Voltage Stack Up

8.3.6 Forced PWM Operation

When constant frequency operation is more important than light load efficiency, the SYNC/MODE input of the

LM53600-Q1 and LM53601-Q1 devices should be pulled high, or a valid synchronization input be provided.

Once activated, this feature ensures that the switching frequency will stay above the AM frequency band, while

operating between the minimum and maximum duty cycle limits. Essentially, the diode emulation feature is

turned off in this mode. This means that the device will remain in CCM under light loads. Under conditions where

the device must reduce the on-time or off-time below the ensured minimum to maintain regulation, the frequency

will reduce to maintain the effective duty cycle required for regulation. This occurs for very high and very low

input/output voltage ratios.

This feature may be activated and deactivated while the part is regulating without removing the load. This feature

activates and deactivates gradually, over approximately 40 µs, preventing perturbation of output voltage. When

in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the

regulators output to its input.

Note that while FPWM is activated, larger currents pass through the inductor, if lightly loaded, than in auto mode.

This may result in more EMI, though at a predictable frequency. Once loads are heavy enough to necessitate

CCM operation, FPWM mode has no measurable effect on regulator operation.

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8.3.7 Auto Mode Operation and I_{Q_VIN}

If SYNC/MODE is held low for a period greater than a few microseconds, the LM53600-Q1 and LM53601-Q1

devices will enable automatic power saving light load operation and diode emulation. In this mode, if peak

current needed to regulate output voltage drops below a selected value, the clock of the LM53600-Q1 or

LM53601-Q1 device slows to maintain regulation. The gain of this clock slowing circuit is low to maintain stability.

Output voltage with no load is approximately 1% higher than with a load high enough to allow full frequency

operation.

I_{Q_VIN}is the current consumed by a converter utilizing a LM53600-Q1 or LM53601-Q1 device while regulating

without a load. While operating without a load, the LM53600-Q1 or LM53601-Q1 is only powering itself. The

LM53600-Q1 and LM53601-Q1 device draws power from two sources, its VIN pin, I_Q, and either its FB pin for

fixed versions or BIAS pin for adjustable versions, I_B. Since BIAS or FB is connected to the circuit’s output,

the power consumed is converted from input power with an effective efficiency, η_eff, of ~80%. Here, effective

efficiency is the added input power needed when lightly loading the converter of the LM53600-Q1 and LM53601-

Q1 devices is divided by the corresponding additional load. This allows unloaded current to be calculated as

follows:

Output Voltage

I_{Q_ VIN}= I_Q+I_EN+ I +I

(

)

B

div

h_effìInput Voltage

(1)

where

•

I_{Q_VIN}is the current consumed by the Buck converter utilizing the LM53600-Q1 or LM53601-Q1 while

unloaded.

•

I_Qis the current drawn by the LM53600-Q1 or LM53601-Q1 from its VIN terminal. See I_Qin section 7.6.

I_ENis current drawn by the LM53600-Q1 or LM53601-Q1 from its EN terminal. Include this current if EN is

connected to VIN. See I_ENin section 7.6. Note that this current drops to a very low value if connected to a

voltage less than 5 V.

•

I_Bis bias/feedback current drawn by the LM53600-Q1 or LM53601-Q1 while the Buck converter utilizing it is

unloaded. See I_Bin section 7.6.

I_divis the current drawn by the feedback voltage divider used to set output voltage for adjustable devices.

This current is zero for fixed output voltage devices.

η_effis the light load efficiency of the Buck converter with I_{Q_VIN}removed from the Buck converter’s input

current. 0.8 is a conservative value that can be used under normal operating conditions

Note that the EN pin consumes a few microamperes when tied to high; see I_EN. Add I_ENto I_Qas shown in the

above equation if EN is tied to V_IN. If EN is tied to a voltage less than 5 V, virtually no current is consumed

allowing EN to be used as a UVL once a voltage divider is added.

8.3.8 SYNC Operation

Often it is desirable to synchronize the operation of multiple regulators in a single system. This technique

results in better defined EMI and can reduce the need for capacitance on some power rails. The LM53600-Q1

and LM53601-Q1 devices provide a SYNC/MODE input, which allows synchronization with an external clock.

The LM53600-Q1/LM53601-Q1 implements an in-phase locking scheme – the rising edge of the clock signal

provided to the input of the LM53600-Q1 or LM53601-Q1 device corresponds to turning on the high side

device within the LM53600-Q1 or LM53601-Q1. This function is implemented using phase locking over a limited

frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the

LM53600-Q1 or LM53601-Q1 device replaces the internal free running clock but does not affect frequency

fold-back operation. Output voltage will continue to be well regulated with duty factors outside of the normal 15%

through 77% range though at reduced frequency.

The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.

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8.3.9 Spread Spectrum

The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Section

5.

The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading

emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems

containing the LM53600-Q1 and LM53601-Q1 devices, low frequency conducted emissions from the first few

harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of

emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment

through electric fields around the switch node. The LM53600-Q1 and LM53601-Q1 devices use a ±4% spread

of frequencies which spread energy smoothly across the FM band but is small enough to limit sub-harmonic

emissions below its switching frequency. Peak emissions at the part’s switching frequency are only reduced by

slightly less than 1 dB, while peaks in the FM band are typically reduced by more than 6dB.

The LM53600-Q1 and LM53601-Q1 devices use a cycle to cycle frequency hopping method based on a linear

feedback shift register (LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to

limit output ripple. Pseudo random pattern repeats by approximately 7 Hz which is below the audio band.

The spread spectrum is only available while the clock of the LM53600-Q1 and LM53601-Q1 devices is free

running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

1. An external clock is applied to the SYNC/MODE terminal.

2. The clock is slowed due to operation low input voltage – this is operation in dropout.

3. The clock is slowed due to high input voltage – input voltage above approximately 21 V disables spread

spectrum.

4. The clock is slowed under light load in Auto mode – this is normally not seen above 200 mA of load. In

FPWM mode, spread spectrum is active even if there is no load.

8.4 Device Functional Modes

8.4.1 Shutdown

The LM53600-Q1 and LM53601-Q1 devices shut down most internal circuitry and both high side and low side

power switches connected to its switch node under any of the following conditions:

1. EN is below V_EN

2. VIN is below V_{in_UVLO}

3. Junction temperature exceeds T_SD

Note that the above conditions have hysteresis. Also, RESET remains active to a very low input voltage,

V_{reset_valid}

.

8.4.2 FPWM Operation

If SYNC/MODE is above V_SYNC/MODEhigh or a valid synchronizing is applied to SYNC/MODE, constant

frequency operation is maintained across load. This requires negative current be allowed in the inductor if load is

light. If a large negative load is present, operation is halted by a reverse current limit, I_L-NEG

.

8.4.3 Auto Mode Operation

If SYNC/MODE is below V_SYNC/MODElow, reverse current in the inductor is not allowed – this feature is called

diode emulation. While load is heavy, operation is the same as in FPWM operation. If load is light, switching

frequency is reduced saving energy and allowing regulation to be maintained. Note that while under loads

which require moderate reduction of frequency, pulses often are seen if small groups, often called burst mode

operation, which can increase output ripple. Under this condition, output ripple can be reduced by increasing

output capacitance.

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9 Applications and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LM53600-Q1 and LM53601-Q1 are step-down DC–DC converters, typically used to convert a higher DC

voltage to a lower DC voltage with a maximum output current of either 1 A or 650 mA. The following design

procedure can be used to select components for the LM53600-Q1 or LM53601-Q1. Alternately, the WEBENCH^®

Design Tool may be used to generate a complete design. This tool utilizes an iterative design procedure and

has access to a comprehensive database of components. This allows the tool to create an optimized design and

allows the user to experiment with various design options.

Figure 9-1 shows the minimum required application circuit for the fixed output voltage versions, while Figure 9-2

shows the connections for complete processor control of the LM53601-Q1. Please refer to these figures while

following the design procedures. Table 9-2 provides an example of typical design requirements.

V_PU

R_PU

RESET

EN

AGND

FB

C_BIAS

0.01 µF

LM53600

LM53601

V_SUPPLY

VIN

VCC

(Fixed output

voltage)

C_VCC

1 µF

SYNC/

MODE

BOOT

SW

C_BOOT

0.1 µF

C_{IN_HF}

0.1 µF

C_IN

(Includes

Filter)

GND

L1

4.7 µH

10 µF

C_OUT(includes load)

≥ 20 µF

(DAP)

Figure 9-1. Off Battery, Automotive, Fixed Output Voltage, Buck, 2.1 MHz, Spread Spectrum

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V_PU

R_PU

RESET

EN

BIAS

FB

C_BIAS

0.01 µF

R_FBT

R_FBB

V_SUPPLY

LM53600

LM53601

(Adjustable)

VIN

VCC

C_VCC

1 µF

SYNC/

MODE

BOOT

SW

C_BOOT

0.1 µF

C_{IN_HF}

0.1 µF

C_IN

(Includes

Filter)

GND

L1

4.7 µH (≤ 4.2 V output)

6.8 µH (> 4.2 V output)

10 µF

C_OUT(includes load)

≥ 20 µF (≤ 4.2 V output)

≥ 30 µF (> 4.2 V output)

(DAP)

Figure 9-2. Off Battery, Automotive, Adjustable Output Voltage, Buck, 2.1 MHz, Spread Spectrum

9.2 Typical Applications

9.2.1 Off-Battery 5-V, 1-A Output Automotive Converter with Spread Spectrum

V_PU

LM53601LQDSXRQ1

100k

AGND

RESET

FB

EN

C_BIAS

0.01 µF

VBATT (6 V to 18 V, 42 V Max)

VIN

VCC

C_VCC

1 µF

SYNC/

MODE

C_BOOT

0.1 µF

BOOT

SW

Typically

part of load

C_{IN_HF}

0.1 µF

CIN2

4.7µF

CIN1

4.7µF

GND

L1

4.7 µH

COUT2

10 µF

COUT1

10 µF

(DAP)

Figure 9-3. Typical LM53601LQDSXRQ1 Application Schematic

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9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters.

Table 9-1. Design Parameters

DESIGN PARAMETER

Input voltage range

VALUE

COMMENT

This converter will run continuously up to 36 V

Fixed option used

6 V to 18 V with excursions to 42 V

Output voltage

5 V

Output current range

Light load mode

Spread spectrum

No Load to 1 A

Switchable

Enabled

Factory option

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Inductor Selection

The LM53600-Q1 and LM53601-Q1 devices run in current mode and has internal compensation. This

compensation is stable with inductance between 4 µH and 10 µH. For most applications, 4.7 µH should be

used with fixed 5-V and 3.3-V versions of the LM53600-Q1 and LM53601-Q1 devices. The output inductor is

limited by current ripple while operating at high input voltage to a minimum rating of 4.7 µH for 3.3 V and

5-V fixed output devices. Since adjustable devices operate at the same frequency under high input voltage

conditions as devices set to deliver 3.3 V, inductor current ripple at high input voltages can become excessive

while using a 4.7µH while using an adjustable device that is delivering output voltage above 4.2 V. 6.8 µH is

recommended if an adjustable device is used to produce output voltage above 4.2 V. Not exceeding 6.8 µH is

recommended since use of large inductance causes poor transient load response. For the LM53601-Q1 (1-A

output), a saturation rating of about 2 A is recommended since this is the maximum current limit rating. Likewise,

a saturation current rating of about 1.5 A is recommended for the LM53600-Q1. See I_{L_HS}in the data sheet.

Table 9-2. Output Inductor

RECOMMENDED

MINIMUM SATURATION

CURRENT⁽²⁾

RECOMMENDED

PART TYPE

COMMENT

INDUCTANCE RATING⁽¹⁾

LM53601-Q1 3.3 V

and 5 V

4.7 µH

about 2 A

about 1.5 A

6.8 µH works in systems with less demanding transient load

requirements

LM53601-Q1 ADJ set 4.7 µH

to ≤ 4.2-V output

LM53601-Q1 ADJ set 6.8 µH

to > 4.2-V output

LM53600-Q1 3.3 V

and 5 V

4.7 µH

LM53600-Q1 ADJ set 4.7 µH

to ≤ 4.2-V output

Up to 10 µH works in systems with less demanding transient

load requirements

LM53600-Q1 ADJ set 6.8 µH

to > 4.2-V output

(1) The values shown in this table are standard inductance ratings. The LM53600-Q1/LM53601-Q1 tolerates reduced inductance due to

DC current and temperature.

(2) The LM53600-Q1/LM53601-Q1 tolerates partial saturation of inductors (reduction of ~40% reduction of inductance of the current value

listed due to saturation. Partial saturation may reduce maximum current available at maximum voltage).

9.2.1.2.2 Output Capacitor Selection

The current mode control scheme of the LM53600-Q1 and LM53601-Q1 devices allows operation over a wide

range of output capacitance. A minimum of 10 µF is needed to ensure stability. Capacitance above 20 µF

is recommended to ensure load transient response typically desired in systems. 40 µF is recommended for

applications with demanding load transient requirements and for which Auto mode ripple is important. 40 µF also

aids devices with output voltage below 4-V transition into high voltage mode. Capacitance above 400 µF can

cause excessive current to be drawn during start up so is not recommended. These capacitance values include

load capacitance – only 10 µF is needed near to the LM53600-Q1 and LM53601-Q1 devices. Output capacitors

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should have low ESR to reduce output ripple. These capacitors should have at least X7R rating and should be of

automotive grade if used in automotive applications.

Table 9-3. Output Capacitor

RECOMMENDED

LM53600-Q1 AND LM53601-Q1

TYPE AND SYSTEM NEED

MINIMUM

TOTAL OUTPUT

CAPACITANCE

COMMENTS

LM53600-Q1 5 V

20 µF

Approximately 200-mV/A step load response with 1-µs rise/fall time.

LM53601-Q1 5 V with typical

system requirements

20 µF

40 µF

LM53601-Q1 5V in high

performance systems

Approximately 150-mV/A step load, approximately 20-mV maximum Auto mode

ripple

LM53600-Q1/LM53601-Q1 3.3 V

and adjustable parts with less

than 4.2-V output setting with

typical system requirements

Approximately 200-mV/A step load response with 1µs rise/fall time, up to 60 mV of

ripple during transition into high voltage mode and in Auto mode.

20 µF

LM53600-Q1/LM53601-Q1 3.3 V

and adjustable parts with less

than 4.2 V in high performance

systems

Approximately 150-mV/A step load, approximately 30-mV maximum Auto mode

ripple, and 15-mV maximum HV mode transition ripple.

40 µF

LM53600-Q1 ADJ set to greater

than 4.2-V output

Larger capacitance is necessitated by higher inductance needed.

9.2.1.2.3 Input Capacitor Selection

Input capacitors serve two important functions: The first is to reduce input voltage ripple into the LM53601-Q1

and the input filter of the system. The second is to reduce high frequency noise. These two functions are

implemented most effectively with separate capacitors, see Table 9-4.

Table 9-4. Input Capacitor

RECOMMENDED

CAPACITOR

COMMENT

VALUE

This capacitor is used to suppress high frequency noise originating during switching events. It is

important to place capacitor as close to the LM53600-Q1 and LM53601-Q1 devices as design rules

allow. Position is more important than exact capacity. Once high frequency propagates into a system,

it can be hard to suppress or filter. Since this capacitor will be exposed to battery voltage in systems

that operate directly off of battery, 50 V or greater rating is recommended.

C_{IN_HF}

0.1 µF

10 µF

This capacitance is used to suppress input ripple and transients due to output load transients. If

CIN is too small, input voltage may dip during load transients resetting the system if the system is

operated under low voltage conditions. 10 µF is intended to include all capacitance in the LM53600-

Q1/LM53601-Q1’s input node. 4.7 µF adjacent to the LM53600-Q1 and LM53601-Q1 devices is

recommended. Since this capacitor will be exposed to battery voltage in systems that operate directly

off of battery, 50 V or greater rating is recommended.

C_IN

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Table 9-5 shows recommended capacitor values other than input and output capacitors.

Table 9-5. Other Capacitors

MINIMUM

VALUE

CAPACITOR

C_BOOT

COMMENT

0.1 µF

While a voltage rating of only 5 V is necessary, using a higher voltage rating is recommended.

While a voltage rating of only 5 V is necessary, 16-V capacitors have a low voltage coefficient.

This capacitor should be rated to survive output voltage.

C_VCC

C_BIAS

1 µF

0.01 µF

Note that performance of converters utilizing an adjustable version of the LM53600-Q1 and LM53601-Q1

devices may be enhanced by adding C_FF, a capacitor in parallel with R_FBT. 100 pF is recommended.

9.2.1.2.4 FB Voltage Divider for Adjustable Versions

The adjustable version of the LM53600RB-Q1 and LM53601RB-Q1 devices regulates output voltage to a level

that results in the FB node being V_refwhich is approximately 1.0 V; see Section 7.5 Output voltage given a

specific feedback divider can be calculated using the following equation:

R_FBB+ R_FBT

R_FBB

Output Voltage = V_ref

ì

(2)

See typical applications schematic for adjustable versions of the LM53600-Q1 and LM53601-Q1 devices. Since

the value of R_FBTis typically set by board leakage considerations, the above equation can be solved for R_FBB

the remaining unknown:

,

V

ìR_FBT

ref

R_FBB

=

Output Voltage - V

ref

(3)

Note that typically, 100 kΩ is used for R_FBT

.

9.2.1.2.5 R_PU- RESET Pull Up Resistor

While RESET is rated to sink up to 8 mA, under low, 1.5-V input voltage conditions, a low output level is only

ensured with loads of 50 µA. If accurate RESET output is needed with 1.5-V input voltage, 100 kΩ should be

used to pull up to 5 V, or a 66-kΩ resistor should be used when pulling up to a 3.3-V supply. If input voltage

is above 3.8 V, values as low as 10 kΩ or 6.6 kΩ can be used to pull up to 5 V or 3.3 V, respectively. Other

considerations, such as power consumption may increase any of the values listed above.

9.2.1.3 Application Curves

The following characteristics apply only to the circuit shown in Figure 9-3. These parameters are not tested and represent

typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 13.5 V, T_A= 25°C.

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100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

60

Input Voltage

8 V

Input Voltage

8 V

13.5 V

18 V

36 V

18 V

36 V

60

0

0.005 0.01

0.1

Output Current (A)

1

0.2

0.4 0.6

Output Current (A)

0.8

1

D002

D001

Device Type = 1 A Mode = Auto

5-V Fixed Output

Device type = 1 A

Mode = High

5-V Fixed Output

Figure 9-5. Efficiency

Figure 9-4. Efficiency

5.1

800

600

400

200

0

5.05

5

4.95

Ambient

25 èC

FPWM Mode

Auto Mode

125 èC

4.9

0

0.2

0.4 0.6

Output Current (A)

0.8

1

0

0.2

0.4 0.6

Output Current (A)

0.8

1

D005

D007

Device Type = 1 A

5-V Fixed Output

Device Type = 1 A

5-V Fixed Output

92-mΩ Inductor

Output = 4.85 V

Figure 9-6. Load Regulation

Figure 9-7. Dropout Voltage

1.8

1.6

1.4

1.2

1

2.5

2

1.5

1

0.8

0.6

0.4

0.2

0

0.5

0

Ambient

25 èC

125 èC

0

0.2

0.4 0.6

Output Current (A)

0.8

1

0

5

10

15

20

25

Input Voltage (V)

30

35

40

D009

D011

Device Type = 1 A

5-V Fixed Output

92-mΩ inductor

Device Type = 1 A

5-V Fixed Output

Load = 500 mA

Spread Spectrum

Frequency drops to 1.85MHz

Figure 9-8. Entry into Dropout

Figure 9-9. Frequency vs. Input Voltage

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SW (2 V/DIV)

Time (1 ms/DIV)

Time (200 ns/DIV)

D019

D020

Device Type = 1 A

Load = 10 mA

5-V Fixed Output

Mode = Auto

Device Type = 1 A

Mode = Auto

5-V Fixed Output

Load = 500 mA

Figure 9-10. SW Node Operation

Figure 9-11. SW Node Operation

9.2.2 Off-Battery 3.3 V, 1 A Output Automotive Converter with Spread Spectrum

V_PU

LM53601NQDSXRQ1

100k

AGND

RESET

FB

EN

C_BIAS

0.01 µF

VBATT (4 V to 18 V, 42 V Max)

VIN

VCC

C_VCC

1 µF

Typically part

of load

SYNC/

MODE

C_BOOT

0.1 µF

BOOT

SW

C_{IN_HF}

0.1 µF

CIN2

CIN1

4.7µF

GND

L1

4.7 µH

COUT1

10 µF

CLOAD

22 µF

COUT2

10 µF

(DAP)

Figure 9-12. Typical LM53601NQDSXRQ1 Application Schematic

9.2.2.1 Design Requirements

For this design example, use the parameters in Table 9-6 as the input parameters.

Table 9-6. Design Parameters

DESIGN PARAMETER

Input voltage range

VALUE

COMMENT

4 V to 18 V with excursions to 42 V This converter will run continuously up to 36 V

Output voltage

3.3 V

Fixed option used

Factory option

Output current range

Light load mode

Spread spectrum

No load to 1 A

Switchable

Enabled

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9.2.2.2 Design Procedure

The same detailed design procedure as shown starting in section 7.1.2.1 is used to create the schematic

for this example. The most important difference is that the LM53601NQDSXRQ1 is used in place of the

LM53601LQDSXRQ1. In addition, more output capacitance is recommended for this option. Most output

capacitance will be part of the load and be used as input bypassing for the load.

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9.2.2.3 Application Curves

The following characteristics apply only to the circuit shown in Figure 9-12. These parameters are not tested and represent

typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 13.5 V, T_A= 25°C.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

Input Voltage

8 V

13.5 V

18 V

36 V

Input Voltage

8 V

13.5 V

18 V

36 V

0

0.2

0.4 0.6

Output Current (A)

0.8

1

0.005 0.01

0.1

Output Current (A)

1

D003

D004

Device Type = 1 A

Mode = FPWM

3.3-V Fixed Output

Device Type = 1 A

Mode = Auto

3.3-V Fixed Output

Figure 9-13. Efficiency

Figure 9-14. Efficiency

3.366

3.333

3.3

800

600

400

200

3.267

Ambient

25 èC

125 èC

FPWM Mode

Auto Mode

3.234

0

0.2

0.4 0.6

Output Current (A)

0.8

1

0.2

0.4 0.6

Output Current (A)

0.8

1

D006

D008

Device Type = 1 A

3.3-V Fixed Output

Device Type = 1 A Output = 3.2 V

3.3-V Fixed Output

92-mΩ Inductor

Figure 9-15. Load Regulation

Figure 9-16. Dropout Voltage

1.8

1.6

1.4

1.2

1

2.5

2

1.5

1

0.8

0.6

0.4

0.2

0

0.5

0

Ambient

25 èC

125 èC

0

0.2

0.4 0.6

Output Current (A)

0.8

1

0

5

10

15

20

Input Voltage (V)

25

30

35

40

D010

D012

Device Type = 1 A

92-mΩ Inductor

3.3-V Fixed Output

Frequency Drops to 1.85 MHz

Device Type = 1 A

3.3-V Fixed Output

Spread Spectrum

Load = 500 mA

Figure 9-17. Entry into Dropout

Figure 9-18. Frequency vs. Input Voltage

9.3 Do's and Don't's

•

Don't: Exceed the Section 7.1.

Don't: Exceed the Section 7.2.

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•

Don't: Exceed the Section 7.3.

Don't: Allow the EN, FPWM or SYNC input to float.

Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

Don't: Use the thermal data given in the Thermal Information table to design your application.

Do: Follow all of the guidelines and/or suggestions found in this data sheet, before committing your design to

production. TI Application Engineers are ready to help critique your design and PCB layout to help make your

project a success.

•

Do: Refer to the helpful documents found in Table 11-1 and Table 11-2.

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10 Power Supply Recommendations

The LM53600-Q1 and LM53601-Q1 devices are designed for automotive direct off battery applications needing

minimal protection. Protection recommended includes reverse battery protection and EMI/ESD filtering. The

LM53600-Q1 and LM53601-Q1 devices are able to continue regulating during load dump with peak voltage less

than 42 V, double battery (jump start) conditions down to input voltage as low as V_DROPabove the selected

output voltage. In addition, the LM53600-Q1 and LM53601-Q1 devices continue to operate though may be out of

regulation with input voltage as low as 3.8 V. This allows the LM53600-Q1 and LM53601-Q1 devices to operate

through cranking in all but the most demanding systems.

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input

capacitors, can form an under-damped resonant circuit. This circuit may cause over-voltage transients at the VIN

pin, each time the input supply is cycled on and off. The parasitic resistance will cause the voltage at the VIN

pin to dip when the load on the regulator is switched on, or exhibits a transient. If the regulator is operating close

to the minimum input voltage, this dip may cause the device to shutdown and/or reset. The best way to solve

these kinds of issues is to reduce the distance from the input supply to the regulator and/or use an aluminum or

tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors will help to

damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is

usually sufficient to provide input damping and help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead

to instability, as well as some of the effects mentioned above, unless it is designed carefully. The Simple

Success with Conducted EMI for DC–DC Converters User's Guide (SNVA489) provides helpful suggestions

when designing an input filter for any switching regulator

In some cases, a Transient Voltage Suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not

recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less

than the output voltage of the regulator, the output capacitors will be discharged through the regulator back to

the input. This uncontrolled current flow could damage the regulator.

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11 Layout

11.1 Layout Guidelines

The following list is in order of importance starting with the most important item:-

•

Place high frequency input bypass capacitor, Cinhf, as close to the LM53600-Q1 and LM53601-Q1 devices

as possible.

•

Connect AGND and GND to the DAP immediately adjacent to the LM53600-Q1 and LM53601-Q1 devices.

Do not interrupt the ground plain under the loop containing the VIN and GND pins and Cinhf of the LM53600-

Q1 and LM53601-Q1 devices.

•

The boot capacitor, CBOOT, should be close to the LM53601-Q1 and the loop from the SW pin, through the

boot capacitor and into the BOOT pin should be kept as small as possible.

Keep the SW node as small as possible. It should be wide enough to carry the converter’s full current without

significant drop.

•

4.7 µF of bypassing should be close to the input of the LM53600-Q1 and LM53601-Q1 devices.

Place CVCC, the VCC pin’s bypass, and CBIAS, the bypass for FB for fixed voltage devices and BIAS for

adjustable devices as close to the LM53600-Q1 and LM53601-Q1 devices as possible.

The first output the trace from the output inductor to the output node should run by an output capacitor before

joining the rest of the output node.

•

Keep 10 µF close to the output (output inductor and GND) of the LM53600-Q1 and LM53601-Q1 devices.

Clear the layer beneath the SW node.

Table 11-1. PCB Layout Resources

TITLE

LINK

AN-1149 Layout Guidelines for Switching Power Supplies

AN-1229 Simple Switcher PCB Layout Guidelines

Constructing Your Power Supply- Layout Considerations

SNVA021

SNVA054

SLUP230

SNVA721 Low Radiated EMI Layout Made SIMPLE with LM4360x

SNVA721

and LM4600x

VIN

CIN

SW

GND

Figure 11-1. Current Loops with Fast Transients

11.1.1 Ground and Thermal Plane Considerations

As mentioned above, it is recommended to use one of the middle layers as a solid ground plane. A ground

plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the

control circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to

the bypass capacitors. PGND pins are connected to the source of the internal low side MOSFET switch. They

should be connected directly to the grounds of the input and output capacitors. The PGND net contains noise

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at the switching frequency and may bounce due to load variations. The PGND trace, as well as PVIN and SW

traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much

less noise and should be used for sensitive routes.

It is recommended to provide adequate device heat sinking by utilizing the exposed pad (EP) of the IC as the

primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the EP to the system ground

plane for heat sinking. The vias should be evenly distributed under the exposed pad. Use as much copper as

possible for system ground plane on the top and bottom layers for the best heat dissipation. It is recommended

to use a four-layer board with the copper thickness, starting from the top, as: 2 oz / 1 oz / 1 oz / 2 oz. A

four-layer board with enough copper thickness and proper layout provides low current conduction impedance,

proper shielding and lower thermal resistance.

Table 11-2. Resources for Thermal PCB Design

TITLE

LINK

AN-2020 Thermal Design By Insight, Not Hindsight

SNVA419

AN-1520 A Guide to Board Layout for Best Thermal Resistance for

SNVA183

SPRA953

SNVA719

Exposed Pad Packages

SPRA953B Semiconductor and IC Package Thermal Metrics

SNVA719 Thermal Design made Simple with LM43603 and

LM43602

SLMA002 PowerPAD^™Thermally Enhanced Package

SLMA004 PowerPAD Made Easy

SLMA002

SLMA004

SBVA025

SBVA025 Using New Thermal Metrics

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11.2 Layout Example

Figure 11-2. Fixed Output Version

Figure 11-2 shows an example layout for a fixed output version of the LM53600-Q1 and LM53601-Q1 similar

to the one used in the Rev A EVM. Note that the via next to CBIAS connects on the back side of the board to

VOUT near CO1. This layout shows 10 µF of output capacitance and 4.7 µF of input capacitance. An additional

>10 µF of output capacitance and about 4.7 µF of input capacitance is assumed to be elsewhere in the system.

A solid, unbroken ground plane is under this entire circuit except immediately below the SW node.

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation request the following:

AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)

Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x (SNVA721)

Constructing Your Power Supply – Layout Considerations (SLUP230)

AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054)

Using New Thermal Metrics (SBVA025)

PowerPAD Made Easy (SLMA004)

PowerPAD^™Thermally Enhanced Package (SLMA002)

Thermal Design made Simple with LM43603 and LM43602 (SNVA719)

Semiconductor and IC Package Thermal Metrics (SPRA953)

AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)

AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages (SNVA183)

Simple Success with Conducted EMI for DC-DC Converters User's Guide (SNVA489)

EVM User's Guide for Adjustable Versions of the LM53600-Q1 and LM53601-Q1 (SNAU190)

EVM User's Guide for Fixed Versions of the LM53600-Q1 and LM53601-Q1 (SNAU191)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

PowerPAD^™are trademarks of TI.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

32

Submit Document Feedback

Product Folder Links: LM53600-Q1 LM53601-Q1

LM53600-Q1, LM53601-Q1

SNAS660D – JUNE 2015 – REVISED MAY 2021

www.ti.com

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

33

Product Folder Links: LM53600-Q1 LM53601-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM536003QDSXRQ1

LM536003QDSXTQ1

LM536005QDSXRQ1

LM536005QDSXTQ1

LM53600AQDSXRQ1

LM53600AQDSXTQ1

LM53600LQDSXRQ1

LM53600LQDSXTQ1

LM53600MQDSXRQ1

LM53600MQDSXTQ1

WSON

DSX

10

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

3.3

1.0

8.0

12.0

Q2

3000

250

3000

250

3000

250

3000

250

LM53600MQUDSXRQ1 WSON

3000

250

LM53600NQDSXRQ1

LM53600NQDSXTQ1

LM536013QDSXRQ1

LM536013QDSXTQ1

LM536013QUDSXRQ1

LM536015QDSXRQ1

LM536015QDSXTQ1

WSON

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM536015QUDSXRQ1

LM53601AQDSXRQ1

LM53601AQDSXTQ1

LM53601LQDSXRQ1

LM53601LQDSXTQ1

LM53601MQDSXRQ1

LM53601MQDSXTQ1

WSON

DSX

10

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

3.3

1.0

8.0

12.0

Q2

3000

250

3000

250

LM53601MQUDSXRQ1 WSON

3000

250

LM53601NQDSXRQ1

LM53601NQDSXTQ1

WSON

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM536003QDSXRQ1

LM536003QDSXTQ1

LM536005QDSXRQ1

LM536005QDSXTQ1

LM53600AQDSXRQ1

LM53600AQDSXTQ1

LM53600LQDSXRQ1

WSON

DSX

10

3000

250

367.0

213.0

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

3000

250

3000

250

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM53600LQDSXTQ1

LM53600MQDSXRQ1

LM53600MQDSXTQ1

LM53600MQUDSXRQ1

LM53600NQDSXRQ1

LM53600NQDSXTQ1

LM536013QDSXRQ1

LM536013QDSXTQ1

LM536013QUDSXRQ1

LM536015QDSXRQ1

LM536015QDSXTQ1

LM536015QUDSXRQ1

LM53601AQDSXRQ1

LM53601AQDSXTQ1

LM53601LQDSXRQ1

LM53601LQDSXTQ1

LM53601MQDSXRQ1

LM53601MQDSXTQ1

LM53601MQUDSXRQ1

LM53601NQDSXRQ1

LM53601NQDSXTQ1

WSON

DSX

10

250

3000

250

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DSX 10

3 x 3, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226665/A

www.ti.com

PACKAGE OUTLINE

DSX0010A

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.05

2.95

B

A

PIN 1 INDEX AREA

3.05

2.95

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

0.8

0.7

C

SEATING PLANE

0.05 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

4X (0.25)

EXPOSED

THERMAL PAD

5

6

11

2X

2

A

2.4 0.1

10

1

8X 0.5

0.3

0.2

10X

0.1

0.05

C A B

C

0.5

0.3

PIN 1 ID

(OPTIONAL)

10X

4221651/C 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSX0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.25)

11

SYMM

(2.4)

(3.4)

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

4X (0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221651/C 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSX0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

METAL

TYP

10X (0.6)

11

1

10

(1.53)

2X

(1.06)

10X (0.25)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221651/C 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DSX0010C

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.05

2.95

B

A

PIN 1 INDEX AREA

3.05

2.95

0.8

0.7

C

SEATING PLANE

0.05 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

4X (0.25)

EXPOSED

THERMAL PAD

5

6

11

2X

2

2.4 0.1

10

1

8X 0.5

0.3

0.2

10X

0.1

0.05

C A B

C

PIN 1 ID

(OPTIONAL)

0.5

0.3

10X

4226664/A 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSX0010C

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.25)

11

SYMM

(2.4)

(3.4)

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

4X (0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226664/A 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSX0010C

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

METAL

TYP

10X (0.6)

11

1

10

(1.53)

2X

(1.06)

10X (0.25)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4226664/A 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM536005QDSXRQ1
厂家：	TEXAS INSTRUMENTS
描述：	用于汽车应用的 3.5V 至 36V、650mA、2.1MHz 同步降压转换器 \| DSX \| 10 \| -40 to 150 转换器
文件：	总47页 (文件大小：2708K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM536005QDSXRQ1 [TI]

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