LM5575QMHX/NOPB [TI]
75V、1.5A 降压开关稳压器 | PWP | 16 | -40 to 125;
| 型号： | LM5575QMHX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 75V、1.5A 降压开关稳压器 | PWP | 16 | -40 to 125 开关 稳压器 |
| 文件： | 总35页 (文件大小：951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
LM5575-Q1 75V、1.5A 降压开关稳压器
1 特性
3 说明
1
•
符合面向汽车 应用的的 AEC-Q100 标准：
LM5575-Q1 降压开关稳压器简单易用，可支持设计工
程师使用最少数量的组件来设计和优化强大的电源。
LM5575-Q1 具有 6V 至 75V 的工作输入电压范围，并
通过一个集成式 330mΩ N 沟道 MOSFET 提供 1.5A
的连续输出电流。该稳压器采用仿真电流模式架构，可
提供固有的线路稳定度、出色的负载瞬态响应以及简化
的环路补偿特性，且无电流模式稳压器中常见的低占空
比限制。该器件的工作频率可在 50kHz 至 500kHz 范
围内进行调节，从而实现解决方案尺寸和效率的最优
化。LM5575-Q1 的逐周期电流限制、短路保护、热关
断及远程关断等特性可确保其运行稳健可靠。该器件采
用功耗增强型 16 引脚 HTSSOP 封装，并且配有用于
散热的裸露芯片连接焊盘。LM5575-Q1 由一整套的
WEBENCH®在线设计工具提供支持。如需了解符合
AEC-Q100 的等级 1 和等级 0 的可订购部件号，请参
阅本数据表末尾的可订购产品附录。
–
–
–
器件温度等级 1：-40°C 至 +125°C 的工作温度
范围
器件温度等级 0：–40°C 至 +150°C 的工作温度
范围
器件 HBM ESD 分类等级 2
•
•
•
•
•
集成 75V、330mΩ N 沟道 MOSFET
6V 至 75V 超宽输入电压范围
低至 1.225V 的可调节输出电压
1.65% 反馈基准电压精度
可使用单个电阻器在 50kHz 与 500kHz 之间调节工
作频率
•
•
•
•
•
•
主/从频率同步
可调节软启动
仿真电流模式控制架构
宽带宽误差放大器
内置保护
使用 LM5575-Q1 并借助 WEBENCH® 电源设计器
创建定制设计
器件信息(1)
器件型号
LM5575-Q1
封装
封装尺寸（标称值）
HTSSOP (16)
5.00mm x 4.40mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
汽车
工业
简化原理图
VIN
BST
SW
VIN
VOUT
SYNC
LM5575
SD
IS
OUT
FB
RT
VCC
SS
COMP
GND
RAMP
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSB23
LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
9
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 24
10.3 Thermal Considerations........................................ 25
11 器件和文档支持 ..................................................... 25
11.1 器件支持 ............................................................... 25
11.2 接收文档更新通知 ................................................. 25
11.3 社区资源................................................................ 25
11.4 商标....................................................................... 25
11.5 静电放电警告......................................................... 26
11.6 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (February 2019) to Revision F
Page
•
•
在“特性”中添加了“等级 0” 信息 .............................................................................................................................................. 1
在“说明”末尾添加了等级 1 和等级 0 的 句子 ......................................................................................................................... 1
Changes from Revision D (March 2018) to Revision E
Page
•
•
•
从数据表中删除了 LM2xxx 器件引用 ...................................................................................................................................... 1
Changed "760" mΩ to "800 mΩ" in buck switch Rds(on) over full operating junction temperature row ................................ 6
Changed forced off-time maximum value from: 590 ns to: 626 ns in full operating junction temperature range................... 6
Changes from Revision C (December 2014) to Revision D
Page
•
•
•
•
已添加 添加了 WEBENCH 链接；对 SEO 改进进行了细微的编辑性更新.............................................................................. 1
Changed RθJA from "50°C/W" to "38.4°C/W" ......................................................................................................................... 5
Changed RθJC(top) from "14°C/W" to "21.8°C/W"; add additional thermal values ................................................................... 5
Corrected unit for RL to "kΩ".................................................................................................................................................. 8
Changes from Revision B (April 2013) to Revision C
Page
•
已添加 添加了引脚配置和功能 部分、处理额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源推荐
部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ......................................................................... 1
Changes from Revision A (April 2013) to Revision B
Page
•
Changed layout of National Semiconductor data sheet to TI format.................................................................................... 25
2
Copyright © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC
BST
PRE
SW
SD
VIN
IS
SYNC
COMP
FB
PGND
OUT
SS
RT
RAMP
AGND
Pin Functions
PIN
NAME
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 V. A 0.1-µF to
1-µF ceramic decoupling capacitor is required. An external voltage (7.5 V –
14 V) can be applied to this pin to reduce internal power dissipation.
1
VCC
O
Output of the bias regulator
If the SD pin voltage is lower than 0.7 V, the regulator is in a low power
state. If the SD pin voltage is between 0.7 V and 1.225 V the regulator is in
standby mode. If the SD pin voltage is higher than 1.225 V, the regulator is
operational. An external voltage divider can be used to set a line
undervoltage shutdown threshold. If the SD pin is left open circuit, a 5-µA
pullup current source configures the regulator fully operational.
2
SD
I
Shutdown or UVLO input
Input supply voltage
3
4
VIN
I
I
Nominal operating range: 6 V to 75 V.
The internal oscillator can be synchronized to an external clock with an
external pulldown device. Multiple LM5575-Q1 devices can be synchronized
together by connection of their SYNC pins.
Oscillator synchronization input
or output
SYNC
Output of the internal error
amplifier
The loop compensation network must be connected between this pin and
the FB pin.
5
6
7
COMP
FB
O
I
Feedback signal from the
regulated output
This pin is connected to the inverting input of the internal error amplifier. The
regulation threshold is 1.225 V.
Internal oscillator frequency set The internal oscillator is set with a single resistor connected between this pin
input
RT
I
and the AGND pin.
An external capacitor connected between this pin and the AGND pin sets the
ramp slope used for current mode control. Recommended capacitor range
50 pF to 2000 pF.
8
RAMP
AGND
SS
O
Ramp control signal
9
GND Analog ground
Internal reference for the regulator control functions
An external capacitor and an internal 10-µA current source set the time
constant for the rise of the error amp reference. The SS pin is held low
during standby, VCC UVLO, and thermal shutdown.
10
O
O
Soft start
11
12
OUT
Output voltage connection
Connect directly to the regulated output voltage.
PGND
GND Power ground
Low-side reference for the PRE switch and the IS sense resistor.
Current measurement connection for the re-circulating diode. An internal
sense resistor and a sample and hold circuit sense the diode current near
the conclusion of the off-time. This current measurement provides the DC
level of the emulated current ramp.
13
14
IS
I
Current sense
Switching node
The source terminal of the internal buck switch. Connect the SW pin to the
external Schottky diode and to the buck inductor.
SW
O
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3
LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
NAME
This open-drain output can be connected to SW pin to help charging the
bootstrap capacitor during very light load conditions or in applications where
the output may be pre-charged before the LM5575-Q1 is enabled. An
internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to
the on-time interval of the buck switch.
Pre-charge assist for the
bootstrap capacitor
15
PRE
O
An external capacitor is required between the BST and the SW pins. TI
recommends a 0.022-µF ceramic capacitor. The capacitor is charged from
VCC through an internal diode during the off-time of the buck switch.
Boost input for bootstrap
capacitor
16
BST
EP
I
Exposed metal pad on the underside of the device. TI recommends to
connect this pad to the PWB ground plane to help with heat dissipation.
NA
--
Exposed Pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
.
MIN
MAX
UNIT
V
VIN to GND
76
BST to GND
90
V
PRE to GND
76
V
SW to GND (steady-state)
BST to VCC
−1.5
V
76
V
SD, VCC to GND
BST to SW
14
V
14
V
OUT to GND
Limited to VIN
SYNC, SS, FB, RAMP to GND
Storage temperature, Tstg
7
V
–65
150
°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the
Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
6
MAX
UNIT
V
VIN
75
Operation junction temperature
−40
150
°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the
Electrical Characteristics.
4
Copyright © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
6.4 Thermal Information
LM5575-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
38.4
21.8
15.6
0.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
16.4
1.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Specifications are for TJ = 25°C. VIN = 48 V, RT = 32.4 kΩ unless otherwise stated.
(1)
PARAMETER
START-UP REGULATOR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
7.15
V
VccReg
VCC regulator output
Over full operating junction
temperature range
6.85
7.5
VCC LDO mode turnoff
VCC current limit
VCC SUPPLY
9
V
VCC = 0 V
25
mA
(VCC increasing)
5.35
V
VCC UVLO threshold
Over full operating junction
temperature range
5.01
5.69
VCC undervoltage hysteresis
Bias current (Iin)
0.35
3.7
V
FB = 1.3 V
mA
Over full operating junction
temperature range
4.5
85
SD = 0 V
57
µA
V
Shutdown current (Iin)
Over full operating junction
temperature range
SHUTDOWN THRESHOLDS
(SD Increasing)
0.7
Shutdown threshold
Shutdown hysteresis
Standby threshold
Over full operating junction
temperature range
0.43
1.15
0.9
0.1
V
V
(Standby Increasing)
1.225
Over full operating junction
temperature range
1.30
Standby hysteresis
0.1
5
V
SD pullup current source
µA
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 2008–2019, Texas Instruments Incorporated
5
LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
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Electrical Characteristics (continued)
Specifications are for TJ = 25°C. VIN = 48 V, RT = 32.4 kΩ unless otherwise stated. (1)
PARAMETER
SWITCH CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
330
mΩ
Buck switch Rds(on)
Over full operating junction
temperature range
800
BOOST UVLO
4
0.56
70
V
V
BOOST UVLO hysteresis
Pre-charge switch Rds(on)
Pre-charge switch on-time
Ω
ns
250
CURRENT LIMIT
RAMP = 0 V
2.1
A
Cycle by cycle current limit
Over full operating junction
temperature range
1.8
2.7
14
Cycle by cycle current limit delay
RAMP = 2.5 V
85
10
ns
SOFT START
SS current source
OSCILLATOR
µA
Over full operating junction
temperature range
7
200
485
kHz
kHz
Frequency1
Frequency2
Over full operating junction
temperature range
180
425
220
545
RT = 11 kΩ
Over full operating junction
temperature range
SYNC source impedance
SYNC sink impedance
SYNC threshold (falling)
11
110
1.3
kΩ
Ω
V
RT = 11 kΩ
kHz
SYNC frequency
Over full operating junction
temperature range
550
15
Over full operating junction
temperature range
ns
µA
µA
SYNC pulse width minimum
RAMP GENERATOR
VIN = 60 V, VOUT=10 V
550
50
Ramp current 1
Ramp current 2
Over full operating junction
temperature range
467
36
633
64
VIN = 10 V, VOUT= 10 V
Over full operating junction
temperature range
PWM COMPARATOR
500
ns
Forced off-time
Over full operating junction
temperature range
390
626
Minimum on-time
80
ns
V
COMP to PWM comparator offset
0.7
6
Copyright © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
Electrical Characteristics (continued)
Specifications are for TJ = 25°C. VIN = 48 V, RT = 32.4 kΩ unless otherwise stated. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
VFB = COMP
1.225
V
Feedback voltage
Over full operating junction
temperature range
1.205
1.245
FB bias current
DC gain
17
70
nA
dB
Over full operating junction
temperature range
2.5
mA
COMP sink / source current
Unity gain bandwidth
3
MHz
DIODE SENSE RESISTANCE
DSENSE
83
mΩ
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
180
25
°C
°C
6.6 Typical Characteristics
1000
100
10
1
10
100
1000
R
T
(kW)
Figure 2. Oscillator Frequency vs Temperature
FOSC = 200 kHz
Figure 1. Oscillator Frequency vs RT
Copyright © 2008–2019, Texas Instruments Incorporated
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LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
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Typical Characteristics (continued)
8
6
4
2
0
12
(mA)
0
4
8
16
20
24
I
CC
Figure 4. VCC vs ICC VIN = 12 V
Figure 3. Soft-Start Current vs Temperature
10
50
40
30
20
10
0
225
180
135
90
8
6
PHASE
45
4
0
Ramp Down
GAIN
-10
-20
-30
-45
-90
-135
2
Ramp Up
0
10k
100k
1M
10M
100M
0
2
4
6
8
10
V
(V)
IN
FREQUENCY (Hz)
Figure 5. VCC vs VIN RL = 7 kΩ
Figure 6. Error Amplifier Gain / Phase AVCL = 101
100
90
80
70
60
50
40
30
20
10
0
V
= 24V
IN
V
= 7V
IN
V
= 48V
IN
V
= 75V
IN
0.25
0.5
0.75
1
1.25
1.5
I
(A)
OUT
Figure 7. Demoboard Efficiency vs IOUT and VIN
8
Copyright © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
7 Detailed Description
7.1 Overview
The LM5575-Q1 switching regulator features the functions necessary to implement an efficient high-voltage buck
regulator using a minimum of external components. This easy-to-use regulator integrates a 75-V N-Channel buck
switch with an output current capability of 1.5 amps. The regulator control method is based on current mode
control using an emulated current ramp. Peak current mode control provides inherent line voltage feed-forward,
cycle-by-cycle current limiting, and ease-of-loop compensation. The use of an emulated control ramp reduces
noise sensitivity of the pulse-width modulation circuit, which allows reliable processing of very small duty cycles
necessary in high-input voltage applications. The operating frequency is user programmable from 50 kHz to 500
kHz. An oscillator synchronization pin allows multiple LM5575-Q1 regulators to self-synchronize or be
synchronized to an external clock. The output voltage can be set as low as 1.225 V. Fault protection features
include, current limiting, thermal shutdown, and remote shutdown capability. The device is available in the 16-pin
HTSSOP package that features an exposed pad to help thermal dissipation.
7.2 Functional Block Diagram
The LM5575-Q1 device can be applied in numerous applications to efficiently step down a high, unregulated
input voltage. The device is designed for telecom, industrial, and automotive power bus voltage ranges.
V
IN
LM5575
7V œ 75V
VIN
VCC
3
7V
1
REGULATOR
5 mA
R1
OPEN
C8
0.47
1.225V
C1
1.0
C2
1.0
THERMAL
SHUTDOWN
UVLO
CLK
2
SD
STANDBY
BST
IN
16
V
SHUTDOWN
DIS
UVLO
C7
0.7V
0.022
SD
DRIVER
R2
OPEN
C12
OPEN
S
R
Q
10 mA
L1
47 mH
LEVEL
SHIFT
10 SS
C4
5V
1.225V
0.7V
14
15
SW
Q
PWM
0.01
C11
PRE
330p
C10
120
C9
10
D1
C_LIMIT
CLK
R7
10
6
5
FB
CMSH3-100
C5
0.01
ERROR
AMP
TRACK
SAMPLE
and
13
IS
2.1V
1V/A
C6
open
R4
49.9k
V
IN
HOLD
+
12
9
PGND
AGND
COMP
CLK
Ir
RAMP GENERATOR
Ir = (10 mA x (VIN œ VOUT))
+ 50 mA
R5
5.11k
OSCILLATOR
CLK
RT
7
RAMP
OUT
11
SYNC
R6
1.65k
8
4
SYNC
C3
470p
R3
21k
7.3 Feature Description
7.3.1 Shutdown and Standby
The LM5575-Q1 contains a dual-level shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the
regulator is in a low-current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225
V, the regulator is in standby mode. In standby mode, the VCC regulator is active but the output switch is
disabled. When the SD pin voltage exceeds 1.225 V, the output switch is enabled and normal operation begins.
An internal 5-µA pullup current source configures the regulator to be fully operational if the SD pin is left open.
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Feature Description (continued)
An external set-point voltage divider from VIN to GND can be used to set the operational input range of the
regulator. The divider must be designed such that the voltage at the SD pin is greater than 1.225 V when VIN is
in the desired operating range. The internal 5-µA pullup current source must be included in calculations of the
external set-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The SD
pin is internally clamped with a 1-kΩ resistor and an 8-V Zener clamp. The voltage at the SD pin should never
exceed 14 V. If the voltage at the SD pin exceeds 8 V, the bias current increase at a rate of 1 mA/V.
The SD pin can also be used to implement various remote enable and disable functions. Pulling the SD pin
below the 0.7-V threshold totally disables the controller. If the SD pin voltage is higher than 1.225 V, the regulator
is operational.
7.3.2 Current Limit
The LM5575-Q1 contains a unique current monitoring scheme for control and overcurrent protection. When set
correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current
with a scale factor of 1 V/A. The emulated ramp signal is applied to the current limit comparator. If the emulated
ramp signal exceeds 2.1 V (2.1 A), the present current cycle is terminated (cycle-by-cycle current limiting). In
applications with small output inductance and high-input voltage, the switch current may overshoot due to the
propagation delay of the current limit comparator. If an overshoot should occur, the diode current sampling circuit
will detect the excess inductor current during the off-time of the buck switch. If the sample and hold DC level
exceeds the 2.1-V current limit threshold, the buck switch will be disabled and skip pulses until the diode current
sampling circuit detects the inductor current has decayed below the current limit threshold. This approach
prevents current runaway conditions due to propagation delays or inductor saturation because the inductor
current is forced to decay following the current overshoot.
7.3.3 Soft Start
The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing
start-up stresses and surges. The internal soft-start current source, set to 10 µA, gradually increases the voltage
of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the
reference input of the error amplifier. Various sequencing and tracking schemes can be implemented using
external circuits that limit or clamp the voltage level of the SS pin.
In the event a fault is detected (overtemperature, Vcc UVLO, SD) the soft-start capacitor will be discharged.
When the fault condition is no longer present, a new soft-start sequence will commence.
7.3.4 Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated (typically at 180°C), the controller is forced into a low-power reset
state, which disables the output driver and the bias regulator. This feature is provided to prevent catastrophic
failures from accidental device overheating.
7.4 Device Functional Modes
7.4.1 High-Voltage Start-Up Regulator
The LM5575-Q1 contains a dual-mode internal high-voltage start-up regulator that provides the VCC bias supply
for the PWM controller and bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to the
input voltage, as high as 75 V. For input voltages lower than 9 V, a low dropout switch connects VCC directly to
VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltage greater than 9 V, the low-dropout
switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating
range of 6 V to 75 V is achieved through the use of this dual-mode regulator.
The output of the VCC regulator is current-limited to 25 mA. Upon power up, the regulator sources current into the
capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 5.35
V and the SD pin is greater than 1.225 V, the output switch is enabled and a soft-start sequence begins. The
output switch remains enabled until VCC falls below 5 V or the SD pin falls below 1.125 V.
10
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Device Functional Modes (continued)
An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 7.3 V, the internal regulator essentially shuts off, reducing the IC power dissipation. The
VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased in
normal operation. Therefore the auxiliary VCC voltage should never exceed the VIN voltage.
In high-voltage applications, take care to ensure the VIN pin does not exceed the absolute maximum voltage
rating of 76 V. During line or load transients, voltage ringing on the VIN line that exceeds the absolute maximum
ratings can damage the IC. Both careful printed-circuit board layout and the use of quality bypass capacitors
located close to the VIN and GND pins are essential.
V
IN
9V
V
CC
7V
5.25V
Internal Enable Signal
Figure 8. VIN and VCC Sequencing
7.4.2 Oscillator and Sync Capability
The LM5575-Q1 oscillator frequency is set by a single external resistor connected between the RT pin and the
AGND pin. Place the RT resistor very close to the device and connected directly to the pins of the IC (RT and
AGND). To set a desired oscillator frequency (F), the necessary value for the RT resistor can be calculated by
Equation 1:
-9
1
F
- 580 x 10
RT =
135 x 10-12
(1)
The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be
of higher frequency than the free-running frequency set by the RT resistor. A clock circuit with an open-drain
output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration must be
greater than 15 ns.
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Device Functional Modes (continued)
LM5575
LM5575
SYNC
SYNC
SW
SYNC
AGND
CLK
SW
LM5575
SYNC
500 ns
UP TO 5 TOTAL
DEVICES
Figure 9. Sync From External Clock
Figure 10. Sync From Multiple Devices
Multiple LM5575-Q1 devices can be synchronized together simply by connecting the SYNC pins together. In this
configuration, all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11
shows the SYNC input and output features of the LM5575-Q1. The internal oscillator circuit drives the SYNC pin
with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low either by the internal oscillator
or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the
SYNC pins of several LM5575-Q1 ICs are connected together, the IC with the highest internal clock frequency
pulls the connected SYNC pins low first and terminate the oscillator ramp cycles of the other ICs. The LM5575-
Q1 with the highest programmed clock frequency will serve as the master and control the switching frequency of
the all the devices with lower oscillator frequency.
5V
SYNC
10k
I = f(RT)
2.5V
Q
Q
S
R
DEADTIME
ONE-SHOT
Figure 11. Simplified Oscillator Block Diagram and Sync I/O Circuit
7.4.3 Error Amplifier and PWM Comparator
The internal high-gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is
connected to the COMP pin, which allows the user to provide loop compensation components, generally a type II
network, as shown in Functional Block Diagram. This network creates a pole at DC, a zero and a noise-reducing,
high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP
generator to the error amplifier output voltage at the COMP pin.
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Device Functional Modes (continued)
7.4.4 Ramp Generator
The ramp signal used in the pulse-width modulator for current-mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.
Using this signal for the PWM ramp simplifies the control-loop-transfer function to a single pole response and
provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current
signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.
Also, the current measurement may introduce significant propagation delays. The filtering, blanking time, and
propagation delay limit the minimum achievable pulse width. In applications where the input voltage may be
relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary
for regulation. The LM5575-Q1 uses a unique ramp generator, which does not actually measure the buck switch
current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp
signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The
current reconstruction is comprised of two elements; a sample and hold DC level and an emulated current ramp.
RAMP
t
ON
(10 m x (V œ V
) + 50 m) x
OUT
IN
C
RAMP
Sample and
Hold DC Level
1V/A
T
ON
Figure 12. Composition of Current Sense Signal
The sample and hold DC level shown in Figure 12 is derived from a measurement of the re-circulating Schottky
diode anode current. The re-circulating diode anode should be connected to the IS pin. The diode current flows
through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense
resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode
current sensing and sample and hold provide the DC level of the reconstructed current signal. The positive slope
inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an
internal voltage controlled current source. The ramp current source that emulates the inductor current is a
function of the VIN and VOUT voltages per Equation 2:
IRAMP = (10 µA × (VIN – VOUT)) + 50 µA
(2)
Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of
CRAMP can be selected from Equation 3:
CRAMP = L × 10–5
where
•
L is the value of the output inductor in Henrys
(3)
13
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Device Functional Modes (continued)
With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC
level sample and hold (1 V/A). Locate the CRAMP capacitor very close to the device and connect directly to the
pins of the IC (RAMP and AGND).
For duty cycles greater than 50%, peak-current-mode control circuits are subject to sub-harmonic oscillation.
Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch
node. Add a fixed slope voltage ramp (slope compensation) to the current sense signal to prevent this oscillation.
The 50 µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal.
In some high-output voltage, high duty cycle applications, additional slope may be required. In these applications,
a pullup resistor may be added between the VCC and RAMP pins to increase the ramp slope compensation.
For VOUT > 7.5 V:
Calculate optimal slope current, IOS = VOUT × 10 µA/V.
For example, at VOUT = 10 V, IOS = 100 µA.
Install a resistor from the RAMP pin to VCC
RRAMP = VCC / (IOS – 50 µA)
:
(4)
VCC
R
RAMP
RAMP
C
RAMP
Figure 13. RRAMP to VCC for VOUT > 7.5 V
7.4.5 BOOST Pin
The LM5575-Q1 integrates an N-Channel buck switch and associated floating high-voltage level shift and gate
driver. This gate-driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. TI
recommends a 0.022-µF ceramic capacitor, connected with short traces between the BST pin and SW pin.
During the off-time of the buck switch, the SW pin voltage is approximately –0.5 V, and the bootstrap capacitor is
charged from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck
switch is forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged.
Under very light-load conditions or when the output voltage is pre-charged, the SW voltage does not remain low
during the off-time of the buck switch. If the inductor current falls to zero and the SW pin rises, the bootstrap
capacitor does not receive sufficient voltage to operate the buck switch gate driver. For these applications, the
PRE pin can be connected to the SW pin to pre-charge the bootstrap capacitor. The internal pre-charge
MOSFET and diode connected between the PRE pin and PGND turns on each cycle for 250 ns just prior to the
onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode
(CCM)), then no current flows through the pre-charge MOSFET/diode.
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Device Functional Modes (continued)
7.4.6 Maximum Duty Cycle and Input Dropout Voltage
There is a forced off-time of 500 ns implemented each cycle to ensure sufficient time for the diode current to be
sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle varies
with the operating frequency.
DMAX = 1 – Fs × 500 ns
where
•
Fs is the oscillator frequency.
(5)
Limiting the maximum duty cycle will raise the input dropout voltage. The input dropout voltage is the lowest input
voltage required to maintain regulation of the output voltage. Equation 6 calculates an approximation of the input
dropout voltage.
Vout + VD
VinMIN
=
1 - Fs x 500 ns
where
•
VD is the voltage drop across the re-circulatory diode.
(6)
Operating at high switching frequency raises the minimum input voltage necessary to maintain regulation.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Bias Power Dissipation Reduction
Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of
the IC. The VCC regulator must step down the input voltage VIN to a nominal VCC level of 7 V. The large voltage
drop across the VCC regulator translates into a large power dissipation within the VCC regulator. There are several
techniques that can significantly reduce this bias regulator power dissipation. Figure 14 and Figure 15 depict two
methods to bias the IC from the output voltage. In each case, the internal VCC regulator is used to initially bias
the VCC pin. After the output voltage is established, the VCC pin potential is raised higher than the nominal 7-V
regulation level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin should
never exceed 14 V. The VCC voltage should never be larger than the VIN voltage.
LM5575
BST
VOUT
SW
L1
C
OUT
D1
IS
GND
VCC
D2
Figure 14. VCC Bias From VOUT for 8 V < VOUT < 14 V
LM5575
BST
VOUT
L1
SW
D1
C
OUT
IS
GND
D2
VCC
Figure 15. VCC Bias With Additional Winding on the Output Inductor
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8.2 Typical Application
V
IN
LM5575
7V œ 75V
VIN
VCC
3
7V
1
REGULATOR
5 mA
R1
OPEN
C8
0.47
1.225V
C1
1.0
C2
1.0
THERMAL
SHUTDOWN
UVLO
CLK
2
SD
STANDBY
BST
IN
16
V
SHUTDOWN
DIS
UVLO
C7
0.7V
0.022
SD
DRIVER
R2
OPEN
C12
OPEN
S
R
Q
10 mA
L1
47 mH
LEVEL
SHIFT
10 SS
C4
5V
1.225V
0.7V
14
15
SW
Q
PWM
0.01
C11
PRE
330p
C10
120
C9
10
D1
C_LIMIT
CLK
R7
10
6
5
FB
CMSH3-100
C5
0.01
ERROR
AMP
TRACK
SAMPLE
and
13
IS
2.1V
1V/A
C6
open
R4
49.9k
V
IN
HOLD
+
12
9
PGND
AGND
COMP
CLK
Ir
RAMP GENERATOR
Ir = (10 mA x (VIN œ VOUT))
+ 50 mA
R5
5.11k
OSCILLATOR
CLK
RT
7
RAMP
OUT
11
SYNC
R6
1.65k
8
4
SYNC
C3
470p
R3
21k
Figure 16. Typical Application Circuit
8.2.1 Design Requirements
The circuit shown in Functional Block Diagram is configured for the following specifications:
•
•
•
•
•
VOUT = 5 V
VIN = 7 V to 75 V
Fs = 300 kHz
Minimum load current (for CCM) = 200 mA
Maximum load current = 1.5 A
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5575-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these steps are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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Typical Application (continued)
8.2.2.2 External Components
The procedure for calculating the external components is illustrated with the following design example.
8.2.2.3 R3 (RT)
RT sets the oscillator switching frequency. Generally, higher-frequency applications are smaller but have higher
losses. Operation at 300 kHz was selected for this example as a reasonable compromise for both small size and
high efficiency. The value of RT for 300-kHz switching frequency can be calculated as Equation 7.
[(1 / 300 x 103) œ 580 x 10-9]
RT =
135 x 10-12
(7)
The nearest standard value of 21 kΩ was chosen for RT.
8.2.2.4 L1
The inductor value is determined based on the operating frequency, load current, ripple current, and the
minimum and maximum input voltage (VIN(min), VIN(max)).
IPK+
IO
IRIPPLE
IPK-
0 mA
1/Fs
Figure 17. Inductor Current Waveform
To keep the circuit in CCM, the maximum ripple current IRIPPLE must be less than twice the minimum load
current, or 0.4 Ap-p. Using this value of ripple current, the value of inductor (L1) is calculated using Equation 8
and Equation 9:
VOUT x (VIN(max) œ VOUT
IRIPPLE x FS x VIN(max)
5V x (75V œ 5V)
)
L1 =
(8)
(9)
L1 =
= 39 mH
0.4A x 300 kHz x 75V
This procedure provides a guide to select the value of L1. The nearest standard value (47 µH) is used. L1 must
be rated for the peak current (IPK+) to prevent saturation. During normal loading conditions, the peak current
occurs at maximum load current plus maximum ripple. During an overload condition, the peak current is limited to
2.1 A nominal (2.5 A maximum). The selected inductor has a conservative 3.25-Amp saturation current rating.
The saturation rating is defined by inductor manufacturers as the current necessary for the inductance to reduce
by 30%, at 20°C.
8.2.2.5 C3 (CRAMP
)
With the inductor value selected, Equation 10 calculates the value of C3 (CRAMP) necessary for the emulation
ramp circuit:
CRAMP = L × 10–5
where
•
L is in Henrys.
(10)
With L1 selected for 47 µH, the recommended value for C3 is 470 pF.
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Typical Application (continued)
8.2.2.6 C9, C10
The output capacitors, C9 and C10, smooth the inductor ripple current and provide a source of charge for
transient loading conditions. For this design a 10-µF ceramic capacitor and a 120-µF AL organic capacitor were
selected. The ceramic capacitor provides ultra-low ESR to reduce the output ripple voltage and noise spikes,
while the AL capacitor provides a large bulk capacitance in a small volume for transient loading conditions.
Equation 11 calculates an approximation for the output ripple voltage.
≈
1
DVOUT = DI x
ESR +
∆
«
L
8 x FS x COUT
(11)
8.2.2.7 D1
A Schottky type re-circulating diode is required for all LM5575-Q1 applications. Ultra-fast diodes are not
recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal
reverse recovery characteristics and low forward-voltage drop are particularly important diode characteristics for
high-input voltage and low-output voltage applications common to the LM5575-Q1. The reverse recovery
characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The
reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch
occurring during turnon each cycle. The resulting switching losses of the buck switch are significantly reduced
when using a Schottky diode. Select the reverse breakdown rating for the maximum VIN, plus some safety
margin.
The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a
low output voltage. Rated current for diodes vary widely from various manufacturers. The worst case is to
assume a short-circuit load condition. In this case the diode carries the output current almost continuously. For
the LM5575-Q1 this current can be as high as 2.1 A. Assuming a worst-case, 1-V drop across the diode, the
maximum diode power dissipation can be as high as 2.1 W. For the reference design a 100-V Schottky in a SMC
package was selected.
8.2.2.8 C1, C2
The regulator supply voltage has a large source impedance at the switching frequency. Good-quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the
inductor current waveform, ramps up to the peak value, then drops to zero at turnoff. The average current into
VIN during the on-time is the load current. Select the input capacitance for RMS current rating and minimum
ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.
Select quality ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage
effects, two 1-µF, 100-V ceramic capacitors are used. If step input voltage transients are expected near the
maximum rating of the LM5575-Q1, a careful evaluation of ringing and possible spikes at the device VIN pin
must be completed. An additional damping network or input voltage clamp may be required in these cases.
8.2.2.9 C8
The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value
of C8 is no smaller than 0.1 µF and should be a good-quality, low-ESR, ceramic capacitor. A value of 0.47 µF
was selected for this design.
8.2.2.10 C7
The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch
gate at turnon. The recommended value of C7 is 0.022 µF and should be a good-quality, low-ESR, ceramic
capacitor.
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Typical Application (continued)
8.2.2.11 C4
The capacitor at the SS pin determines the soft-start time; that is, the time for the reference voltage and the
output voltage, to reach the final regulated value. Equation 12 determines the time.
C4 x 1.225V
tss
=
10 mA
(12)
For this application, a C4 value of 0.01 µF was chosen which corresponds to a soft-start time of 1 ms.
8.2.2.12 R5, R6
R5 and R6 set the output voltage level. The ratio of these resistors is calculated from Equation 13:
R5/R6 = (VOUT / 1.225V) – 1
(13)
For a 5-V output, the R5/R6 ratio calculates to 3.082. Choose the resistors from standard value resistors. A good
starting point is selection in the range of 1 kΩ to 10 kΩ. Values of 5.11 kΩ for R5,and 1.65 kΩ for R6, were
selected.
8.2.2.13 R1, R2, C12
A voltage divider can be connected to the SD pin to set a minimum operating voltage VIN(min) for the regulator. If
this feature is required, the easiest approach to select the divider resistor values is to select a value for R1
(between 10 kΩ and 100 kΩ recommended) then calculate R2 from Equation 14:
≈
∆
«
R1
R2 = 1.225 x
V
IN(min) + (5 x 10-6 x R1) œ 1.225
(14)
Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8 V. When using
an external set-point divider, it may be necessary to clamp the SD pin at high input-voltage conditions. The
reference design uses the full range of the LM5575-Q1 (6 V to 75 V); therefore, these components can be
omitted. With the SD pin open circuit the LM5575-Q1 responds once the VCC UVLO threshold is satisfied.
8.2.2.14 R7, C11
A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing
and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the
rating of the LM5575-Q1 or the re-circulating diode can damage these devices. TI recommends to select the
values for the snubber through empirical methods. First, make sure the lead lengths for the snubber connections
are very short. For the current levels typical for the LM5575-Q1, a resistor value between 5 and 20 Ω is
adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a
minimum value of C11 that provides adequate damping of the SW pin waveform at high load.
8.2.2.15 R4, C5, C6
These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One
advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.
The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of
the LM5575-Q1 is calculated by Equation 15:
DC Gain(MOD) = Gm(MOD) × RLOAD = 1 × RLOAD
(15)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output
capacitance (COUT). The corner frequency of this pole is calculated by Equation 16:
fp(MOD) = 1 / (2π RLOAD COUT
)
(16)
For RLOAD = 5 Ω and COUT = 130 µF then fp(MOD) = 245 Hz
DC Gain(MOD) = 1 × 5 = 14 dB
For the design example of Functional Block Diagram, the measured modulator gain vs. frequency characteristic
is shown in Figure 18.
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Typical Application (continued)
REF LEVEL /DIV
0.000 dB
0.0 deg
10.000 dB
45.000 deg
GAIN
0
PHASE
100
1k
10k
100k
START 100.000 Hz
STOP 100 000.000 Hz
RLOAD = 5 Ω
COUT = 130 µF
Figure 18. Gain and Phase of Modulator
Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a
zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole and leaves a single pole response
at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very
stable loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. Select the
compensation network zero (fZ) at least an order of magnitude less than the target crossover frequency. This
constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2
kHz. If the user increases R4 while they proportionally decrease C5, the error amp gain increases. Conversely, if
the user decreases R4 while proportionally they increase C5, the error amp gain decreases. For the design
example, C5 was selected for 0.01 µF and R4 was selected for 49.9 kΩ. These values configure the
compensation network zero at 320 Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is
approximately 10 (20 dB).
REF LEVEL /DIV
0.000 dB
0.0 deg
10.000 dB
45.000 deg
PHASE
GAIN
0
100
1k
10k
START 50.000 Hz
STOP 50 000.000 Hz
Figure 19. Error Amplifier Gain and Phase
The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
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Typical Application (continued)
REF LEVEL /DIV
0.000 dB
0.0 deg
10.000 dB
45.000 deg
GAIN
PHASE
0
100
1k
10k
100k
START 100.000 Hz
STOP 100 000.000 Hz
Figure 20. Overall Loop Gain and Phase
If a network analyzer is available, the modulator gain can be measured, and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step-load transient tests can be
performed to verify acceptable performance. The step-load goal is minimum overshoot with a damped response.
C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value
of C6 must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer
function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of
the pole added by C6 is: fp2 = fz × C5 / C6.
8.2.3 Application Curves
1000
100
90
80
70
60
50
40
30
20
10
0
V
= 24V
IN
100
V
= 7V
IN
V
= 48V
V
IN
= 75V
IN
10
1
10
100
1000
0.25
0.5
0.75
1
1.25
1.5
R
T
(kW)
I
(A)
OUT
Figure 21. Oscillator Frequency vs RT
Figure 22. Demoboard Efficiency vs IOUT and VIN
22
Copyright © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
9 Power Supply Recommendations
The LM5575-Q1 is designed to operate from an input voltage supply range between 6 V and 75 V. This input
supply must be able to withstand the maximum input current and maintain a voltage higher than 6 V. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LM5575-Q1 supply voltage. That drop in supply voltage can cause a false UVLO fault trigger
and system reset. If the input supply is placed more than a few inches from the LM5575-Q1, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not
critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
The circuit in Functional Block Diagram serves as both a block diagram of the LM5575-Q1 and a typical
application board schematic for the LM5575-Q1. In a buck regulator, there are two loops where currents are
switched very fast. The first loop starts from the input capacitors, to the regulator VIN pin, to the regulator SW
pin, and then to the inductor then out to the load. The second loop starts from the output capacitor ground, to the
regulator PGND pins, to the regulator IS pins, to the diode anode, to the inductor and then out to the load. The
user can minimize the loop area of these two loops to reduce the stray inductance and to minimize noise and
possible erratic operation. A ground plane in the printed-circuit board (PCB) is recommended as a means to
connect the input filter capacitors to the output filter capacitors and the PGND pins of the regulator. Connect all
of the low-power ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND
and PGND pins together through the top-side copper area that covers the entire underside of the device. Place
several vias in this underside copper area to the ground plane.
The two highest power-dissipating components are the re-circulating diode and the LM5575-Q1 regulator IC. The
easiest method to determine the power dissipated within the LM5575-Q1 is to measure the total conversion
losses (Pin – Pout) then subtract the power losses in the Schottky diode, output inductor, and snubber resistor.
Equation 17 calculates an approximation for the Schottky diode loss.
P = (1 – D) × IOUT × Vfwd
(17)
(18)
(19)
Equation 18 calculates an approximation for the output inductor power.
P = IOUT2 × R x 1.1
where
•
R is the DC resistance of the inductor and the 1.1 factor is an approximation for the AC losses
If a snubber is used, Equation 19 calculates an approximation for the damping resistor power dissipation.
P = VIN2 × Fsw × Csnub
where
•
Fsw is the switching frequency and Csnub is the snubber capacitor
The regulator has an exposed thermal pad to help power dissipation. Add several vias under the device to the
ground plane to greatly reduce the regulator junction temperature. Select a diode with an exposed pad to help
the power dissipation of the diode.
The most significant variables that affect the power dissipated by the LM5575-Q1 are the output current, input
voltage, and operating frequency. The power dissipated while the device operates near the maximum output
current and maximum input voltage can be appreciable. The operating frequency of the LM5575-Q1 evaluation
board has been designed for 300 kHz. When the device operates at 1.5-A output current with a 70-V input, the
power dissipation of the LM5575-Q1 regulator is approximately 1.25 W.
Copyright © 2008–2019, Texas Instruments Incorporated
23
LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
www.ti.com.cn
10.2 Layout Examples
Figure 23. Silkscreen
Figure 24. Component Side
Figure 25. Solder Side
24
版权 © 2008–2019, Texas Instruments Incorporated
LM5575-Q1
www.ti.com.cn
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
10.3 Thermal Considerations
The junction-to-ambient thermal resistance of the LM5575-Q1 varies with the application. The most significant
variables are the area of copper in the PCB, the number of vias under the IC exposed pad, and the amount of
forced air cooling provided. As shown in the evaluation board artwork, the area under the LM5575-Q1
(component side) is covered with copper and there are 5 connection vias to the solder-side ground plane.
Additional vias under the IC have diminishing value as more vias are added. The integrity of the solder
connection from the IC exposed pad to the PCB is critical. Excessive voids will greatly diminish the thermal
dissipation capacity. The junction-to-ambient thermal resistance of the LM5575-Q1 mounted in the evaluation
board varies from 50°C/W with no airflow to 28°C/W with 900 LFM (linear feet per minute). With a 25°C ambient
temperature and no airflow, the predicted junction temperature for the LM5575-Q1 is 25 + (50 × 1.25) = 88°C. If
the evaluation board operates at 1.5-A output current, 70-V input voltage, and a high ambient temperature for a
prolonged period of time, the thermal shutdown protection within the IC may activate. The IC turns off to allow
the junction to cool, followed by restart with the soft-start capacitor reset to zero.
11 器件和文档支持
11.1 器件支持
11.1.1 使用 WEBENCH® 工具创建定制设计
请单击此处，使用 LM5575-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
版权 © 2008–2019, Texas Instruments Incorporated
25
LM5575-Q1
ZHCSHU8F –OCTOBER 2008–REVISED JULY 2019
www.ti.com.cn
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2008–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5575Q0MH/NOPB
LM5575Q0MHX/NOPB
LM5575QMH/NOPB
LM5575QMHX/NOPB
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
16
16
16
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 125
-40 to 125
LM5575
Q0MH
ACTIVE
ACTIVE
ACTIVE
PWP
2500 RoHS & Green
92 RoHS & Green
2500 RoHS & Green
SN
SN
SN
LM5575
Q0MH
PWP
LM5575
QMH
PWP
LM5575
QMH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5575Q0MHX/NOPB HTSSOP PWP
LM5575QMHX/NOPB HTSSOP PWP
16
16
2500
2500
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5575Q0MHX/NOPB
LM5575QMHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM5575Q0MH/NOPB
LM5575QMH/NOPB
PWP
PWP
HTSSOP
HTSSOP
16
16
92
92
495
495
8
8
2514.6
2514.6
4.06
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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