LM5642X_技术文档

LM5642, LM5642X

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SNVS219K –JUNE 2003–REVISED APRIL 2013

LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator

Synchronization

Check for Samples: LM5642, LM5642X

1

FEATURES

DESCRIPTION

The LM5642 series consists of two current mode

synchronous buck regulator controllers operating

180° out of phase with each other at a normal

switching frequency of 200kHz for the LM5642 and at

375kHz for the LM5642X.

2

•

Two Synchronous Buck Regulators

180° Out of Phase Operation

•

200 kHz Fixed Nominal Frequency: LM5642

375 kHz Fixed Nominal Frequency: LM5642X

Synchronizable Switching Frequency from 150

kHz to 250 kHz for the LM5642 and 200 kHz to

500 kHz for the LM5642X

Out of phase operation reduces the input RMS ripple

current, thereby significantly reducing the required

input capacitance. The switching frequency can be

synchronized to an external clock between 150 kHz

and 250 kHz for the LM5642 and between 200 kHz

and 500 kHz for the LM5642X. The two switching

regulator outputs can also be paralleled to operate as

a dual-phase, single output regulator.

•

4.5V to 36V Input Range

50 µA Shutdown Current

Adjustable Output from 1.3V to 90% of Vin

0.04% (Typical) Line and Load Regulation

Accuracy

The output of each channel can be independently

adjusted from 1.3V to 90% of Vin. An internal 5V rail

is also available externally for driving bootstrap

circuitry.

•

Current Mode Control with or without a Sense

Resistor

Independent Enable/Soft-start Pins Allow

Simple Sequential Startup Configuration.

Current-mode feedback control assures excellent line

and load regulation and wide loop bandwidth for

excellent response to fast load transients. Current is

sensed across either the Vds of the top FET or

across an external current-sense resistor connected

in series with the drain of the top FET.

Configurable for Single Output Parallel

Operation. (See Figure 4)

•

Adjustable Cycle-by-cycle Current Limit

Input Under-voltage Lockout

Output Over-voltage Latch Protection

Output Under-voltage Protection with Delay

Thermal Shutdown

The LM5642 features analog soft-start circuitry that is

independent of the output load and output

capacitance making the soft-start behavior more

predictable and controllable than traditional soft-start

circuits.

Self Discharge of Output Capacitors when the

Regulator is OFF

Over-voltage protection is available for both outputs.

A UV-Delay pin is also available to allow delayed shut

off time for the IC during an output under-voltage

event.

•

TSSOP and HTSSOP (Exposed PAD) Packages

APPLICATIONS

•

Embedded Computer Systems

Navigation Systems

Telecom Systems

Typical Application Circuit

V

IN

4.5V - 36V

Set-Top Boxes

UV_Delay

Vout1

1.3V-0.9V_IN

WebPAD

SYNC

Point Of Load Power Architectures

LM5642/LM5642X

SS/ON1

SS/ON2

Vout2

1.3V-0.9V_IN

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM5642, LM5642X

SNVS219K –JUNE 2003–REVISED APRIL 2013

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Connection Diagram

KS1

1

RSNS1

SW1

RSNS1

SW1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

28

27

26

25

24

23

22

21

20

19

18

17

16

15

KS1

ILIM1

1

2

ILIM1

2

COMP1

3

HDRV1

CBOOT1

VDD1

HDRV1

CBOOT1

VDD1

COMP1

FB1

3

FB1

4

SYNC

5

SYNC

5

UVDELAY

6

LDRV1

VIN

LDRV1

VIN

UVDELAY

VLIN5

SGND

ON/SS1

ON/SS2

FB2

6

VLIN5

7

DAP

SGND

8

PGND

LDRV2

VDD2

PGND

LDRV2

VDD2

8

ON/SS1

9

ON/SS2

10

11

12

13

14

FB2

11

CBOOT2

HDRV2

SW2

CBOOT2

HDRV2

SW2

COMP2

12

COMP2

ILIM2

13

KS2

14

RSNS2

KS2

Figure 1. Top View

Figure 2. Top View

PIN DESCRIPTIONS

The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to

connect this pin to the current-sense point. It should be connected to VIN as close as possible to the current-

sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the

upper MOSFET.

KS1 (Pin 1)

Current limit threshold setting for Channel 1. It sinks a constant current of 9.9 µA, which is converted to a voltage

across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the V_DS

of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current

condition has occurred in Channel 1.

ILIM1 (Pin 2)

COMP1 (Pin 3)

Compensation pin for Channel 1. This is the output of the internal transconductance error amplifier. The loop

compensation network should be connected between this pin and the signal ground, SGND (Pin 8).

Feedback input for channel 1. Connect to VOUT through a voltage divider to set the Channel 1 output voltage.

FB1 (Pin 4)

The switching frequency of the LM5642 can be synchronized to an external clock.

SYNC (Pin 5)

SYNC = LOW: Free running at 200 kHz for LM5642, and at 375kHz for LM5642X. Channels are 180° out of

phase.

SYNC = HIGH: Waiting for external clock

SYNC = Falling Edge: Channel 1 HDRV pin goes high. Channel 2 HDRV pin goes high after 2.5 µs delay. The

maximum SYNC pulse width must be greater than 100 ns.

For SYNC = Low operation, connect this pin to signal ground through a 220 kΩ resistor.

A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5 µA current

source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to

ground will disable the output under-voltage protection.

UV_DELAY (Pin 6)

VLIN5 (Pin 7)

The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and powers

the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7 µF ceramic capacitor.

The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system.

SGND (Pin 8)

Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V

(open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip

goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush

current and output voltage overshoot.

ON/SS1 (Pin 9)

Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for simultaneous

startup or for parallel operation.

ON/SS2 (Pin 10)

FB2 (Pin 11)

Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2 output voltage.

2

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SNVS219K –JUNE 2003–REVISED APRIL 2013

PIN DESCRIPTIONS (continued)

Compensation pin for Channel 2. This is the output of the internal transconductance error amplifier. The loop

compensation network should be connected between this pin and the signal ground SGND (Pin 8).

COMP2 (Pin 12)

Current limit threshold setting for Channel 2. See ILIM1 (Pin 2).

ILIM2 (Pin 13)

KS2 (Pin 14)

The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2. See KS1 (Pin 1).

The negative (-) Kelvin sense for the internal current sense amplifier of Channel 2. Connect this pin to the low side

of the current sense resistor that is placed between VIN and the drain of the top MOSFET. When the Rds of the

top MOSFET is used for current sensing, connect this pin to the source of the top MOSFET. Always use a

separate trace to form a Kelvin connection to this pin.

RSNS2 (Pin 15)

Switch-node connection for Channel 2, which is connected to the source of the top MOSFET of Channel 2. It

serves as the negative supply rail for the top-side gate driver, HDRV2.

SW2 (Pin 16)

Top-side gate-drive output for Channel 2. HDRV is a floating drive output that rides on the corresponding

switching-node voltage.

HDRV2 (Pin 17)

CBOOT2 (Pin 18)

VDD2 (Pin 19)

Bootstrap capacitor connection. It serves as the positive supply rail for the Channel 2 top-side gate drive. Connect

this pin to VDD2 (Pin 19) through a diode, and connect the low side of the bootstrap capacitor to SW2 (Pin16).

The supply rail for the Channel 2 low-side gate drive. Connected to VLIN5 (Pin 7) through a 4.7Ω resistor and

bypassed to power ground with a ceramic capacitor of at least 1µF. Tie this pin to VDD1 (Pin 24).

Low-side gate-drive output for Channel 2.

LDRV2 (Pin 20)

PGND (Pin 21)

VIN (Pin 22)

The power ground connection for both channels. Connect to the ground rail of the system.

The power input pin for the chip. Connect to the positive (+) input rail of the system. This pin must be connected

to the same voltage rail as the top FET drain (or the current sense resistor when used).

Low-side gate-drive output for Channel 1.

LDRV1 (Pin 23)

VDD1 (Pin 24)

The supply rail for Channel 1 low-side gate drive. Tie this pin to VDD2 (Pin 19).

Bootstrap capacitor connection. This pin serves as the positive supply rail for the Channel 1 top-side gate drive.

See CBOOT2 (Pin 18).

CBOOT1 (Pin 25)

Top-side gate-drive output for Channel 1. See HDRV2 (Pin 17).

HDRV1 (Pin 26)

SW1 (Pin 27)

RSNS1 (Pin 28)

PGND (DAP)

Switch-node connection for Channel 1. See SW2 (Pin16).

The negative (-) Kelvin sense for the internal current sense amplifier of Channel 1. See RSNS2 (Pin 15).

The power ground connection for both channels. Connect to the ground rail of the system. Use of multiple vias to

internal ground plane or GND layer helps to dissipate heat generated by output power.

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SNVS219K –JUNE 2003–REVISED APRIL 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

Voltages from the indicated pins to SGND/PGND:

VIN, ILIM1, ILIM2, KS1, KS2

SW1, SW2, RSNS1, RSNS2

FB1, FB2, VDD1, VDD2

−0.3V to 38V

−0.3 to (V_IN+ 0.3)V

−0.3V to 6V

SYNC, COMP1, COMP2, UV Delay

−0.3V to (VLIN5 +0.3)V

−0.3V to (VLIN5 +0.6)V

43V

(3)

ON/SS1, ON/SS2

CBOOT1, CBOOT2

CBOOT1 to SW1, CBOOT2 to SW2

LDRV1, LDRV2

−0.3V to 7V

−0.3V to (VDD+0.3)V

−0.3V

HDRV1 to SW1, HDRV2 to SW2

HDRV1 to CBOOT1, HDRV2 to CBOOT2

Power Dissipation (T_A= 25°C)⁽⁴⁾

TSSOP

+0.3V

1.1W

3.4W

HTSSOP

Ambient Storage Temp. Range

Soldering Dwell Time, Temp.⁽⁵⁾

−65°C to +150°C

4 sec, 260°C

10sec, 240°C

75sec, 219°C

2kV

Wave

Infrared

Vapor Phase

(6)

ESD Rating

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for

which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) ON/SS1 and ON/SS2 are internally pulled up to one diode drop above VLIN5. Do not apply an external pull-up voltage to these pins. It

may cause damage to the IC.

(4) The maximum allowable power dissipation is calculated by using P_DMAX= (T_JMAX- T_A)/θ_JA, where T_JMAXis the maximum junction

temperature, T_Ais the ambient temperature and θ_JAis the junction-to-ambient thermal resistance of the specified package. The power

dissipation ratings results from using 125°C, 25°C, and 90.6°C/W for T_JMAX, T_A, and θ_JArespectively. A θ_JAof 90.6°C/W represents the

worst-case condition of no heat sinking of the 28-pin TSSOP. The HTSSOP package has a θ_JAof 29°C/W. The HTSSOP package

thermal ratings results from the IC being mounted on a 4 layer JEDEC standard board using the same temperature conditions as the

TSSOP package above. A thermal shutdown will occur if the temperature exceeds the maximum junction temperature of the device.

(5) See http://www.ti.com for other methods of soldering plastic small-outline packages.

(6) For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5 kΩ resistor.

(1)

OPERATING RATINGS

VIN (VLIN5 tied to VIN)

VIN (VIN and VLIN5 separate)

Junction Temperature

4.5V to 5.5V

5.5V to 36V

−40°C to +125°C

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for

which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

4

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SNVS219K –JUNE 2003–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, V_IN= 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply

over the specified operating junction temperature range, (-40°C to +125°C, if not otherwise specified). Specifications

(1)

appearing in plain type are measured using low duty cycle pulse testing with T_A= 25°C

design, test, or statistical analysis.

,

⁽²⁾. Min/Max limits are specified by

Symbol

System

Parameter

Conditions

Min

Typ

Max

Units

ΔV_OUT/V_OUT

V_{FB1_FB2}

I_VIN

Load Regulation

VIN = 28V, V_compx= 0.5V to 1.5V

5.5V ≤ VIN ≤ 36V, V_compx=1.25V

5.5V ≤ VIN ≤ 36V

0.04

%

Line Regulation

Feedback Voltage

1.2154

1.2179

1.2364

1.2574

1.2549

V

-20°C to 85°C

Input Supply Current

VLIN5 Output Voltage

V_{ON_SSx}> 2V

5.5V ≤ VIN ≤ 36V

1.1

50

5

2.0

110

5.30

mA

µA

V

(3)

Shutdown

V_{ON_SS1}= V_{ON_SS2}= 0V

VLIN5

V_CLos

I_CL

IVLIN5 = 0 to 25mA,

5.5V ≤ VIN ≤ 36V

4.70

Current Limit Comparator

Offset (VILIMX −VRSNSX)

V_IN= 6V

±2

9.9

2.4

±7.0

11.4

5.0

mV

µA

Current Limit Sink Current

Soft-Start Source Current

8.4

0.5

I_{ss_SC1}

I_{ss_SC2}

,

V_{ON_ss1}= V_{ON_ss2}= 1.5V (on)

V_{ON_ss1}= V_{ON_ss2}= 1.5V

I_{ss_SK1}

I_{ss_SK2}

,

Soft-Start Sink Current

Soft-Start On Threshold

2

5.5

1.12

3.4

10

µA

V

V_{ON_SS1}

V_{ON_SS2}

,

0.7

1.4

(4)

V_SSTO

Soft-Start Timeout

Threshold

V

I_{sc_uvdelay}

I_{sk_uvdelay}

V_UVDelay

UV_DELAY Source Current UV-DELAY = 2V

2

5

9

µA

UV_DELAY Sink Current

UV-DELAY = 0.4V

0.2

0.48

1.2

mA

UV_DELAY Threshold

Voltage

2.3

V

V_UVP

FB1, FB2, Under Voltage

Protection Latch Threshold (falling edge)

As a percentage of nominal output voltage

75

80.7

3.7

86

%

Ω

Hysteresis

V_OVP

V_OUTOvervoltage

Shutdown Latch Threshold

As a percentage measured at V_FB1, V_FB2

107

114

487

122

S_{wx_R}

SW1, SW2 ON-Resistance V_SW1= V_SW2= 0.4V

420

560

(1) A typical is the center of characterization data measured with low duty cycle pulse tsting at T_A= 25°C. Typicals are not ensured.

(2) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with T_A= T_J= 25°C. All

hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical

process control.

(3) Both switching controllers are off. The linear regulator VLIN5 remains on.

(4) When SS1 and SS2 pins are charged above this voltage and either of the output voltages at Vout1 or Vout2 is still below the regulation

limit, the under voltage protection feature is initialized.

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise specified, V_IN= 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply

over the specified operating junction temperature range, (-40°C to +125°C, if not otherwise specified). Specifications

,

appearing in plain type are measured using low duty cycle pulse testing with T_A= 25°C ^{(1) (2)}. Min/Max limits are specified by

design, test, or statistical analysis.

Symbol

Gate Drive

I_CBOOT

Parameter

Conditions

Min

Typ

Max

Units

CBOOTx Leakage Current

V_CBOOT1= V_CBOOT2= 7V

10

nA

A

I_{SC_DRV}

HDRVx and LDRVx Source V_CBOOT1= V_CBOOT2= 5V, VSWx=0V,

0.5

Current

HDRVx=LDRVx=2.5V

I_{sk_HDRV}

I_{sk_LDRV}

R_HDRV

HDRVx Sink Current

V_CBOOTx= VDDx = 5V, V_SWx= 0V, HDRVX

= 2.5V

0.8

1.1

3.1

1.5

3.1

1.1

A

LDRVx Sink Current

V_CBOOTx= VDDx = 5V, V_SWx= 0V, LDRVX

= 2.5V

HDRV1 & 2 Source On-

Resistance

V_CBOOT1= V_CBOOT2= 5V,

V_SW1= V_SW2= 0V

Ω

HDRV1 & 2 Sink On-

Resistance

R_LDRV

LDRV1 & 2 Source On-

Resistance

V_CBOOT1= V_CBOOT2= 5V,

V_SW1= V_SW2= 0V

V_DD1= V_DD1= 5V

LDRV1 & 2 Sink On-

Resistance

Oscillator and Sync Controls

5.5 ≤ V_IN≤ 36V, LM5642

5.5 ≤ V_IN≤ 36V, LM5642X

166

311

200

375

226

424

F_osc

Oscillator Frequency

kHz

Don_max

Maximum On-Duty Cycle

V_FB1= V_FB2= 1V, Measured at pins

HDRV1 and HDRV2

96

98.9

166

20

%

ns

T_{on_min}

Minimum On-Time

SS_{OT_delta}

HDRV1 and HDRV2 Delta

On Time

ON/SS1 = ON/SS2 = 2V

250

0.8

V_HS

SYNC Pin Min High Input

SYNC Pin Max Low Input

2

1.52

1.44

V

V_LS

Error Amplifier

I_FB1, I_FB2

Feedback Input Bias

Current

V_{FB1_FIX}= 1.5V, V_{FB2_FIX}= 1.5V

80

±200

nA

µA

I_{comp1_SC}

I_{comp2_SC}

,

COMP Output Source

Current

V_{FB1_FIX}= V_{FB2_FIX}= 1V,

V_COMP1= V_COMP2= 1V

6

18

6

127

-20°C to 85°C

I_{comp1_SK}

I_{comp2_SK}

,

COMP Output Sink Current V_{FB1_FIX}= V_{FB2_FIX}= 1.5V and

V_COMP1= V_COMP2= 0.5V

118

µA

-20°C to 85°C

18

gm1, gm2

Transconductance

720

5.2

µmho

GI_SNS1

,

Current Sense Amplifier

(1&2) Gain

V_COMPx= 1.25V

4.2

7.5

GI_SNS2

Voltage References and Linear Voltage Regulators

UVLO

VLIN5 Under-voltage

Lockout

ON/SS1, ON/SS2 transition

from low to high

3.6

4.0

4.4

V

Threshold Rising

6

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SNVS219K –JUNE 2003–REVISED APRIL 2013

C

3 100 pF

2

10 nF

V

IN

Vin = 24V+10%

R

1

100W

2

22

2

ILIM1

V

IN

12 kW

100 pF

IC1

LM5642

C

6

1

R

7

KS1

10 mF

50V

2.8Arms

C

1

1 mF

C

4

10 mW

28

RSNS1

R

6

Q

1

6

26

100W

UV_DELAY

HDRV1

CBOOT1

SW1

Si4850EY

D

BAS40-06

3A

25

27

C

100 nF

34

V

DD

C

Vo1 = 1.8V, 7A

L

1

7

100 nF

SYNC

5

4.2 mH

7 mW

SYNC

C

9

+

R

Q

R

10

2.26

kW

28

2

330 mF

6.3V

10 mW

23

21

4

9

LDRV1

PGND

FB1

220 kW

ON/SS1

R

11

Si4840DY

C

S

11

10 nF

1

2

4.99 kW

C

14 100 pF

C

10 nF

V

IN

13

10

ON/SS2

R

C

R

14

100W

12

10 nF

24

13

14

ILIM2

KS2

V

1

2

DD

6.8 kW

C

16

V

DD

19

R

15

10 mF

50V

2.8Arms

C

DD

16

100 pF

10 mW

15

R

27

RSNS2

R

16

7

3

VLIN5

4.7 W

Q

4

17

18

100W

HDRV2

CBOOT2

SW2

COMP1

COMP2

Si4850EY

BAS40-06

V

D

3B

12

C

27

C

26

C

DD

8.2 nF

19

L

2

Vo2 = 3.3V, 4A

C

25

100 nF

16

C

15 nF

13.7

4.7 mF

1 mF

20

10 mH

12 mW

R

23

Q

C

23

5

R

20

11

24

19

8.25

kW

+

8.45

kW

LDRV2

FB2

330 mF

6.3V

10 mW

kW

8

Si4840DY

R

SGND

20

4.99 kW

Figure 3. Typical 2 Channel Application Circuit

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C

100 pF

3

2

10 nF

V

IN

10%

Vin = 30V

ê

R

2

1

100W

22

2

ILIM1

KS1

V

IN

16.9 kW

IC1

LM5642

1

C

10 mF

50V

6

C

1

R

7

1 mF

C

4 100 pF

10 mW

28

R

6

RSNS1

2.8Arms

Q

1

6

26

100W

UV_DELAY

Si4850EY

HDRV1

D

BAS40-06

V

3A

100

nF

C

34

25

27

CBOOT1

DD

L

1

C

7

Vo = 1.8V, 20A

100 nF

SYNC

R

SW1

5

9

2.7 mH

4.5 mW

SYNC

R

10

C

9

10

Q

3

2

+

28

1000 mF

16V

22 mW

23

21

4

2.26

kW

220 kW

LDRV1

PGND

R

11

ON/SS1

1 mF

C

11

S

1

22 nF

Si4470DY x 2

4.99 kW

FB1

FB2

10

11

ON/SS2

C

14 100 pF

C

10 nF

V

IN

13

R

13

16.9 kW

24

19

14

100W

13

14

V

1

2

DD

V

DD

ILIM2

KS2

C

16

DD

R

15

10 mW

27

10 mF

50V

C

16

100 pF

7

3

15

VLIN5

RSNS2

R

16

2.8Arms

4.7W

COMP1

COMP2

Q

4

100W

17

18

C

Si4850EY

19

HDRV2

CBOOT2

SW2

12

D

3B

C

27

C

BAS40-06

26

27 nF

V

DD

L

2

1 mF 4.7 mF

C

25

100 nF

16

20

R

23

2.7 mH

4.5 mW

Q

C

Q

5

6

23

11.5 kW

8

C

24

1 mF

+

SGND

1000 mF

16V

22 mW

LDRV2

Si4470DY x 2

Figure 4. Typical Single Channel Application Circuit

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BLOCK DIAGRAM

Input Power

VIN

Supply

Voltage

and

BG

Bias

Generator

Current

+

-

SD Disable

generator

BG

reference

+

Vref

-

Current

bias

5V LDO

(Allways ON)

IREF

VLIN5

From another Ch.

10 mA

COMPx

ILIM

Comp

ILIMx

KSx

Ch1 and Ch2 are identical

+

-

+

-

CHx

output

RSNSx

ISENSE

amp

error amp

FBx

PWM comp

Normal:

ON

CBOOTx

Shifter

and latch

+

-

+

PWM logic

control

Q

R

S

HDRVx

SWx

SS:

ON

BG

CHx

Corrective

ramp

Output

2 mA

ON/OFF

and

+

-

+

Shoot through

protection

sequencer

S/S

control

Cycle

+

-

0.50V

ON/SSx

Skip

S/S level

VDDx

LDRVx

PGNDx

comp

7 mA

FAULT

TSD

UVLO

fault

UVP

Active

discharge

Rdson =

500W

5 mA

R

Q

UV_DELAY

S

UV

UVP

OVP

To Ch2

R

S

Q

From

another

CH.

UVPG1

0

2.5 ms

delay

OSC

comparator

Reset by

POR or SD

200 kHz LM5642

or

SYNC

375 kHz LM5642X

OVP

SGND

Figure 5. Block Diagram

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TYPICAL PERFORMANCE CHARACTERISTICS

Softstart Waveforms (No-Load Both Channels)

UVP Startup Waveform (VIN = 24V)

ON/SS1, 2V/div

Vo2, 2V/div

Vo1,

1V/div

Vo1, 2V/div

ON/SS1 and 2,

5V/div, VIN = 36V

Vo2, 2V/div

Io1, 5A/div

Vo1, 2V/div

ON/SS1 and 2,

5V/div, VIN = 24V

UV DELAY, 2V/div

20ms/DIV

Figure 7.

4 ms/DIV

Figure 6.

Over-Current and UVP Shutdown (VIN = 24V, Io2 = 0A)

Shutdown Waveforms (VIN = 24V, No-Load)

Io1, 5A/div

Vo2, 1V/div

Vo1, 1V/div

Vo2, 1V/div

Vo1, 1V/div

ON/SS1 and 2, 5V/div

UV DELAY, 1V/div

100ms/DIV

20ms/DIV

Figure 8.

Figure 9.

Ch.1 Load Transient Response (VIN = 24V, Vo1 = 1.8V)

Ch.2 Load Transient Response (VIN = 24V, Vo2 = 3.3V)

Io2, 2A/DIV

Io1, 2A/DIV

Vo2, 100mV/DIV

Vo1, 100mV/DIV

100ms/DIV

Figure 10.

Figure 11.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Ch. 2 Load Transient Response (VIN = 36V, Vo2 = 3.3V)

Ch.1 Load Transient Response (VIN = 36V, Vo1 = 1.8V)

Io2, 2A/DIV

Io1, 2A/DIV

Vo2, 100mV/DIV

Vo1, 100mV/DIV

100ms/DIV

Figure 12.

Figure 13.

Input Supply Current vs Temperature

(Shutdown Mode V_IN= 28V)

Input Supply Current vs V_IN

Shutdown Mode (25°C)

55

53.5

53

50

45

40

52.5

52

51.5

51

50.5

50

35

30

49.5

125

-40 -20

0

25

50

75 100

5.5

8

12 16 20 24 28 32 36

TEMPERATURE (^oC)

V_IN

Figure 14.

Figure 15.

VLIN5 vs Temperature

VLIN5 vs V_IN(25°C)

5.095

5.09

5.1

5.08

5.06

5.04

5.02

5

V_IN= 36V

5.085

5.08

V_IN= 5.5V

5.075

5.07

4.98

5.065

4.96

-40 -20

0

25

50

75 100 125

5.5

8

12 16 20 24 28 32 36

TEMPERATURE (^oC)

V_IN(V)

Figure 16.

Figure 17.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Operating Frequency vs Temperature

(VIN = 28V)

FB Reference Voltage vs Temperature

1.237

1.2365

1.236

204

202

200

198

196

194

192

190

188

186

184

1.2355

1.235

1.2345

1.234

1.2335

1.233

1.2325

1.232

-40 -20

0

25

50

75 100 125

-40 -20

0

25

50

75 100 125

TEMPERATURE (^oC)

Figure 18.

Figure 19.

Error Amplifier Tranconductance Gain

vs

Efficiency vs Load Current Using Resistor Sense

Ch.1 = 1.8V, Ch.2 = Off

Temperature

750

700

650

600

550

500

450

400

100

V_IN= 24V

90

V_IN= 36V

80

70

60

50

40

30

-40 -20

0

25

50

75 100 125

0

1

2

3

4

5

6

7

TEMPERATURE (^oC)

LOAD CURRENT (A)

Figure 20.

Figure 21.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Efficiency vs Load Current

Ch.2 = 3.3V, Ch.1 = Off

Efficiency vs Load Current Using Vds Sense

Ch.2 = 1.8V, Ch.2 = Off

100

90

80

70

60

50

100

V_IN= 24V

90

V_IN= 36V

80

V_IN= 36V

70

60

50

40

30

0

1

2

3

4

5

0

1

2

3

4

5

6

7

LOAD CURRENT (A)

Figure 22.

Figure 23.

Efficiency vs Load Current Using Vds Sense

Ch.2 = 3.3V, Ch.1 = Off

100

V_IN= 24V

90

V_IN= 36V

80

70

60

50

0

1

2

3

4

5

LOAD CURRENT (A)

Figure 24.

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OPERATING DESCRIPTIONS

SOFT START

The ON/SS1 pin has dual functionality as both channel enable and soft start control. Referring to the soft start

block diagram is shown in Figure 25, the LM5642 will remain in shutdown mode while both soft start pins are

grounded.

In a normal application (with a soft start capacitor connected between the ON/SS1 pin and SGND) soft start

functions as follows: As the input voltage rises (note, Iss starts to flow when VIN ≥ 2.2V), the internal 5V LDO

starts up, and an internal 2.4 µA current charges the soft start capacitor. During soft start, the error amplifier

output voltage at the COMPx pin is clamped at 0.55V and the duty cycle is controlled only by the soft start

voltage. As the SSx pin voltage ramps up, the duty cycle increases proportional to the soft start ramp, causing

the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft

start capacitor. The higher the capacitance, the slower the output voltage ramps up. When the corresponding

output voltage exceeds 98% (typical) of the set target voltage, the regulator switches from soft start to normal

operating mode. At this time, the 0.55V clamp at the output of the error amplifier releases and peak current

feedback control takes over. Once in peak current feedback control mode, the output voltage of the error

amplifier will travel within a 0.5V and 2V window to achieve PWM control. See Figure 26.

The amount of capacitance needed for a desired soft-start time can be approximated in the following equation:

I_ssx t_ss

C_ss

=

V_ss

where

•

I_ss= 2.4 µA for one channel and 4.8µA if the channels are paralleled

t_ssis the desired soft-start time

(1)

(2)

Finally,

V_ss= 1.5

V_o

≈

«

’

+ 1

◊

V_in

During soft start, over-voltage protection and current limit remain in effect. The under voltage protection feature is

activated when the ON/SS pin exceeds the timeout threshold (3.4V typical). If the ON/SSx capacitor is too small,

the duty cycle may increase too rapidly, causing the device to latch off due to output voltage overshoot above the

OVP threshold. This becomes more likely in applications with low output voltage, high input voltage and light

load. A capacitance of 10 nF is recommended at each soft start pin to provide a smooth monotonic output ramp.

+

-

R

S>R

S

Q

2mA

disable

fault

ONx

+

-

ON/SSx

1.2V/

1.05V

ON/OFF

comparator

ON: 2.4mA source

Fault: 5.5mA sink

7mA

+

-

S/S level

S/S buffer

Figure 25. Soft-Start and ON/OFF

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low clamp

+

-

0.45V

COMPx

+

-

SS:0.55V

OP:2V

high clamp

Figure 26. Voltage Clamp at COMPx Pin

FBx

shutdown

latch OVP

HDRV: off

LDRV:on

from other CH.

OVPx

OVP

OVP 1/2

-

+

1.13BG

S

Q

R

Q

5u

A

UVP

UV_DELAY

UVPx

ONx

SS Timeout

in: 0.84BG

out:0.80BG

-

+

from other CH.

S

R

Q

SD

power on

reset

shutdown

latch UVP

HDRV: off

LDRV:off

fault

TSD

UVLO

Figure 27. OVP and UVP

OVER VOLTAGE PROTECTION (OVP)

If the output voltage on either channel rises above 113% of nominal, over voltage protection activates. Both

channels will latch off. When the OVP latch is set, the high side FET driver, HDRVx, is immediately turned off

and the low side FET driver, LDRVx, is turned on to discharge the output capacitor through the inductor. To reset

the OVP latch, either the input voltage must be cycled, or both channels must be switched off (both ON/SS pins

pulled low).

UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY

If the output voltage on either channel falls below 80% of nominal, under voltage protection activates. As shown

in Figure 27, an under-voltage event will shut off the UV_DELAY MOSFET, which will allow the UV_DELAY

capacitor to charge with 5µA (typical). If the UV_DELAY pin voltage reaches the 2.3V threshold both channels

will latch off. UV_DELAY will then be disabled and the UV_DELAY pin will return to 0V. During UVP, both the

high side and low side FET drivers will be turned off. If no capacitor is connected to the UV_DELAY pin, the UVP

latch will be activated immediately. To reset the UVP latch, either the input voltage must be cycled, or both

ON/SS pins must be pulled low. The UVP function can be disabled by connecting the UV_DELAY pin to ground.

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THERMAL SHUTDOWN

The LM5642 IC will enter thermal shutdown if the die temperature exceeds 160°C. The top and bottom FETs of

both channels will be turned off immediately. In addition, both soft start capacitors will begin to discharge through

separate 5.5 µA current sinks. The voltage on both capacitors will settle to approximately 1.1V, where it will

remain until the thermal shutdown condition has cleared. The IC will return to normal operating mode when the

die temperature has fallen to below 146°C. At this point the two soft start capacitors will begin to charge with

their normal 2.4 µA current sources. This allows a controlled return to normal operation, similar to the soft start

during turn-on. If the thermal shutdown condition clears before the voltage on the soft start capacitors has fallen

to 1.1V, the capacitors will first be discharged to 1.1V, and then immediately begin charging back up.

OUTPUT CAPACITOR DISCHARGE

Each channel has an embedded 480Ω MOSFET with the drain connected to the SWx pin. This MOSFET will

discharge the output capacitor of its channel if its channel is off, or the IC enters a fault state caused by one of

the following conditions:

1. UVP

2. UVLO

If an output over voltage event occurs, the HDRVx will be turned off and LDRVx will be turned on immediately to

discharge the output capacitors of both channels through the inductors.

BOOTSTRAP DIODE SELECTION

The bootstrap diode and capacitor form a supply that floats above the switch node voltage. VLIN5 powers this

supply, creating approximately 5V (minus the diode drop) which is used to power the high side FET drivers and

driver logic. When selecting a bootstrap diode, Schottky diodes are preferred due to their low forward voltage

drop, but care must be taken for circuits that operate at high ambient temperature. The reverse leakage of some

Schottky diodes can increase by more than 1000x at high temperature, and this leakage path can deplete the

charge on the bootstrap capacitor, starving the driver and logic. Standard PN junction diodes and fast rectifier

diodes can also be used, and these types maintain tighter control over reverse leakage current across

temperature.

SWITCHING NOISE REDUCTION

Power MOSFETs are very fast switching devices. In synchronous rectifier converters, the rapid increase of drain

current in the top FET coupled with parasitic inductance will generate unwanted Ldi/dt noise spikes at the source

node of the FET (SWx node) and also at the VIN node. The magnitude of this noise will increase as the output

current increases. This parasitic spike noise may produce excessive electromagnetic interference (EMI), and can

also cause problems in device performance. Therefore, it must be suppressed using one of the following

methods.

When using resistor based current sensing, it is strongly recommended to add R-C filters to the current sense

amplifier inputs as shown in Figure 29. This will reduce the susceptibility to switching noise, especially during

heavy load transients and short on time conditions. The filter components should be connected as close as

possible to the IC.

As shown in Figure 28, adding a resistor in series with the HDRVx pin will slow down the gate drive, thus slowing

the rise and fall time of the top FET, yielding a longer drain current transition time.

Usually a 3.3Ω to 4.7Ω resistor is sufficient to suppress the noise. Top FET switching losses will increase with

higher resistance values.

Small resistors (1-5 ohms) can also be placed in series with the CBOOTx pin to effectively reduce switch node

ringing. A CBOOT resistor will slow the rise time of the FET, whereas a resistor at HDRV will increase both rise

and fall times.

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CBOOTx

HDRVx

SWx

Rsw

4R7

0.1 mF

Figure 28. HDRV Series Resistor

CURRENT SENSING AND LIMITING

As shown in Figure 29, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is

accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor

connected from VIN to the drain of the top FET. The advantages of sensing current across the top FET are

reduced parts count, cost and power loss.

The R_DS-ONof the top FET is not as stable over temperature and voltage as a sense resistor, hence great care

must be used in layout for V_DSsensing circuits. At input voltages above 30V, the maximum recommended output

current is 5A per channel.

Keeping the differential current-sense voltage below 200mV ensures linear operation of the current sense

amplifier. Therefore, the R_DS-ONof the top FET or the current sense resistor must be small enough so that the

current sense voltage does not exceed 200 mV when the top FET is on. There is a leading edge blanking circuit

that forces the top FET on for at least 166ns. Beyond this minimum on time, the output of the PWM comparator

is used to turn off the top FET. Additionally, a minimum voltage of at least 50 mV across Rsns is recommended

to ensure a high SNR at the current sense amplifier.

Assuming a maximum of 200 mV across Rsns, the current sense resistor can be calculated as follows:

where

•

Imax is the maximum expected load current, including overload multiplier (ie: 120%)

Irip is the inductor ripple current (see Equation 17)

(3)

The above equation gives the maximum allowable value for Rsns. Conduction losses will increase with larger

Rsns, thus lowering efficiency.

The peak current limit is set by an external resistor connected between the ILIMx pin and the KSx pin. An

internal 10 µA current sink on the ILIMx pin produces a voltage across the resistor to set the current limit

threshold which is then compared to the current sense voltage. A 10 nF capacitor across this resistor is required

to filter unwanted noise that could improperly trip the current limit comparator.

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10 mA

LIMx

comp

13k

LIMx

KSx

+

-

POWER

SUPPLY

100

10 nF

+

-

20m

RSNSx 100

100 pF

ISENSE

amp

100 pF

Figure 29. Current Sense and Current Limit

Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be

lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately. The

comparator is disabled when the top FET is turned off and during the leading edge blanking time. The equation

for current limit resistor, R_lim, is as follows:

where

•

Ilim is the load current at which the current limit comparator will be tripped

(4)

When sensing current across the top FET, replace Rsns with the R_DS-ONof the FET. This calculated Rlim value

specifies that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor

be used.

When sensing across the top FET (V_DSsensing), R_DS-ONwill show more variation than a current-sense resistor,

largely due to temperature variation. R_DS-ONwill increase proportional to temperature according to a specific

temperature coefficient. Refer to the FET manufacturer's datasheet to determine the range of R_DS-ONvalues over

operating temperature or see the Component Selection section (Equation 27) for a calculation of maximum R_DS-

_ON. This will prevent R_DS-ONvariations from prematurely tripping the current limit comparator as the operating

temperature increases.

To ensure accurate current sensing using V_DSsensing, special attention in board layout is required. The KSx and

RSNSx pins require separate traces to form a Kelvin connection at the corresponding current sense nodes. In

addition, the filter components R14, R16, C14, C15 should be removed.

INPUT UNDER VOLTAGE LOCKOUT (UVLO)

The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical).

Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480Ω MOSFETs will be turned

on to discharge the output capacitors through the SWx pins. When the input voltage is below the UVLO

threshold, the ON/SS pins will sink 5mA to discharge the soft start capacitors and turn off both channels. As the

input voltage increases again above 4.0V, UVLO will be de-activated, and the device will restart through a normal

soft start phase. If the voltage at VLIN5 remains below 4.5V, but above the 4.0V UVLO threshold, the device

cannot be ensured to operate within specification.

If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately 200

mV below the input voltage.

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DUAL-PHASE PARALLEL OPERATION

In applications with high output current demand, the two switching channels can be configured to operate as a

two phase converter to provide a single output voltage with current sharing between the two switching channels.

This approach greatly reduces the stress and heat on the output stage components while lowering input ripple

current. The inductor ripple currents also cancel to a varying degree which results in lowered output ripple

voltage. Figure 4 shows an example of a typical two-phase circuit. Because precision current sense is the

primary design criteria to ensure accurate current sharing between the two channels, both channels must use

external sense resistors for current sensing. To minimize the error between the error amplifiers of the two

channels, tie the feedback pins FB1 and FB2 together and connect to a single voltage divider for output voltage

sensing. Also, tie the COMP1 and COMP2 together and connect to the compensation network. ON/SS1 and

ON/SS2 must be tied together to enable and disable both channels simultaneously.

EXTERNAL FREQUENCY SYNC

The LM5642 series has the ability to synchronize to external sources in order to set the switching frequency. This

allows the LM5642 to use frequencies from 150 kHz to 250 kHz and the LM5642X to use frequencies from 200

kHz to 500 kHz. Lowering the switching frequency allows a smaller minimum duty cycle, DMIN, and hence a

greater range between input and output voltage. Increasing switching frequency allows the use of smaller output

inductors and output capacitors (see Component Selection). In general, synchronizing all the switching

frequencies in multi-converter systems makes filtering of the switching noise easier.

The sync input can be from a system clock, from another switching converter in the system, or from any other

periodic signal with a logic low-level less than 1.4V and a logic high level greater than 2V. Both CMOS and TTL

level inputs are acceptable.

The LM5642 series uses a fixed delay between Channel 1 and Channel 2. The nominal switching frequency of

200kHz for the LM5642 corresponds to a switching period of 5µs. Channel 2 always turns its high-side switch on

2.5µs after Channel 1 Figure 30 (a). When the converter is synchronized to a frequency other than 200kHz, the

switching period is reduced or increased, while the fixed delay between Channel 1 and Channel 2 remains

constant. The phase difference between channels is therefore no longer 180°. At the extremes of the sync range,

the phase difference drops to 135° Figure 30 (b) and Figure 30 (c). The result of this lower phase difference is a

reduction in the maximum duty cycle of one channel that will not overlap the duty cycle of the other. As shown in

Input Capacitor Selection section, when the duty cycle D1 for Channel 1 overlaps the duty cycle D2 for Channel

2, the input rms current increases, requiring more input capacitors or input capacitors with higher ripple current

ratings. The new, reduced maximum duty cycle can be calculated by multiplying the sync frequency (in Hz) by

2.5x10^-6(the fixed delay in seconds). The same logic applies to the LM5642X. However the LM5642X has a

nominal switching frequency of 375kHz which corresponds to a period of 2.67µs. Therefore channel 2 of the

LM5642X always begins it's period after 1.33µs.

D_MAX= FSYNC^*2.5x10^-6

(5)

At a sync frequency of 150 kHz, for example, the maximum duty cycle for Channel 1 that will not overlap

Channel 2 would be 37.5%. At 250 kHz, it is the duty cycle for Channel 2 that is reduced to a D_MAXof 37.5%.

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F_SW= 200 kHz

5 ms

D1

5 ms

D2

2.5 ms

(a)

F_SW= 150 kHz

6.67 ms

D1

D2

6.67 ms

2.5 ms

(b)

F_SW= 250 kHz

4 ms

D1

4 ms

D2

2.5 ms

(c)

Figure 30. Period Fixed Delay Example

Component Selection

OUTPUT VOLTAGE SETTING

The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 31. The resistor

values can be determined by the following equation:

where

•

Vfb = 1.238V

(6)

Although increasing the value of R1 and R2 will increase efficiency, this will also decrease accuracy. Therefore, a

maximum value is recommended for R2 in order to keep the output within .3% of Vnom. This maximum R2 value

should be calculated first with the following equation:

where

•

200nA is the maximum current drawn by FBx pin

(7)

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Vout

R2

R1

FBx

GND

Figure 31. Output Voltage Setting

Example: Vnom = 5V, Vfb = 1.2364V, Ifbmax = 200nA.

Choose 60K

(8)

(9)

The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output

voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum

output voltage is determined by the Cycle Skip Comparator. This circuitry skips the high side FET ON pulse

when the COMP pin voltage is below 0.5V at the beginning of a cycle. The converter will continue to skip every

other pulse until the duty cycle (and COMP pin voltage) rise above 0.5V, effectively halving the switching

frequency.

Maximum output voltage is determined by the Dropout circuitry, which skips the low side FET ON pulse

whenever the COMP pin voltage exceeds the ramp voltage derived from the current sense. Up to three low side

pulses may be skipped in a row before a minimum on-time pulse must be applied to the low side FET.

Figure 32 shows the range of ouput voltage (for Io = 3A) with respect to input voltage that will keep the converter

from entering either Skip Cycle or Dropout mode.

For input voltages below 5.5V, VLIN5 must be connected to Vin through a small resistor (approximately 4.7

ohm). This will ensure that VLIN5 does not fall below the UVLO threshold.

35

30

25

20

15

Operating Region

10

5

0

4

8

12 16 20 24 28 32 36

V

IN

Figure 32. Output Voltage Range

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Output Capacitor Selection

In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely

be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worst-

case load transients, special consideration should be given to output capacitor selection. The total combined

ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater

than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple

voltage must be low, starting from the required output voltage ripple will often result in fewer design iterations.

ALLOWED TRANSIENT VOLTAGE EXCURSION

The allowed output voltage excursion during a load transient (ΔVc_s) is:

where

•

±δ% is the output voltage regulation window

±ε% is the output voltage initial accuracy

(10)

(11)

Example: Vnom = 5V, δ% = 7%, ε% = 3.4%, Vrip = 40mV peak to peak.

MAXIMUM ESR CALCULATION

Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the

total combined ESR (Re) is too high, the load transient requirement will not be met, no matter how large the

capacitance.

The maximum allowed total combined ESR is:

(12)

Since the ripple voltage is included in the calculation of ΔVc_s, the inductor ripple current should not be included

in the worst-case load current excursion. Simply use the worst-case load current excursion for ΔIc_s.

Example: ΔVc_s = 160 mV, ΔIc_s = 3A. Then Re_max = 53.3 mΩ.

Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more

capacitors than the number determined by this criterion should be used in parallel.

MINIMUM CAPACITANCE CALCULATION

In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient

requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed

value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that

happens when the input voltage is the highest and when the current switching cycle has just finished. The

corresponding minimum capacitance is calculated as follows:

(13)

Notice it is already assumed the total ESR, Re, is no greater than Re_max, otherwise the term under the square

root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L

value should be calculated before C_minand after Re (see Inductor Selection below). Example: Re = 20 mΩ,

Vnom = 5V, ΔVc_s = 160 mV, ΔIc_s = 3A, L = 8 µH

(14)

Generally speaking, C_mindecreases with decreasing Re, ΔIc_s, and L, but with increasing Vnom and ΔVc_s.

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Inductor Selection

The size of the output inductor can be determined from the desired output ripple voltage, Vrip, and the

impedance of the output capacitors at the switching frequency. The equation to determine the minimum

inductance value is as follows:

(15)

In the above equation, Re is used in place of the impedance of the output capacitors. This is because in most

cases, the impedance of the output capacitors at the switching frequency is very close to Re. In the case of

ceramic capacitors, replace Re with the true impedance at the switching frequency.

Example: Vin = 36V, Vo = 3.3V, V_RIP= 60 mV, Re = 20 mΩ, F = 200 kHz.

3.3 x 0.02

.060

36 - 3.3

x

L_min

=

= 5mH

200kHz x 36

(16)

The actual selection process usually involves several iterations of all of the above steps, from ripple voltage

selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output

voltages and load transient requirements should be considered. If an inductance value larger than Lmin is

selected, make sure that the Cmin requirement is not violated.

Priority should be given to parameters that are not flexible or more costly. For example, if there are very few

types of capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of

3.2 capacitors can be reduced to 3 capacitors.

Since inductor ripple current is often the criterion for selecting an output inductor, it is a good idea to double-

check this value. The equation is:

(17)

Also important is the ripple content, which is defined by Irip /Inom. Generally speaking, a ripple content of less

than 50% is ok. Larger ripple content will cause too much power loss in the inductor.

Example: Vin = 36V, Vo = 3.3V, F = 200 kHz, L = 5 µH, 3A max I_OUT

36 - 3.3

200kHz x 5x10^-6

3.3

36

x

I_rip

=

= 3A

(18)

3A is 100% ripple which is too high.

In this case, the inductor should be reselected on the basis of ripple current.

Example: 40% ripple, 40% • 3A = 1.2A

36 - 3.3

3.3

36

x

1.2A =

L x 200kHz

(19)

(20)

36 - 3.3

3.3

36

x

= 12.5mH

L =

200kHz x 1.2A

When choosing the inductor, the saturation current should be higher than the maximum peak inductor current

and the RMS current rating should be higher than the maximum load current.

Input Capacitor Selection

The fact that the two switching channels of the LM5642 are 180° out of phase will reduce the RMS value of the

ripple current seen by the input capacitors. This will help extend input capacitor life span and result in a more

efficient system. Input capacitors must be selected that can handle both the maximum ripple RMS current at

highest ambient temperature as well as the maximum input voltage. In applications in which output voltages are

less than half of the input voltage, the corresponding duty cycles will be less than 50%. This means there will be

no overlap between the two channels' input current pulses.

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The equation for calculating the maximum total input ripple RMS current for duty cycles under 50% is:

where

•

I1 is maximum load current of Channel 1

I2 is the maximum load current of Channel 2

D1 is the duty cycle of Channel 1

D2 is the duty cycle of Channel 2

(21)

(22)

Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2 = 0.275

Choose input capacitors that can handle 1.66A ripple RMS current at highest ambient temperature. In

applications where output voltages are greater than half the input voltage, the corresponding duty cycles will be

greater than 50%, and there will be overlapping input current pulses. Input ripple current will be highest under

these circumstances. The input RMS current in this case is given by:

(23)

Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles.

This equation should be used when both duty cycles are expected to be higher than 50%.

If the LM5642 is being used with an external clock frequency other than 200kHz, or 375 kHz for the LM5642X,

the preceding equations for input rms current can still be used. The selection of the first equation or the second

changes because overlap can now occur at duty cycles that are less than 50%. From the EXTERNAL

FREQUENCY SYNC section, the maximum duty cycle that ensures no overlap between duty cycles (and hence

input current pulses) is:

D_MAX= F_SYNC^*2.5 x 10^-6

(24)

There are now three distinct possibilities which must be considered when selecting the equation for input rms

current. The following applies for the LM5642, and also the LM5642X by replacing 200 kHz with 375 kHz:

1. Both duty cycles D₁and D₂are less than D_MAX. In this case, the first, simple equation can always be used.

2. One duty cycle is greater than D_MAXand the other duty cycle is less than D_MAX. In this case, the system

designer can take advantage of the fact that the sync feature reduces D_MAXfor one channel, but lengthens it

for the other channel. For F_SYNC< 200kHz, D₁is reduced to D_MAXwhile D₂actually increases to (1-D_MAX).

For F_SYNC> 200kHz, D₂is reduced to D_MAXwhile D₁increases to (1-D_MAX). By using the channel reduced to

D_MAXfor the lower duty cycle, and the channel that has been increased for the higher duty cycle, the first,

simple rms input current equation can be used.

3. Both duty cycles are greater than D_MAX. This case is identical to a system at 200 kHz where either duty cycle

is 50% or greater. Some overlap of duty cycles is specified, and hence the second, more complicated rms

input current equation must be used.

Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the

capacitor should then be selected based on hold up time requirements. Bench testing for individual applications

is still the best way to determine a reliable input capacitor value. Input capacitors should always be placed as

close as possible to the current sense resistor or the drain of the top FET. When high ESR capacitors such as

tantalum are used, a 1µF ceramic capacitor should be added as closely as possible to the high-side FET drain

and low-side FET source.

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MOSFET Selection

BOTTOM FET SELECTION

During normal operation, the bottom FET is switching on and off at almost zero voltage. Therefore, only

conduction losses are present in the bottom FET. The most important parameter when selecting the bottom FET

is the on-resistance (R_DS-ON). The lower the on-resistance, the lower the power loss. The bottom FET power loss

peaks at maximum input voltage and load current. The equation for the maximum allowed on-resistance at room

temperature for a given FET package, is:

where

•

Tj_max is the maximum allowed junction temperature in the FET

Ta_max is the maximum ambient temperature

R_θjais the junction-to-ambient thermal resistance of the FET

TC is the temperature coefficient of the on-resistance which is typically in the range of 4000ppm/°C

(25)

If the calculated R_{DS-ON (MAX)}is smaller than the lowest value available, multiple FETs can be used in parallel.

This effectively reduces the I_maxterm in the above equation, thus reducing R_DS-ON. When using two FETs in

parallel, multiply the calculated R_{DS-ON (MAX)}by 4 to obtain the R_{DS-ON (MAX)}for each FET. In the case of three

FETs, multiply by 9.

(26)

If the selected FET has an Rds value higher than 35.3Ω, then two FETs with an R_DS-ONless than 141 mΩ (4 x

35.3 mΩ) can be used in parallel. In this case, the temperature rise on each FET will not go to Tj_max because

each FET is now dissipating only half of the total power.

TOP FET SELECTION

The top FET has two types of losses: switching loss and conduction loss. The switching losses mainly consist of

crossover loss and losses related to the low-side FET body diode reverse recovery. Since it is rather difficult to

estimate the switching loss, a general starting point is to allot 60% of the top FET thermal capacity to switching

losses. The best way to precisely determine switching losses is through bench testing. The equation for

calculating the on resistance of the top FET is thus:

(27)

Example: Tj_max = 100°C, Ta_max = 60°C, Rqja = 60°C/W, Vin_min = 5.5V, Vnom = 5V, and Iload_max = 3.6A.

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(28)

When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET.

Loop Compensation

The general purpose of loop compensation is to meet static and dynamic performance requirements while

maintaining stability. Loop gain is what is usually checked to determine small-signal performance. Loop gain is

equal to the product of control-output transfer function and the feedback transfer function (the compensation

network transfer function). Generally speaking it is desirable to have a loop gain slope that is roughly -20dB

/decade from a very low frequency to well beyond the crossover frequency. The crossover frequency should not

exceed one-fifth of the switching frequency. The higher the bandwidth, the faster the load transient response

speed will be. However, if the duty cycle saturates during a load transient, further increasing the small signal

bandwidth will not help. Since the control-output transfer function usually has very limited low frequency gain, it is

a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain will be

relatively large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or

line variations). The rest of the compensation scheme depends highly on the shape of the control-output plot.

20

0

Asymptoti

c

0

-45

-90

-135

-180

-20

Phas

e

-40

-60

Gain

1

k

10

k

100

k

10

100

1M

FREQUENCY

(Hz)

Figure 33. Control-Output Transfer Function

As shown in Figure 33, the control-output transfer function consists of one pole (fp), one zero (fz), and a double

pole at fn (half the switching frequency). The following can be done to create a -20dB /decade roll-off of the loop

gain: Place the first pole at 0Hz, the first zero at fp, the second pole at fz, and the second zero at fn. The

resulting feedback transfer function is shown in Figure 34.

(f_p1is at zero frequency)

B

f_z1

f_z2

f_p2

FREQUENCY

Figure 34. Feedback Transfer Function

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The control-output corner frequencies, and thus the desired compensation corner frequencies, can be

determined approximately by the following equations:

(29)

1

1 - D - .5

f_P=

+

2pR_OC_O

2pfLC_O

(30)

Since fp is determined by the output network, it will shift with loading (Ro). It is best to use a minimum Iout value

of approximately 100mA when determining the maximum Ro value.

Example: Re = 20 mΩ, Co = 100 uF, Romax = 5V/100 mA = 50Ω:

(31)

(32)

First determine the minimum frequency (fpmin) of the pole across the expected load range, then place the first

compensation zero at or below that value. Once fpmin is determined, Rc1 should be calculated using:

where

•

B is the desired gain in V/V at fp (fz1)

gm is the transconductance of the error amplifier

R1 and R2 are the feedback resistors

(33)

(34)

A gain value around 10dB (3.3v/v) is generally a good starting point.

Example: B = 3.3v/v, gm = 650m, R1 = 20 kKΩ, R2 = 60.4 kΩ:

Bandwidth will vary proportional to the value of Rc1. Next, Cc1 can be determined with the following equation:

(35)

(36)

Example: fpmin = 995 Hz, Rc1 = 20 kΩ:

The compensation network (Figure 35) will also introduce a low frequency pole which will be close to 0 Hz.

A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted

Rc2 (see Figure 35). The minimum value for this capacitor can be calculated by:

(37)

Cc2 may not be necessary, however it does create a more stable control loop. This is especially important with

high load currents and in current sharing mode.

Example: fz = 80 kHz, Rc1 = 20 kΩ:

(38)

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A second zero can also be added with a resistor in series with Cc2. If used, this zero should be placed at fn,

where the control to output gain rolls off at -40dB/dec. Generally, fn will be well below the 0dB level and thus will

have little effect on stability. Rc2 can be calculated with the following equation:

(39)

V_o

V_c

g_m

R₂

C_C1

C_C2

R_C2

compensation

network

R_C1

R₁

Figure 35. Compensation Network

PCB Layout Considerations

To produce an optimal power solution with the LM5642 series, good layout and design of the PCB are as

important as the component selection. The following are several guidelines to aid in creating a good layout.

KELVIN TRACES FOR SENSE LINES

When using the current sense resistor to sense the load current connect the KS pin using a separate trace to

VIN, as close as possible to the current-sense resistor. The RSNS pin should be connected using a separate

trace to the low-side of the current sense resistor. The traces should be run parallel to each other to give

common mode rejection. Although it can be difficult in a compact design, these traces should stay away from the

output inductor and switch node if possible, to avoid coupling stray flux fields. When a current-sense resistor is

not used the KS pin should be connected as close as possible to the drain node of the upper MOSFET and the

RSNS pin should be connected as close as possible to the source of the upper MOSFET using Kelvin traces. To

further help minimize noise pickup on the sense lines is to use RC filtering on the KS and RSNS pins.

SEPARATE PGND AND SGND

Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components

like the compensation and feedback resistors should be connected to a section of this internal SGND plane. The

SGND section of the plane should be connected to the power ground at only one point. The best place to

connect the SGND and PGND is right at the PGND pin..

MINIMIZE THE SWITCH NODE

The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use

just enough copper to give low impedance to the switching currents, preferably in the form of a wide, but short,

trace run.

LOW IMPEDANCE POWER PATH

The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these

components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the

same layer. Vias add resistance and inductance to the power path, and have relatively high impedance

connections to the internal planes. If high switching currents must be routed through vias and/or internal planes,

use multiple vias in parallel to reduce their resistance and inductance. The power components should be kept

close together. The longer the paths that connect them, the more they act as antennas, radiating unwanted EMI.

Please see AN-1229 (literature number SNVA054) for further PCB layout considerations.

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Table 1. Bill Of Materials for Figure 3 24V to 1.8, 3.3V LM5642

ID

Part Number

Type

Size

Parameters

Qty

Vendor

U1

LM5642

Dual

TSSOP-28

1

TI

Synchronous

Controller

Q1, Q4

Q2, Q5

D3

Si4850EY

Si4840DY

N-MOSFET

Schottky Diode

Inductor

SO-8

60V

40V

2

1

3

Vishay

TDK

BAS40-06

SOT-23

40V

L1

RLF12560T-4R2N100

RLF12545T-100M5R1

C3216X7R1H105K

VJ1206Y101KXXAT

12.5x12.5x 6mm

12.5x12.5x 4.5mm

1206

4.2µH, 7mΩ 10A

10µH, 12mΩ 5.1A

1µF, 50V

L2

Inductor

TDK

C1

Capacitor

TDK

C3, C4, C14,

C15

Capacitor

1206

100pF, 25V

Vishay

C27

C2012X5R1C105K

C5750X5R1H106M

6TPD330M

Capacitor

0805

2220

1µF, 16V

10µF 50V, 2.8A

330µF, 6.3V, 10mΩ

10nF, 25V

1

2

4

TDK

C6, C16

C9, C23

7.3x4.3x 3.8mm

1206

Sanyo

Vishay

C2, C11, C12,

C13

VJ1206Y103KXXAT

C7, C25, C34

VJ1206Y104KXXAT

VJ1206Y822KXXAT

VJ1206Y153KXXAT

C3216X7R1C475K

CRCW1206123J

Capacitor

Resistor

1206

100nF, 25V

8.2nF 10%

15nF 10%

4.7µF 25V

12kΩ 5%

3

1

Vishay

TDK

C19

C20

C26

R1

Vishay

R2, R6, R14,

R16

CRCW1206100J

Resistor

100Ω 5%

R13

CRCW1206682J

WSL-2512 .010 1%

CRCW1206000Z

Resistor

1206

2512

1206

6.8kΩ 12%

10mΩ 1W

0Ω

1

2

8

Vishay

R7, R15

R8, R9, R12,

R17, R18, R21,

R31, R32

R10

R23

CRCW12062261F

CRCW12068451F

CRCW12061372F

CRCW12064991F

CRCW12068251F

CRCW12064R7J

CRCW1206224J

Resistor

1206

2.26kΩ 1%

8.45kΩ 1%

13.7kΩ 1%

4.99kΩ 1%

8.25kΩ 1%

4.7Ω 5%

1

2

1

Vishay

R24

R11, R20

R19

R27

R28

220kΩ 5%

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Table 2. Bill of Materials for Figure 4 30V to 1.8V, 20A LM5642

ID

Part Number

Type

Size

Parameters

Qty

Vendor

U1

LM5642

Dual

TSSOP-28

1

TI

Synchronou

s Controller

Q1, Q4

Q2, Q3, Q5, Q6

D3

Si4850EY

Si4470DY

BAS40-06

N-MOSFET

SO-8

60V

40V

2

4

1

Vishay

Schottky

Diode

SOT-23

L1,L2

C1

RLF12560T-2R7N110

C3216X7R1H105K

C2012X5R1C105K

C5750X5R1H106M

Inductor

Capacitor

12.5x12.5x 6mm

1206

2.7µH,4.5mΩ 11.5A

1µF, 50V

2

1

3

4

TDK

C10, C24, C27

0805

1µF, 16V

C6, C16, C28,

C30

2220

10µF 50V, 2.8A

C9, C23

C2, C13

C11

16MV1000WX

VJ1206Y103KXXAT

VJ1206Y223KXXAT

VJ1206Y104KXXAT

VJ1206Y273KXXAT

C3216X7R1C475K

CRCW1206123J

Capacitor

Resistor

10mm D20mm H

1206

1000µF, 16V, 22mΩ

10nF, 25V

2

1

3

1

Sanyo

Vishay

TDK

1206

22nF, 25V

C7,C25, C34

C19

1206

100nF, 25V

27nF 10%

1206

C26

1206

4.7µF 25V

R1, R13

1206

16.9kΩ 1%

100Ω 5%

Vishay

R2, R6, R14,

R16

CRCW1206100J

Resistor

1206

R7, R15

WSL-2512 .010 1%

CRCW1206000Z

Resistor

2512

1206

10mΩ 1W

0Ω

2

8

Vishay

R8, R9, R12,

R17, R18, R21,

R31, R32

R10

R11

R23

R27

R28

CRCW12062261F

CRCW12064991F

CRCW12061152F

CRCW12064R7J

CRCW1206224J

Resistor

1206

2.26kΩ 1%

4.99kΩ 1%

11.5kΩ 1%

4.7Ω 5%

1

Vishay

220kΩ 5%

30

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Table 3. Bill Of Materials Based on Figure 3 V_in= 9-16V, V_O1,2=1.5V,1.8V, 5A LM5642X

ID

Part Number

Type

Size

Parameters

Qty

Vendor

U1

LM5642X

Dual

TSSOP-28

1

TI

Synchronous

Controller

Q1, Q4

Q2, Q5

D3

Si4850EY

Si4840DY

N-MOSFET

Schottky Diode

Inductor

SO-8

60V

40V

2

1

2

1

4

Vishay

TDK

BA54A

SOT-23

30V

L1, L2

C1

RLF12545T-4R2N100

C3216X7R1H105K

VJ1206Y101KXXAT

12.5x12.5x 4.5mm

1206

4.2µH, 7mΩ 6.5A

1µF, 50V

100pF, 25V

Capacitor

TDK

C3, C4, C14,

C15

Capacitor

1206

Vishay

C27

C2012X5R1C105K

C5750X7R1H106M

C4532X7R0J107M

VJ1206Y103KXXAT

Capacitor

0805

2220

1812

1206

1µF, 16V

10µF 50V, 2.8A

100µF, 6.3V, 1mΩ

10nF, 25V

1

2

4

TDK

C6, C28

C9, C23

TDK

C2, C11, C12,

C13

Vishay

C7, C25, C34

C18, C20

C26

VJ1206Y104KXXAT

VJ1206Y473KXXAT

C3216X7R1C475K

CRCW12061912F

CRCW1206100J

Capacitor

Resistor

1206

100nF, 25V

47nF 10%

4.7µF 25V

19.1kΩ 1%

100Ω 5%

3

2

1

2

1

Vishay

TDK

R1, R13

Vishay

R2, R6, R14,

R16

Resistor

R7, R15

WSL-1206 .020 1%

CRCW1206000Z

Resistor

1206

20mΩ 1W

0Ω

2

8

Vishay

R8, R9, R12,

R17, R18, R21,

R31, R32

R10, R19

R11

CRCW12061001F

CRCW12062611F

CRCW12062321F

CRCW12063011F

CRCW12064R7J

CRCW1206224J

Resistor

1206

1kΩ 1%

2.61kΩ 1%

2.32kΩ 1%

3.01kΩ 1%

4.7Ω 5%

2

1

2

1

Vishay

R20

R22, R24

R27

R28

220kΩ 5%

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31

Product Folder Links: LM5642 LM5642X

LM5642, LM5642X

SNVS219K –JUNE 2003–REVISED APRIL 2013

www.ti.com

Table 4. Bill Of Materials Based on Figure 3 V_in= 9-16V, V_O1,2=3.3V,5V, 5A LM5642X

ID

Part Number

Type

Size

Parameters

Qty

Vendor

U1

LM5642X

Dual

TSSOP-28

1

TI

Synchronous

Controller

Q1, Q4

Q2, Q5

D3

Si4850EY

Si4840DY

N-MOSFET

Schottky Diode

Inductor

SO-8

60V

40V

2

1

2

1

4

Vishay

TDK

BA54A

SOT-23

30V

L1, L2

C1

RLF12545T-5R6N6R1

C3216X7R1H105K

VJ1206Y101KXXAT

12.5x12.5x 4.5mm

1206

5.6µH, 9mΩ 6.1A

1µF, 50V

100pF, 25V

Capacitor

TDK

C3, C4, C14,

C15

Capacitor

1206

Vishay

C27

C2012X5R1C105K

C5750X7R1H106M

C4532X7R0J107M

VJ1206Y103KXXAT

Capacitor

0805

2220

1812

1206

1µF, 16V

10µF 50V, 2.8A

100µF, 6.3V, 1mΩ

10nF, 25V

1

2

4

TDK

C6, C28

C9, C23

TDK

C2, C11, C12,

C13

Vishay

C7, C25, C34

C18, C20

C26

VJ1206Y104KXXAT

VJ1206Y393KXXAT

C3216X7R1C475K

CRCW12061912F

CRCW1206100J

Capacitor

Resistor

1206

100nF, 25V

39nF 10%

4.7µF 25V

19.1kΩ 1%

100Ω 5%

3

2

1

2

1

Vishay

TDK

R1, R13

Vishay

R2, R6, R14,

R16

Resistor

R7, R15

WSL-1206 .020 1%

CRCW1206000Z

Resistor

1206

20mΩ 1W

0Ω

2

8

Vishay

R8, R9, R12,

R17, R18, R21,

R31, R32

R10, R19

R11

CRCW12061002F

CRCW12066191F

CRCW12063321F

CRCW12063831F

CRCW12064R7J

CRCW1206224J

Resistor

1206

10kΩ 1%

6.19kΩ 1%

3.32kΩ 1%

3.83kΩ 1%

4.7Ω 5%

2

1

2

1

Vishay

R20

R22, R24

R27

R28

220kΩ 5%

32

Submit Documentation Feedback

Product Folder Links: LM5642 LM5642X

LM5642, LM5642X

www.ti.com

SNVS219K –JUNE 2003–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision J (April 2013) to Revision K

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 32

Submit Documentation Feedback

33

Product Folder Links: LM5642 LM5642X

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5642MHX/NOPB

LM5642MTCX

HTSSOP PWP

28

2500

330.0

16.4

6.8

10.2

1.6

8.0

16.0

Q1

TSSOP

PW

LM5642MTCX/NOPB

LM5642XMHX

HTSSOP PWP

LM5642XMHX/NOPB HTSSOP PWP

LM5642XMTX

TSSOP

PW

LM5642XMTX/NOPB

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5642MHX/NOPB

LM5642MTCX

HTSSOP

TSSOP

HTSSOP

TSSOP

PWP

PW

28

2500

367.0

35.0

38.0

35.0

38.0

LM5642MTCX/NOPB

LM5642XMHX

PW

PWP

PW

LM5642XMHX/NOPB

LM5642XMTX

LM5642XMTX/NOPB

PW

Pack Materials-Page 2

MECHANICAL DATA

PWP0028A

MXA28A (Rev D)

www.ti.com

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型号：	LM5642X
厂家：	TEXAS INSTRUMENTS
描述：	具有振荡器同步的高电压、双路同步降压转换器开关控制器开关式稳压器开关式控制器电源电路振荡器转换器开关式稳压器或控制器
文件：	总40页 (文件大小：1403K)
中文：	中文翻译
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