LM61480Q5RPHRQ1 [TI]
LM62460-Q1, LM61480-Q1, and LM61495-Q1 Pin-Compatible 6-A/8-A/10-A Automotive Buck Converter Optimized for Power Density and Low EMI;型号: | LM61480Q5RPHRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | LM62460-Q1, LM61480-Q1, and LM61495-Q1 Pin-Compatible 6-A/8-A/10-A Automotive Buck Converter Optimized for Power Density and Low EMI |
文件: | 总64页 (文件大小:4721K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LM61495-Q1, LM61480-Q1, LM62460-Q1
SNVSBA0D – FEBRUARY 2020 – REVISED AUGUST 2021
LM62460-Q1, LM61480-Q1, and LM61495-Q1 Pin-Compatible 6-A/8-A/10-A Automotive
Buck Converter Optimized for Power Density and Low EMI
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Input voltage range from 3 V to 36 V
RESET output with filter and delayed release
Designed for low EMI:
– CISPR 25 class 5 compliant EVM
– Pin-configurable spread spectrum
– Adjustable SW node rise time
The LM6x4xx-Q1 buck regulator family are
automotive-focused regulators providing either fixed
or an adjustable output voltage which can be set
from 1 V to 95% of expected input voltage. These
regulators operate under a wide input voltage range of
3 to 36V and has transient tolerance up to 42 V.
•
•
•
•
The family is designed for low EMI. The device
incorporates pin selectable spread spectrum, and an
adjustable SW node rise time. Dual Random Spread
Spectrum (DRSS) frequency hopping is set to ±4%
(typical), drastically reducing peak emissions through
a combination of triangular and pseudorandom
modulation, and includes advanced techniques to
reduce output voltage ripple caused by spread
spectrum modulation.
– Above and below AM band operation: pin
configurable 400 kHz and 2.2 MHz fixed or
adjustable from 200 kHz – 2.2 MHz
– Low EMI symmetrical pinout
– Light load mode is pin-configurable for constant
frequency or pulse frequency modulation (PFM)
High-efficiency solution
An open-drain RESET output, with filtering and
delayed release, gives a true indication of system
status. In auto mode the device automatically
transitions between Fixed frequency Pulse Width
Modulation (FPWM) and Pulse Frequency Modulation
(PFM) modes of operation, allowing an unloaded
•
•
– 95% efficient for an 8-A load
– 5-µA input current while unloaded in auto mode
– <1-µA shutdown current (typical)
High power density
– Built-in compensation, soft start, current limit,
thermal shutdown, and UVLO
– 4.5-mm × 3.5-mm wettable flank QFN package
– ϴJA = 21.6°C/W, measured on
LM61495RPHEVM
current consumption of only
5
µA (typical).
Electrical characteristics are specified over a junction
temperature range of –40°C to +150°C.
Device Information
PART NUMBER
LM61495-Q1
PACKAGE(1)
BODY SIZE (NOM)
2 Applications
LM61480-Q1
VQFN (16)
4.50 mm × 3.50 mm
•
•
•
Automotive infotainment
Instrument cluster
ADAS
LM62460-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3.0 V to 36 V input
VIN1
EN
VIN2
PGND2
PGND1
BIAS
SW
RESET
SPSP
CBOOT
RBOOT
FB
MODE/SYNC
VCC
RT
AGND
EVM Efficiency: VOUT = 5 V, FSW = 2.2 MHz
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM61495-Q1, LM61480-Q1, LM62460-Q1
SNVSBA0D – FEBRUARY 2020 – REVISED AUGUST 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
7.6 Timing Characteristics ................................................9
7.7 Switching Characteristics .........................................10
7.8 System Characteristics ............................................ 10
7.9 Typical Characteristics..............................................12
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................33
9.1 Application Information............................................. 33
9.2 Typical Application.................................................... 33
10 Power Supply Recommendations..............................50
11 Layout...........................................................................51
11.1 Layout Guidelines................................................... 51
11.2 Layout Example...................................................... 53
12 Device and Documentation Support..........................54
12.1 Device Support....................................................... 54
12.2 Receiving Notification of Documentation Updates..54
12.3 Support Resources................................................. 54
12.4 Trademarks.............................................................54
12.5 Glossary..................................................................54
12.6 Electrostatic Discharge Caution..............................54
13 Mechanical, Packaging, and Orderable
Information.................................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2021) to Revision D (August 2021)
Page
•
•
•
Changed status of 8-A devices to released........................................................................................................3
Changed status of 4-V options to released.........................................................................................................3
Updated Figure 9-29 to Figure 9-45 ................................................................................................................ 40
Changes from Revision B (March 2021) to Revision C (May 2021)
Page
Changed status of 6-A devices to released........................................................................................................3
Added sentence to the SYNC/MODE pin........................................................................................................... 4
•
•
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5 Device Comparison Table
DEVICE
VARIANT
LIGHT LOAD
SPREAD
OUTPUT
TYPICAL
CURRENT
SPECTRUM
VOLTAGE
FREQUENCY
LM61495QRPHRQ1
LM61495Q3RPHRQ1
LM61495Q4RPHRQ1
Adjustable
3.3 V
LM61495-Q1
(10-A rating)
Pin selectable
Pin selectable
Pin selectable
10 A
4.0 V
LM61495Q5RPHRQ1
5.0 V
LM61480QRPHRQ1
LM61480Q3RPHRQ1
LM61480Q4RPHRQ1
LM61480Q5RPHRQ1
LM62460QRPHRQ1
LM62460Q3RPHRQ1
LM62460Q4RPHRQ1
LM62460Q5RPHRQ1
Adjustable
3.3 V
LM61480-Q1
(8-A rating)
Pin selectable
Pin selectable
Pin selectable
Pin selectable
Pin selectable
Pin selectable
8 A
6 A
4.0 V
5.0 V
Adjustable
3.3 V
LM62460-Q1
(6-A rating)
4.0 V
5.0 V
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6 Pin Configuration and Functions
3.5 mm
16
PGND2
15
14
1
2
PGND1
VIN2
VIN1
13
12
3
4
RBOOT
CBOOT
BIAS
EN
SYNC/
MODE
SPSP 11
5
6
VCC
RESET
10
7
8
9
Figure 6-1. 16-Pin VQFN RPH Package (Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Power ground to internal low-side MOSFET. Connect to system ground. Low-impedance
connection must be provided to PGND1. Connect a high-quality bypass capacitor or
capacitors from this pin to VIN2.
PGND2
1
G
Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this
pin to PGND2. Provide a low-impedance connection to VIN1.
VIN2
2
3
4
P
P
P
Connect to CBOOT through a resistor. A resistance, typically between 0 Ω and 100 Ω, is
used to adjust the slew rate of the SW node rise time. See Figure 8-10.
RBOOT
CBOOT
High-side driver upper supply rail. Connect a 100-nF capacitor between the SW pin and
CBOOT. An internal diode charges the capacitor while SW node is low.
Input to internal voltage regulator. Connect the pin to an output voltage point or an external
bias supply from 3.3 V to 12 V. Connect an optional high-quality 0.1-µF capacitor from this
pin to GND for the best performance. If output voltage is above 12 V and no external supply
is used, tie the pin to ground.
BIAS
5
P
Internal regulator output. Used as supply to internal control circuits. Do not connect this pin
to any external loads. Connect a high-quality 1-µF capacitor from this pin to AGND.
VCC
FB
6
7
8
9
O
I
Feedback input to regulator. Connect this pin to an output voltage sense point for fixed
output versions (for example, 3.3 V and 5 V). Connect this pin to a feedback divider tap point
for adjustable output options. Do not float or ground.
Analog ground for regulator and system. All electrical parameters are measured with respect
to this pin. Connect this pin to PGND1 and PGND2 on PCB.
AGND
RT
G
Connect this pin to ground through a resistor with a value between 6.8 kΩ and 80 kΩ to
set the switching frequency between 200 kHz and 2200 kHz. Connect to VCC for 400 kHz.
Connect to GND for 2.2 MHz. Do not float.
I/O
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Table 6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Open-drain RESET output. Connect to a suitable voltage supply through a current limiting
resistor. High = power OK, low = fault. RESET goes low when EN = low.
RESET
10
O
Connect to VCC or through a resistor to ground to enable spread spectrum. Connect to GND
to disable spread spectrum. If using spread spectrum, a VCC connection turns off the spread
spectrum tone correction while a resistor to ground adjusts the tone correction to lower the
output voltage ripple. Do not float this pin. See Section 8.3.10.
SPSP
11
12
I
I
This pin controls the mode of operation of the LM6x4xx. Modes include Auto mode
(automatic PFM/PWM operation), forced pulse width modulation (FPWM), and synchronized
to an external clock. The clock triggers on the rising edge of an applied external clock.
Pull low to enable PFM operation, pull high to enable FPWM, or connect to a clock to
synchronize to an external frequency in FPWM mode. Do not float this pin.
SYNC/MODE
When synchronized to an external clock, use the RT pin to set the internal frequency close
to the synchronized frequency to avoid disturbances if the external clock is turned on and off.
Precision enable input to regulator. High = on, low = off. Can be connected to VIN. Precision
enable allows the pin to be used as an adjustable UVLO. Do not float. See Section 8.3.2.
EN
13
14
I
Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this
pin to PGND1. Low-impedance connection must be provided to VIN2.
VIN1
P
Power ground to internal low-side MOSFET. Connect to system ground. Low-impedance
connection must be provided to PGND2. Connect a high-quality bypass capacitor or
capacitors from this pin to VIN1.
PGND1
SW
15
16
G
P
Switch node of the regulator. Connect to the output inductor.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
42
UNIT
Transient VIN to AGND, PGND(2)
Continuous VIN to AGND, PGND(2)
SW to AGND, PGND(3)
36
VIN + 0.3
5.5
42
RBOOT, CBOOT to SW
Transient EN or SYNC/MODE to AGND, PGND(2)
Voltages
V
Continuous EN or SYNC/MODE to AGND, PGND(2)
36
BIAS to AGND, PGND
16
FB to AGND, PGND: Fixed Versions
FB to AGND, PGND: Adjustable Versions
RESET to AGND, PGND
16
5.5
20
Current
Voltages
Tstg
RESET sink current(5)
RT to AGND, PGND
VCC to AGND, PGND
PGND to AGND(4)
0
10
mA
V
-0.3
–0.3
–1
5.5
5.5
2
Storage temperature
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) A maximum of 42V can be sustained at this pin for duration of ≤100ms at a duty cycle of ≤0.01%. 36 V can be sustained for the life of
this device.
(3) A voltage of 2V below GND and 2V above VIN can appear on this pin for ≤200ns with a duty cycle of ≤ 0.01%.
(4) This specification applies to voltage durations of 100 ns or less. The maximum D.C. voltage should not exceed +/- 0.3V.
(5) Do not exceed pin 's voltage rating.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC
±2000
V
Q100-002(1) HBM ESD Clasification Level 2
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011 CDM ESD clasiffication Level C5
±750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
UNIT
V
Input voltage
Output voltage Output Adjustment Range for adjustable output versions (2)
Input Voltage Range(1)
3
36
0.95 × VIN
2200
1
V
Frequency
Frequency adjustment range
200
kHz
Sync
Frequency
Synchronization frequency range
200
2200
kHz
Output current IOUT, LM62460
Output current IOUT, LM61480
Output current IOUT, LM61495
0
0
0
6
8
A
A
A
10
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Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
UNIT
Temperature
Operating junction temperature, TJ
–40
150
°C
(1) 3.7 V is required at VIN for start up, an extended input voltage range down to 3.0 V is possible after start up; See the minimum input
voltage for startup conditions.
(2) Under no conditions should the output voltage be allowed to fall below zero volts.
7.4 Thermal Information
LM6X4XX
THERMAL METRIC (1)
RPH
16 PINS
21.6
51.3
19.2
12.2
1.1
UNIT
RθJA
Junction-to-ambient thermal resistance (LM61495RPHEVM) (3)
Junction-to-ambient thermal resistance (JESD 51-7) (2)
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJC(top)
RθJB
Junction-to-board thermal resistance
ΨJT
Junction-to-top characterization parameter
ΨJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12
RθJC(bot)
-
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes.
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For example, the EVM RΘJA = 21.6 °C/W. For design information please see the
Maximum Ambient Temperature section.
(3) Refer to the EVM User's Guide for board layout and additional information. For thermal design information please see the Maximum
Ambient Temperature section.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is output set point.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Needed to start up
3.7
3
V
V
V
VIN
Minimum operating input voltage
Minimum voltage hysteresis
Once Operating
VIN_OP_H
IQ
ISD
IB
1
Non-switching input current; measured
at VIN pin (3)
VIN =13.5 V, VFB = +5%, VBIAS = 5 V
VEN = 0 V, VIN = 13.5V
0.662
10
7.5
26
µA
µA
µA
Shutdown quiescent current; measured
at VIN pin
0.662
18.5
VIN = 13.5 V, VFB = +5%, VBIAS = 5 V,
Auto Mode Enabled
Current into BIAS pin (not switching)
ENABLE (EN PIN)
VEN
Enable input-threshold voltage - rising
VEN rising
1.161
0.25
0.4
1.263
0.3
1.365
0.5
V
V
VEN_HYST
VEN_WAKE
IEN
Enable threshold hysteresis
Enable Wake-up threshold
Enable pin input current
V
VIN = VEN = 13.5 V
50
nA
INTERNAL LDO (VCC PIN)
VIN = 13.5 V, VBIAS = 0V
3.4
3.2
VCC
Internal VCC voltage
V
VIN = 13.5 V, VBIAS = 3.3 V, 20 mA
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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is output set point.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN voltage at which Internal VCC under
voltage lock-out is released
VCC_UVLO
IVCC = 0A
3.7
V
V
Internal VCC under voltage lock-out
hysteresis
VCC_UVLO_HYST
Hysteresis below VCC_UVLO
1.2
VOLTAGE REFERENCE (FB PIN)
Initial reference voltage accuracy for 3.3
V option
VFB_3.3V
VFB_4V
VFB_5V
VFB
VIN = 5 V to 36 V, FPWM Mode
VIN = 5 V to 36 V, FPWM Mode
VIN = 6 V to 36 V, FPWM Mode
VIN = 3.0 V to 36 V, FPWM Mode
3.24
3.9
3.3
4
3.34
4.04
5.06
1.01
V
Initial reference voltage accuracy for 4
V option
Initial reference voltage accuracy for 5
V option
4.91
0.99
5
V
V
Initial reference voltage accuracy for
adjustable (1 V FB) versions
1
5 V Fixed Option
1.8
2.1
2.2
RFB
Resistance from FB to AGND
Input current from FB to AGND
4 V Fixed Option
MΩ
nA
3.3 V Fixed Option
IFB
CURRENT LIMITS
Adjustable versions only, VFB = 1 V
50
ISC_6
Short circuit high-side current Limit
8
10.35
6.9
12.6
8.1
A
A
A
A
A
A
A
A
A
A
A
A
ILS-LIMIT_6
IPEAK-MIN_6
IL-NEG_6
Low-side current limit
5.7
6 A Variant, Duty cycle approaches 0%
8 A Variant, Duty cycle approaches 0%
Minimum Peak Inductor Current
Negative current limit
1.2
–4.9
11.5
8
–3.8
13.8
9.2
–2.4
15.6
10.4
ISC_8
Short circuit high-side current Limit
Low-side current limit
ILS-LIMIT_8
IPEAK-MIN_8
IL-NEG_8
Minimum Peak Inductor Current
Negative current limit
1.6
–6.4
14
–5.3
17.3
11.5
1.8
–3.9
20
ISC_10
Short circuit high-side current Limit
Low-side current limit
ILS-LIMIT_10
IPEAK-MIN_10
IL-NEG_10
9.8
12.9
10 A Variant, Duty cycle approaches
0%
Minimum Peak Inductor Current
Negative current limit
–6.6
10
–5.3
–4
200
Zero-cross current limit. Positive current
direction is out of SW pin.
IL-ZC
Auto Mode, static measurement
mA
V
VHICCUP
Hiccup threshold on FB pin
0.36
0.4
0.44
POWER GOOD (/RESET PIN)
V RESET-OV RESET upper threshold - Rising
V RESET-UV
% of FB voltage
% of FB voltage
110
92
112
94
114
%
%
RESET lower threshold - Falling
96.5
RESET UV threshold as percentage of
steady state output voltage with output
voltage and UV threshold, falling, read
at the same TJ, and VIN.
V RESET_GUARD
Falling
97
%
V RESET-HYS-
RESET fallling threshold hysteresis
RESET rising threshold hysteresis
% of FB voltage
% of FB voltage
0.5
0.5
1.3
1.3
2.5
2.5
1.2
%
%
V
FALLING
V RESET-HYS-
RISING
Minimum input voltage for proper
RESET function
Measured when VRESET < 0.4 V with 10
kOhm pullup to external 5 V
V RESET_VALID
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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is output set point.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
46.0 µA pull up to RESET pin, VIN = 1.0
V, VEN = 0 V
0.4
RESET Low-level function output
voltage
1 mA pull up to RESET pin, VIN = 13.5
V, VEN = 0 V
VOL
0.4
0.4
V
2 mA pull up to RESET pin, VIN = 13.5
V, VEN = 3.3 V
RRESET
RRESET
RESET ON resistance,
RESET ON resistance,
VEN = 5 V, 1mA pull up current
VEN = 0 V, 1mA pull up current
44
18
125
40
Ω
Ω
OSCILLATOR (SYNC/MODE PIN)
VSYNCDL
SYNC/MODE input voltage low
0.4
V
V
V
VSYNCDH
SYNC/MODE input voltage high
1.7
1
VSYNCD_HYST
SYNC/MODE input voltage hysteresis
0.185
Internal pulldown resistor to ensure
SYNC/MODE doesn't float
RSYNC
100
1.9
kΩ
HIGH SIDE DRIVE (CBOOT PIN)
Voltage on CBOOT pin compared to
SW which will turnoff high-side switch
VCBOOT_UVLO
V
MOSFETS
RDS-ON-HS
RDS-ON-LS
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
Load = 1 A, CBOOT-SW = 3.2 V
Load = 1 A, CBOOT-SW = 3.2 V
21
13
39
25
mΩ
mΩ
7.6 Timing Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
6.9
TYP
MAX UNIT
PWM LIMITS (SW PIN)
VIN =18 V, VSYNC/MODE = 5 V, IOUT = 2A,
RBOOT = 0 Ω
tON-MIN
Minimum HS switch on-time
62
81
ns
tOFF-MIN
Minimum HS switch off-time
Maximum switch on-time
VIN = 5 V
70
103
11
ns
µs
tON-MAX
HS timeout in dropout
8.9
START UP
VIN = 13.5 v, CVCC = 1 µF, time from EN
high to first SW pulse if output starts at
0 V
tEN
Turn-on delay
0.82
1.2
2.7
ms
Time from first SW pulse to VREF at
90%, of set point.
tSS
tW
1.7
2.2
40
ms
ms
Short circuit wait time ("hiccup" time)
POWER GOOD (/RESET PIN) and OVERVOLTAGE PROTECTION
tRESET_FILTER
tRESET_ACT
RESET edge deglitch delay
RESET active time
10
26
45
µs
Time FB must be valid before RESET is
released.
1.2
2.1
3.75
ms
OSCILLATOR (SYNC/MODE PIN)
High duration needed to be recognized
on SYNC/MODE pin
tPULSE_H
tPULSE_L
tMSYNC
100
100
7
ns
ns
µs
Low duration needed to be recognized
on SYNC/MODE pin
Time at one level needed to indicate
FPWM or Auto Mode
20
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Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MIN
TYP
MAX UNIT
Time needed for clock to lock to a valid
synchronization signal
tLOCK
RT = 39.2 kΩ
4.3
ms
7.7 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX UNIT
OSCILLATOR (RT and SYNC PINS)
fOSC
fOSC
Internal oscillator frequency
RT = GND
RT = VCC
1.90
350
2.2
2.42
440
MHz
kHz
Internal oscillator frequency
400
Oscillator frequency measured using
fFIXED_2.2MHz
maximum value of RT resistor to select RT = 6.81 kΩ
2.2 MHz
1.95
2.2
2.42
MHz
Oscillator frequency measured using
minimum value of RT resistor to select RT = 40.2 kΩ
0.4 MHz
fFIXED_0.4MHz
352
630
400
700
448
770
kHz
kHz
fADJ
Center Trim oscillator frequency
RT = 22.6 kΩ
SPREAD SPECTRUM
Frequency increase of internal oscillator
from spread spectrum
ΔFc+
1
4
7.5
-1
%
%
Frequency decrease of internal
oscillator from spread spectrum
ΔFc-
-8
-4
SWITCH NODE
While in frequency fold-back
fsw =1.85 MHz
98
DMAX
Maximum switch duty cycle
%
87
7.8 System Characteristics
The following specifications apply only to the typical application circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to
the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Input voltage for full functionality at
reduced load, after start-up.
VVIN_MIN1
3
V
V
Input voltage for full functionality at
100% of maximum rated load, after
start-up.
VVIN_MIN2
VOUT set to 3.3 V
3.95
VIN = 13.5 V, VOUT = 3.3 V fixed, IOUT
0 A, Auto mode
=
5
8
Input current to VIN node of DC/DC for
fixed VOUT versions
IQ_VIN
µA
VIN = 13.5 V, VOUT = 5 V fixed, IOUT = 0
A, Auto mode
VOLTAGE REFERENCE (FB PIN)
VOUT = 5 V, VIN = 6 V to 36 V, IOUT = 1 A
VOUT_5V_ACC
VIN = 6 V to 36 V , PWM Operation
–1.5
–1.5
–1.5
–1.5
1.5
2.5
1.5
2.5
%
%
to full load (1)
VOUT = 5 V, VIN = 6 V to 36 V, IOUT = 0 A VIN = 6 V to 36 V, PFM and PWM
to full load (1)
operation
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT
1 A to full load (1)
=
VOUT_3r3V_ACC
VIN = 3.8 V to 36 V , PWM Operation
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = VIN = 3.8 V to 36 V, PFM and PWM
0 A to full load (1)
operation
THERMAL SHUTDOWN
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The following specifications apply only to the typical application circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to
the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
158
150
TYP
168
159
MAX UNIT
TSD_R
TSD_F
Thermal shutdown tripping threshold
Thermal shutdown recovery threshold
180
ºC
ºC
OTHER PARAMATERS
Input to output voltage differential to
VDROP1
maintain regulation accuracy, without
inductor DCR drop
0.45
1.2
V
V
Input to output voltage differential to
maintain fSW ≥ 1.85 MHz, without
inductor DCR drop
VDROP2
VIN =13.5 V, VOUT = 5.0 V, IOUT = 5 A,
RRBOOT = 0 Ω
Typical 2.2MHz Efficiency
Typical 400 kHz Efficiency
Typical 250 kHz Efficiency
92.6
95.1
93.7
VIN = 13.5 V, Vout = 5.0 V, IOUT = 8 A,
RRBOOT = 0 Ω
ƞ
%
VIN = 13.5 V, Vout = 5.0 V, IOUT = 10 A,
RRBOOT = 0 Ω
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7.9 Typical Characteristics
Unless otherwise specified, VIN = 13.5 V.
1.004
1.003
1.002
1.001
1
1.5
1.25
1
0.75
0.5
0.25
0
0.999
0.998
0.997
0.996
3 V
13.5 V
36 V
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
EN = 0 V
Figure 7-1. Feedback Voltage
Figure 7-2. Shutdown Supply Current
35
30
25
20
15
10
18
17
16
15
14
13
12
11
10
9
HS Switch
LS Switch
HS Limit
LS Limit
8
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 7-3. High-side and Low-side Switches
RDS_ON
Figure 7-4. High-side and Low-side Current Limits
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8 Detailed Description
8.1 Overview
The LM6x4xx-Q1 is a wide-input and output-voltage range, low-quiescent current, high-performance regulator
that operates over a wide range of frequencies and conversion ratios. If the minimum on-time or minimum
off-time does not support the desired conversion ratio, the frequency is reduced. This action automatically allows
regulation to be maintained during load dump and with very low dropout during cranking.
This device is designed to minimize end-product cost and size while operating in demanding automotive and
high-performance industrial environments. The LM6x4xx-Q1 can be set to operate at fixed 400 kHz, fixed 2.2
MHz, or is adjustable from 200 kHz to 2.2 MHz using the RT pin. Internal compensation and an accurate current
limit scheme minimizes BOM cost and component count. In addition, the RESET output feature with built-in
delayed release and low-current light-load mode lets the user eliminate a backup LDO and reset chip in many
applications.
The LM6x4xx-Q1 has been designed for low EMI. The device includes the following:
•
•
•
•
Adjustable switch node rising slew rate
Pin-configurable spread spectrum
Low input inductance package
Operation over a frequency range above and below AM radio band
Together, these features can eliminate shielding and other expensive EMI mitigation measures.
To use the device in reliability-conscious environments, the LM6x4xx-Q1 has a package with enlarged corner
terminals for improved BLR and wettable flanks, allowing optical inspection.
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8.2 Functional Block Diagram
SPSP
RT
VCC
Clock
VCC
MODE/
SYNC
Detect
MODE
/SYNC
Sync
Oscillator
BIAS
VCC UVLO
OTP
Slope
compensation
LDO
VIN
Over
Temperature
detect
FPWM/Auto
Frequency Foldback
RBOOT
CBOOT
VIN1
System enable
Enable
EN
HS Current
sense
Error
amplifier
+
+
œ
VIN
VIN2
Comp Node
œ
Clock
+
High and
low limiting
circuit
+
Output
low
HS
Current
Limit
œ
SW
System enable
OTP
FB
Drivers and
logic
Soft start
circuit and
bandgap
Hiccup active
VCC UVLO
LS
Current
Limit
œ
AGND
+
Voltage Reference
œ
PGND1
PGND2
+
LS
Current
Min
FPWM/Auto
Vout OV
PGOOD
PGOOD
Logic with
filter and
LS Current
sense
release delay
System enable
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8.3 Feature Description
8.3.1 Output Voltage Selection
A voltage divider between output voltage and the FB pin is used to adjust output voltage. See Figure 8-1.
VOUT
RFBT
FB
RFBB
AGND
Figure 8-1. Setting Output Voltage of Adjustable Versions
The LM6x4xx-Q1 uses a 1-V reference for control to derive Equation 1. This equation can be used to determine
RFBB for a desired output voltage and a given RFBT. Usually, RFBT is limited to a maximum value of 100 kΩ
to prevent shifting due to PCB leakage under harsh conditions. A larger resistance of up to 1 MΩ can be
used to improve light load efficiency in cleaner environments, or the fixed output voltage options under harsher
conditions.
RFBT
RFBB
=
VOUT Å 1
(1)
In addition, a feedforward capacitor CFF can be used to optimize the transient response.
8.3.2 Enable EN Pin and Use as VIN UVLO
Apply a voltage less than 0.4 V to the EN pin to put the device into shutdown mode. In shutdown mode, the
quiescent current drops to 0.66 µA (typical). Above this voltage but below the LM6x4xx-Q1 lower EN threshold,
VCC is active but the SW node remains inactive. Once EN is above VEN, the chip operates normally as long as
input voltage is above the minimum operating voltage.
The EN terminal cannot be left floating. The simplest way to enable the operation is to connect the EN pin to
VIN. This action allows the self-start-up of the device when VIN drives the internal VCC above its UVLO level.
However, many applications benefit from employing an enable divider string, which establishes a precision input
undervoltage lockout (UVLO). The precision UVLO can be used for the following:
•
•
•
Sequencing
Preventing the device from retriggering when used with long input cables
Reducing the occurrence of deep discharge of a battery power source
Note that EN thresholds are accurate. The rising enable threshold has 8.1% tolerance. Hysteresis is enough to
prevent retriggering upon shutdown of the load (approximately 25%). The external logic output of another IC can
also be used to drive the EN terminal, allowing system power sequencing.
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VIN
RENT
EN
RENB
AGND
Figure 8-2. VIN UVLO Using the EN Pin
Resistor values can be calculated using Equation 2:
V
VEN
ON Å 1
‡ RENB
RENT
=
(1 Å V
)
VOFF =VON
‡
EN-HYST
(2)
where
•
•
VON = VIN turn-on voltage
VOFF = VIN turn-off voltage
8.3.3 SYNC/MODE Uses for Synchronization
The LM6x4xx-Q1 SYNC/MODE pin can be used to synchronize the internal oscillator to an external clock. The
internal oscillator can be synchronized by coupling a positive edge into the SYNC/MODE pin. The coupled edge
voltage at the SYNC/MODE pin must exceed the SYNC amplitude threshold of VSYNCDH to trip the internal
synchronization pulse detector. The minimum SYNC rising pulse and falling pulse durations must be longer than
tPULSE_H and tPULSE_L respectively. The LM6x4xx-Q1 switching action can be synchronized to an external clock
from 200 kHz to 2.2 MHz.
SYNC/MODE
Clock
Range
AGND
Figure 8-3. Typical Implementation Allowing Synchronization Using the SYNC/MODE Pin
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tPULSE_L
VSYNCDH
VSYNCDL
t
tPULSE_H
This image shows the conditions needed for detection of a synchronization signal.
Figure 8-4. Typical SYNC/MODE Waveform
8.3.4 Clock Locking
Once a valid synchronization signal is detected, a clock locking procedure is initiated. After approximately
2048 pulses, the clock frequency abruptly changes to the frequency of the synchronization signal. While the
frequency adjusts suddenly, phase is maintained so the clock cycle lying between operation at the default
and synchronization frequencies is of intermediate length. There are no very long or very short pulses. Once
frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges
correspond to rising the SW node pulses. See Figure 8-5.
Pulse
~2048
Pulse
~2049
Pulse
~2050
Pulse
~2051
Pulse 1
Pulse 2
Pulse 3
Pulse 4
VSYNCDH
VSYNCDL
Synchronization
signal
Spread Spectrum is on between pulse 1 and pulse 2048,
there is no change to operating frequency. At pulse 4,
the device transitions from Auto Mode to FPWM.
Also clock frequency matches the
synchronization signal and phase
locking begins
Phase lock achieved, Rising edges
align to within approximately 45 ns,
no spread spectrum
On approximately pulse 2048, spread
spectrum turns off
SW Node
VIN
GND
At pulse 4, the synchronization signal is detected. After approximately pulse 2048, it is ready to synchronize and the frequency is
adjusted using a glitch-free technique. Later, phase is locked.
Figure 8-5. Synchronization Process
8.3.5 Adjustable Switching Frequency
The RT pin is configurable. This pin can be tied to VCC for 400-kHz operation, grounded for 2.2-MHz operation,
or a resistor to AGND can be used to set an adjustable operating frequency. See Figure 8-6 for resistor values.
Note that if a resistor value falls outside of the recommended range, it can cause the LM6x4xx-Q1 to revert
to 400 kHz or 2.2 MHz. Do not apply a pulsed signal to this pin to force synchronization. If synchronization is
needed, see the SYNC/MODE pin in Section 8.3.3.
RT (kΩ) = (16.4 / fSW (MHz)) - 0.633
(3)
For example, for fSW = 400 kHz, RT = (16.4 / 0.4) - 0.633 = 40.37, so a 40.2-kΩ resistor is selected as the closest
choice.
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Figure 8-6. Setting Clock Frequency
8.3.6 RESET Output Operation
While the RESET function of the LM6x4xx-Q1 resembles a standard power-good function, the functionality is
designed to replace a discrete reset IC, reducing BOM cost. There are three major differences between the reset
function and the normal power-good function seen in most regulators:
•
•
•
A delay has been added for release of reset. See Table 8-1.
RESET output signals a fault (pulls its output to ground) while the part is disabled.
RESET continues to operate with input voltage as low as 1.2 V. Below this input voltage, RESET output can
be high impedance.
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VOUT
VRESET-OV
VRESET-HYS-FALLING
VRESET-HYS-RISING
VRESET-UV
RESET
High = Power Good
Low = Fault
Figure 8-7. RESET Static Voltage Thresholds
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VIN
VCC_UVLO_HYS
VCC_UVLO
VRESET-VALID
t
Glitches do not cause false operation nor reset timer
VOUT
VRESET-HYS-RISING
VRESET-UV
< tdg
t
RESET
< 20 V
RESET
t
trise-delay
tdg
trise-delay
Figure 8-8. RESET Timing Diagram (Excludes OV Events)
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Table 8-1. Conditions that Cause RESET to Signal a Fault (Pull Low)
FAULT CONDITION ENDS (AFTER WHICH tRESET_ACT MUST PASS
BEFORE RESET OUTPUT IS RELEASED)
FAULT CONDITION INITIATED
FB below VRESET_UV for longer than tRESET_FILTER
FB above VRESET_OV for longer than tRESET_FILTER
Junction temperature exceeds TSD_R
EN low
FB above VRESET_UV + VRESET_HYST for longer than tRESET_FILTER
FB below VRESET_OV - VRESET_HYST for longer than tRESET_FILTER
(1)
Junction temperature falls below TSD_F
tEN passes after EN becomes high(1)
VIN falls low enough so that VCC falls below VCC_UVLO
-
(1)
Voltage on VIN is high enough so that VCC pin exceed VCC_UVLO
VCC_UVLO_HYST. This value is called VIN_OPERATE
.
(1) As an additional operational check, RESET remains low during soft start. It is defined as until the lesser of either full output voltage
reached or tSS2 has passed since initiation. This is true even if all other conditions in this table are met and tRESET_ACT has passed.
Lockout during soft start does not require tRESET_ACT to pass before RESET is released.
The threshold voltage for the RESET function is specified to take advantage of the availability of the LM6x4xx-
Q1 internal feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected
output voltage to be specified at the same time as 96% of actual operating point. The net result is a more
accurate reset function while expanding the system allowance for transient response. See the output voltage
error stack-up comparison in Figure 8-9.
In addition to signaling a fault upon overvoltage detection (FB above VRESET_OV), the switch node is shut down
and a small, approximately 1-mA pulldown is applied to the SW node.
Typical SMPS upper specification
112%
Highest VFB
101.25%
100%
1.25%
Selected output voltage
VFB accuracy
Typical VFB - VRESET_UV
-1.25%
Lowest VFB
98.75%
98%
-5.75%
Typical VFB - VRESET_UV
Lowest VOUT
-5.75%
-4%
VGAURD
Highest VRESET_UV
96.5%
95%
1%
Typical SMPS lower specification
Lowest VOUT - VGAURD
-1%
94%
93%
1%
-1%
Lowest VRESET_UV
92%
High VFB case
Low VFB case
VGAURD is available margin for
ripple and step loads
Figure 8-9. Reset Threshold Voltage Stack-up
8.3.7 Internal LDO, VCC UVLO, and BIAS Input
The LM6x4xx-Q1 uses VCC as its internal power supply. VCC is, in turn, powered from VIN or BIAS. Once
the LM6x4xx-Q1 is active, power comes from VIN if BIAS is less than approximately 3.1 V. Power comes from
BIAS if BIAS is more than 3.1 V. VCC is typically 3 V to 3.3 V under most conditions, but can be lower if VIN
is very low. To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too
low. See VCC_UVLO and VCC_UVLO_HYST in Section 7.5. During start-up, VCC momentarily exceeds its normal
operating voltage until VCC_UVLO is exceeded, then drops to its normal operating voltage. These UVLO values,
when combined with the dropout of the LDO when only powering the LM6x4xx-Q1, are used to derive minimum
VIN_OPERATE and VIN_OP_H
.
8.3.8 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The
capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the CBOOT
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terminal to (SW + VCC). The boot diode is integrated on the LM6x4xx-Q1 die to minimize the physical solution
size. TI recommends a 100-nF capacitor rated for 10 V with X7R or better dielectric for the CBOOT capacitor.
The boot (CBOOT) rail has a UVLO to protect the chip from operation with too little bias. This UVLO has a
threshold of VBOOT_UVLO and is typically 2.1 V. If the CBOOT capacitor voltage drops below VBOOT_UVLO, then
the device initiates a charging sequence using the low-side FET before attempting to turn on the high-side
device.
8.3.9 Adjustable SW Node Slew Rate
To allow optimization of EMI with respect to efficiency, the LM6x4xx-Q1 is designed to allow a resistor to select
the strength of the high-side FET driver during turn-on. See Figure 8-10. The current drawn through the RBOOT
pin (the dotted loop) is magnified and drawn through from CBOOT (the dashed line). This current is used to turn
on the high-side power MOSEFT.
VIN
VCC
CBOOT
HS FET RBOOT
HS
Driver
SW
LS FET
Figure 8-10. Simplified Circuit Showing How RBOOT Functions
Rise time is rapid with RBOOT short circuited to CBOOT. In this condition SW node harmonics roll off at -20
dBµV per decade until around 150 MHz where the harmonics begin rolling off at -40 dBµV per decade. Slowing
the rise time decreases the frequency where this transition occurs which provides more rolloff in the higher
frequencies which provides more margin on EMI scans. If CBOOT and RBOOT are connected through 700 Ω,
slew time due to high-side turnon is limited to no more than 13 ns. 10 ns is typical when converting 13.5 V to
5 V. This slow rise time allows energy in SW node harmonics to roll off near 50 MHz under most conditions.
Rolling off harmonics eliminates the need for shielding and common mode chokes in many applications. Note
that rise time increases with increasing input voltage. Noise due to stored charge is also greatly reduced with
higher RBOOT resistance. Switching with a slower slew rate decreases efficiency. Take care to optimize the
resistance to provide the best EMI while not generating too much heat. If RBOOT is left open, rise time is set to
its maximum value.
8.3.10 Spread Spectrum
Spread spectrum is configurable using the SPSP pin. Spread spectrum eliminates peak emissions at specific
frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency
operation. The LM6x4xx-Q1 implements a modulation pattern designed to reduce low frequency-conducted
emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher
harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the
environment through electric fields around the switch node and inductor. The LM6x4xx-Q1 uses a ±4% (typical)
spread of frequencies which can spread energy smoothly across the FM and TV bands. The device implements
Dual Random Spread Spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern
and pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at
spreading the energy at the following:
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•
•
Fundamental switching harmonic with slow triangular pattern
High frequency harmonics with additional psuedorandom jumps at the switching frequency
The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller
fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is
introduced at the modulating frequency. Additionally, the LM6x4xx-Q1 also allows you to further reduce the
output voltage ripple caused by the spread spectrum modulating pattern. With the SPSP pin grounded, the
spread spectrum is disabled. With the SPSP pin tied to VCC, the spread spectrum is on. With the SPSP pin
tied through a resistor to ground, the spread spectrum is on. Also, a modulating tone correction is applied to the
switcher to reduce the output voltage ripple caused by the frequency modulation. The resistor is usually around
20 kΩ, and can be more precisely calculated using Equation 4.
VIN
14.17 x
VOUT
RSPSP (kꢀ) =
VIN - VOUT
+ 1.22
I RATED x L x fSW
(4)
Figure 8-11. Output Ripple Without Ripple Cancellation Showing VSW (top), FSW (middle), VOUT (bottom)
Figure 8-12. Output Ripple with Ripple Cancellation Showing VSW (top), FSW (middle), VOUT (bottom)
The spread spectrum is only available while the clock of the LM6x4xx-Q1 are free running at their natural
frequency. Any of the following conditions overrides spread spectrum, turning it off:
•
The clock is slowed due to operation at low input voltage. This is operation in dropout.
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•
•
•
The clock is slowed under light load in auto mode. This is normally not seen above 750-mA load. Note that if
the device is operating in FPWM mode, spread spectrum is active, even if there is no load.
The clock is slowed due to high input-to-output voltage ratio. This mode of operation is expected if on-time
reaches minimum on-time. See the Timing Characteristics.
The clock is synchronized with an external clock.
8.3.11 Soft Start and Recovery From Dropout
When designing with the LM6x4xx-Q1, slowed rise in output voltage due to recovery from dropout and soft start
must be considered separate phenomena. Soft start is triggered by any of the following conditions:
•
•
•
•
EN is used to turn on the device.
Recovery from a hiccup waiting period; see Section 8.3.13.
Recovery from shutdown due to overtemperature protection
Power is applied to the VIN of the IC or the VCC UVLO is released.
Once soft start is triggered, the IC takes the following actions:
•
•
•
The reference used by the IC to regulate output voltage is slowly ramped from zero. The net result is that
output voltage, if previously 0 V, takes tSS to reach 90% of its desired value.
Operating mode is set to auto, activating diode emulation. This allows start-up without pulling output low if
there is a voltage already present on the output.
Hiccup is disabled for the duration of soft start; see Section 8.3.13.
All of these actions together provide start-up with limited inrush currents. They also allow the use of output
capacitors and loading conditions that cause current to border on current limit during start-up without triggering
hiccup. In addition, if output voltage is already present, output is not pulled down. See Figure 8-13.
If selected, FPWM
is enabled after
regulation but no
later than tSS2
If selected, FPWM
is enabled after
regulation but no
later than tSS2
Triggering event
Triggering event
tEN
tSS
tEN
tSS
V
V
VEN
VEN
VOUT Set
Point
VOUT Set
Point
VOUT
VOUT
90% of
VOUT Set
Point
90% of
VOUT Set
Point
t
t
0 V
0 V
Time
Time
tSS2
tSS2
The left curves show soft start from 0 V. The right curves show soft starting behavior from a pre-biased or non-zero voltage. In either
case, the output voltage reaches within 10% of the desired setpoint tSS time after soft start is initiated. During soft start, FPWM and
hiccup are disabled. Both hiccup and FPWM are enabled once output reaches regulation or tSS2, whichever happens first.
Figure 8-13. Soft-Start Operation
Any time output voltage is more than a few percent low for any reason, output voltage ramps up slowly. This
condition, called recovery from dropout, differs from soft start in three important ways:
•
•
Hiccup is allowed only if output voltage is less than 0.4 times its set point. Note that during dropout regulation
itself, hiccup is inhibited. See Section 8.3.13.
FPWM mode is allowed during recovery from dropout. If output voltage were to suddenly be pulled up by an
external supply, the LM6x4xx-Q1 can pull down on the output. Note that all the protections that are present
during normal operation are in place, protecting the device if output is shorted to a high voltage or ground.
The reference voltage is set to approximately 1% above that needed to achieve the current output voltage. It
is not started from zero.
•
Despite the name, recovery from dropout is active whenever output voltage is more than a few percent lower
than the setpoint for long enough that:
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•
•
Duty factor is controlled by minimum on-time or
When the part is operating in current limit.
This primarily occurs under the following conditions:
•
•
Dropout: When there is insufficient input voltage for the desired output voltage to be generated. See Section
8.4.3.5.
Overcurrent that is not severe enough to trigger hiccup or if the duration is too short to trigger hiccup. See
Section 8.3.13.
V
Load
current
VOUT Set
Point
and max
output
Slope
VOUT
the same
as during
soft start
current
t
Time
Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall below its setpoint is
removed, output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, it can, in principal,
be triggered during recovery if output voltage is below 0.4 times output the setpoint for more than 128 clock cycles during recovery.
Figure 8-14. Recovery From Dropout
8.3.12 Overcurrent and Short Circuit Protection
The LM6x4xx-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
and the low-side MOSFETs.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is
compared to the minimum of a fixed current setpoint, or the output of the voltage regulation loop minus slope
compensation, every switching cycle. Since the voltage loop has a maximum value and slope compensation
increases with duty cycle, the HS current limit decreases with increased duty cycle if duty cycle is above 35%.
See Figure 8-15.
12
10
8
6
4
2
HS Maximum Current
Rated Maximum Output
0
0
0.2
0.4 0.6 0.8
Duty Cycle
1
FEAT
Figure 8-15. Maximum Current Allowed Through the HS FET - Function of Duty Cycle for LM62460-Q1
When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side
device, the low-side device turn-off is commanded by the voltage control loop. For a low-side device, turn-off is
prevented if current exceeds this value, even if the oscillator normally starts a new switching cycle. See Section
8.4.3.4. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This is
called the low-side current limit; see the Electrical Characteristics for values. If the LS current limit is exceeded,
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the LS MOSFET stays on and the HS switch is not turned on. The LS switch is turned off once the LS current
falls below its limit. The HS switch is turned on again as long as at least one clock period has passed since the
last time the HS device has turned on.
VSW
VIN
tON < tON_MAX
0
t
Typically, tSW > Clock setting
iL
IL-HS
IL-LS
IOUT
t
0
Figure 8-16. Current Limit Waveforms
The net effect of the operation of high-side and low-side current limit is that the IC operates in hysteretic control.
Since the current waveform assumes values between IL-HS and IL-LS, output current is close to the average of
these two values unless duty cycle is very high. Once operating in current limit, hysteretic control is used and
current does not increase as output voltage approaches zero.
If duty cycle is very high, current ripple must be very low to prevent instability; see Section 9.2.2.3. Since current
ripple is low, the part is able to deliver full current. The current delivered is very close to IL-LS
.
VOUT
IL-LS
IOUT rated
IL-HS
VOUT Setting
VIN > 2 ‡ VOUT Setting
VIN ~ VOUT Setting
IOUT
0
0
Output Current
Under most conditions, current is limited to the average of IL-HS and IL-LS, approximately 1.4 times the rated current. If input voltage is
low, current can be limited to approximately IL-LS. Current does not exceed the average of IL-HS and IL-LS as output drops to 0.4 times
the output voltage setting. Below 0.4 times the output voltage setting, the peak current does not exceed the average of IL-HS and IL-LS
and the hiccup mode activates, preventing excessive heating.
Figure 8-17. Output Voltage versus Output Current
Once the overload is removed, the device recovers as though in soft start; see Section 8.3.11. Note that hiccup
can be triggered if output voltage drops below approximately 0.4 times the intended output voltage.
8.3.13 Hiccup
The LM6x4xx-Q1 employs hiccup overcurrent protection when all of the following conditions are met for 128
consecutive switching cycles:
•
•
•
A time greater than tSS2 has passed since soft start has started; see Section 8.3.11.
Output voltage is below approximately 0.4 times output setpoint.
The part is not operating in dropout defined as having minimum off-time controlled by duty factor.
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In hiccup mode, the device shuts itself down and attempts to soft start after tW. Hiccup mode helps reduce the
device power dissipation under severe overcurrent conditions and short circuits.
Figure 8-18. Inductor Current Bursts During
Figure 8-19. Short-Circuit Transient and Recovery
Hiccup
8.3.14 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the IC junction
temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C. After thermal shutdown
occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately
159°C. When the junction temperature falls below 159°C (typical), the LM6x4xx-Q1 attempts to soft start.
While the LM6x4xx-Q1 is shut down due to high junction temperature, power continues to be provided to
VCC. To prevent overheating from a short circuit applied to VCC, the LDO providing power to VCC has
reduced current limit while the part is disabled due to high junction temperature. The LDO only provides a
few milliamperes during thermal shutdown.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical on and off control of the device. When the EN pin voltage is below 0.4 V, both the
regulator and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode, the
quiescent current drops to typically 0.66 µA.
8.4.2 Standby Mode
The internal LDO has a lower EN threshold than the output of the regulator. The internal LDO regulates the VCC
voltage at 3.3 V, typically when:
•
•
The EN pin voltage is above 1.1 V (maximum) and
The EN pin voltage is below the precision enable threshold for the output voltage.
The precision enable circuitry is ON once VCC is above its UVLO. The internal power MOSFETs of the SW node
remain off unless the voltage on the EN terminal goes above its precision enable threshold. The LM6x4xx-Q1
also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the regulator is turned
off.
8.4.3 Active Mode
The LM6x4xx-Q1 is in active mode when the following occurs:
•
•
•
•
The EN pin is above VEN
.
VIN is above VEN
.
VIN is high enough to satisfy the VIN minimum operating input voltage.
No other fault conditions are present.
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See Section 8.3 for protection features. The simplest way to enable the operation is to connect EN to VIN,
allowing self-start-up when the applied input voltage exceeds the minimum VIN_OPERATE
.
In active mode, depending on the load current, input voltage, and output voltage, the LM6x4xx-Q1 is in one of six
sub-modes:
•
•
Continuous conduction mode (CCM) with fixed switching frequency and peak current mode operation
Discontinuous conduction mode (DCM) while in auto mode when the load current is lower than half of the
inductor current ripple. If current continues to reduce, the device enters Pulse Frequency Modulation (PFM)
which reduces the switch frequency to maintain regulation while reducing switching losses to achieve higher
efficiency at light load.
•
•
Minimum on-time operation while the on-time of the device needed for full-frequency operation at the
requested low-duty cycle is not supported by TON_MIN
Forced pulse width modulation (FPWM) similar to CCM with fixed-switching frequency, but extends the fixed
frequency range of operation from full to no load
•
•
Dropout mode when switching frequency is reduced to minimize dropout
Recovery from dropout similar to other modes of operation except the output voltage setpoint is gradually
moved up until the programmed setpoint is reached.
8.4.3.1 Peak Current Mode Operation
The following operating description of the LM6x4xx-Q1 refers to Section 8.2 and the waveforms in Figure 8-20.
Both supply a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS
switches with varying duty cycle (D). During the HS switch on-time, the SW terminal voltage, VSW, swings up to
approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by the
control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through
the LS switch, forcing VSW to swing below ground by the voltage drop across the LS switch. The regulator loop
adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over
the switching period: D = TON / (TON + TOFF).
In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
tON
VOUT
VIN
VSW
D =
≈
tSW
VIN
tOFF
tON
0
t
- IOUT‡RDSLS
tSW
iL
ILPK
IOUT
Iripple
t
0
Figure 8-20. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
To get accurate DC load regulation, a voltage feedback loop is used. Peak and valley inductor currents are
sensed for peak current mode control and current protection. The regulator operates with continuous conduction
mode with constant switching frequency when load level is above one half of the minimum peak inductor
current. The internally-compensated regulation network achieves fast and stable operation with small external
components and low-ESR capacitors.
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8.4.3.2 Auto Mode Operation
The LM6x4xx-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation,
allows a seamless transition between normal current mode operation while heavily loaded and in highly-efficient
light-load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded.
Which mode the LM6x4xx-Q1 operates in depends on the SYNC/MODE pin. When SYNC/MODE is high, the
part is in FPWM. When SYNC/MODE is low, the part is in PFM.
In auto mode, light-load operation is employed in the LM6x4xx-Q1 at load lower than approximately 1/10th of the
rated maximum output current. Light-load operation employs two techniques to improve efficiency:
•
•
Diode emulation, which allows DCM operation
Frequency reduction
Note that while these two features operate together to create excellent light load behavior, they operate
independently of each other.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current though the inductor, which requires a lower frequency needed to
regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.
Frequency will be reduced when peak inductor current goes below IPEAK-MIN. With a fixed peak current, as output
current is reduced to zero, frequency must be reduced to near zero to maintain regulation.
tON
VOUT
VIN
D =
VSW
<
tSW
VIN
tOFF
tON
tHIGHZ
0
t
tSW
iL
ILPK
IOUT
0
t
In auto mode, the low-side device is turned off once inductor current is near zero. As a result, once output current is less than half of
inductor ripple in CCM, the part operates in DCM. This is equivalent to saying that diode emulation is active.
Figure 8-21. PFM Operation
The LM6x4xx-Q1 has a minimum peak inductor current setting in auto mode. That being said, when current is
reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting
frequency . This mode of operation is called PFM mode regulation.
8.4.3.3 FPWM Mode Operation
Like auto mode operation, FPWM mode operation during light-load operation is selected using the SYNC/MODE
pin.
In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current
is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See the
Electrical Characteristics for reverse current limit values.
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VSW
tON
VOUT
VIN
D =
≈
tSW
VIN
tOFF
tON
0
t
tSW
iL
ILPK
IOUT
0
Iripple
t
FPWM mode Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple.
Figure 8-22. FPWM Mode Operation
In FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum
on-time, even while lightly loaded. This allows good behavior during faults which involves the output being pulled
up.
8.4.3.4 Minimum On-time (High Input Voltage) Operation
The LM6x4xx-Q1 continues to regulate output voltage. This is true even if the input-to-output voltage ratio
requires an on-time less than the minimum on-time of the chip with a given clock setting. This is accomplished
using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current
and a maximum valley inductor current. If, for any reason, valley current is exceeded, the clock cycle is extended
until valley current falls below that determined by the compensation circuit. If it is not operating in current limit,
the maximum valley current is set above the peak inductor current. This prevents valley control from being used
unless there is a failure to regulate using peak current only. If the input-voltage to output-voltage ratio is too
high, even though current exceeds the peak value dictated by compensation, the high-side device cannot be
turned off quickly enough to regulate output voltage. See tON_MIN in the Electrical Characteristics. As a result,
the compensation circuit reduces both peak and valley current. Once a low enough current is selected by the
compensation circuit, valley current matches that being commanded by the compensation circuit. Under these
conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor
current drops below the desired valley current. Since on-time is fixed at its minimum value, this type of operation
resembles that of a device using a COT control scheme. See Figure 8-23.
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tON
VOUT
VIN
VSW
D =
≈
tSW
VIN
tON = tON_MIN
tOFF
0
t
- IOUT‡RDSLS
tSW > Clock setting
iL
IOUT
Iripple
ILVLY
t
0
In valley control mode, the minimum inductor current is regulated, not peak inductor current.
Figure 8-23. Valley Current Mode Operation
8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the
needed duty factor. At a given clock frequency, duty factor is limited by minimum off-time. Once this limit is
reached, if clock frequency is maintained, output voltage falls. Instead of allowing the output voltage to drop, the
LM6x4xx-Q1 extends on-time past the end of the clock cycle until the required peak inductor current is achieved.
The clock can start a new cycle once peak inductor current is achieved or once a pre-determined maximum
on-time, tON-MAX, of approximately 9 µs passes. As a result, once the needed duty factor cannot be achieved at
the selected clock frequency due to the existence of a minimum off-time, frequency drops to maintain regulation.
If input voltage is low enough that the output voltage cannot be regulated even with an on-time of tON_MAX, output
voltage drops to slightly below input voltage, VDROP1. See Section 7.
VDROP2 if
frequency =
1.85 MHz
Input
Voltage
iL
VDROP1
Output
Voltage
Output
Setting
VIN
0
Input Voltage
iL
Frequency
Setting
IOUT
~100kHz
0
VIN
Input Voltage
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC
reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,
output voltage tracks input voltage.
Figure 8-24. Frequency and Output Voltage in Dropout
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tON
VOUT
VIN
VSW
D =
≈
tSW
tOFF = tOFF_MIN
VIN
tON < tON_MAX
0
t
- IOUT‡RDSLS
tSW > Clock setting
iL
ILPK
IOUT
Iripple
t
0
This image shows the switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired
peak value. As a result, frequency drops. This frequency drop is limited by tON_MAX
.
Figure 8-25. Dropout Waveforms
8.4.3.6 Recovery from Dropout
In some applications, input voltage can drop below the desired output voltage then recover to a higher value
suddenly. With most regulators, the sudden increase in input voltage results in output voltage rising at a rate
limited only by current limit until regulation is achieved. As input voltage reaches the desired output voltage,
there is overshoot due to wind up in the control loop. This overshoot can be large in applications that have small
output capacitors and light loads. Also, large inrush currents can cause large fluctuations on the input line once
the regulator starts regulating the output voltage. This typically requires less current than during this initial inrush.
The LM6x4xx-Q1 greatly reduces inrush current and overshoot. This is done by engaging the soft-start circuit
whenever the input voltage suddenly rises, after dipping low enough to cause the output voltage to droop. To
prevent this feature from accidently engaging, output voltage must fall more than 1% to engage this feature.
Also, this feature engages only if operating in dropout or current limit, preventing interference with normal
transient response but allowing several percent overshoot while engaging. If output voltage is very close to its
desired level, overshoot is reduced by inductor current not having time to rise to a high level before regulation
starts.
V
VIN
Slope
VOUT
VOUT Set
Point
the same
as during
soft start
t
Time
Figure 8-26. When Output Voltage Falls, It Recovers Slowly Preventing Overshoot and Large Inrush
Currents
8.4.3.7 Other Fault Modes
Fault modes and their description can be found in Section 8.3 of this data sheet.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LM6x4xx-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 10 A. If run at 400 kHz, 10 A can be sustained continuously. If run
at 2.2 MHz, continuous current must be limited to 6 A if ambient temperature is 105°C. The following design
procedure can be used to select components for the LM6x4xx-Q1.
9.2 Typical Application
Figure 9-1 shows a typical application circuit for the LM6x4xx-Q1. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, Table 9-2 provides typical
component values for some of the most common configurations. The values given in the table are typical. Other
values can be used to enhance certain performance criterion as required by the application. Note that for this
QFN package, the input capacitors are split and placed on either side of the package. See Section 9.2.2.5 for
more details.
6 V to 36 V input
CIN1
CIN_HF1
VIN1
VIN2
CIN2
CIN_HF2
PGND1
PGND2
L1
Output
SW
EN
CBOOT
RFF
CFF
COUT
SYNC/MODE
SPSP
CBOOT
RBOOT
RFBT
RT
FB
VCC
BIAS
RRESET
RFBB
CVCC
RESET
AGND
Figure 9-1. Example Application Circuit - 400-kHz Adjustable Output
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6 V to 36 V input
CIN1
CIN_HF1
VIN1
VIN2
CIN2
CIN_HF2
PGND1
PGND2
L1
Output
SW
EN
CBOOT
COUT
SYNC/MODE
SPSP
CBOOT
RBOOT
RT
FB
VCC
BIAS
RRESET
CVCC
RESET
AGND
Figure 9-2. Example Application Circuit - 400-kHz Fixed Output
9.2.1 Design Requirements
Table 9-1 provides the parameters for our detailed design procedure example:
Table 9-1. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
13.5 V (6 V to 36 V)
5 V
Output voltage
Maximum output current
Switching frequency
10 A continuous
400 kHz
Table 9-2. Typical External Component Values
CIN
CHF
(µF)
+
fSW
(kHz)
VOUT
RFBT
(kΩ)
RFBB
(kΩ)
CBOOT RBOOT
CVCC
(µF)
CFF
(pF)
RFF
(kΩ)
IOUT (A) L1 (µH)
(V)
COUT (RATED)
(µF)
(Ω)
5 × 22 µF ceramic or 2 x
22 µF + 15 mΩ 150 µF
2 x 10 +
2 x 0.47
400
400
400
5
10
10
10
2.7
2.7
2.2
100
Short
100
24.9
Open
43.2
0.1
0
1
1
1
10
4.99
5 Fixed
Min
BOM
1 x 10 +
2 x 0.47
2 × 47 µF ceramic
0.1
0.1
Short
0
Open
10
Open
4.99
3 × 47 µF ceramic or 3 x
22 µF + 15 mΩ 150 µF
2 x 10 +
2 x 0.47
3.3
3.3
Fixed
Min
1 x 10 +
2 x 0.47
400
10
2.2
3 × 47 µF ceramic
Short
Open
0.1
Short
1
Open
Open
BOM
3 × 22 µF ceramic or 1 x
22 µF + 15 mΩ 150 µF
2 x 10 +
2 x 0.47
2200
2200
2200
5
6
6
6
0.75
0.75
0.62
100
Short
100
24.9
Open
43.2
0.1
0.1
0.1
0
Short
0
1
1
1
10
Open
10
4.99
Open
4.99
5 Fixed
Min
BOM
1 x 10 +
2 x 0.47
2 × 33 µF ceramic
3 × 33 µF ceramic or 1 x
33 µF + 15 mΩ 150 µF
2 x 10 +
2 x 0.47
3.3
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Table 9-2. Typical External Component Values (continued)
CIN
CHF
(µF)
+
fSW
(kHz)
VOUT
(V)
RFBT
(kΩ)
RFBB
(kΩ)
CBOOT RBOOT
CVCC
(µF)
CFF
(pF)
RFF
(kΩ)
IOUT (A) L1 (µH)
COUT (RATED)
(µF)
(Ω)
3.3
Fixed
Min
1 x 10 +
2 x 0.47
2200
6
0.62
2 × 47 µF ceramic
Short
Open
0.1
Short
1
Open
Open
BOM
9.2.2 Detailed Design Procedure
The following design procedure refers to Figure 9-1 and Table 9-1.
9.2.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses, usually resulting in less power dissipated in the
IC. Lower power dissipated in the IC results in higher system efficiency and a lower IC temperature. However,
higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more compact
design. Many applications require that the AM band be avoided. These applications tend to operate at either 400
kHz below the AM band, or 2.2 MHz above the AM band. In this example, 400 kHz is chosen.
9.2.2.2 Setting the Output Voltage
The output voltage of the LM6x4xx-Q1 is externally adjustable using a resistor divider network. Two divider
networks for two recommended output voltages are found in Table 9-2. The divider network is comprised of the
top and bottom feedback resistors, RFBT and RFBB, and closes the loop between the output voltage and the
converter. The converter regulates the output voltage by holding the voltage on the FB pin equal to the internal
reference voltage, VFB = 1 V. The total resistance of the divider is a compromise between excessive noise
pickup and excessive loading of the output. Lower resistance values reduce noise sensitivity but also reduce
the light-load efficiency. The recommended value for RFBT is 100 kΩ with a maximum value of 1 MΩ. If 1 MΩ
is selected for RFBT, then a feedforward capacitor CFF must be used across this resistor to provide adequate
loop phase margin (see Section 9.2.2.9). Once RFBT is selected, Equation 1 is used to select RFBB. For this 5-V
example, RFBT = 100 kΩ and RFBB = 24.9 kΩ.
9.2.2.3 Inductor Selection
The main parameters for selecting the inductor are the inductance and saturation current. The inductance is
based on the desired peak-to-peak ripple current. It is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current for systems with a fixed input voltage. For systems with a variable input voltage such
as the 12-V battery in a car, 25% is commonly used. This example uses VIN = 13.5 V, which is closer to the
nominal voltage of a 12-V car battery. When selecting the ripple current for applications with much smaller
maximum load than the maximum available from the device, the maximum device current must still be used
for this calculation. Equation 5 can be used to determine the value of the inductance. The constant K is the
percentage of peak-to-peak inductor current ripple to rated output current. For this 10-A, 400-kHz, 5-V example,
K = 0.25 is chosen and an inductance of approximately 3.15 μH is found. The closest standard value of 3.0 μH
was selected.
VIN Å VOUT
fSW ‡ K ‡ IOUT(MAX)
VOUT
VIN
L=
‡
(5)
Ideally, the saturation current rating of the inductor should be at least as large as the high-side switch current
limit, ISC. This ensures that the inductor does not saturate, even during a soft-short condition on the output. A
hard short causes the LM6x4xx-Q1 to enter hiccup mode (see Section 8.3.13). A soft short can hold the output
current at current limit without triggering hiccup. When the inductor core material saturates, the inductance can
fall to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, ILS-LIMIT
,
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is designed to reduce the risk of current runaway, a saturated inductor can cause the current to rise to high
values very rapidly. This could lead to component damage, so it is crucial that the inductor does not saturate.
Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core
losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the
saturation current rating of the inductor. However, they have more core losses at frequencies typically above 1
MHz. To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 6. The
maximum inductance is limited by the minimum current ripple required for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device
maximum rated current under nominal conditions.
VOUT
fSW * 0.6 * IRATED
L >
(6)
9.2.2.4 Output Capacitor Selection
The output capacitor value and ESR determine the output voltage ripple and load transient performance. The
output capacitor is usually limited by the load transient requirements rather than the output voltage ripple. Table
9-3 can be used to find capacitor values for COUT and CFF for a few common applications. Note that 4.99-kΩ
RFF must be used in series with CFF. In this example, good transient performance is desired, giving 4 x 47-µF
ceramic + 220-µF electrolytic as the output capacitor and 15 pF as CFF.
Table 9-3. Selected Output Capacitor and CFF Values
3.3-V OUTPUT
5-V OUTPUT
COUT
TRANSIENT
PERFORMANCE
FREQUENCY
IOUT
COUT
CFF
CFF
400 kHz
400 kHz
10 A
10 A
Minimum
6 x 22-µF ceramic
15 pF
5 x 22-µF ceramic
15 pF
6 x 22-µF ceramic + 220-µF
electrolytic
5 x 22-µF ceramic + 220-µF
electrolytic
Better Transient
15 pF
15 pF
2.2 MHz
2.2 MHz
6 A
6 A
Minimum
5 x 22-µF ceramic
15 pF
15 pF
3 x 22-µF ceramic
15 pF
15 pF
Better Transient
5 x 22-µF ceramic + 220-µF
electrolytic
3 x 22-µF ceramic + 220-µF
electrolytic
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum of 10-μF ceramic capacitance is required
on the input of the LM6x4xx-Q1. Use 2 x 10-μF ceramic capacitance or more for better EMI performance. This
must be rated for at least the maximum input voltage that the application requires. It is preferable to have twice
the maximum input voltage to reduce DC bias derating. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size (0603 or 0402)
ceramic capacitor must be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2, immediately
adjacent to the regulator. The capacitor should have a voltage rating of at least double the maximum input
voltage to minimize derating. The capacitor must also have an X7R or better dielectric. Choose the highest
capacitor value with these parameters. This provides a high frequency bypass to reduce switch-node ring and
electromagnetic interference emissions. The QFN (RJR) package provides two input voltage pins and two power
ground pins on opposite sides of the package. This allows the input capacitors to be split and placed optimally
with respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. This
example places two 10-μF, 50-V, 1206, X7R ceramic capacitors and two 0.47-μF, 50-V, 0603, X7R ceramic
capacitors at each VIN/PGND pin pair.
Often, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help dampen ringing on the input supply caused by the inductance of the long power leads. The
use of this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually
high impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate worst
case RMS value of this current can be calculated with Equation 7. This value must be checked against the
manufacturers' maximum ratings.
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IOUT
IRMS
≈
2
(7)
9.2.2.6 BOOT Capacitor
The LM6x4xx-Q1 requires a bootstrap capacitor connected between the CBOOT pin and the SW pin. This
capacitor stores energy which is used to supply the gate drivers for the power MOSFETs. A high-quality 100-nF
ceramic capacitor with a rating of at least 10 V is required. The package provides space between the VIN2 and
RBOOT pins to route SW to the boot capacitor without needing long traces or multi-layer routing.
9.2.2.7 BOOT Resistor
A BOOT resistor can be connected between the CBOOT and RBOOT pins to slow the rise-time of the SW node.
If EMI performance is not critical, these two pins can be shorted. If EMI is critical, use a 0-Ω placeholder. The
value can be increased if additional EMI margin is required. Increase to 200 Ω as a first step. This slows the
rise-time of the SW node, reducing EMI at hundreds of MHz by a few dBµV. This is at the expense of about 0.3%
efficiency at 400 kHz at 10 A. Use 50 Ω for a similar efficiency drop at 2.2 MHz at 6 A. In this example, 0 Ω is
chosen to maximize efficiency. Continue to increase the value of RBOOT to further improve high-frequency EMI
emissions at the expense of more efficiency. RBOOT connected to pins RBOOT and CBOOT can be any value
between a short and an open without triggering BOOT UVLO.
9.2.2.8 VCC
The VCC pin is the output of the internal LDO used as a supply to the internal control circuits of the regulator.
This output requires a 1-μF, 16-V, X7R or similar, 0603 or similar ceramic capacitor connected from VCC to
AGND for proper operation. Generally avoid loading this output with any external circuitry. However, this output
can be used to supply the pullup for the RESET (power-good) function (see Section 8.3.6). A pullup resistor with
value of 100 kΩ is a good choice in this case. The nominal output voltage on VCC is 3.3 V. Do not short this
output to ground or any other external voltage.
9.2.2.9 CFF and RFF Selection
A feedforward capacitor, CFF on the order of tens of picofarads, is used to improve phase margin and transient
response of circuits which have output capacitors with low ESR. Since this CFF capacitor can conduct noise from
the output of the circuit directly to the FB node of the IC, a 4.99-kΩ resistor, RFF, must be placed in series with
CFF. If the ESR zero of the output capacitor is below 200 kHz, no CFF must be used.
If output voltage is less than 2.5 V, CFF has little effect, so it can be omitted. If output voltage is greater than 14 V,
CFF must be used cautiously since it can easily introduce too much gain at higher frequencies.
If 1 MΩ is selected for RFBT, then a feedforward capacitor CFF must be used.
9.2.2.10 RSPSP Selection
The SPSP pin can be connected to GND to disable spread spectrum. The pin can be connected to VCC to
enable spread spectrum. The pin can also be connected to GND through a resistor to enable spread spectrum
with ripple cancellation. This actively reduces the output ripple associated with spread spectrum which arises
from the inductor current ripple amplitude modulation caused by the spread spectrum frequency modulation. The
value is typically approximately 20 kΩ and can be more precisely calculated using Equation 4.
9.2.2.11 RT Selection
The RT resistor sets the switching frequency of the converter. See Section 8.3.5 for more details. A resistor value
of 40.2 kΩ corresponds to 400 kHz. The pin is also configured to set the switching frequency at 400 kHz when
the RT pin is connected to VCC. Connecting the RT pin to VCC allows you to save cost and space, but placing a
40.2-k resistor allows for more flexibility if a different frequency is desired at a later time.
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9.2.2.12 RMODE Selection
The SYNC/MODE pin allows you to synchronize the converter to an external clock voltage (SYNC). The pin also
allows the selection between two modes (MODE). The following are the selectable modes:
•
Forced pulse width modulation (FPWM) operation, which operates at a fixed frequency at all loads in typical
operation
•
Auto mode which automatically switches to pulse-frequency modulation (PFM) at light loads to improve
light-load efficiency
Connect the SYNC/MODE pin to VCC for FPWM. Connect to GND for auto. You can also apply a clock signal to
synchronize the switching frequency to an external clock. See Section 8.3.3 for more information.
9.2.2.13 External UVLO
In some cases, the user may need an input undervoltage lockout (UVLO) level different than that provided
internal to the device. This can be accomplished by using the circuit shown in Figure 8-2. The input voltage at
which the device turns on is designated VON while the turn-off voltage is VOFF. First, a value for RENB is chosen
in the range of 10 kΩ to 100 kΩ, then Equation 2 is used to calculate RENT and VOFF
.
9.2.2.14 Maximum Ambient Temperature
As with any power conversion device, the LM6x4xx-Q1 dissipates internal power while operating. The effect
of this power dissipation is to raise the internal temperature of the converter above ambient temperature. The
internal die temperature (TJ) is a function of the following:
•
•
•
•
Ambient temperature
Power loss
Effective thermal resistance, RθJA of the device
PCB layout
The maximum internal die temperature for the LM6x4xx-Q1 must be limited to 150°C. This establishes a limit
on the maximum device power dissipation and, therefore, the load current. Equation 8 shows the relationships
between the important parameters. Larger ambient temperatures (TA) and larger values of RθJA reduce the
maximum available output current. The converter efficiency can be estimated by using the curves provided in
the Application Curves section. If the desired operating conditions cannot be found in one of the curves, then
interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired
application requirements and the efficiency can be measured directly. The correct value of RθJA is more difficult
to estimate. As stated in the Semiconductor and IC Package Thermal Metrics Application Report, the value of
RθJA given in the Section 7.4 is not valid for design purposes and must not be used to estimate the thermal
performance of the device in a real application. The values reported in the Section 7.4 table were measured
under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(8)
where
•
•
•
•
η = efficiency
TA = ambient temperature
TJ = junction temperature
RθJA = the effective thermal resistance of the IC junction to the air, mainly through the PCB
The effective RθJA is a critical parameter and depends on many factors (just to mention a few of the most critical
parameters:
•
•
•
•
•
Power dissipation
Air temperature
Airflow
PCB area
Copper heat-sink area
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•
•
Number of thermal vias under or near the package
Adjacent component placement
Due to the ultra-miniature size of the VQFN (RNX) package, a die-attach pad is not available, requiring most of
the heat to flow from the pins to the board. This means that this package exhibits a somewhat large RθJA value
when the layout does not allow for heat to flow from the pins. A typical curve of maximum output current versus
ambient temperature is shown in Figure 9-3 and Figure 9-4 for a good thermal layout. This data was taken on
the LM61495RPHEVM evaluation board with a device and PCB combination, giving an RθJA of about 21.6°C/W.
It must be remembered that the data given in these graphs are for illustration purposes only, and the actual
performance in any given application depends on all of the previously mentioned factors.
VIN = 13.5 V
VOUT = 5 V
VIN = 13.5 V
VOUT = 5 V
ƒSW = 400 kHz
RθJA = 22°C/W
ƒSW = 2.2 MHz
RθJA = 22°C/W
Figure 9-3. Maximum Output Current versus
Ambient Temperature
Figure 9-4. Maximum Output Current versus
Ambient Temperature
Use the following resources as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPAD™ Thermally Enhanced Package
PowerPAD™ Made Easy
Using New Thermal Metrics
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9.2.3 Application Curves
Unless otherwise specified, the following conditions apply: Device: LM61495-Q1, VIN = 13.5 V, TA = 25°C. The circuit is
shown in Figure 9-1, with the appropriate BOM from Table 9-4.
100%
95%
90%
85%
80%
75%
70%
65%
60%
VIN = 8 V
VIN = 13.5 V
VIN = 24 V
55%
50%
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
1
1
2 3 45 7 10
VOUT = 5 V
FSW = 400 kHz
Auto mode
VOUT = 5 V
VOUT = 3.3 V
VOUT = 5 V
FSW = 400 kHz
FPWM mode
FPWM mode
FPWM mode
Figure 9-5. Efficiency
Figure 9-6. Efficiency
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
VIN = 8 V
VIN = 13.5 V
VIN = 24 V
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
2 3 45 7 10
VOUT = 3.3 V
FSW = 400 kHz
Auto mode
FSW = 400 kHz
Figure 9-7. Efficiency
Figure 9-8. Efficiency
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
VIN = 8 V
VIN = 13.5 V
VIN = 24 V
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
2 3 45 7 10
VOUT = 5 V
FSW = 2.2 MHz
Auto mode
FSW = 2.2 MHz
Figure 9-9. Efficiency
Figure 9-10. Efficiency
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9.2.3 Application Curves (continued)
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
VIN = 8 V
VIN = 13.5 V
VIN = 24 V
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
2 3 45 7 10
VOUT = 3.3 V
FSW = 2.2 MHz
Auto mode
VOUT = 3.3 V
FSW = 2.2 MHz
FPWM mode
Figure 9-11. Efficiency
Figure 9-12. Efficiency
VOUT = 5 V
FSW = 400 kHz
Auto mode
VOUT = 5 V
FSW = 400 kHz
FPWM mode
Figure 9-13. Load and Line Regulation
Figure 9-14. Load and Line Regulation
VOUT = 3.3 V
FSW = 400 kHz
Auto mode
VOUT = 3.3 V
FSW = 400 kHz
FPWM mode
Figure 9-15. Load and Line Regulation
Figure 9-16. Load and Line Regulation
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 2.2 MHz
Auto mode
VOUT = 5 V
FSW = 2.2 MHz
FPWM mode
Figure 9-17. Load and Line Regulation
Figure 9-18. Load and Line Regulation
VOUT = 3.3 V
FSW = 2.2 MHz
Auto mode
VOUT = 3.3 V
FSW = 2.2 MHz
FPWM mode
Figure 9-19. Load and Line Regulation
Figure 9-20. Load and Line Regulation
VOUT = 5 V
FSW = 400 kHz
Auto mode
VOUT = 3.3 V
FSW = 400 kHz
Auto mode
Figure 9-21. Dropout
Figure 9-22. Dropout
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 2.2 MHz
Auto mode
Auto mode
Auto mode
VOUT = 3.3 V
FSW = 2.2 MHz
Auto mode
Auto mode
Auto mode
Figure 9-23. Dropout
Figure 9-24. Dropout
VOUT = 5 V
FSW = 400 kHz
VOUT = 3.3 V
FSW = 400 kHz
Figure 9-25. Frequency Dropout
Figure 9-26. Frequency Dropout
VOUT = 5 V
FSW = 2.2 MHz
VOUT = 3.3 V
FSW = 2.2 MHz
Figure 9-27. Frequency Dropout
Figure 9-28. Frequency Dropout
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
Auto mode
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
FPWM mode
IOUT = 50 mA
IOUT = 50 mA
Figure 9-29. Switching Waveform and VOUT Ripple
Figure 9-30. Switching Waveform and VOUT Ripple
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
Auto mode
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
FPWM mode
IOUT = 50 mA
IOUT = 50 mA
Figure 9-31. Start-up with 50-mA Load
Figure 9-32. Start-up with 50-mA Load
VOUT = 3.3 V
IOUT = 3.25 A
FSW = 2100 kHz
VIN = 13.5 V
FPWM mode
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
FPWM mode
IOUT = 5 A to Short
Circuit
Figure 9-33. Start-up with 3.25-A Load
Figure 9-34. Short Circuit Protection
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 2100 kHz
FPWM mode
VIN = 13.5 V
VOUT = 5 V
IOUT = 4 A
FSW = 2100 kHz
FPWM mode
IOUT = Short Circuit to 5 A
VIN = 13.5 V to 4 V to 13.5 V
Figure 9-35. Short Circuit Recovery
Figure 9-36. Recovery from Dropout
VOUT = 5 V
IOUT = 10 mA to 10
A to 10 mA
FSW = 400 kHz
VIN = 13.5 V
FPWM mode
TR = TF = 1 µs
VOUT = 5 V
FSW = 400 kHz
VIN = 13.5 V
Auto mode
IOUT = 10 mA to 10
A to 10 mA
TR = TF = 1 µs
Figure 9-38. Load Transient
Figure 9-37. Load Transient
VOUT = 5 V
FSW = 400 kHz
VIN = 13.5 V
Auto mode
VOUT = 5 V
FSW = 400 kHz
VIN = 13.5 V
Auto mode
IOUT = 2 A to 4 A to
2 A
TR = TF = 1 µs
IOUT = 5 A to 10 A
to 5 A
TR = TF = 1 µs
Figure 9-39. Load Transient
Figure 9-40. Load Transient
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9.2.3 Application Curves (continued)
VOUT = 3.3 V
IOUT = 10 mA to 10
A to 10 mA
FSW = 400 kHz
VIN = 13.5 V
Auto mode
VOUT = 3.3 V
IOUT = 5 A to 10 A
to 5 A
FSW = 400 kHz
VIN = 13.5 V
Auto mode
TR = TF = 1 µs
TR = TF = 1 µs
Figure 9-41. Load Transient
Figure 9-42. Load Transient
VOUT = 5 V
FSW = 2200 kHz
VIN = 13.5 V
Auto mode
IOUT = 2 A to 4 A to
2 A
TR = TF = 1 µs
Figure 9-44. Load Transient
VOUT = 5 V
FSW = 2200 kHz
VIN = 13.5 V
FPWM mode
TR = TF = 1 µs
IOUT = 10 mA to 10
A to 10 mA
Figure 9-43. Load Transient
VOUT = 5 V
FSW = 2200 kHz
VIN = 13.5 V
Auto mode
IOUT = 5 A to 10 A
to 5 A
TR = TF = 1 µs
VOUT = 5 V
FSW = 400 kHz
IOUT = 10 A
Frequency Tested: 150 kHz to 30 MHz
Figure 9-45. Load Transient
Figure 9-46. Conducted EMI versus CISPR25 Class 5 Limits
(Green: Peak Signal, Blue: Average Signal)
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 400 kHz
IOUT = 10 A
VOUT = 5 V
FSW = 400 kHz
IOUT = 10 A
Frequency Tested: 30 MHz to 300 MHz
Frequency Tested: 30 MHz to 300 MHz
Figure 9-47. Radiated EMI Bicon Horizontal versus CISPR25
Class 5 Limits
Figure 9-48. Radiated EMI Bicon Vertical versus CISPR25 Class
5 Limits
VOUT = 5 V
Frequency Tested: 300 MHz to 1 GHz
Figure 9-49. Radiated EMI Log Horizontal versus CISPR25 Class Figure 9-50. Radiated EMI Log Vertical versus CISPR25 Class 5
FSW = 400 kHz
IOUT = 10 A
VOUT = 5 V
FSW = 400 kHz
IOUT = 10 A
Frequency Tested: 300 MHz to 1 GHz
5 Limits
Limits
VOUT = 5 V
FSW = 2.2 MHz
IOUT = 4 A
Frequency Tested: 150 kHz to 30 MHz
Figure 9-51. Recommended Input EMI Filter
Figure 9-52. Conducted EMI versus CISPR25 Class 5 Limits
(Green: Peak Signal, Blue: Average Signal)
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 2.2 MHz
IOUT = 4 A
VOUT = 5 V
FSW = 2.2 MHz
IOUT = 4 A
Frequency Tested: 30 MHz to 300 MHz
Frequency Tested: 30 MHz to 300 MHz
Figure 9-53. Radiated EMI Bicon Horizontal versus CISPR25
Class 5 Limits
Figure 9-54. Radiated EMI Bicon Vertical versus CISPR25 Class
5 Limits
VOUT = 5 V
Frequency Tested: 300 MHz to 1 GHz
Figure 9-55. Radiated EMI Log Horizontal versus CISPR25 Class Figure 9-56. Radiated EMI Log Vertical versus CISPR25 Class 5
FSW = 2.2 MHz
IOUT = 4 A
VOUT = 5 V
FSW = 2.2 MHz
IOUT = 4 A
Frequency Tested: 300 MHz to 1 GHz
5 Limits
Limits
Figure 9-57. Recommended Input EMI Filter
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9.2.3 Application Curves (continued)
Table 9-4. BOM for Typical Application Curves
VOUT
FREQUENCY
RFBB
COUT
CIN + CHF
L
CFF
4 x 47 µF + 100 µF
electrolytic + 2 x 2.2 µF
4 × 10 µF + 2 × 470 nF +
100 µF electrolytic
3.3 V
400 kHz
43.2 kΩ
2.4 µH (744325240)
22 pF
2 x 47 µF + 100 µF
electrolytic + 2 x 2.2 µF
2 × 10 µF + 2 × 470 nF +
100 µF electrolytic
0.68 µH
(744373460068)
3.3 V
5 V
2200 kHz
400 kHz
43.2 kΩ
24.9 kΩ
24.9 kΩ
10 pF
22 pF
10 pF
4 x 47 µF + 100 µF
electrolytic + 2 x 2.2 µF
4 × 10 µF + 2 × 470 nF +
100 µF electrolytic
2.4 µH (744325240)
2 x 47 µF + 100 µF
electrolytic + 2 x 2.2 µF
2 × 10 µF + 2 × 470 nF +
100 µF electrolytic
0.68 µH
(744373460068)
5 V
2200 kHz
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10 Power Supply Recommendations
The characteristics of the input supply must be capable of delivering the required input current to the loaded
regulator. The average input current can be estimated with Equation 9.
VOUT ‡ IOUT
VIN ‡ ꢀ
IIN =
(9)
where
•
η is the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input
capacitors, can form an underdamped resonant circuit. This can result in overvoltage transients at the input to
the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the
output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If
the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily
shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply
to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR
of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A
value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help hold the input
voltage steady during large load transients.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this
device has a snap-back characteristic (thyristor type). It is not recommended to use a device with this type of
characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then use a Schottky diode between the input supply and the output.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly,
bad PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck
converter, the most EMI-critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground. This is shown in Figure 11-1. This loop carries large transient currents that can cause large transient
voltages when reacting with the trace inductance. Excessive transient voltages can disrupt the proper operation
of the converter. Because of this, the traces in this loop must be wide and short while keeping the loop area as
small as possible to reduce the parasitic inductance. Figure 11-2 shows a recommended layout for the critical
components of the LM6x4xx-Q1 circuit.
•
Place the input capacitor or capacitors as close as possible to the input pin pairs: VIN1 to PGND1
and VIN2 to PGND2. Place the small capacitors closest. Each pair of pins are adjacent, simplifying the input
capacitor placement. With the QFN package, there are two VIN/PGND pairs on either side of the package.
This provides a symmetrical layout and helps minimize switching noise and EMI generation. Use a wide
VIN plane on a mid-layer to connect both of the VIN pairs together to the input supply. It is best to route
symmetrically from the supply to each VIN pin to best utilize the benefits of the symmetric pinout.
Place the bypass capacitor for VCC close to the VCC pin and AGND pin: This capacitor must be routed
with short, wide traces to the VCC and AGND pins.
Place the CBOOT capacitor as close as possible to the device with short, wide traces to the CBOOT
and SW pins: It is important to route the SW connection under the device through the gap between VIN2 and
RBOOT pins, reducing exposed SW node area. If an RBOOT resistor is used, place it as close as possible
to the CBOOT and RBOOT pins. If high efficiency is desired, RBOOT and CBOOT pins can be shorted. This
short must be placed as close as possible to the RBOOT and CBOOT pins.
•
•
•
•
Place the feedback divider as close as possible to the FB pin of the device: Place RFBB, RFBT, CFF if
used, and RFF if used, physically close to the device. The connections to FB and AGND through RFBB must
be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However,
this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple
into the feedback path of the regulator.
Layer 2 of the PCB must be a ground plane: This plane acts as a noise shield and as a heat dissipation
path. Using layer 2 reduces the inclosed area in the input circulating current in the input loop, reducing
inductance.
•
•
Provide wide paths for VIN, VOUT, and GND: These paths must be as wide and direct as possible to reduce
any voltage drops on the input or output paths of the converter to maximize efficiency.
Provide enough PCB area for proper heat sinking: Enough copper area must be used to ensure a
low RθJA, considering maximum load current and ambient temperature. Make the top and bottom PCB
layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers
(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note
that the package of this device dissipates heat through all pins. Wide traces can be used for all pins except
where noise considerations dictate minimization of area.
•
Keep switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
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VIN1
VIN2
HS
FET
CIN_HF1
CIN_HF2
SW
LS
FET
PGND1
PGND2
Figure 11-1. Input Current Loop
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low-side MOSFET, and connect directly to the
grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one
side of the ground plane. The other side of the ground plane contains much less noise and must be used for
sensitive traces.
TI recommends providing adequate device heat sinking by using vias near PGND and VIN pins to connect to the
system ground plane or VIN strap, both of which dissipate heat. Use as much copper as possible for the system
ground plane on the top and bottom layers and avoid plane cuts and bottlenecks for the heat flow for the best
heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2
oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness and proper layout provides low current
conduction impedance, proper shielding, and low thermal resistance.
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11.2 Layout Example
Figure 11-2. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM61480Q3RPHRQ1
LM61480Q4RPHRQ1
LM61480Q5RPHRQ1
LM61480QRPHRQ1
LM61495Q3RPHRQ1
LM61495Q4RPHRQ1
LM61495Q5RPHRQ1
LM61495QRPHRQ1
LM62460Q3RPHRQ1
LM62460Q4RPHRQ1
LM62460Q5RPHRQ1
LM62460QRPHRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
16
16
16
16
16
16
16
16
16
16
16
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
6148Q3
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
6148Q4
6148Q5
61480Q
1495Q3
1495Q4
1495Q5
61495Q
6246Q3
6246Q4
6246Q5
62460Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM61480-Q1, LM61495-Q1, LM62460-Q1 :
Catalog : LM61480, LM61495, LM62460
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM61480Q3RPHRQ1
LM61480Q4RPHRQ1
LM61480Q5RPHRQ1
LM61480QRPHRQ1
LM61495Q3RPHRQ1
LM61495Q4RPHRQ1
LM61495Q5RPHRQ1
LM61495QRPHRQ1
LM62460Q3RPHRQ1
LM62460Q4RPHRQ1
LM62460Q5RPHRQ1
VQFN-
HR
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
16
16
16
16
16
16
16
16
16
16
16
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
1.18
1.18
1.18
1.18
1.18
1.18
1.18
1.18
1.18
1.18
1.18
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HR
LM62460QRPHRQ1
VQFN-
HR
RPH
16
3000
330.0
12.4
3.8
4.8
1.18
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM61480Q3RPHRQ1
LM61480Q4RPHRQ1
LM61480Q5RPHRQ1
LM61480QRPHRQ1
LM61495Q3RPHRQ1
LM61495Q4RPHRQ1
LM61495Q5RPHRQ1
LM61495QRPHRQ1
LM62460Q3RPHRQ1
LM62460Q4RPHRQ1
LM62460Q5RPHRQ1
LM62460QRPHRQ1
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
RPH
16
16
16
16
16
16
16
16
16
16
16
16
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RPH 16
3.5 x 4.5, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227133/A
www.ti.com
PACKAGE OUTLINE
RPH0016A
VQFN-HR - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
A
-
A
3
0
.
0
0
0
SECTION A-A
TYPICAL
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
1.0
0.8
2X
4X (0.3)
0.725
0.525
0.525
0.325
7X
(0.2) TYP
2X
(0.15) TYP
6
10
2X 2
2X 1.525
2X 1.025
2X 0.525
0.25
0.15
0.1
2X
C A B
C
0.05
A
A
0.3
9X
0.2
0.1
0.05
0.000 PKG
C A B
2.825
2.625
C
2X 0.55
4X (0.325)
0.45
2X
0.35
C A B
C
2X 1.5
0.1
0.05
2X 1.95
0.35
15
4X
1
0.25
0.1
0.05
16
PIN 1 ID
C A B
C
0.4
0.3
0.925
0.725
2X
SYMM
0.1
C A B
C
1.05
0.85
2X
0.05
4224442/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RPH0016A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
16
15
2X (0.8)
1
2X (1.1)
2X (1.9)
2X (0.75)
(2.975)
2X (1.15)
(0.963)
2X (0.55)
2X (0.4)
(R0.05) TYP
2X (1.075)
0.000 PKG
6X (0.825)
9X (0.25)
2X (0.525)
2X (1.025)
2X (1.525)
(0.35)
SEE SOLDER MASK
DETAILS
2X
(0.675)
(0.825)
(2.038)
2X (2.113)
2X (2.175)
2X (0.2)
2X (0.55)
10
6
2X (0.75)
2X (1.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224442/A 08/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RPH0016A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
16
EXPOSED METAL
2X (1.04)
15
2X (0.74)
1
EXPOSED METAL
2X (1.87)
2X (0.69)
(2.975)
2X (1.04)
2X (0.963)
2X (0.55)
2X (0.4)
(R0.05) TYP
2X (1.075)
0.000 PKG
6X (0.825)
9X (0.25)
2X (0.525)
2X (1.025)
(0.35)
2X
(0.825)
(0.675)
2X (1.525)
(2.038)
2X (0.2)
2X (0.5)
2X (2.113)
2X (2.15)
10
6
EXPOSED METAL
EXPOSED METAL
2X
(0.72)
2X (1.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
PADS 1 & 15:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 6 & 10:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224442/A 08/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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