LM73100RPWR [TI]
具有集成式理想二极管和过压保护功能的 2.7V 至 23V、28mΩ、5.5A 负载开关 | RPW | 10 | -40 to 125;
| 型号： | LM73100RPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成式理想二极管和过压保护功能的 2.7V 至 23V、28mΩ、5.5A 负载开关 | RPW | 10 | -40 to 125 开关 二极管 |
| 文件： | 总52页 (文件大小：5269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM7310
ZHCSLY9A –OCTOBER 2020 –REVISED DECEMBER 2020
LM73100 具有输入反极性保护和过压保护功能的2.7V 至23V、5.5A 集成式理想
二极管
借助集成的背对背 FET 和始终阻断从输出到输入的反
向电流等特性，该器件非常适合电源多路复用器/
ORing 应用。该器件采用基于线性 ORing 的方案，可
确保实现几乎为零的直流反向电流，并以超小的正向压
降和功率耗散来模拟理想的二极管行为。
1 特性
• 宽工作输入电压范围：2.7V 至23V
– 绝对最大值为28V
– 可耐受高达-15 V 的负电压
• 具有低导通电阻的集成式背对背FET：RON
28.4mΩ（典型值）
• 具有真反向电流阻断功能的理想二极管运行状态
• 快速过压保护
=
浪涌电流有特别要求的应用可以通过单个外部电容器设
定输出转换率。通过在输入超过可调过压阈值时切断输
出，可以保护负载免受输入过压情况的影响。该器件还
可在稳态期间对瞬态过流事件提供快速跳变响应。
– 响应时间为1.2μs（典型值）
– 可调节过压锁定(OVLO)
• 稳态期间针对瞬态过流实现快速跳变响应
– 响应时间为500ns（典型值）
– 故障后锁存
该器件可在模拟电流监测引脚上精确检测输出负载电
流。
该器件可采用 2mm x 2mm 10 引脚 HotRod QFN 封
装，旨在改善热性能并减小系统尺寸。
• 模拟负载电流监测器输出(IMON)
器件的额定工作结温范围为–40°C 至+125°C。
– 电流范围：0.5A 至5.5A
器件信息
– 精度：±15%（最大值）(IOUT ≥1A)
• 具有可调节欠压锁定阈值(UVLO) 的高电平有效使
能输入
封装(1)
封装尺寸（标称值）
器件型号
LM73100RPW
QFN (10)
2mm x 2mm
• 可调节的输出压摆率控制(dVdt)
• 过温保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 具有可调节阈值(PGTH) 的电源正常状态指示(PG)
• 小尺寸：QFN 2mm x 2mm，0.45mm 间距
VOUT
VIN = 2.7 to 23 V
IN
OUT
2 应用
PGTH
EN/UVLO
COUT
LM73100
• 电源多路复用器/ORing
• 适配器输入保护
VLOGIC
• 机顶盒/智能扬声器
• USB PD 端口保护
• PC/笔记本电脑/显示器/扩展坞
• 电动工具/充电器
OVLO
PG
dVdt
GND
IMON
RIMON
CDVDT
• POS 终端
3 说明
简化版原理图
LM73100 是一款采用小型封装的高度集成电路保护和
电源管理解决方案。该器件使用很少的外部元件即可提
供多种保护模式，能够非常有效地抵御电压浪涌、反极
性、反向电流和过多浪涌电流。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDC0
LM7310
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ZHCSLY9A –OCTOBER 2020 –REVISED DECEMBER 2020
Table of Contents
8.1 Application Information............................................. 27
8.2 Single Device, Self-Controlled.................................. 27
8.3 Active ORing.............................................................31
8.4 Priority Power MUXing..............................................33
8.5 USB PD Port Protection............................................35
8.6 Parallel Operation..................................................... 37
9 Power Supply Recommendations................................39
9.1 Transient Protection..................................................39
10 Layout...........................................................................41
10.1 Layout Guidelines................................................... 41
10.2 Layout Example...................................................... 42
11 Device and Documentation Support..........................44
11.1 Documentation Support.......................................... 44
11.2 接收文档更新通知................................................... 44
11.3 支持资源..................................................................44
11.4 商标.........................................................................44
11.5 静电放电警告...........................................................44
11.6 术语表..................................................................... 44
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................7
6.7 Switching Characteristics ...........................................8
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................26
8 Application and Implementation..................................27
Information.................................................................... 45
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2020) to Revision A (December 2020)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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5 Pin Configuration and Functions
VIN
VOUT
1
10
DNC
EN/UVLO
OVLO
9
8
2
3
IMON
5
6
PG
GND
PGTH
DVDT
4
7
图5-1. LM73100 RPW Package 10-Pin QFN Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
节7.3.2 for more details.
Analog
Input
EN/UVLO
1
A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage
Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do
not leave floating. Refer to 节7.3.3 for more details.
Analog
Input
OVLO
2
Power Good indication. This is an Open Drain signal which is asserted High when the
internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer
to 节7.3.9 for more details.
Digital
Output
PG
3
4
Analog
Input
PGTH
Power Good Threshold. Refer to 节7.3.9 for more details.
IN
5
6
Power Power Input.
Power Power Output.
OUT
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
for the fastest turn on slew rate. Refer to 节7.3.4.1 for more details.
Analog
Output
DVDT
GND
7
8
Ground This is the ground reference for all internal circuits and must be connected to system GND.
Analog load current monitor. The pin voltage can be used to monitor the output load
current. An external resistor from this pin to ground sets the current monitor gain.
Analog
Output
Recommended to connect external clamp to limit the voltage below abs max rating in case
IMON
DNC
9
of large current spikes. Connect to ground if not used. Do not leave floating. Refer to 节
7.3.5 for more details.
10
X
Internal test pin. Do not connect anything on this pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
MAX UNIT
max (–15, VOUT
-
28
28
V
V
Maximum Input Voltage Range, –40 ℃≤TJ ≤125 ℃
21)
VIN
IN
max (–15, VOUT
-
Maximum Input Voltage Range, –10 ℃≤TJ ≤125 ℃
22)
Maximum Output Voltage Range, –40 ℃≤TJ ≤125
℃
min (28, VIN + 21)
min (28, VIN + 22)
–0.3
–0.3
VOUT
OUT
OUT
Maximum Output Voltage Range, –10 ℃≤TJ ≤125
℃
VOUT,PLS
Minimum Output Voltage Pulse (< 1 µs)
–0.8
–0.3
–0.3
VEN/UVLO Maximum Enable Pin Voltage Range (2)
EN/UVLO
OVLO
dVdt
6.5
6.5
V
V
VOVLO
VdVdT
VPGTH
VPG
Maximum OVLO Pin Voltage Range (2)
Maximum dVdT Pin Voltage Range
Maximum PGTH Pin Voltage Range (2)
Maximum PG Pin Voltage Range
Maximum IMON Pin Voltage Range
Maximum Continuous Switch Current
Junction temperature
Internally Limited
–0.3
V
PGTH
PG
6.5
6.5
1.8
V
V
–0.3
VIMON
IMAX
IMON
V
IN to OUT
5.5
A
TJ
Internally Limited
°C
°C
°C
TLEAD
TSTG
Maximum Lead Temperature
300
150
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where
IN can be exposed to reverse polarity.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX UNIT
VIN
Input Voltage Range
Output Voltage Range
IN
2.7
23
V
V
VOUT
OUT
min (23, VIN + 20)
VEN/UVLO Enable Pin Voltage Range
EN/UVLO
OVLO
dVdt
5 (2)
V
VOVLO
VdVdT
VPGTH
VPG
OVLO Pin Voltage Range
dVdT Capacitor Voltage Rating
PGTH Pin Voltage Range
PG Pin Voltage Range
0.5
1.5
V
VIN + 5 V (1)
V
PGTH
PG
5 (3)
5 (3)
1.5
V
V
VIMON
IMAX
IMON Pin Voltage
IMON
V
IN to OUT
5.5
A
Continuous Switch Current, , TJ ≤125 ℃
Junction temperature
TJ
125
°C
–40
(1) In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the
highest of the 2 rails.
(2) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(3) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
6.4 Thermal Information
LM73100
THERMAL METRIC (1)
RPW (QFN)
10 PINS
41.7 (2)
74.5 (3)
1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
ΨJT
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20 (2)
ΨJB
27.6 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
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6.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open,
RIMON = 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
VUVP(R)
VUVP(F)
IN supply UVP rising threshold
IN supply UVP falling threshold
2.44
2.35
2.53
2.42
347
2.64
2.55
492
509
612
234
97.6
8.2
V
V
IN supply quiescent current, VIN = 2.7 V
µA
µA
µA
µA
µA
µA
µA
µA
IQ(ON)
IN supply quiescent current, VIN = 12 V
426
IN supply quiescent current, VIN = 23 V
459
IQ(RCB)
IQ(OFF)
ISD
IN supply quiescent current during RCB, VOUT > VIN
IN supply disabled state current (VSD(F) < VEN < VUVLO(R)
189.7
74.5
4.6
)
IN supply shutdown current (VEN < VSD(F)
)
IQ(OVLO)
IINLKG(IRPP)
IN supply OFF state current (OVLO condition), VOUT > VIN
191
-3.5
IN supply leakage current (VIN = –14 V, VOUT = 0 V)
ON RESISTANCE (IN - OUT)
VIN = 12 V, IOUT = 3 A, TJ = 25 ℃
2.7 ≤VIN ≤23 V, –40 ℃≤TJ ≤125 ℃
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
28.4
mΩ
mΩ
RON
44.85
VUVLO(R)
VUVLO(F)
VSD(F)
EN/UVLO rising threshold
1.183
1.076
0.45
1.2
1.09
0.74
1.223
1.116
V
V
EN/UVLO falling threshold
EN/UVLO falling threshold for lowest shutdown current
EN/UVLO leakage current
V
IENLKG
0.1
µA
–0.1
OVERVOLTAGE LOCKOUT (OVLO)
VOV(R)
VOV(F)
IOVLKG
OVLO rising threshold
1.183
1.076
–0.1
1.2
1.223
1.116
0.1
V
V
OVLO falling threshold
1.09
OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V
µA
µA
IOUTLKG(OVLO) OUT leakage current (OVLO condition), VOUT > VIN
317
FIXED FAST-TRIP (OUT)
IFT
OUTPUT LOAD CURRENT MONITOR (IMON)
Analog load current monitor gain (IMON : IOUT), IOUT = 0.5 A to
Fixed fast-trip current threshold
21.9
A
144
153
181
181
216
207
µA/A
µA/A
1 A
GIMON
Analog load current monitor gain (IMON : IOUT), IOUT = 1 A to
5.5 A
REVERSE CURRENT BLOCKING (IN - OUT)
VFWD
(VIN - VOUT) forward regulation voltage, IOUT = 10 mA
4.8
16.4
29.3
28.4
36.5
mV
mV
(VOUT - VIN) threshold for fast BFET turn off (enter reverse
current blocking)
VREVTH
22.7
(VIN - VOUT) threshold for fast BFET turn on (exit reverse
current blocking)
VFWDTH
85.9
105.8
125
mV
Reverse leakage current (unpowered condition), VOUT = 12
V, VIN = 0 V
IREVLKG(OFF)
IREVLKG
4.8
10.10
247.6
µA
µA
µA
Reverse leakage current, (VOUT - VIN) = 21.5 V
15.86
322
OUT leakage current during RCB state while ON, (VOUT
VIN) = 1 V
-
IOUTLKG(RCB)
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6.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open,
RIMON = 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
POWER GOOD INDICATION (PG)
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN
VSD, IPG = 26 µA
<
<
0.67
0.78
0.9
1
V
V
VPGD
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN
VSD, IPG = 242 µA
PG pin low voltage while de-asserted, VIN > VUVP(R)
PG pin leakage current while asserted
0.6
2
V
IPGLKG
0.5
µA
POWERGOOD THRESHOLD (PGTH)
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH rising threshold
PGTH falling threshold
PGTH leakage current
1.183
1.076
–1
1.2
1.223
1.116
1
V
V
1.09
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
154
10
°C
°C
Thermal shutdown rising threshold, TJ↑
Thermal shutdown hysteresis, TJ↓
TSDHYS
DVDT
IdVdt
dVdt pin charging current
1.15
2.34
3.66
µA
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
VOVLO > VOV(R) to VOUT
IOUT > IFT to IOUT
(VIN - VOUT) > VFWDTH to VOUT
MIN TYP MAX
UNIT
µs
tOVLO
tFT
Overvoltage lock-out response time
1.1
500
50
↓
Fixed fast-trip response time
ns
↓
tSWRCB
Reverse Current Blocking recovery time
µs
↑
Reverse Current Blocking fast comparator
response time
tRCB
(VOUT - VIN) > 1.3 x VREVTH to BFET OFF
1
µs
tPGA
tPGD
PG Assertion de-glitch
12
12
µs
µs
PG De-assertion de-glitch
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6.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load
capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
UNIT
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
12.14
28.1
44.78
0.09
0.1
0.87
1.09
1.25
0.6
0.5
SRON
tD,ON
tR
Output Rising slew rate
0.61
V/ms
0.71
0.97
Turn on delay
Rise time
1.32
1.99
2.51
8.1
2.35
ms
ms
ms
µs
0.11
3.69
0.17
0.35
0.40
0.27
0.45
0.50
64.44
25.32
23.02
4.33
15.37
25.89
5.31
14.4
3.11
10.08
16.41
64.44
25.32
23.02
tON
Turn on time
Turn off delay
17.72
29.57
64.44
25.32
23.02
tD,OFF
VEN/UVLO
EN/UVLO
VUVLO(R)
VUVLO(F)
0
tON
SRON
tD,OFF
90%
VIN
OUT
10%
0V
tR
tF
tD,ON
Time
图6-1. LM73100 Switching Times
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6.8 Typical Characteristics
图6-2. ON-Resistance vs Supply Voltage
图6-3. Forward Voltage Drop vs Load Current
图6-4. IN Quiescent Current vs Supply Voltage
图6-5. IN Quiescent Current vs Temperature
图6-6. IN Undervoltage Threshold vs Temperature
图6-7. EN/UVLO Threshold vs Temperature
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6.8 Typical Characteristics (continued)
图6-9. EN/UVLO Shutdown Threshold vs Supply Voltage
图6-8. EN/UVLO Shutdown Threshold vs Temperature
图6-10. OVLO Threshold vs Temperature
图6-11. PGTH Threshold vs Temperature
图6-12. Reverse Comparator Threshold vs Temperature
图6-13. Forward Regulation Voltage vs Temperature
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6.8 Typical Characteristics (continued)
图6-14. Forward Regulation Voltage vs Supply Voltage
图6-15. Forward Comparator Threshold vs Temperature
图6-16. OUT Leakage Current During ON-State Reverse Current
图6-17. Reverse Leakage Current During OFF-State
Blocking
图6-19. Analog Current Monitor gain vs Temperature
图6-18. Analog Current Monitor Gain Accuracy
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6.8 Typical Characteristics (continued)
图6-20. Analog Current Monitor Gain vs Load Current
图6-21. DVDT Charging Current vs Temperature
图6-22. Steady State Fast-Trip Comparator Threshold vs
图6-23. Steady State Fast-Trip Current Threshold vs
Temperature
Temperature
图6-24. Time to Thermal Shut-Down During Inrush State
图6-25. Time to thermal Shut-Down During Steady State
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6.8 Typical Characteristics (continued)
VEN/UVLO = 3 V, COUT = 220 μF, CdVdt = 10 nF, VIN ramped up
VIN = 12 V, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped
to 12 V
up to 3 V
图6-26. Start Up with IN Supply
图6-27. Start Up with EN
VIN = 12 V, ROUT = 20 Ω, COUT = 220 μF, CdVdt = 10 nF, VEN/
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN
UVLO stepped up to 3 V
through resistor ladder, 12 V hot-plugged to IN
图6-29. Inrush Current with RC Load
图6-28. Input Hot-Plug
COUT = 220 μF, PG pulled up to 3 V, -15 V hot-plugged to IN
图6-30. Input Reverse Polarity Protection - Fast Ramp
COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0
V to -15 V and then ramped up to 0 V
图6-31. Input Reverse Polarity Protection - Slow Ramp
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6.8 Typical Characteristics (continued)
IN= Open, COUT = 220 μF, PG pulled up to 3 V, 20 V hot-
IN= Open, COUT = 220 μF, PG pulled up to 3 V, VOUT ramped
plugged to OUT
up from 0 V to 20 V
图6-32. Reverse Current Blocking Response in OFF State
图6-33. Reverse Current Blocking Response in OFF State
VIN = 12 V, COUT = Open, OUT stepped from Open →Short-
COUT = 220 μF, ROUT = 20 Ω, OVLO threshold = 13.2 V, VIN
circuit to GND
ramped up from 12 V to 16 V
图6-35. Fast-Trip Response During Steady State
图6-34. Input Overvoltage Protection
VIN = 12 V, COUT = Open, OUT stepped from Open →Short-circuit to GND
图6-36. Fast-Trip Response During Steady State - Zoomed In
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7 Detailed Description
7.1 Overview
The LM73100 is an integrated ideal diode that is used to ensure safe power delivery in a system. The device
starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage
protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO(R)) on this pin enables
the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT. When EN/
UVLO pin is held low (< VUVLO(F)), the internal power path is turned off. In case of reverse voltages appearing at
the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the fast-trip threshold (IFT) is not exceeded and overvoltage spikes are
cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO). This helps to keep the system
safe from harmful levels of voltage and current.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is
linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off
completely to block reverse current from OUT to IN if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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7.2 Functional Block Diagram
FFT
LM73100
16.4 mV
350 mV
Temp Sense &
Overtemperature
protection
TSD
5
6
OUT
IN
INRUSH_
DONE
BFET
IRPP
HFET
7
DVDT
CP
2.8 V
2.3 ꢀA
+
UVPb
181 ꢀA/A
2.53 V9
-
GHI
2.42 V;
RCB
9
-
IMON
OVLO
2
OVLOb
1.2 V9
+
BFET Control
HFET Control
1.09 V;
+
1
EN/UVLO
UVLOb
1.2 V9
-
1.09 V;
SWEN
INRUSH_DONE
-
SD
+
0.74 V
PG_int
INRUSH_DONE
SD
UVPb
R
/Q
Q
RCB
PG_int
10
TSD
FLT
S
PG_int
8
GND
R
Q
S
/Q
GHI FFT
1.2 V9
1.09 V;
3
4
PG
PGTH
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7.3 Feature Description
The LM73100 integrated ideal diode is a compact, feature rich power management device that provides
detection, protection and indication in the event of system faults.
7.3.1 Input Reverse Polarity Protection
The LM73100 device is internally protected against transient and steady state negative voltages applied at the
input supply pin. The device blocks the negative voltage from appearing at the output, thereby protecting the
load circuits. There’s no reverse current flowing from output to the input in this condition. The maximum
negative voltage the device can handle at the input is limited to -15 V or VOUT –21 V, whichever is higher. It’s
also recommended that all signal pins (e.g. EN/UVLO, OVLO, PGTH) which are derived from input supply
should have a sufficiently large pull-up resistor to limit the current flowing out of these pins during reverse
polarity conditions. Please refer to Absolute Maximum Ratings table for more details.
7.3.2 Undervoltage Protection (UVLO & UVP)
The LM73100 implements undervoltage protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which
is fixed internally. Apart from that, the UVLO comparator on the EN/UVLO pin allows the undervoltage Protection
threshold to be externally adjusted to a user defined value. The 图 7-1 and 方程式 1 below show how a resistor
divider can be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
图7-1. Adjustable Undervoltage Protection
VUVLO x (R1 + R2)
VIN(UV)
=
R2
(1)
7.3.3 Overvoltage Lockout (OVLO)
The LM73100 allows the user to implement overvoltage lockout to protect the load from input overvoltage
conditions. The OVLO comparator on the OVLO pin allows the overvoltage protection threshold to be adjusted to
a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising threshold VOV(R), the device
turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin to fall below the
OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and falling thresholds are
slightly different to provide hysterisis. The 图 7-2 and 方程式 2 below show how a resistor divider can be used to
set the OVLO set point for a given input supply voltage.
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Power
Supply
IN
R1
OVLO
R2
GND
图7-2. Adjustable Overvoltage Protection
VOV x (R1 + R2)
R2
VIN(OV)
=
(2)
While recovering from an overvoltage event, the LM73100 starts up with inrush control (dVdt).
Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
OUT
PG
dVdt Limited Start-up
tPGA
0
VPG
0
tPGD
Time
图7-3. LM73100 Overvoltage Lockout and Recovery
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7.3.4 Inrush Current control and Fast-trip
LM73100 incorporates 2 mechanisms to handle overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Fixed threshold (IFT) for fast-trip response to transient overcurrent events during steady-state
7.3.4.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate. 方程式 3 can be used to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH (mA)
SR (V/ms) =
C
OUT (µF)
(3)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using the following
equation:
2000
CdVdt (pF) =
SR (V/ms)
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
备注
For CdVdt > 10 nF, it's recommended to add a 100-Ω resistor in series with the capacitor on the dVdt
pin.
7.3.4.2 Fast-Trip During Steady State
During certain system faults, the current through the device can increase very rapidly. In such events, the device
provides fast-trip response with a fixed threshold (IFT) during steady state. Once the current exceeds IFT, the
HFET is turned off completely within tFT. Thereafter, the device remains latched-off until it's power cycled or re-
enabled by toggling the EN/UVLO pin.
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Transient overcurrent
during steady state
Device enabled
Device re-enabled
Load step
Device latched-off
VUVLO(R)
EN/UVLO
IN
VSD(F)
0
0
tFT
IFT
Fast-trip
IOUT
IINRUSH
0
VIN
OUT
PG
0
tPGA
tPGA
tPGD
VPG
0
Time
图7-4. LM73100 Fast-Trip Response
备注
The LM73100 fast-trip response is active only during steady state and offers one level of fast
response to severe overcurrents of transient nature. However, for systems which may experience
persistent faults such as short-circuits or overloads, it's recommended to use an additional level of
overcurrent protection in series for safety.
7.3.5 Analog Load Current Monitor Output
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the IMON pin which is proportional to the current through the FET. The user can sense the voltage
(VIMON) across the RIMON to get a measure of the output load current.
VIMON (V) x 10-6
IOUT (A) =
RIMON :À; ∏ GIMON (µA/A)
(5)
The waveform below shows the IMON signal response to a dynamically varying load profile at the output.
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VIN = 12 V, COUT = 22 μF, RIMON = 1.15 kΩ, IOUT varied dynamically between 0 A and 3.5 A
图7-5. Analog Load Current Monitor Output Response
备注
1. It's recommended to choose RIMON such that VIMON ≤1.5 V at the maximum DC load current.
2. It's also recommended to add a zener diode on the IMON pin to clamp the voltage below 1.8 V
during high current transients.
3. Connect IMON pin to GND if not used. Do not leave the pin floating.
7.3.6 Reverse Current Protection
The LM73100 functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions.
The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop
between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted
as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme enables graceful
turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow.
The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast
response to transient reverse currents.Once the device enters reverse current blocking condition, it waits for the
(VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures
minimum supply droop which is helpful in applications such as power MUX/ORing.
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VFWD
IN
OUT
OUT
IN
BFET regulation mode
BFET full conduction mode
VFWTH
BFET turned OFF
VREVTH
VFWD
0 V
VIN - VOUT
图7-6. Reverse Current Blocking Response
The waveforms below illustrate the reverse current blocking performance in various scenarios.
During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism
ensures minimum jump/glitch on the input rail.
图7-7. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC
current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
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图7-8. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (capacitor bank or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
图7-9. Reverse Current Blocking Performance During Input Supply Failure
7.3.7 Overtemperature Protection (OTP)
The LM73100 monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS).
When the device detects thermal overload, it will shut down and remain latched-off until the device is power
cycled or re-enabled by toggling the EN/UVLO pin.
表7-1. Thermal Shutdown
Enter TSD
Exit TSD
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO toggled
below VSD(F)
TJ ≥TSD
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7.3.8 Fault Response
The following table summarizes the LM73100 response to various fault conditions.
表7-2. Fault Summary
Event
Protection Response
Fault Latched Internally
Overtemperature
Shutdown
Y
N
N
N
N
Y
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Overvoltage
Shutdown
Shutdown
Shutdown
Reverse Current
Reverse Current Blocking
Shutdown
Transient overcurrent during steady state
Faults which are not latched internally are automatically cleared once the trigger condition goes away and
thereafter the device recovers without any external intervention. Faults which are latched internally can be
cleared either by power cycling the part (pulling VIN to 0 V and then above VUVP(R)) or by pulling the EN/UVLO
pin voltage below VSD(F)
.
After a latched fault, pulling the EN/UVLO just below the UVLO threshold (VUVLO(F)) has no impact on the device.
7.3.9 Power Good Indication (PG)
The LM73100 provides an active high digital output (PG) which serves as a power good indication signal and is
asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an
open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on
in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault. The PG de-assertion de-glitch time is tPGD
.
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Device Enabled
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
OUT
0
VPGTH(R)
VPGTH(F)
PGTH
PG
0
VPG
tPGA
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
IINRUSH
IOUT
0
Time
图7-10. LM73100 PG Timing Diagram
表7-3. LM73100 PG Indication Summary
Event
Protection Response
Shutdown
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Overvoltage (OVLO)
L
Shutdown
Shutdown
L
L
tPGD
H (If PGTH pin voltage > VPGTH(R)
)
tPGA
tPGD
Steady State
N/A
L (If PGTH pin voltage < VPGTH(F)
)
Transient overcurrent during
steady state
H (If PGTH pin voltage > VPGTH(R)
)
tPGA
tPGD
Fast-trip
L (If PGTH pin voltage < VPGTH(F)
)
Reverse current ((VOUT - VIN) >
Reverse current blocking
Shutdown
L
L
tPGD
tPGD
VREVTH
)
Overtemperature
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When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
7.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM73100 is an integrated 5.5-A ideal diode that is typically used for power rail monitoring and protection
applications . It operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. It provides
ability to control inrush current and protection against input reverse polarity as well as reverse current conditions.
It also has integrated analog load current monitoring and digital power good indication with adjustable threshold.
It can be used in a variety of systems such as set-top boxes, smart speakers, handheld power tools/chargers,
PC/notebooks and Retail ePOS (Point-of-sale) terminals.
The design procedure explained in the subsequent sections can be used to select the supporting component
values based on the application requirement. Additionally, a spreadsheet design tool LM73100 Design Calculator
is available in the web product folder.
8.2 Single Device, Self-Controlled
VOUT
VIN = 2.7 to 23 V
IN
OUT
COUT
VLOGIC
PGTH
EN/UVLO
OVLO
LM73100
PG
dVdt
GND IMON
图8-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
IMON pin can be connected to the MCU ADC input for current monitoring purpose.
Either VIN or VOUT can be used to drive the PGTH resistor divider depending on which supply needs to be
monitored for power good indication.
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8.2.1 Typical Application
VIN = 12 V
VOUT
IN
OUT
R4
R1
COUT
470 …F
47 kO
470 kO
D2*
PGTH
EN/UVLO
3.3 V
LM73100
R2
5.6 kO
R2
11 kO
CIN
1 …F
D1*
47 kO
OVLO
PG
dVdt GND IMON
R3
47 kO
D3*
1.8 V
RIMON
549 O
CdVdt
3300 pF
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
图8-2. AC-DC Adapter Powered System - Barrel Jack Input Protection
8.2.1.1 Design Requirements
表8-1. Design Parameters
PARAMETER
VALUE
Adapter nominal output voltage (VIN)
12 V
Maximum input reverse voltage
–12 V
Undervoltage threshold (VIN(UV)
Overvoltage threshold (VIN(OV)
Output Power Good threshold (VPG
Max continuous current (IOUTmax
Analog load current monitor voltage range (VIMONmax
)
10.8 V
13.2 V
11.4 V
5 A
)
)
)
)
0.5 V
Output capacitance (COUT
Output rise time (tR)
)
470 μF
20 ms
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2 & R3 whose values can
be calculated using 方程式6 and 方程式7:
VUVLO(R) x (R1 + R2 + R3)
VIN(UV)
=
R2 + R3
(6)
(7)
VOV(R) x (R1 + R2 + R3)
R3
VIN(OV)
=
Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold . Because R1, R2 and R3
leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current
from input power supply VIN. The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 +
R2 + R3). However, leakage currents due to external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the
leakage current expected on the EN/UVLO and OVLO pins.
From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (max),
VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8 V. To solve
the equation, first choose the value of R1 = 470 kΩand use the above equations to solve for R2 = 10.7 kΩand
R3= 48 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
8.2.1.2.2 Setting Output Voltage Rise Time (tR)
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
VIN (V)
12 V
SR (V/ms) =
=
= 0.6 V/ms
tR (ms) 20 ms
(8)
(9)
The CdVdt needed to achieve this slew rate can be calculated as:
2000
2000
0.6
:
;
CdVdt pF =
=
= 3333 pF
:
SR V/ms
;
Choose the nearest standard capacitor value as 3300 pF.
For this slew rate, the inrush current can be calculated as:
:
;
:
IINRUSH mA = SR (V/ms) x COUT µF = 0.6 x 470 = 282 mA
;
(10)
(11)
The average power dissipation inside the part during inrush can be calculated as:
: ;
IINRUSH A T VIN
: ;
8
0.282 x 12
2
:
;
PDINRUSH W =
=
= 1.69 W
2
The power dissipation is below the allowed limit for a successful start-up without hitting thermal shut-down within
the target rise time as shown in the 图8-3.
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图8-3. Thermal shut-down plot during inrush
8.2.1.2.3 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R4 & R5 connected to the PGTH pin whose
values can be calculated as:
VPGTH(R) x (R4 + R5)
VPG
=
R5
(12)
Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH
leakage current expected.
From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2 V and from
design requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩand calculate R5
= 5.52 kΩ. Choose nearest 1% standard resistor value as R5 = 5.6 kΩ.
8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range
The analog current monitor voltage range can be set using the RIMON resistor whose value can be calculated as:
V
IMONmax (V) x 10-6
IOUTmax(A) x GIMON (µA/A)
0.5 x 10-6
5 x 182
RIMON :À; =
=
= 549.5 À
(13)
Choose nearest 1% standard resistor value as 549 Ω.
备注
An additional 1.8 V zener may be needed in parallel with the RIMON in applications which expect large
transient currents. Please refer to the Analog Load Current Monitor section for more details.
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8.2.1.3 Application Curves
图8-4. Power up
图8-5. Overvoltage protection
图8-6. Analog Load Current Monitor Output
8.3 Active ORing
A typical redundant power supply configuration is shown in 图 8-7 below. Schottky ORing diodes have been
popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a hold-
up storage capacitor. Similar ORing requirements can be seen in end equipements such as PC, Notebook,
Docking stations, Monitors etc.. which can take power from multiple USB ports and/or power adapter. The
disadvantage of using ORing diodes is high voltage drop and associated power loss. The LM73100 with
integrated, low-ohmic, back-to-back FETs provides a simple and efficient solution. Figure below shows the Active
ORing implementation using the devices.
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VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
OVLO
COUT
PGTH
LM73100
PG_SYS
PG
IMON
VIN1
VIN2
IN
OUT
VIN2
VLOGIC
EN/UVLO
OVLO
PGTH
LM73100
PG
IMON
图8-7. Two Devices, Active ORing Configuration
The linear ORing mechanism in LM73100 ensures that there's no reverse current flowing from one power source
to the other during fast or slow ramp of either supply.
The following waveforms illustrate the active ORing behavior.
VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to
VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to
13 V and then ramped down
13 V and then ramped down
图8-8. Active ORing Response
图8-9. Active ORing Response
When bus voltages (IN1 and IN2) are matched, device in each rail sees a forward voltage drop and is ON
delivering the load current. During this period, current is shared between the rails in the ratio of differential
voltage drop across each device.
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In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current and
transient overcurrent events during steady state.
备注
1. ORing can be done either between two similar rails (such as 12 V & 12 V; 3.3 V & 3.3 V) or
between dissimilar rails (such as 12 V & 5 V).
2. For ORing cases with skewed voltage combinations, care must be taken to design circuit
components on PGTH, EN/UVLO & OVLO pins for the lower voltage channel device such that the
absolute maximum ratings on those pins are not exceeded when higher voltage is present on the
other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2
supplies. Refer to Absolute Maximum Ratings and Recommended Operating Conditions tables for
more details.
8.4 Priority Power MUXing
Applications having two or more power sources such as POS terminals, Tablets and other portable battery
powered equipment require preference of one source to another. For example, mains power (wall-adapter) has
the priority over the internal battery back-up power. These applications demand for switchover from mains power
to backup power only when main input voltage falls below a user defined threshold. The LM73100 devices
provide a simple solution for priority power multiplexing needs.
图 8-10 below shows a typical priority power multiplexing implementation using LM73100 devices. When the
primary (priority) power source (IN1) is present and above the undervoltage (UVLO) threshold, the primary path
device path powers the OUT bus irrespective of whether auxiliary supply voltage condition. The device in
auxiliary path is held in off condition by forcing its OVLO pin to high using the EN/UVLO signal of the primary
path device.
Once the primary supply voltage falls below the user-defined undervoltage threshold (UVLO), the primary path
device is turned off. At the same the auxiliary, the auxiliary path device turns on and starts delivering power to
the load.
In this configuration, supply overvoltage protection is not available on both channels.
The PG pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and
delivering power to the load.
A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the
switchover from one supply to another. This in turn depends on multiple factors including the output load current
(ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).
While switching from one supply rail to the other, the minimum bus voltage can be calculated using 方程式 14
below. Here, the maximum switchover time (tSW) is the time taken by the device to turn on and start delivering
power to the load, which is equal to the device turn on time (tON), which in turn includes the turn on delay (tD,ON
)
and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.
t SW ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
(
)
= min VIN1,VIN2
-
)
(
)
min
(
COUT ꢀF
(
)
(14)
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VOUT
IN
OUT
VIN1
VLOGIC
IMON
EN/UVLO
PGTH
COUT
LM73100
IN1 supply active
PG
OVLO
dVdt
CdVdt
GND
IN
OUT
VIN2
VLOGIC
IMON
EN/UVLO
PGTH
LM73100
IN2 supply active
PG
dVdt
CdVdt
GND
OVLO
图8-10. Two Devices, Priority Power MUX Configuration
备注
1. Power MUXing can be done either between two similar rails (such as 12-V Primary & 12-V Aux;
3.3-V Primary & 3.3-V Aux) or between dissimilar rails (such as 12 V-Primary & 5-V Aux or vice
versa).
2. For Power MUXing cases with skewed voltage combinations, care must be taken to design circuit
components on PGTH, EN/UVLO & OVLO pins for the lower voltage channel devices such that
the absolute maximum ratings on those pins are not exceeded when higher voltage is present on
the other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of
the 2 supplies. Refer to Absolute Maximum Ratings and Recommended Operating Conditions
tables for more details.
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8.5 USB PD Port Protection
End equipments like PC, Notebooks, Docking Stations, Monitors etc. have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). LM73100 can be used independently or in
conjunction with TPS259470x to handle the power path protection requirements of USB PD ports as shown in 图
8-11 below.
LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink rail
to the port.
TPS259470x provides overcurrent & short-circuit protection in the source path, while blocking any reverse
current from the port to the internal source power rail. The fast recovery from reverse current blocking ensures
minimum supply droop during Fast Role Swap (FRS) events. The PD controller can also use the OVLO pin as
an active low enable signal to control the power path. Holding the OVLO pin high keeps the device in OFF state
in sink mode and blocks current in both directions. Once the PD controller determines the need to start sourcing
power, it can pull the OVLO pin low to trigger a fast recovery from OFF to ON state, meeting the FRS timing
requirements.
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VOUT = 5 V to 20 V
IN
OUT
OVLO
IMON
LM73100
PGTH
dVdt
RIMON
GND
EN/UVLO PG
VBUS = 5 V to 20V
CDVDT
PD Controller
VLOGIC
EN/UVLO
OVLO
FLT
IN
OUT
VIN = 5 V to 20 V
TPS259470L
AUXOFF
ILM
ITIMER dVdt
GND
RILM
CITIMER
CDVDT
图8-11. USB PD Port Protection
The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from
one power source to the other during fast or slow ramp of either supply.
The following waveforms illustrate the LM73100 reverse current blocking behavior in USB applications.
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图8-12. LM73100 Reverse Current Protection
During 20-V Hot-Plug at Output
图8-13. LM73100 Reverse Current Protection
During 20-V Voltage Ramp at Output
8.6 Parallel Operation
Applications which need higher steady state current can use multiple LM73100 devices connected in parallel as
shown in 图 8-14 below. In this configuration, the first device turns on initially to provide the inrush current
limiting. The second device is held in an OFF state by driving its EN/UVLO pin low by the PG signal of the first
device. Once the inrush sequence is complete, the first device asserts its PG pin high, allowing the second
device to turn. The second device asserts its PG signal to indicate that it has turned on fully, thereby indicating to
the system that the parallel combination is ready to deliver the full steady state current.
Once in steady state, the devices share current nearly equally. There could be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
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IN
OUT
VLOGIC
EN/UVLO
PGTH
LM73100
PG
OVLO
dVdt
GND
IMON
VIN = 2.7 to 23 V
VOUT
CdVdt
COUT
IN
OUT
VLOGIC
EN/UVLO
PGTH
LM73100
To
PG
downstream
enable
IMON
OVLO
dVdt
GND
图8-14. Two Devices Connected in Parallel for Higher Steady State Current Capability
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9 Power Supply Recommendations
The LM73100 devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. An input ceramic bypass
capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
The maximum negative voltage the device can handle at the input is limited to -15 V or VOUT – 21 V, whichever
is higher. Any low voltage signals (e.g. EN/UVLO, OVLO, PGTH) derived from the input supply must have a
sufficiently large pull-up resistor to limit the current through those pins to < 10 μA during reverse polarity
conditions. Please refer to Absolute Maximum Ratings table for more details.
9.1 Transient Protection
When the device interrupts current flow in the case of a fast-trip event or during normal switch off, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
• Connect a low ESR capacitor of value greater than 1 μF at the OUT pin very close to the device.
• Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The
capacitor voltage rating should be atleast twice the input supply voltage to be able to withstand the positive
voltage excursion during inductive ringing.
The approximate value of input capacitance can be estimated with 方程式15:
LIN
VSPIKE(Absolute) = VIN + ILOAD x
CIN
(15)
where
• VIN is the nominal supply voltage.
• ILOAD is the load current.
• LIN equals the effective inductance seen looking into the source.
• CIN is the capacitance present at the input.
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the
transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy
dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple
to the internal control circuits and cause unexpected behavior.
备注
If there's a likelihood of input reverse polarity in the system, it's recommended to use a bi-directional
TVS, or a reverse blocking diode in series with the TVS.
The circuit implementation with optional protection components is shown in 图9-1.
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VOUT
VIN = 2.7 to 23 V
IN
OUT
PGTH
EN/UVLO
D2
COUT
LM73100
VLOGIC
CIN
D1
OVLO
PG
dVdt
GND
IMON
RIMON
CDVDT
图9-1. Circuit Implementation with Optional Protection Components
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10 Layout
10.1 Layout Guidelines
• For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
• The optimal placement of the decoupling capacitor is closest to the IN pin and GND terminals of the device.
Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin and the
GND terminal of the IC.
• High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND terminal of the device must be tied to the PCB ground plane at the terminal of the IC with the
shortest possible trace. The PCB ground must be a copper plane or island on the board. It's recommended to
have a separate ground plane island for the device. This plane doesn't carry any high currents and serves as
a quiet ground reference for all the critical analog signals of the device. The device ground plane should be
connected to the system power ground plane using a star connection.
• The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
• Locate the following support components close to their connection pins:
– RIMON
– CdVdT
– Resistors for the EN/UVLO, OVLO and PGTH pins
• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the CdVdt must be as short as possible to reduce parasitic effects on the soft-start timing. These
traces must not have any coupling to switching signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended between OUT terminal and GND
terminal to address negative transients due to switching of inductive loads. It's also recommended to add a
ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be
physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky
diode/bypass-capacitor connection, the OUT pin and the GND terminal of the IC.
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10.2 Layout Example
Inner GND layer
IN
OUT
Power layer
Top layer
图10-1. Layout Example - Single LM73100 with PGTH Referred to OUT
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Inner GND layer
OUT
IN1
Power layer
Top layer
IN2
图10-2. Layout Example - 2 x LM73100 in ORing Configuration
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• LM73100EVM Ideal Diode Evaluation Board
• Application note - eFuses for USB Type-C protection
• LM73100 Design Calculator
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM73100RPWR
ACTIVE
VQFN-HR
RPW
10
3000 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2AEH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM73100RPWR
VQFN-
HR
RPW
10
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RPW 10
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
LM73100RPWR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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