LM7481-Q1 [TI]
支持驱动背对背 NFET、具有高栅极驱动能力的 3V 至 65V、汽车理想二极管控制器;
| 型号： | LM7481-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持驱动背对背 NFET、具有高栅极驱动能力的 3V 至 65V、汽车理想二极管控制器 栅极驱动 控制器 二极管 |
| 文件： | 总37页 (文件大小：6786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM7481-Q1
ZHCSLA3A – MAY 2020 – REVISED DECEMBER 2020
具有有源整流和负载突降保护功能的 LM7481-Q1 理想二极管控制器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准
LM74810-Q1 理想二极管控制器可驱动和控制外部背
对背 N 沟道 MOSFET，从而模拟具有电源路径开/关控
制和过压保护的理想二极管整流器。3V 至 65V 的宽输
入电源电压可保护和控制 12V 和 24V 汽车类电池供电
的 ECU。该器件可以承受并保护负载免受低至 –65V
的 负 电 源 电 压 的 影 响 。 集 成 的 理 想 二 极 管 控 制 器
(DGATE) 可驱动第一个 MOSFET 来代替肖特基二极
管，以实现反向输入保护和输出电压保持。具有 60mA
峰值栅极拉电流驱动器级以及短导通和关断延迟时间的
3.8mA 强电荷泵可确保快速的瞬态响应，从而确保在
汽车测试（如 ISO16750 或 LV124）期间实现稳健、
高效的 MOSFET 开关性能，在汽车测试中 ECU 会收
到输入短时中断以及频率高达 200KHz 的交流叠加输
入信号。在电源路径中使用了第二个 MOSFET 的情况
下，该器件允许负载断开（开/关控制）并使用 HGATE
控制提供过压保护。该器件具有可调节过压切断保护功
能，以提供负载突降保护。
– 器件温度等级 1：
–40°C 至 +125°C 环境工作温度范围
– 器件 HBM ESD 分类等级 2
– 器件 CDM ESD 分类等级 C4B
• 3V 至 65V 输入范围
•
•
反向输入保护低至 –65V
驱动外部背对背 N 沟道 MOSFET
• 9.1mV 阳极至阴极正向压降调节下，理想二极管正
常运行
•
•
低反向检测阈值 (–4mV)，能够快速响应 (0.5µs)
高达 200KHz 的有源整流
• 60mA 峰值栅极 (DGATE) 导通电流
• 2.6A 峰值 DGATE 关断电流
•
•
集成 3.8mA 电荷泵
可调节过压保护
器件信息 (1)
• 2.87µA 低关断电流（EN/UVLO = 低电平）
• 2.6A 峰值 DGATE 关断电流
封装尺寸（标称值）
器件型号
封装
WSON (12)
LM74810-Q1
3.0mm x 3.0mm
•
采用合适的 TVS 二极管，符合汽车 ISO7637 瞬态
要求
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
采用节省空间的 12 引脚 WSON 封装
2 应用
•
汽车电池保护
– ADAS 域控制器
– 音响主机
– 高端音响
•
用于冗余电源的有源 ORing
VOUT2
(Always ON)
Q1
Q2
VBATT
12 V
VOUT1
(VBATT Switched)
DGATE CAP VS
C
D1
SMBJ36CA
HGATE
A
OUT
VSNS
SW
R1
BATT_MON
LM74810-Q1
GND
R2
EN/UVLO
ON OFF
OV
R3
具有开关输出的理想二极管
ISO16750、LV124 交流叠加性能
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD98
LM7481-Q1
ZHCSLA3A – MAY 2020 – REVISED DECEMBER 2020
www.ti.com.cn
Table of Contents
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical 12-V Reverse Battery Protection
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
6.7 Typical Characteristics................................................8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................16
8.5 Application Examples................................................17
Application...................................................................18
9.3 Do's and Don'ts.........................................................26
10 Power Supply Recommendations..............................27
10.1 Transient Protection................................................27
10.2 TVS Selection for 12-V Battery Systems................ 28
10.3 TVS Selection for 24-V Battery Systems................ 28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Receiving Notification of Documentation Updates..30
12.2 Support Resources................................................. 30
12.3 Trademarks.............................................................30
12.4 Electrostatic Discharge Caution..............................30
12.5 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2020) to Revision A (December 2020)
Page
更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
•
•
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5 Pin Configuration and Functions
12
11
10
1
2
3
4
DGATE
A
C
CAP
VSNS
VS
RTN
9
8
7
OUT
SW
OV
Exposed
Thermal
Pad
HGATE
GND
5
6
EN/UVLO
图 5-1. 12-Pin WSON Top View
表 5-1. Pin Functions
PIN
LM74810-Q1
WSON
TYPE
DESCRIPTION
NAME
Diode Controller Gate Drive Output. Connect to the GATE of the external
MOSFET. Anode of the ideal diode.
DGATE
1
O
A
2
3
I
I
Anode of the ideal diode. Connect to the source of the external MOSFET
Voltage sensing input.
VSNS
Voltage sensing disconnect switch terminal. VSNS and SW are internally
connected through a switch. Use SW as the top connection of the battery
sensing or OV resistor ladder network. When EN/UVLO is pulled low, the switch
is OFF disconnecting the resistor ladder from the battery line thereby cutting off
the leakage current. If the internal disconnect switch between VSNS and SW is
not used then short them together and connect to VS pin.
SW
4
I
Adjustable over voltage threshold input. Connect a resistor ladder across SW to
OV terminal. When the voltage at OVP exceeds the over voltage cut-off
threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns
ON when the sense voltage goes below the OVP falling threshold.
OV
5
6
I
I
EN/UVLO Input. Connect to VS pin for always ON operation. Can be driven
externally from a mirco controller I/O. Pulling it low below V(ENF) makes the
device enter into low Iq shutdown mode. For UVLO, connect an external resistor
ladder to EN/UVLO to GND.
EN/UVLO
GND
7
8
9
G
O
I
Connect to the system ground plane.
HGATE
OUT
GATE driver output for the HSFET. Connect to the GATE of the external FET
Connect to the output rail (external MOSFET source).
Input power supply to the IC. Connect VS to middle point of the common drain
back to back MOSFET configuration. Connect a 100nF capacitor across VS and
GND pins.
VS
10
I
CAP
C
11
12
O
I
Charge pump output. Connect a 100-nF capacitor across CAP and VS pins.
Cathode of the ideal diode. Connect to the drain of the external MOSFET
Leave exposed pad floating. Do not connect to GND plane.
RTN
Thermal Pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
MAX
70
UNIT
A to GND
VS to GND
70
–1
VSNS, SW, EN/UVLO, C, OV, OUT to GND, V(A) > 0 V
70
V
–0.3
V(A)
(70 + V(A)
)
VSNS, SW, EN/UVLO, C, OV, OUT to GND, V(A) ≤ 0 V
Input Pins
RTN to GND
0.3
10
–65
IVSNS, ISW
mA
mA
–1
IEN/UVLO, IOV, V(A) > 0 V
–1
Internally limited
–65
IEN/UVLO, IOV,
OUT to VS
CAP to VS
CAP to A
V(A) ≤ 0 V
Output Pins
16.5
15
V
V
–0.3
–0.3
–0.3
–0.3
–5
85
Output Pins
DGATE to A
15
HGATE to OUT
15
Output to Input Pins
C to A
85
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
150
150
–40
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
±750
±500
V(ESD) Electrostatic discharge
Corner pins (DGATE, OV, and C)
Other pins
V
Charged device model (CDM), per
AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–60
0
NOM
MAX
65
UNIT
A to GND
V
V
V
Input Pins
External
VS to GND
65
EN/UVLO to GND
0
65
Capacitanc CAP to A, VS to GND, A to GND
e
0.1
15
µF
V
External
MOSFET
DGATE to A and HGATE to OUT
max VGS
rating
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
Tj
Operating Junction temperature(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM74810-Q1
THERMAL METRIC(1)
DRR (WSON)
UNIT
12 PINS
60.9
48
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
31.5
1.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
31.4
7.1
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = V(VSNS) = 12 V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,
V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(VS)
Operating input voltage
VS POR threshold, rising
VS POR threshold, falling
SHDN current, I(GND)
3
2.4
1.9
65
2.85
2.3
5
V
V
V(VS_PORR)
V(VS_PORF)
I(SHDN)
2.6
2.1
V
V(EN/UVLO) = 0 V
2.87
396
408
µA
µA
µA
V(EN/UVLO) = 2 V
I(Q)
Total System Quiescent current, I(GND)
V(A) = V(VS) = 24 V, V(EN/UVLO) = 2 V
480
112
I(A) leakage current during Reverse
Polarity,
19
µA
µA
I(REV)
0 V ≤ V(A) ≤ – 65 V
I(OUT) leakage current during Reverse
Polarity
1
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(UVLOR)
V(UVLOF)
EN/UVLO threshold voltage, rising
EN/UVLO threshold voltage, falling
1.195
1.091
1.231
1.132
1.267
1.159
V
V
Enable threshold voltage for low Iq
shutdown, falling
V(ENF)
0.3
37
0.67
0.93
V
V(EN_Hys)
I(EN/UVLO)
Enable Hysteresis
72
52
95
mV
nA
200
0 V ≤ V(EN/UVLO) ≤ 65 V
OVER VOLTAGE PROTECTION AND BATTERY SENSING (VSNS, SW, OV) INPUT
Battery sensing disconnect switch
resistance
R(SW)
10
19.5
46
3 V ≤ V(SNS) ≤ 65 V
Ω
V(OVR)
V(OVF)
Overvoltage threshold input, rising
Overvoltage threshold input, falling
1.195
1.091
1.231
1.13
1.267
1.159
V
V
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = V(VSNS) = 12 V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,
V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I(OV)
OV Input leakage current
53
200
nA
0 V ≤ V(OV) ≤ 65 V
CHARGE PUMP (CAP)
Charge Pump source current (Charge
pump on)
V
V
(CAP) – V(A) = 7 V, 6 V ≤ V(S) ≤ 65
I(CAP)
2.5
3.8
mA
Charge Pump Turn ON voltage
Charge Pump Turnoff voltage
11
12.2
13.2
13.2
14.1
V
V
VCAP – VS
11.9
Charge Pump UVLO voltage
threshold, rising
5.4
4.4
6.6
5.5
7.9
6.6
V
V
V(CAP UVLO)
Charge Pump UVLO voltage
threshold, falling
IDEAL DIODE (A, C, DGATE)
V(A_PORR) V(A) POR threshold, rising
V(A_PORF)
2.2
2
2.35
2.2
2.6
2.4
V
V
V(A) POR threshold, falling
Regulated Forward V(A)–V(C)
Threshold
V(AC_REG)
V(AC_REV)
V(AC_FWD)
5.8
–6.4
150
9.1
–4
177
12.4
–1.3
200
mV
mV
mV
V
(A)–V(C) Threshold for Fast Reverse
Current Blocking
V
(A)–V(C) Threshold for Reverse to
Forward transition
3 V < V(S) < 5 V
5 V < V(S) < 65 V
7
V
V
Gate Drive Voltage
V
(DGATE) – V(A)
10
11.5
60
13
V(A) – V(C) = 100 mV, V(DGATE) – V(A)
Peak Gate Source current
Peak Gate Sink current
mA
mA
= 1 V
V
(A) – V(C) = –12 mV, V(DGATE) –
I(DGATE)
2670
V(A) = 11 V
V
V
(A) – V(C) = 0 V, V(DGATE) – V(A) = 11
Regulation sink current
Cathode leakage Current
8.4
4
14.9
9
µA
µA
I(C)
32
V(A) = –14 V, V(C) = 12 V
HIGH SIDE CONTROLLER (HGATE, OUT, SNS, SW, OV)
3 V < V(S) < 5 V
5 V < V(S) < 65 V
7
10
V
V
Gate Drive Voltage
(HGATE) – V(OUT)
V
11.1
55
14.5
75
Source Current
Sink Current
39
µA
mA
I(HGATE)
V(OV) > V(OVR)
168
260
6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(C) = V(OUT) = V(VS) = 12V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,
V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V
(A) – V(C) = +30 mV to –100 mV
DGATE Turnoff Delay during reverse
voltage detection
tDGATE_OFF(dly)
0.5
0.875
µs
to V(DGATE–A) < 1 V, C(DGATE–A) = 10
nF
V
(A) – V(C) = –20 mV to +700
DGATE Turnon Delay during forward
voltage detection
tDGATE_ON(dly)
0.85
175
1.6
µs
µs
mV to V(DGATE-A) > 5 V, C(DGATE-A) = 10
nF
DGATE Turnon Delay during EN/
UVLO
EN/UVLO ↑ to V(DGATE-A) > 5V,
C(DGATE-A) = 10 nF
tEN(dly)_DGATE
98
270
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6.6 Switching Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(C) = V(OUT) = V(VS) = 12V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,
V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DGATE Turnoff Deglitch during EN/
UVLO
tEN_OFF(deg)_DGATE
8.1
µs
EN/UVLO ↓ to DGATE ↓
HGATE Turnoff Deglitch during EN/
UVLO
tEN_OFF(deg)_HGATE
3
4.6
6
µs
EN/UVLO ↓ to HGATE ↓
tOVP_OFF(deg)_HGAT
HGATE Turnoff Deglitch during OV
3.98
2.95
5.4
µs
µs
OV ↑ to HGATE ↓
OV ↓ to HGATE ↑
E
tOVP_ON(deg)_HGATE HGATE Turnon Deglitch during OV
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6.7 Typical Characteristics
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
500
450
400
350
300
-40èC
25èC
85èC
125èC
150èC
-40èC
25èC
85èC
125èC
150èC
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
LM74
IQ_1
图 6-1. Operating Quiescent Current vs Supply Voltage
图 6-2. Operating Quiescent Current vs Supply Voltage (> 10 V)
28
26
24
22
20
18
16
14
12
10
5.5
5
4.5
4
3.5
3
2.5
2
-40èC
-40èC
25èC
8
6
4
2
0
25èC
1.5
85èC
85èC
125èC
125èC
150èC
1
150èC
0.5
3
4
5
6
7
8
9
10
11
12
0
5
10 15 20 25 30 35 40 45 50 55 60 65
V(S) (V)
VS (V)
ICP
ISHU
图 6-4. Charge Pump Current vs Supply Voltage at CAP = 6 V
图 6-3. Shutdown Supply Current vs Supply Voltage
12.25
12
8
-40èC
11.75
11.5
11.25
11
7
25èC
85èC
6
125èC
150èC
10.75
10.5
10.25
10
5
4
3
2
1
-40èC
25èC
85èC
125èC
150èC
9.75
9.5
9.25
9
8.75
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
0
2
4
6
8
10
12
D024
VCAP - VS (V)
ICPV
图 6-6. DGATE Drive Voltage vs Supply Voltage
图 6-5. Charge Pump V-I Characteristics at VS > = 12 V
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6.7 Typical Characteristics (continued)
12
11.75
11.5
11.25
11
-9
-12
-15
-18
-21
-24
-27
-30
-33
-36
-39
-42
-45
-48
-51
-54
10.75
10.5
10.25
10
9.75
9.5
-40èC
25èC
-40èC
25èC
85èC
125èC
150èC
85èC
9.25
9
125èC
150èC
8.75
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
-65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
VA (V)
0
D024
D024
图 6-7. HGATE Drive Voltage vs Supply Voltage
图 6-8. ANODE Leakage Current vs Reverse ANODE Voltage
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D024
D024
图 6-9. UVLO Thresholds vs Temperature
图 6-10. OVP Thresholds vs Temperature
7.5
6
3
2.4
1.8
1.2
0.6
0
4.5
3
1.5
(VCAP-VS) UVLOR
(VCAP-VS) UVLOF
VA PORR
VA PORF
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D024
D024
图 6-11. Charge Pump UVLO Threshold vs Temperature
图 6-12. VA POR Threshold vs Temperature
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6.7 Typical Characteristics (continued)
3
3
2.8
2.6
2.4
2.2
2
2.5
2
1.5
1
0.5
VS PORR
VS PORF
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D024
HGAT
图 6-13. VS POR Threshold vs Temperature
图 6-14. HGATE Turn OFF Delay during OV
57.2
57
56.8
56.6
56.4
56.2
56
55.8
55.6
55.4
55.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
D024
图 6-15. HGATE Current (IHGATE) vs Supply Voltage
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7 Parameter Measurement Information
30 mV
VA > VC
0 mV
VC > VA
-100 mV
VDGATE
1V
0 V
ttDGATE_OFF(DLY)
t
700 mV
VA > VC
0 mV
VC > VA
-20 mV
VDGATE
5V
0 V
ttDGATE_ON(DLY)
t
VOVR + 0.1V
0V
VHGATE
0 V
ttOVP_OFF(deg)HGATE
t
图 7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74810-Q1 ideal diode controller drives and controls external back to back N-Channel MOSFETs to
emulate an ideal diode rectifier with power path ON/OFF control, inrush current limiting and over voltage
protection. The wide input supply of 3 V to 65 V allows protection and control of 12-V and 24-V automotive
battery powered ECUs. The device can withstand and protect the loads from negative supply voltages down to
–65 V. An integrated ideal diode controller (DGATE) drives the first MOSFET to replace a Schottky diode for
reverse input protection and output voltage holdup. A strong charge pump with 60-mA peak GATE source
current driver stage and short turn ON and turn OFF delay times ensures fast transient response ensuring robust
performance during automotive testing such as ISO16750 or LV124 where an ECU is subjected to AC
superimpose input signals upto 200-KHz frequency. With a second MOSFET in the power path the device allows
load disconnect (ON/OFF control) and over voltage protection using HGATE control. The device features an
adjustable over voltage cut-off protection feature using a programming resistor across SW and OVP terminal.
The LM74810-Q1 controls the DGATE of the MOSFET to regulate the forward voltage drop at 9.1 mV. The linear
regulation scheme in these devices enables graceful control of the GATE voltage and turns off of the MOSFET
during a reverse current event and ensures zero DC reverse current flow.
The device features enable control. With the enable pin low during the standby mode, both the external
MOSFETs and controller is off and draws a very low 2.87 μA of current. The high voltage rating of LM74810-Q1
helps to simplify the system designs for automotive ISO7637 protection. The LM74810-Q1 are also suitable for
ORing applications
8.2 Functional Block Diagram
Q1
Q2
VBATT
VOUT
OUT
HGATE
C
VS
CAP
OUT+12V
55µA
A
DGATE
CP
VSNS
SW
EN
3.8mA
Reverse Current
Protection controller and
Gate Driver
Gate
Driver
R1
BATT_MON
A+12V
VCAP
R2
R3
OV
VCAP
+
OV
EN
Charge
Pump
Enable
Logic
1.23 V
1.13
œ
EN
VS
+
EN/UVLO
1 V
A+12V
VCAP
œ
0.3 V
Bias Rail
Generation
VA
VOUT
OUT+12V
+
Internal Rails
UVLO
1.23 V
1.13
œ
A
Reverse
Protection Logic
VS
GND
LM74810-Q1
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8.3 Feature Description
8.3.1 Charge Pump
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between CAP and VS pins to provide energy to turn on the external MOSFET. In order
for the charge pump to supply current to the external capacitor the EN/UVLO pin voltage must be above the
specified input high threshold, V(ENR). When enabled, the charge pump sources a charging current of 3.8-mA
typical. If EN/UVLO pin is pulled low, then the charge pump remains disabled. To ensure that the external
MOSFET can be driven above its specified threshold voltage, the CAP to VS voltage must be above the
undervoltage lockout threshold, typically 6.6 V, before the internal gate driver is enabled. Use 方程式 1 to
calculate the initial gate driver enable delay.
V
(CAP _UVLOR)
T DRV _EN = 175ms + C(CAP)
x
(
)
3.8mA
(1)
where
• C(CAP) is the charge pump capacitance connected across VS and CAP pins
• V(CAP_UVLOR) = 6.6 V (typical)
To remove any chatter on the gate drive approximately 1 V of hysteresis is added to the VCAP undervoltage
lockout. The charge pump remains enabled until the CAP to VS voltage reaches 13.2 V, typically, at which point
the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until
the CAP to VS voltage is below to 12.2 V typically at which point the charge pump is enabled. The voltage
between CAP and VS continue to charge and discharge between 12.2 V and 13.2 V as shown in 图 8-1. By
enabling and disabling the charge pump, the operating quiescent current of the LM74810-Q1 is reduced. When
the charge pump is disabled it sinks 15 µA.
TON
TDRV_EN
TOFF
VIN
VA=Vs
0V
VEN/UVLO
13.2 V
12.2 V
VCAP-VS
6.6 V
V(VCAP UVLOR)
GATE DRIVER
ENABLE
图 8-1. Charge Pump Operation
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8.3.2 Dual Gate Control (DGATE, HGATE)
The LM74810-Q1 features two separate gate control and driver outputs to drive back to back N-channel
MOSFETs.
8.3.2.1 Reverse Battery Protection (A, C, DGATE)
A, C, DGATE comprises of Ideal Diode stage. Connect the Source of the external MOSFET to A, Drain to C and
Gate to DGATE. The LM74810-Q1 has integrated reverse input protection down to –65 V.
Before the DGATE driver is enabled, following conditions must be achieved:
• The EN/UVLO pin voltage must be greater than the specified input high voltage.
• The CAP to VS voltage must be greater than the undervoltage lockout voltage.
• Voltage at A pin must be greater than VA POR Rising threshold.
• Voltage at Vs pin must be greater than Vs POR Rising thershold.
If the above conditions are not achieved, then the DGATE pin is internally connected to the A pin, assuring that
the external MOSFET is disabled.
In LM74810-Q1 the voltage drop across the MOSFET is continuously monitored between the A and C pins, and
the DGATE to A voltage is adjusted as needed to regulate the forward voltage drop at 9.1 mV (typ). This closed
loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures
zero DC reverse current flow. This scheme ensures robust performance during slow input voltage ramp down
tests. Along with the linear regulation amplifier scheme, the LM74810-Q1 also integrates a fast reverse voltage
comparator. When the voltage drop across A and C reaches V(AC_REV) threshold then the DGATE goes low
within 0.5-µs (typ). This fast reverse voltage comparator scheme ensures robust performance during fast input
voltage ramp down tests such as input micro-shorts. The external MOSFET is turned ON back when the voltage
across A and C hits V(AC_FWD) threshold within 0.85 µs (typ).
For Ideal Diode only designs, connect LM74810-Q1 as shown in 图 8-2.
Q1
VBATT
12 V
VOUT
DGATE CAP VS C
D1
SMBJ36CA
HGATE
OUT
A
VSNS
SW
R1
BATT_MON
R2
LM74810-Q1
GND
EN/UVLO
ON OFF
OV
图 8-2. Configuring LM74810-Q1 for Ideal Diode Only
8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
HGATE and OUT comprises of Load disconnect switch control stage. Connect the Source of the external
MOSFET to OUT and Gate to HGATE.
Before the HGATE driver is enabled, following conditions must be achieved:
• The EN/UVLO pin voltage must be greater than the specified input high voltage.
• The CAP to VS voltage must be greater than the undervoltage lockout voltage.
• Voltage at Vs pin must be greater than Vs POR Rising thershold.
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If the above conditions are not achieved, then the HGATE pin is internally connected to the OUT pin, assuring
that the external MOSFET is disabled.
For Inrush Current limiting, connect CdVdT capacitor and R1 as shown in 图 8-3.
Q1
R1
CdVdT
HGATE OUT
LM74810-Q1
图 8-3. Inrush Current Limiting
The CdVdT capacitor is required for slowing down the HGATE voltage ramp during power up for inrush current
limiting. Use 方程式 2 to calculate CdVdT capacitance value .
IHGATE _ DRV
CdVdT
=
xCOUT
IINRUSH
(2)
where IHATE_DRV is 55 μA (typ), IINRUSH is the inrush current and COUT is the output load capacitance. An extra
resistor, R1, in series with the CdVdT capacitor improves the turn off time.
For Load disconnect switch only designs, configure the LM74810-Q1 as shown in 图 8-4
Q1
VOUT
VIN
CAP
DGATE C
A
VS
HGATE OUT
VSNS
SW
R1
R2
R3
LM74810-Q1
EN/UVLO
OV
GND
图 8-4. Configuring LM74810-Q1 for Load Disconnect Switch Only
8.3.3 Over Voltage Protection and Battery Voltage sensing (VSNS, SW, OV)
Connect a resistor ladder as shown in 图 8-5 for Over Voltage threshold programming.
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VBATT
A
SNS
SW
EN
R1
R2
R3
BATT_MON
LM74810-Q1
OV
+
HGATE_OFF
1.23 V
œ
1.123 V
图 8-5. Programming Over Voltage Threshold and Battery Sensing
A disconnect switch is integrated between VSNS and SW pins. This switch is turned OFF when EN/UVLO pin is
pulled low. This helps to reduce the leakage current through the resistor divider network during system shutdown
state (IGN_OFF state).
8.3.4 Low Iq Shutdown and Under Voltage Lockout (EN/UVLO)
The enable pin allows for the gate driver to be either enabled or disabled by an external signal. If the EN/UVLO
pin voltage is greater than the rising threshold, the gate driver and charge pump operates as described in
Charge Pump section. If EN/UVLO pin voltage is less than the input low threshold, V(ENF), the charge pump and
both the gate drivers (DGATE and HGATE) are disabled placing the LM74810-Q1 in shutdown mode.
If V(ENF) < V(EN/UVLO) < V(UVLOF) then only HGATE is disabled disconnecting the load from the supply, DGATE
remains ON.
The EN/UVLO pin can withstand a maximum voltage of 65 V. For always ON operation connect EN/UVLO pin to
VS.
8.4 Device Functional Modes
The LM74810-Q1 enters shutdown mode when the EN/UVLO pin voltage is below the specified input low
threshold V(ENF). Both the gate drivers and the charge pump are disabled in shutdown mode. During shutdown
mode the LM74810-Q1 enters low IQ operation with a total input quiescent consumption of 2.87 μA (typ). When
the LM74810-Q1 is in shutdown mode, forward current flow to always ON loads connected to the common drain
point of the back to back MOSFETs is not interrupted but is conducted through the MOSFET's body diode.
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8.5 Application Examples
8.5.1 Redundant Supply OR-ing with Inrush Current Limiting, Over Voltage Protection and ON/OFF
Control
Q1
VIN1
D1
SMBJ36CA
CATHODE
GATE
ANODE
VCAP
LM74700-Q1
GND
EN
Q1
ON OFF
VOUT2
Q2
VIN2
VOUT1
VS
DGATE CAP VS C
D2
SMBJ36CA
HGATE
A
OUT
VSNS
SW
VS
R1
LM74810-Q1
BATT_MON
R2
EN/UVLO
ON OFF
GND
OV
R3
图 8-6. Redundant Supply OR-ing with Over Voltage Protection and ON/OFF Control
图 8-6 shows the implementation of Dual OR-ing with Inrush Current Limiting, Over Voltage Protection and
power path ON/OFF control. The input side SMBJ36CA TVS across the ideal diodes is required for ISO7637
Pulse 1 transient suppression to limit the input voltage within the device max voltage rating of –65 V.
R1 and R2 are the programming resistors for over voltage protection (OVP) threshold. When the voltage at OVP
pin exceeds OVP cut-off reference threshold then the HGATE driver turns OFF the FET Q3, disconnecting the
power path and protecting the downstream load. HGATE goes high once the OVP pin voltage goes below the
OVP falling hysteresis threshold. Use 0.1-μF to 1-μF capacitor across VS to CAP pins of the LM74810-Q1.
This is the charge pump capacitor and acts as the supply for both the DGATE and HGATE driver stages. The
DGATE driver of the LM74810-Q1 is equipped with 60-mA peak source current and 1.5-A peak sink current
capability resulting in fast and efficient transient responses during the ISO16750 or LV124 short interruptions as
well as AC superimpose testing.
Pull EN low during the sleep/standby mode. With EN low, both the DGATE and HGATE drivers are pulled low
turning OFF both the power FETs. VOUT1 gets disconnected from the VBATT rail reducing the system IQ.
VOUT2 is gets power through the body diode of the MOSFET Q2 and this supply can be utilized for always ON
loads. The LM74810-Q1 draws a 2.87-μA current during this mode.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
LM74810-Q1 controls two N-channel power MOSFETs with DGATE used to control diode MOSFET to emulate
an ideal diode and HGATE controlling second MOSFET for power path cut-off when disabled or during an over
voltage protection. HGATE controlled MOSFET can be used to clamp the output during over voltage or load
dump conditions. LM74810-Q1 can be placed into low quiescent current mode using EN/UVLO, where both
DGATE and HGATE are turned OFF.
9.2 Typical 12-V Reverse Battery Protection Application
A typical application circuit of LM74810-Q1 configured to provide reverse battery protection with over voltage
protection is shown in 图 9-1.
图 9-1. Typical Application Circuit - 12-V Reverse Battery Protection and Over Voltage Protection
9.2.1 Design Requirements for 12-V Battery Protection
The system design requirements are listed in 表 9-1.
表 9-1. Design Parameters - 12-V Reverse Battery Protection and Over Voltage Protection
DESIGN PARAMETER
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V Cold Crank and 35-V Load
Dump
Operating Input Voltage Range
Output Power
Output Current Range
Input Capacitance
200 W
12-A Nominal, 18-A maximum
0.1-µF minimum
0.1-µF minimum, (optional 470bµF for E-10 functional class A
performance)
Output Capacitance
Over Voltage Cut-off
AC Super Imposed Test
37.0 V, output cut-off >37.0 V
2-V Peak-Peak to 6-V Peak-Peak, 20 Hz to 30 KHz extendable to
200 KHz
Automotive Transient Immunity Compliance
Battery Monitor Ratio
ISO 7637-2, ISO 16750-2 and LV124
8:1
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9.2.2 Automotive Reverse Battery Protection
The LM74810-Q1 feature two separate gate control and driver outputs i.e DGATE and HGATE to drive back to
back N-channel MOSFETs. This enables LM74810-Q1 to provide comprehensive immunity with robust system
protection during various automotive transient tests as per ISO 7637-2 and ISO 16750-2 standard as well as
other automotive OEM standards. For more information, see the Automotive EMC-compliant reverse-battery
protection with ideal-diode controllers article.
LM74810-Q1 gate drive output DGATE controls MOSFET Q1 to provide reverse battery protection and true
reverse current blocking functionality. HGATE controls MOSFET Q2 to turn off the power path during input over
voltage condition. Resistor network R1, R2 and R3 connected to OV and SW can be configured for over voltage
protection and also for battery monitoring under normal operating conditions as well as reverse battery
conditions. TVS D1 and D2 clamps the automotive transient input voltages on the 12-V battery, both positive and
negative transients, to voltage levels safe for MOSFET Q1 and LM74810-Q1.
Fast reverse current blocking response and quick reverse recovery enables LM74810-Q1 to turn ON/OFF
MOSFET Q1 during AC super imposed input specified by ISO 16750-2 and LV124 E-06 and provide active
rectification of the AC input superimposed on DC battery voltage. Fast reverse current blocking response of
LM74810-Q1 helps to turn off MOSFET Q1 during negative transients inputs such as –150-V 2-ms Pulse 1
specified in ISO 7637-2 and input micro short conditions such as LV124 E-10 test.
9.2.3 Input Transient Protection: ISO 7637-2 Pulse 1
ISO 7637-2 Pulse 1 specifies negative transient immunity of electronic modules connected in parallel with an
inductive load when the battery is disconnected. A typical pulse 1 specified in ISO 7637-2 starts with battery
disconnection where supply voltage collapses to 0 V followed by –150 V 2 ms applied with a source impedance
of 10 Ω at a slew rate of 1 µs on the supply input. LM74810-Q1 blocks reverse current and prevents the output
voltage from swinging negative, protecting the rest of the electronic circuits from damage due to negative
transient voltage. MOSFET Q1 is quickly turned off within 0.5 µs by fast reverse comparator of LM74810-Q1.
A single bi-directional TVS or two uni-directional TVS are required at the input to clamp the negative transient
pulse within the operating maximum voltage across cathode to anode of 85 V and does not violate the MOSFET
Q1 drain-source breakdown voltage rating. ISO 7637-2 Pulse 1 performance of LM74810-Q1 is shown in 图 9-2.
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图 9-2. ISO 7637-2 Pulse 1
9.2.4 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
Alternators are used to power the automotive electrical system and charge the battery during normal runtime of
the vehicle. Rectified alternator output contains residual AC ripple voltage superimposed on the DC battery
voltage due to various reasons which includes engine speed variation, regulator duty cycle with field switching
ON/OFF and electrical load variations. On a 12-V battery supply, alternator output voltage is regulated by a
voltage regulator between 14.5 V to 12.5 V by controlling the field current of alternator's rotor. All electronic
modules are tested for proper operation with superimposed AC ripple on the DC battery voltage. AC super
imposed test specified in ISO 16750-2 and LV124 E-06 requires AC ripple of 2-V Peak-Peak on a 13.5-V DC
battery voltage, swept from 15 Hz to 30 KHz and extended to 200 KHz in case of LV148 E48-05. LM74810-Q1
rectifies the AC superimposed voltage by turning the MOSFET Q1 OFF quickly to cut-off reverse current and
turning the MOSFET Q1 ON quickly during forward conduction.
Active rectification of 2-V peak-peak 200 KHz AC input by LM74810-Q1 is shown in 图 9-3. Fast turn off and
quick turn ON of the MOSFET reduces power dissipation in the MOSFET Q1 and active rectification reduces
power dissipation in the output hold-up capacitor's ESR by half. Active rectification of 2-V peak-peak 5-KHz AC
input is shown in 图 9-4.
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图 9-3. AC Super Imposed Test on 15 nC QGS- 2-V
图 9-4. AC Super Imposed Test - 2-V Peak-Peak 5
Peak-Peak 200 KHz
KHz
9.2.5 Input Micro-Short Protection: LV124 E-10
E-10 test specified in LV124 standard checks for immunity of electronic modules to short interruptions in power
supply input due to contact issues or relay bounce. During this test (case 2), micro-short is applied on the input
for a duration as low as 10 µs to several ms. For a functional pass status A, electronic modules are required to
run uninterrupted during the E-10 test (case 2) with 100-µs duration. Dual-Gate drive architecture of LM74810-
Q1 - DGATE and HGATE - enables to achieve a functional pass status A with optimum hold up capacitance on
the output when compared to a single gate drive controller. When input micro-short is applied for 100 µs,
LM74810-Q1 quickly turns off MOSFET Q1 by shorting DGATE to ANODE (source of MOSFET) within 0.5 µs to
prevent the output from discharging and the HGATE remains ON keeping MOSFET Q2 ON, enabling fast
recovery after the input short is removed.
Performance of LM74810-Q1 during E10 input power supply interruption test case 2 is shown in 图 9-5. After the
input short is removed, input voltage recovers and MOSFET Q1 is turned back ON within 130 µs. Note that dual-
gate drive topology allows MOSFET Q2 to remain ON during the test and helps in restoring the input power
faster. Output voltage remains unperturbed during the entire duration, achieving functional status A.
图 9-5. Input Micro-Short - LV124 E10 TC 2 100 µs
图 9-6. Input Micro-Short - LV124 E10 TC 2 100 µs
with HGATE
9.2.6 Detailed Design Procedure
9.2.6.1 Design Considerations
表 9-1 summarizes the design parameters that must be known for designing an automotive reverse battery
protection circuit with over voltage cut-off. During power up, inrush current through MOSFET Q2 needs to be
limited so that the MOSFET operates well within its SOA. Maximum load current, maximum ambient temperature
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and thermal properties of the PCB determine the RDSON of the MOSFET Q2 and maximum operating voltage
determines the voltage rating of the MOSFET Q2. Selection of MOSFET Q2 is determined mainly by the
maximum operating load current, maximum ambient temperature, maximum frequency of AC super imposed
voltage ripple and ISO 7637-2 pulse 1 requirements. Over voltage threshold is decided based on the rating of
downstream DC/DC converter or other components after the reverse battery protection circuit. A single bi-
directional TVS or two back-back uni-directional TVS are required to clamp input transients to a safe operating
level for the MOSFETs Q1, Q2 and LM74810-Q1.
9.2.6.2 Charge Pump Capacitance VCAP
Minimum required capacitance for charge pump VCAP is based on input capacitance of the MOSFET Q1,
CISS(MOSFET_Q1)and input capactiance of Q2 CISS(MOSFET)
.
Charge Pump VCAP: Minimum 0.1 µF is required; recommended value of VCAP (µF) ≥ 10 x ( CISS(MOSFET_Q1)
+ CISS(MOSFET_Q2) ) (µF).
9.2.6.3 Input and Output Capacitance
A minimum input capacitance CIN of 0.1 µF and output capacitance COUT of 0.1 µF is recommended.
9.2.6.4 Hold-up Capacitance
Usually bulk capacitors are placed on the output due to various reasons such as uninterrupted operation during
power interruption or micro-short at the input, hold-up requirements for doing a memory dump before turning of
the module and filtering requirements as well. This design considers minimum bulk capacitors requirements for
meeting functional status "A" during LV124 E10 test case 2 100-µs input interruption. To achieve functional pass
status A, acceptable voltage droop in the output of LM74810-Q1 is based on the UVLO settings of downstream
DC-DC converters. For this design, 4.0-V drop in output voltage for 100 µs is considered and the minimum hold-
up capacitance required is calculated by
(3)
Minimum hold-up capacitance required to hold output with 4.0-V drop at 18-A current for 100 µs is 450 µF. A
470-uF electrolytic capacitor is a closest standard value that can be placed at the output. Note that the typical
application circuit shows the hold-up capacitor as optional because not all designs require hold-up capacitance.
9.2.6.5 Over Voltage Protection and Battery Monitor
Resistors R1, R2 and R3 connected in series are used to program the over voltage threshold and battery monitor
ratio. The resistor values required for setting the over voltage threshold VOV to 37.0 V and battery monitor ratio
VBATT_MON : VBATT to 1:8 are calculated by solving 方程式 4 and 方程式 5.
(4)
(5)
For minimizing the input current drawn from the battery through resistors R1, R2 and R3, it recommended to use
higher value of resistance. Using high value resistors will add error in the calculations because the current
through the resistors at higher value will become comparable to the leakage current into the OV pin. Maximum
leakage current into the OV pin is 1 µA and choosing (R1 + R2 + R3) < 120 kΩ ensures current through resistors
is 100 times greater than leakage through OV pin.
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Based on the device electrical characteristics, VOVR is 1.23 V and battery monitor ratio (VBATT_MON / VBATT) is
designed for a ratio of 1/8. To limit (R1 + R2 + R3) < 120 kΩ, select (R1 + R2) = 100 kΩ. Solving 方程式 4 gives
R3 = 3.45 kΩ. Solving 方程式 5 for R2 using (R1 + R2) = 100 kΩ and R3 = 3.45 kΩ, gives R2 = 9.48 kΩ and R1
= 90.52 kΩ.
Standard 1% resistor values closest to the calculated resistor values are R1 = 90.9 kΩ, R2 = 9.09 kΩ and R3 =
3.48 kΩ.
9.2.7 MOSFET Selection: Blocking MOSFET Q1
For selecting the blocking MOSFET Q1, important electrical parameters are the maximum continuous drain
current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), the
maximum source current through body diode and the drain-to-source ON resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This would include all the automotive transient events and any anticipated fault
conditions. It is recommended to use MOSFETs with VDS voltage rating of 60 V along with a single bidirectional
TVS or a VDS rating 40-V maximum rating along with two unidirectional TVS connected back-back at the input.
The maximum VGS LM74810-Q1 can drive is 14 V, so a MOSFET with 15-V minimum VGS rating should be
selected. If a MOSFET with < 15-V VGS rating is selected, a zener diode can be used to clamp VGS to safe level,
but this would result in increased IQ current.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred, but selecting a MOSFET based
on low RDS(ON) may not be beneficial always. Higher RDS(ON) will provide increased voltage information to
LM74810-Q1's reverse comparator at a lower reverse current. Reverse current detection is better with increased
RDS(ON). Choosing a MOSFET with < 50-mV forward voltage drop at maximum current is a good starting point.
For active rectification of AC super imposed ripple on the battery supply voltage, gate-source charge QGS of Q1
must be selected to meet the required AC ripple frequency. Maximum gate-source charge QGS (at 4.5-V VGS) for
active rectification every cycle is
2.5mA
QGS_MAX
=
FAC_RIPPLE
(6)
where 2.5 mA is minimum charge pump current at 7-V VDGATE - VA, FAC_RIPPLE is frequency of the AC ripple
superimposed on the battery and QGS_MAX is the QGS value specified in manufacturer datasheet at 6-V VGS. For
active rectification at FAC_RIPPLE = 30 KHz, QGS_MAX = 83 nC. Further for active rectification at FAC_RIPPLE = 200
KHz, QGS_MAX = 12.5 nC.
Based on the design requirements, BUK9J0R9-40H MOSFET is selected and its ratings are:
• 40-V VDS(MAX) and 16-V VGS(MAX)
• RDS(ON) 0.97-mΩ typical at 4.5-V VGS and 0.82 mΩ rated at 10-V VGS
• MOSFET QGS_MAX 30.2 nC
Thermal resistance of the MOSFET should be considered against the expected maximum power dissipation in
the MOSFET to ensure that the junction temperature (TJ) is well controlled.
9.2.8 MOSFET Selection: Hot-Swap MOSFET Q2
The VDS rating of the MOSFET Q2 should be sufficient to handle the maximum system voltage along with the
input transient voltage. For this 12-V design, transient over voltage events are during suppressed load dump 35
V 400 ms and ISO 7637-2 pulse 2 A 50 V for 50 µs. Further, ISO 7637-2 Pulse 3B is a very fast repetitive pulse
of 100 V 100 ns that is usually absorbed by the input and output ceramic capacitors and the maximum voltage
on the 12-V battery can be limited to < 40 V the minimum recommended input capacitance of 0.1 µF. The 50-V
SO 7637-2 Pulse 2 A can also be absorbed by input and output capacitors and its amplitude could be reduced to
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40-V peak by placing sufficient amount of capacitance at input and output. For this 12-V design, a 40-V VDS
rated MOSFET is selected.
The VGS rating of the MOSFET Q2 should be higher than that maximum HGATE-OUT voltage 15 V.
Inrush current through the MOSFET during input hot-plug into the 12-V battery is determined by output
capacitance. External capacitor on HGATE, CDVDT is used to limit the inrush current during input hot-plug or
startup. The value of inrush current determined by 方程式 2 need to be selected to ensure that the MOSFET Q2
is operating well within its safe operating area (SOA). Considering COUT = 470 µF and inrush current of 2.5 A,
the calculated value of CDVDT is 9.96 nF. Closest standard value of 10.0 nF is chosen for this design.
Duration of inrush current is calculated by
(7)
Calculated inrush current duration is 2.36 ms with 2.5-A inrush current.
MOSFET BUK9J0R9-40H having 40-V VDS and 16 V VGS rating is selected for Q2. Power dissipation during
inrush is well within the MOSFET's safe operating area (SOA).
9.2.9 TVS selection
For 40-V rated MOSFET, two bi-directional 600-W SMBJ TVS, SMBJ33A and SMBJ16A are recommended for
input transient clamping and protection. For detailed explanation on TVS selection for 12-V battery systems,
refer to TVS Selection for 12-V Battery Systems and refer to TVS Selection for 24-V Battery Systems for 24-V
battery systems.
9.2.10 Application Curves
图 9-7. Startup 12 V with EN pulled to VIN
图 9-8. Startup 12 V showing Charge Pump VCAP
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图 9-10. Reverse Input Voltage -12 V for 60s
图 9-9. Reverse Input Voltage -12 V
图 9-11. Over Voltage Cut-off
图 9-12. Over Voltage Recovery
图 9-13. Turn ON with ENABLE Control
图 9-14. Turn OFF with ENABLE Control
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图 9-15. Disable Delay DGATE
图 9-16. Disable Delay HGATE
图 9-17. Enable Delay HGATE
图 9-18. Load Transient Response DGATE
9.3 Do's and Don'ts
Leave exposed pad (RTN) of the IC floating. Do not connect it to the GND plane. Connecting RTN to GND
disables the Reverse Polarity protection feature.
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10 Power Supply Recommendations
10.1 Transient Protection
When the external MOSFETs turn OFF during the conditions such as over voltage cut-off, reverse current
blocking, EN/UVLO causing an interruption of the current flow, the input line inductance generates a positive
voltage spike on the input and output inductance generates a negative voltage spike on the output. The peak
amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the
device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to
address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Use of a Schottky diode across the output and GND to absorb negative spikes
• A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with 方程式 8.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(8)
where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during EMC testing such as
automotive ISO7637 pulses.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in 图 10-1
Q1
Q2
VOUT
VIN
CVS
CVCAP
*
*
COUT
CIN
D2
D1
C
HGATE OUT
DGATE
A
VS CAP
VSNS
SW
R1
BATT_MON
R2
LM74810-Q1
GND
EN/UVLO
ON OFF
OV
R3
* Optional components needed for suppression of transients
图 10-1. Circuit Implementation with Optional Protection Components for LM74810-Q1
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10.2 TVS Selection for 12-V Battery Systems
In selecting the TVS, important specifications are breakdown voltage and clamping voltage. The breakdown
voltage of the TVS+ should be higher than 24-V jump start voltage and 35-V suppressed load dump voltage and
less than the maximum ratings of LM74810-Q1 (65 V). The breakdown voltage of TVS- should be beyond than
maximum reverse battery voltage –16 V, so that the TVS- is not damaged due to long time exposure to reverse
connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V
with a generator impedance of 10 Ω. This translates to 15 A flowing through the TVS - and the voltage across
the TVS would be close to its clamping voltage.
The next criterion is that the absolute maximum rating of cathode to anode voltage of the LM74810-Q1 (85 V)
and the maximum VDS rating MOSFET are not exceeded. In the design example, 40-V rated MOSFET is chosen
and maximum limit on the cathode to anode voltage is 40 V.
During ISO 7637-2 pulse 1, the anode of LM74810-Q1 is pulled down by the ISO pulse, clamped by TVS- and
the MOSFET Q1 is turned off quickly to prevent reverse current from discharging the bulk output capacitors.
When the MOSFET turns off, the cathode to anode voltage seen is equal to (TVS Clamping voltage + Output
capacitor voltage). If the maximum voltage on output capacitor is 16 V (maximum battery voltage), then the
clamping voltage of the TVS- should not exceed, (40 V – 16) V = –24 V.
On the positive side, the SMBJ33A TVS diode can be used for 12-V battery protection application. The
breakdown voltage of 36.7 V meets the jump start, load dump requirements on the positive side. On the negative
side, TVS has to withstand 16-V reverse battery connection and clamping voltage has to be –(40 V - 16 V) = –
24 V. SMBJ16A can be used.
However if 60-V rated MOSFET is selected, a single bi-directional TVS SMBJ33CA is recommended. SMBJ
series of TVS' are rated up to 600-W peak pulse power levels and are sufficient for ISO 7637-2 pulses.
10.3 TVS Selection for 24-V Battery Systems
For 24-V battery protection application, the TVS and MOSFET Q1 and Q2 needs to be changed to suit 24-V
battery requirements.
The breakdown voltage of the TVS+ should be higher than 48-V jump start voltage, less than the absolute
maximum ratings of anode and enable pin of LM74810-Q1 (70 V) and should withstand 65-V suppressed load
dump. The breakdown voltage of TVS- should be lower than maximum reverse battery voltage –32 V, so that
the TVS- is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. This
translates to 12-A flowing through the TVS-. The clamping voltage of the TVS- cannot be same as that of 12-V
battery protection circuit because during the ISO 7637-2 pulse, the Anode to Cathode voltage seen is equal to (-
TVS Clamping voltage + Output capacitor voltage). For 24-V battery application, the maximum battery voltage is
32 V, then the clamping voltage of the TVS- should not exceed, 85 V – 32 V = 53 V.
Single bi-directional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥
65V, maximum clamping voltage is ≤ 53 V and the clamping voltage cannot be less than the breakdown
voltage. Two un-directional TVS connected back-back needs to be used at the input. For positive side TVS+,
SMBJ58A with the breakdown voltage of 64.4 V (minimum), 67.8 (typical) is recommended. For the negative
side TVS-, SMBJ28A with breakdown voltage close to 32 V (to withstand maximum reverse battery voltage –32
V) and maximum clamping voltage of 42.1 V is recommended.
For 24-V battery protection, a 75-V rated MOSFET is recommended to be used along with SMBJ28A and
SMBJ58A connected back-back at the input.
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11 Layout
11.1 Layout Guidelines
• For the ideal diode stage, connect A, DGATE and C pins of LM74810-Q1 close to the MOSFET's SOURCE,
GATE and DRAIN pins.
• For the load disconnect stage, connect HGATE and OUT pins of LM74810-Q1 close to the MOSFET's GATE
and SOURCE pins.
• The high current path of for this solution is through the MOSFET, therefore it is important to use thick and
short traces for source and drain of the MOSFET to minimize resistive losses.
• The DGATE pin of the LM74810-Q1 must be connected to the MOSFET GATE with short trace.
• Place transient suppression components close to LM74810-Q1.
• Place the decopuling capacitor, CVS close to VS pin and chip GND.
• The charge pump capacitor across CAP and VS pins must be kept away from the MOSFET to lower the
thermal effects on the capacitance value.
• Obtaining acceptable performance with alternate layout schemes is possible, however the layout shown in
the Layout Example is intended as a guideline and to produce good results.
11.2 Layout Example
S
D
D
D
D
S
Q1
Q2
S
G
VIN PLANE
DGTE
C
CAP
VS
A
CCAP
VOUT PLANE
VSNS
OUT
HGATE
GND
SW
OV
CVS
D1
COUT
EN/
UVLO
GND PLANE
图 11-1. PCB Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74810QDRRRQ1
ACTIVE
WSON
DRR
12
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
L74810
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM7481-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2023
Catalog : LM7481
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
WSON - 0.8 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
DRR0012E
3.1
2.9
A
B
3.1
2.9
PIN 1 INDEX AREA
0.100 MIN
(0.130)
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
1.4
1.2
SYMM
(0.2) TYP
(0.43) TYP
6
10X 0.5
7
A
A
SYMM
2X
2.6
2.4
2.5
13
1
12
0.3
0.2
12X
PIN 1 ID
(OPTIONAL)
0.52
0.32
12X
0.1
C A B
C
0.05
4224874/B 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max height
DRR0012E
PLASTIC QUAD FLAT PACK- NO LEAD
2X (2.78)
(1.3)
12X (0.62)
12X (0.25)
1
12
10X (0.5)
SYMM
(2.5)
13
2X
(2.5)
2X
(1)
(R0.05)
TYP
7
6
SYMM
(Ø0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
0.07 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224874/B 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max height
DRR0012E
PLASTIC QUAD FLAT PACK- NO LEAD
2X (2.78)
12X (0.62)
12X (0.25)
2X (1.21)
13
1
12
2X
(1.1)
10X (0.5)
SYMM
2X
(2.5)
(R0.05)
TYP
2X
(0.65)
7
6
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED COVERAGE BY AREA
SCALE: 20X
4224874/B 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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