LM78S40CN/NOPB [TI]
1.5A 可调节升压、降压或反向稳压器 | NFG | 16 | 0 to 70;
| 型号： | LM78S40CN/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5A 可调节升压、降压或反向稳压器 | NFG | 16 | 0 to 70 开关 光电二极管 稳压器 |
| 文件： | 总14页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM78S40
LM78S40 Universal Switching Regulator Subsystem
Literature Number: SNVS021
April 1998
LM78S40
Universal Switching Regulator Subsystem
General Description
Features
n Step-up, step-down or inverting switching regulators
n Output adjustable from 1.25V to 40V
n Peak currents to 1.5A without external transistors
n Operation from 2.5V to 40V input
The LM78S40 is a monolithic regulator subsystem consisting
of all the active building blocks necessary for switching regu-
lator systems. The device consists of a temperature com-
pensated voltage reference, a duty-cycle controllable oscilla-
tor with an active current limit circuit, an error amplifier, high
current, high voltage output switch, a power diode and an
uncommitted operational amplifier. The device can drive ex-
ternal NPN or PNP transistors when currents in excess of
1.5A or voltages in excess of 40V are required. The device
can be used for step-down, step-up or inverting switching
regulators as well as for series pass regulators. It features
wide supply voltage range, low standby power dissipation,
high efficiency and low drift. It is useful for any stand-alone,
low part count switching system and works extremely well in
battery operated systems.
n Low standby current drain
n 80 dB line and load regulation
n High gain, high current, independent op amp
n Pulse width modulation with no double pulsing
Block and Connection Diagrams
DS010057-2
16-Lead DIP
DS010057-1
Top View
© 1998 National Semiconductor Corporation
DS010057
www.national.com
Ordering Information
Part Number
LM78S40J/883
LM78S40N
NS Package
Temperature Range
−55˚C to +125˚C
−40˚C to +125˚C
0˚C to +70˚C
J16A Ceramic DIP
N16E Molded DIP
N16E Molded DIP
LM78S40CN
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
to GND
40V
Common Mode Input Range
(Comparator and Op Amp)
Differential Input Voltage
(Note 4)
−0.3 to V+
±
30V
Storage Temperature Range
Output Short Circuit
Duration (Op Amp)
Ceramic DIP
−65˚C to +175˚C
−65˚C to +150˚C
Continuous
10 mA
Molded DIP
Current from VREF
Operating Temperature Range
Extended (LM78S40J)
Industrial (LM78S40N)
Commercial (LM78S40CN)
Lead Temperature
Voltage from Switch
Collectors to GND
−55˚C to +125˚C
−40˚C to +125˚C
0˚C to +70˚C
40V
40V
Voltage from Switch
Emitters to GND
Voltage from Switch
Collectors to Emitter
Voltage from Power Diode to GND
Reverse Power Diode Voltage
Current through Power Switch
Current through Power Diode
ESD Susceptibility
Ceramic DIP (Soldering, 60 sec.)
Molded DIP (Soldering, 10 sec.)
300˚C
265˚C
40V
40V
Internal Power Dissipation (Note 2) (Note 3)
16L-Ceramic DIP
40V
1.5A
1.50W
1.04W
40V
16L-Molded DIP
1.5A
Input Voltage from VIN to GND
Input Voltage from V+ (Op Amp)
(to be determined)
LM78S40
Electrical Characteristics (Note 5)
+
=
=
=
TA Operating temperature range, VIN 5.0V, V (Op Amp) 5.0V, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
GENERAL CHARACTERISTICS
=
ICC
Supply Current
VIN 5.0V
1.8
2.3
3.5
5.0
4.0
5.5
mA
mA
mA
mA
=
VIN 40V
(Op Amp Disconnected)
Supply Current
=
VIN 5.0V
ICC
=
(Op Amp Connected)
VIN 40V
REFERENCE SECTION
=
<
<
VREF
Reference Voltage
IREF 1.0 mA Extend −55˚C TA
+125˚C,
<
<
Comm 0 TA +70˚C,
1.180
1.245
0.04
0.2
1.310
0.2
V
<
<
Indus −40˚C TA +85˚C
=
=
VR LINE
Reference Voltage
Line Regulation
VIN 3.0V to VIN 40V,
mV/V
mV/mA
=
=
IREF 1.0 mA, TA 25˚C
=
=
VR LOAD Reference Voltage
Load Regulation
IREF 1.0 mA to IREF 10 mA,
0.5
=
TA 25˚C
OSCILLATOR SECTION
=
=
ICHG
Charging Current
Charging Current
Discharge Current
Discharge Current
Oscillator Voltage Swing
Ratio of Charge/
VIN 5.0V, TA 25˚C
20
20
50
70
µA
µA
= =
VIN 40V, TA 25˚C
ICHG
=
=
IDISCHG
IDISCHG
VOSC
VIN 5.0V, TA 25˚C
150
150
250
350
µA
=
=
VIN 40V, TA 25˚C
µA
=
=
VIN 5.0V, TA 25˚C
0.5
6.0
V
t
on/toff
µs/µs
Discharge Time
CURRENT LIMIT SECTION
=
VCLS
Current Limit Sense
Voltage
TA 25˚C
250
350
mV
OUTPUT SWITCH SECTION
VSAT 1 Output Saturation Voltage 1 ISW 1.0A (Figure 1)
VSAT 2
=
1.1
1.3
0.7
V
V
=
Output Saturation Voltage 2 ISW 1.0A (Figure 2)
0.45
3
www.national.com
LM78S40
Electrical Characteristics (Note 5) (Continued)
+
=
=
=
TA Operating temperature range, VIN 5.0V, V (Op Amp) 5.0V, unless otherwise specified.
Symbol
OUTPUT SWITCH SECTION
hFE Output Transistor Current
Parameter
Conditions
Min
Typ
Max
Units
=
=
=
IC 1.0A, VCE 5.0V, TA 25˚C
70
10
Gain
=
=
IL
Output Leakage Current
VO 40V, TA 25˚C
nA
POWER DIODE
=
VFD
IDR
Forward Voltage Drop
Diode Leakage Current
ID 1.0A
1.25
10
1.5
V
=
=
VD 40V, TA 25˚C
nA
COMPARATOR
=
VIO
IIB
Input Offset Voltage
VCM VREF
1.5
35
15
200
75
mV
nA
nA
V
=
VCM VREF
Input Bias Current
Input Offset Current
=
IIO
VCM VREF
5.0
=
VCM
Common Mode Voltage
Range
TA 25˚C
0
VIN–2
=
=
PSRR
Power Supply Rejection
Ratio
VIN 3.0V to 40V, TA 25˚C
70
96
dB
OPERATIONAL AMPLIFIER
=
VIO
IIB
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain+
VCM 2.5V
4.0
30
15
200
75
mV
nA
=
VCM 2.5V
=
IIO
VCM 2.5V
5.0
250
nA
+
−
=
AVS
RL 2.0 kΩ to GND;
25
25
0
V/mV
=
=
VO 1.0V to 2.5V, TA 25˚C
+
Voltage Gain−
RL 2.0 kΩ to V (Op Amp)
250
V/mV
V
=
AVS
=
=
VO 1.0V to 2.5V, TA 25˚C
=
VCM
Common Mode Voltage
Range
TA 25˚C
VCC − 2
=
=
CMR
Common Mode Rejection
VCM 0V to 3.0V, TA 25˚C
V+ (Op Amp) 3.0V to 40V, TA 25˚C
= =
76
76
100
100
dB
dB
PSRR
Power Supply Rejection
Ratio
+
=
IO
Output Source Current
Output Sink Current
Slew Rate
TA 25˚C
75
10
150
35
mA
mA
V/µs
V
−
=
TA 25˚C
IO
=
SR
TA 25˚C
0.6
=
=
VOL
VOH
Output Voltage LOW
Output Voltage High
IL −5.0 mA, TA 25˚C
1.0
=
=
IL 50 mA, TA 25˚C
V + (Op
V
Amp) −
3V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when ordering the device
beyond its rated operating conditions.
=
150˚C for the Molded DIP, and 175˚C for the Ceramic DIP.
Note 2:
T
J
Max
Note 3: Ratings apply to ambient temperature at 25˚C. Above this temperature, derate the 16L-Ceramic DIP at 10 mW/˚C, and the 16L-Molded DIP at 8.3 mW/˚C.
Note 4: For supply voltages less than 30V, the absolute maximum voltage is equal to the supply voltage.
Note 5: A military RETS specification is available on request. At the time of printing, the LM78S40 RETS specification complied with the Min and Max limits in this
table. The LM78S40J may also be procured as a Standard Military Drawing.
www.national.com
4
Typical Performance Characteristics
CT vs OFF Time
Reference Voltage vs
Junction Temperature
DS010057-6
DS010057-7
Discharge Current vs
Input Voltage
Current Limit Sense
Voltage vs Input Voltage
DS010057-8
DS010057-9
Design Formulas
Characteristic
Step-Down
Step-Up
Inverting
Units
(ton + toff) Max
µs
µF
A
CT
Ipk
4 x 10−5 ton
2 IO Max
4 x 10−5 ton
4 x 10−5 ton
LMin
µH
RSC
CO
0.33/Ipk
0.33/Ipk
0.33/Ipk
Ω
µF
=
Note 6:
V
Saturation voltage of the switching element.
SAT
=
V
Forward voltage of the flyback diode.
D
5
www.national.com
Functional Description
Typical Applications
SWITCHING FREQUENCY CONTROL
The LM78S40 is a variable frequency, variable duty cycle
device. The initial switching frequency is set by the timing
capacitor. (Oscillator frequency is set by a single external
capacitor and may be varied over a range of 100 Hz to
100 kHz). The initial duty cycle is 6:1. This switching fre-
quency and duty cycle can be modified by two
mechanisms — the current limit circuitry (Ipk sense) and the
comparator.
The comparator modifies the OFF time. When the output
voltage is correct, the comparator output is in the HIGH
state and has no effect on the circuit operation. If the out-
put voltage is too high then the comparator output goes
LOW. In the LOW state the comparator inhibits the turn-on
of the output stage switching transistors. As long as the
comparator is LOW the system is in OFF time. As the out-
put current rises the OFF time decreases. As the output
current nears its maximum the OFF time approaches its
minimum value. The comparator can inhibit several ON
cycles, one ON cycle or any portion of an ON cycle. Once
the ON cycle has begun the comparator cannot inhibit un-
til the beginning of the next ON cycle.
The current limit modifies the ON time. The current limit is
activated when a 300 mV potential appears between lead
13 (VCC) and lead 14 (Ipk). This potential is intended to re-
sult when designed for peak current flows through RSC
.
When the peak current is reached the current limit is
turned on. The current limit circuitry provides for a quick
end to ON time and the immediate start of OFF time.
Generally the oscillator is free running but the current limit
action tends to reset the timing cycle.
Increasing load results in more current limited ON time
and less OFF time. The switching frequency increases
with load current.
DS010057-3
FIGURE 1. Typical Step-Down Regulator and
=
Operational Performance (TA 25˚C)
USING THE INTERNAL REFERENCE, DIODE, AND
SWITCH
Characteristic Condition
Typical
Value
10V
The internal 1.245V reference (pin 8) must be bypassed,
with 0.1 µF directly to the ground pin (pin 11) of the
LM78S40, to assure its stability.
=
Output Voltage
Line Regulation
Load Regulation
IO 200 mA
20V ≤ VI ≤ 30V
5.0 mA ≤ IO
1.5 mV
3.0 mV
VFD is the forward voltage drop across the internal power
diode. It is listed on the data sheet as 1.25V typical, 1.5V
maximum. If an external diode is used, then its own for-
IO ≤ 300 mA
=
Max Output Current
Output Ripple
Efficiency
VO 9.5V
500 mA
50 mV
74%
ward voltage drop must be used for VFD
.
=
VSAT is the voltage across the switch element (output tran-
sistors Q1 and Q2) when the switch is closed or ON. This
is listed on the data sheet as Output Saturation Voltage.
IO 200 mA
=
IO 200 mA
=
Standby Current
IO 200 mA
2.8 mA
“Output saturation voltage 1” is defined as the switching
element voltage for Q2 and Q1 in the Darlington configu-
ration with collectors tied together. This applies to Figure
1, the step down mode.
Note 7: For
I
O
≥ 200 mA use external diode to limit on-chip power
dissipation.
“Output saturation voltage 2” is the switching element volt-
age for Q1 only when used as a transistor switch. This ap-
plies to Figure 2, the step up mode.
For the inverting mode, Figure 3, the saturation voltage of
the external transistor should be used for VSAT
.
www.national.com
6
Typical Applications (Continued)
DS010057-4
DS010057-5
FIGURE 2. Typical Step-Up Regulator and
FIGURE 3. Typical Inverting Regulator and
=
Operational Performance (TA 25˚C)
=
Operational Performance (TA 25˚C)
Characteristic Condition
Typical
Value
25V
Characteristic Condition
Typical
Value
=
Output Voltage
Line Regulation
Load Regulation
IO 50 mA
=
Output Voltage
Line Regulation
Load Regulation
IO 100 mA
8.0V ≤ VI ≤ 18V
5.0 mA ≤ IO
−15V
5.0V ≤ VI ≤ 15V
5.0 mA ≤ IO
IO ≤ 100 mA
4.0 mV
2.0 mV
5.0 mV
3.0 mV
IO ≤ 150 mA
=
Max Output Current
Output Ripple
Efficiency
VO 23.75V
160 mA
30 mV
79%
=
Max Output Current
Output Ripple
Efficiency
VO 14.25V
160 mA
20 mV
70%
=
IO 50 mA
=
IO 100 mA
=
IO 50 mA
=
IO 100 mA
=
Standby Current
IO 50 mA
2.6 mA
=
Standby Current
IO 100 mA
2.3 mA
7
www.national.com
Typical Applications (Continued)
DS010057-10
=
FIGURE 4. Pulse Width Modulated Step-Down Regulator (fOSC 20 kHz)
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8
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM78S40CN/NOPB
ACTIVE
PDIP
NFG
16
25
RoHS &
Non-Green
SN
Level-1-NA-UNLIM
0 to 70
LM78S40CN
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
NFG PDIP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM78S40CN/NOPB
16
25
502
14
11938
4.32
Pack Materials-Page 1
MECHANICAL DATA
NFG0016E
N16E (Rev G)
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