LM8262MM/NOPB [TI]
Dual, 22-V, 21-MHz operational amplifier | DGK | 8 | -40 to 85;
| 型号： | LM8262MM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual, 22-V, 21-MHz operational amplifier | DGK | 8 | -40 to 85 放大器 光电二极管 |
| 文件： | 总18页 (文件大小：1011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM8262
SNOS975G –MAY 2001–REVISED AUGUST 2015
LM8262 Dual RRIO, High Output Current and Unlimited Cap Load Op Amp in VSSOP
1 Features
3 Description
The LM8262 is a Rail-to-Rail input and output Op
Amp which can operate with a wide supply voltage
range. This device has high output current drive,
greater than Rail-to-Rail input common mode voltage
range, unlimited capacitive load drive capability, and
provides tested and ensured high speed and slew
rate. It is specifically designed to handle the
requirements of flat panel TFT panel VCOM driver
applications as well as being suitable for other low
power and medium speed applications which require
ease of use and enhanced performance over existing
devices.
1
(VS = 5V, TA = 25°C, Typical Values Unless
Specified).
•
•
•
•
•
•
•
GBWP 21MHz
Wide Supply Voltage Range 2.5 V to 22 V
Slew Rate 12V/µs
Supply Current/channel 1.15 mA
Cap Load Limit Unlimited
Output Short Circuit Current +53mA/−75 mA
+/−5% Settling Time 400ns (500 pF, 100 mVPP
step)
Greater than Rail-to-Rail input common mode voltage
range with 50 dB of Common Mode Rejection allows
high side and low side sensing for many applications
without concern for exceeding the range and with no
compromise in accuracy. In addition, most device
parameters are insensitive to power supply variations.
This design enhancement is yet another step in
simplifying its usage. The output stage has low
•
•
•
•
Input Common Mode Voltage 0.3 V Beyond Rails
Input Voltage Noise 15nV/√Hz
Input Current Noise 1pA/√Hz
THD+N < 0.05%
2 Applications
•
•
•
•
TFT-LCD Flat Panel VCOM driver
A/D Converter Buffer
distortion (0.05% THD+N) and can supply
a
respectable amount of current (15 mA) with minimal
headroom from either rail (300 mV).
High Side/low Side Sensing
Headphone Amplifier
The LM8262 is offered in the space saving VSSOP
package.
Device Information(1)
PART NUMBER
LM8262
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Output Response with Heavy Capacitive Load
Gain/Phase vs. Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM8262
SNOS975G –MAY 2001–REVISED AUGUST 2015
www.ti.com
Table of Contents
6.5 2.7V Electrical Characteristics ................................. 5
6.6 5V Electrical Characteristics .................................... 6
6.7 +/−11V Electrical Characteristics............................. 7
6.8 Typical Performance Characteristics ........................ 9
Device and Documentation Support.................. 12
7.1 Community Resources............................................ 12
7.2 Trademarks............................................................. 12
7.3 Electrostatic Discharge Caution.............................. 12
7.4 Glossary.................................................................. 12
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
7
8
Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2014) to Revision G
Page
•
•
•
•
Changed pin 5 From: -IN B To: +IN B Non-Inverting Input B in the Pin Functions table....................................................... 3
Changed pin 6 From: +IN B To: -IN B Inverting Input B in the Pin Functions table............................................................... 3
Moved "Storage temperature range" to the Absolute Maximum Ratings (1)(2) ....................................................................... 4
Changed Handling Ratings To: ESD Ratings ........................................................................................................................ 4
Changes from Revision E (April 2013) to Revision F
Page
•
Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device and
Documentation Support; Mechanical, Packaging, and Ordering Information......................................................................... 1
Changed from "Junction Temperature Range" to "Operating Temperature Range".............................................................. 4
Deleted TJ = 25°C, ................................................................................................................................................................. 5
Deleted TJ = 25°C, ................................................................................................................................................................. 6
Deleted TJ = 25°C................................................................................................................................................................... 7
•
•
•
•
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 10
2
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SNOS975G –MAY 2001–REVISED AUGUST 2015
5 Pin Configuration and Functions
8-Pin
VSSOP
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUT A
-IN A
+IN A
V-
1
2
3
4
5
6
7
8
O
I
Output A
Inverting Input A
Non-Inverting Input A
Negative Supply
Non-Inverting Input B
Inverting Input B
Output B
I
I
+IN B
-IN B
OUT B
V+
I
I
O
I
Positive Supply
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SNOS975G –MAY 2001–REVISED AUGUST 2015
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6 Specifications
(1)(2)
6.1 Absolute Maximum Ratings
(3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN Differential
+/−10
V
(4) (5)
Output Short Circuit Duration
Supply Voltage (V+ - V−)
Voltage at Input/Output pins
See
24
V
V+ +0.8, V− −0.8
V
(6)
Junction Temperature
+150
°C
°C
°C
°C
Storage temperature range, Tstg
−65
+150
235
Soldering Information:
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
260
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(6) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2)
Machine Model (MM)(3)
V(ESD)
Electrostatic discharge(1)
V
(1) Human Body Model, 1.5 kΩ in series with 100 pF. Machine Model, 0 Ω is series with 200 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
22
UNIT
V
Supply Voltage (V+ - V−)
2.5
Operating Temperature Range(1)
−40
+85
°C
(1) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information
DGK
THERMAL METRIC(1)
UNIT
°C/W
8 PINS
RθJA
Junction-to-ambient thermal resistance(2)
235
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(max),RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
4
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SNOS975G –MAY 2001–REVISED AUGUST 2015
6.5 2.7V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 2.7V, V− = 0V, VCM = 0.5V, VO = V+/2, and RL > 1MΩ to V−. Boldface
limits apply at the temperature extremes.
PARAMETER
Input Offset Voltage
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
VOS
VCM = 0.5V & VCM = 2.2V
+/−5
+/−7
mV
–
+/−0.7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
VCM = 0.5V & VCM = 2.2V
µV/C
–
–
–
–
+/−2
−1.20
+0.49
20
–
(3)
VCM = 0.5V
−2.00
−2.70
(4)
µA
nA
VCM = 2.2V
+1.00
+1.60
(4)
IOS
Input Offset Current
VCM = 0.5V & VCM = 2.2V
250
400
CMRR
Common Mode Rejection Ratio
VCM stepped from 0V to 1.0V
76
60
100
100
70
–
–
–
VCM stepped from 1.7V to 2.7V
VCM stepped from 0V to 2.7V
–
dB
58
50
+PSRR
CMVR
Positive Power Supply Rejection V+ = 2.7V to 5V
Ratio
78
74
dB
V
104
−0.3
3.0
78
–
Input Common-Mode Voltage
Range
CMRR > 50dB
−0.1
0.0
–
2.8
2.7
V
–
–
–
–
–
AVOL
Large Signal Voltage Gain
VO = 0.5 to 2.2V,
RL = 10k to V−
70
67
dB
dB
VO = 0.5 to 2.2V,
RL = 2k to V−
67
63
73
VO
Output Swing
High
RL = 10k to V−
RL = 2k to V−
RL = 10k to V−
Sourcing to V−
2.49
2.46
2.59
2.53
90
V
2.45
2.41
Output Swing
Low
100
120
mV
–
ISC
Output Short Circuit Current
30
20
48
–
–
(5)(6)
VID = 200mV
mA
mA
Sinking to V+
VID = −200mV
50
30
65
(5)(6)
IS
Supply Current (both amps)
No load, VCM = 0.5V
2.5
3.0
–
2.0
(7)
SR
Slew Rate
AV = +1,VI = 2VPP
VI = 10mV, RL = 2kΩ to V+/2
f = 50KHz
–
–
9
–
–
V/µs
MHz
MHz
fu
Unity Gain-Frequency
10
GBWP
Gain Bandwidth Product
15.5
14
21
–
Phim
en
Phase Margin
VI = 10mV
–
–
–
–
50
15
1
–
–
–
–
Deg
Input-Referred Voltage Noise
Input-Referred Current Noise
Full Power Bandwidth
f = 2KHz, RS = 50Ω
nV/ √Hz
pA/ √Hz
MHz
in
f = 2KHz
ZL = (20pF || 10kΩ) to V+/2
fmax
1
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 5V, V− = 0V, VCM = 1V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits
apply at the temperature extremes.
PARAMETER
Input Offset Voltage
TEST CONDITIONS
VCM = 1V & VCM = 4.5V
MIN(1)
TYP(2)
MAX(1)
UNIT
VOS
+/−5
+/− 7
mV
–
+/−0.7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
VCM = 1V & VCM = 4.5V
µV/°C
–
–
–
–
+/−2
−1.18
+0.49
20
–
(3)
VCM = 1V
−2.00
−2.70
(4)
µA
nA
VCM = 4.5V
+1.00
+1.60
(4)
IOS
Input Offset Current
VCM = 1V & VCM = 4.5V
250
400
CMRR
Common Mode Rejection Ratio
VCM stepped from 0V to 3.3V
84
72
110
100
80
–
–
–
VCM stepped from 4V to 5V
VCM stepped from 0V to 5V
–
dB
64
61
+PSRR
CMVR
Positive Power Supply Rejection
Ratio
V+ = 2.7V to 5V, VCM = 0.5V
CMRR > 50dB
78
74
dB
V
104
−0.3
5.3
84
–
Input Common-Mode Voltage
Range
−0.1
0.0
–
5.1
5.0
V
–
–
–
–
–
AVOL
Large Signal Voltage Gain
VO = 0.5 to 4.5V,
RL = 10k to V−
74
70
dB
VO = 0.5 to 4.5V,
RL = 2k to V−
70
66
80
VO
Output Swing
High
RL = 10k to V−
RL = 2k to V−
RL = 10k to V−
Sourcing to V−
4.75
4.72
4.87
4.81
86
V
4.70
4.66
Output Swing
Low
125
135
mV
–
ISC
Output Short Circuit Current
35
20
53
–
–
(5)(6)
VID = 200mV
mA
Sinking to V+
VID = −200mV
60
50
75
(5)(6)
IS
Supply Current (both amps)
No load, VCM = 1V
AV = +1, VI = 5VPP
2.8
3.5
mA
–
2.3
12
(7)
SR
fu
Slew Rate
10
7
V/µs
MHz
MHz
–
–
–
Unity Gain Frequency
VI = 10mV,
–
10.5
21
RL = 2kΩ to V+/2
GBWP
Gain-Bandwidth Product
f = 50KHz
16
15
Phim
en
Phase Margin
VI = 10mV
–
–
–
53
15
1
–
–
–
Deg
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 2KHz, RS = 50Ω
f = 2KHz
nV/ √Hz
pA/ √Hz
in
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 5V, V− = 0V, VCM = 1V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits
apply at the temperature extremes.
PARAMETER
Full Power Bandwidth
Settling Time (+/−5%)
TEST CONDITIONS
ZL = (20pF || 10kΩ) to V+/2
100mVPP Step, 500pF load
MIN(1)
TYP(2)
900
MAX(1)
UNIT
KHz
ns
fmax
–
–
–
–
tS
400
THD+N
Total Harmonic Distortion + Noise RL = 1kΩ to V+/2
f = 10KHz to AV= +2, 4VPP swing
–
0.05%
–
6.7 +/−11V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 11V, V− = −11V, VCM = 0V, VO = 0V, and RL > 1MΩ to 0V. Boldface
limits apply at the temperature extremes.
PARAMETER
Input Offset Voltage
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
VOS
VCM = −10.5V & VCM = 10.5V
+/−7
+/− 9
mV
–
+/−0.7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
VCM = −10.5V & VCM = 10.5V
µV/°C
–
–
–
–
+/−2
−1.05
+0.49
30
–
(3)
VCM = −10.5V
−2.00
−2.80
(4)
µA
nA
VCM = 10.5V
+1.00
+1.50
(4)
IOS
Input Offset Current
VCM = −10.5V & VCM = 10.5V
VCM stepped from −11V to 9V
275
550
CMRR
Common Mode Rejection Ratio
84
80
100
100
88
–
–
–
VCM stepped from 10V to 11V
–
dB
VCM stepped from −11V to 11V
74
72
+PSRR
−PSRR
CMVR
Positive Power Supply Rejection V+ = 9V to 11V
Ratio
Negative Power Supply Rejection V− = −9V to −11V
70
66
dB
dB
V
100
100
–
–
70
66
Ratio
Input Common-Mode Voltage
Range
CMRR > 50dB
−11.1
−11.0
–
−11.3
11.3
11.1
11.0
V
–
–
–
–
–
AVOL
Large Signal Voltage Gain
VO = 0V to +/−9V,
RL = 10kΩ
78
74
85
dB
V
VO = 0V to +/−9V,
RL = 2kΩ
72
66
79
VO
Output Swing
High
RL = 10kΩ
RL = 2kΩ
RL = 10kΩ
RL = 2kΩ
10.65
10.61
10.77
10.69
−10.98
−10.91
10.6
10.55
Output Swing
Low
−10.75
−10.65
–
–
V
−10.65
−10.6
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
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+/−11V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 11V, V− = −11V, VCM = 0V, VO = 0V, and RL > 1MΩ to 0V. Boldface
limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
Sourcing to ground
VID = 200mV
MIN(1)
TYP(2)
MAX(1)
UNIT
ISC
Output Short Circuit Current
40
25
60
–
(5)(6)
mA
Sinking to ground
VID = 200mV
65
55
100
2.5
–
(5)(6)
IS
Supply Current
No load, VCM = 0V
AV = +1, VI = 16VPP
4
5
mA
–
SR
Slew Rate
10
8
V/µs
15
13
24
–
–
–
(7)
fU
Unity Gain Frequency
VI = 10mV, RL = 2kΩ
–
MHz
MHz
GBWP
Gain-Bandwidth Product
f = 50KHz
18
16
Phim
en
Phase Margin
VI = 10mV
–
–
–
–
–
58
15
–
–
–
–
–
Deg
Input-Referred Voltage Noise
Input-Referred Current Noise
Settling Time (+/−1%, AV = +1)
f = 2KHz, RS = 50Ω
f = 2KHz
nV/ √Hz
pA/ √Hz
in
1
tS
Positive Step, 5VPP
Negative Step, 5VPP
320
600
ns
THD+N
CTREJ
Total Harmonic Distortion +Noise RL = 1kΩ, f = 10KHz,
–
–
0.01%
68
–
–
AV = +2, 15VPP swing
Cross-Talk Rejection
f = 5MHz, Driver
dB
RL = 10kΩ
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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6.8 Typical Performance Characteristics
TA = 25°C, Unless Otherwise Noted
Figure 1. VOS vs. VCM for 3 Representative Units
Figure 2. VOS vs. VCM for 3 Representative Units
Figure 4. VOS vs. VS for 3 Representative Units
Figure 3. VOS vs. VCM for 3 Representative Units
Figure 5. VOS vs. VS for 3 Representative Units
Figure 6. VOS vs. VS for 3 Representative Units
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Typical Performance Characteristics (continued)
TA = 25°C, Unless Otherwise Noted
Figure 7. IB vs. VCM
Figure 8. IB vs. VS
Figure 9. IS vs. VCM
Figure 10. IS vs. VCM
Figure 11. IS vs. VCM
Figure 12. IS vs. VS (PNP side)
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Typical Performance Characteristics (continued)
TA = 25°C, Unless Otherwise Noted
Figure 13. IS vs. VS (NPN side)
Figure 14. Gain/Phase vs. Frequency
Figure 15. Unity Gain Frequency vs. VS
Figure 16. Phase Margin vs. VS
Figure 17. Unity Gain Freq. and Phase Margin vs. VS
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7 Device and Documentation Support
7.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
7.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
7.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM8262
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM8262MM
LIFEBUY
VSSOP
DGK
8
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 85
A46
LM8262MM/NOPB
LM8262MMX/NOPB
LIFEBUY
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A46
A46
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM8262MM
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000
1000
3500
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
LM8262MM/NOPB
LM8262MMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM8262MM
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000
1000
3500
208.0
208.0
367.0
191.0
191.0
367.0
35.0
35.0
35.0
LM8262MM/NOPB
LM8262MMX/NOPB
Pack Materials-Page 2
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Copyright © 2023, Texas Instruments Incorporated
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