LM8327JGR8X_技术文档

September 14, 2011

LM8327

Mobile I/O Companion Supporting Keyscan, I/O Expansion,

PWM, and ACCESS.bus Host Interface

matrix, or as a host-programmable general purpose input or

output.

1.0 General Description

The LM8327 GenI/O-Expander and Keypad Controller is a

Any pin programmed as an input can also sense hardware

dedicated device to unburden a host processor from scanning

interrupts. The interrupt polarity (“high-to-low” or “low-to-high”

a matrix-addressed keypad and to provide flexible and gen-

transition) is thereby programmable.

eral purpose, host-programmable input/output functions.

The LM8327 follows a predefined register based set of com-

Three independent PWM timer outputs are provided for dy-

mands. Upon startup (power on) a configuration file must be

namic LED brightness modulation.

sent from the host to setup the hardware of the device.

It communicates with a host processor through an I²C-com-

patible ACCESS.bus serial interface. It can communicate in

Standard (100 kHz) and Fast-Mode (400 kHz) in slave Mode

only.

2.0 Applications:

Cordless Phones

■

Smart Handheld Devices

Keyboard Applications

All available input/output pins can alternately be used as a

direct key input connection, an input or an output in a keypad

3.0 LM8327 Function Blocks

30124201

301242

www.national.com

•

Three PWM outputs with dedicated script buffer for up to

32 commands

Register-based command interpreter with auto-increment

address

4.0 Features

4.1 KEY FEATURES

•

Internal RC oscillator, no external clock required

Internal PWM clock generation, no external clock required

Programmable I²C-compatible ACCESS.bus address

4.2 HOST-CONTROLLED FEATURES

•

PWM scripting for three PWM outputs

(Default 0x8A)

Period of inactivity that triggers entry into HALT mode

Debounce time for reliable key event polling

Configuration of general purpose I/O ports

Various initialization options (keypad size, etc.)

•

Support for Keypad matrices of up to of 8 x 12 keys, plus

8 special function (SF) keys, for a full 104 key support

•

Support for up to 26 direct connect keys

I²C-compatible ACCESS.bus slave interface at 100 kHz

(Standard-Mode) and 400 kHz (Fast-Mode)

4.3 KEY DEVICE FEATURES

•

Three host-programmable PWM outputs for smooth LED

brightness modulation

Supports general-purpose I/O expansion on pins not

otherwise used for keypad or PWM output

15-byte Key event buffer

Multiple Key event storage

Key events, errors, and dedicated hardware interrupts

request host service by asserting an IRQ output

•

1.8V ± 10% single-supply operation

On-chip power-on reset (POR)

ESD glitch filter on RESETN pin

Watchdog timer

Dedicated slow clock input for 32 kHz up to 8MHz

−40°C to +85°C temperature range

36-pin MICRO ARRAY package

•

Automatic HALT Mode for low power operation

Wake-up from HALT mode on any interface (rising edge,

falling edge or pulse)

www.national.com

2

5.0 Pin Assignments

30124202

FIGURE 1. LM8327 Pinout - Top View

3

www.national.com

Table of Contents

1.0 General Description ......................................................................................................................... 1

2.0 Applications: ................................................................................................................................... 1

3.0 LM8327 Function Blocks .................................................................................................................. 1

4.0 Features ........................................................................................................................................ 2

4.1 KEY FEATURES ...................................................................................................................... 2

4.2 HOST-CONTROLLED FEATURES ............................................................................................. 2

4.3 KEY DEVICE FEATURES ......................................................................................................... 2

5.0 Pin Assignments ............................................................................................................................. 3

6.0 Ordering Information ........................................................................................................................ 7

7.0 Signal Descriptions .......................................................................................................................... 7

7.1 DEVICE PIN FUNCTIONS ........................................................................................................ 7

7.2 PIN CONFIGURATION AFTER RESET ...................................................................................... 9

8.0 Typical Application Setup ............................................................................................................... 10

8.1 FEATURES ........................................................................................................................... 10

8.1.1 Hardware .................................................................................................................... 10

8.1.2 Communication Layer ................................................................................................... 10

9.0 Halt Mode .................................................................................................................................... 11

9.1 HALT MODE DESCRIPTION ................................................................................................... 11

9.2 ACCESS.BUS ACTIVITY ........................................................................................................ 11

10.0 LM8327 Programming Interface ..................................................................................................... 12

10.1 ACCESS.BUS COMMUNICATION ......................................................................................... 12

10.1.1 Starting a Communication Cycle ................................................................................... 12

10.1.2 Communication Initialized from Host (Restart from Sleep Mode) ....................................... 13

10.1.3 ACCESS.Bus Communication Flow .............................................................................. 13

10.1.4 Auto Increment ........................................................................................................... 13

10.1.5 Reserved Registers and Bits ........................................................................................ 13

10.1.6 Global Call Reset ........................................................................................................ 13

11.0 Keyscan Operation ...................................................................................................................... 15

11.1 KEYSCAN INITIALIZATION ................................................................................................... 15

11.2 KEYSCAN INITIALIZATION EXAMPLE ................................................................................... 16

11.3 KEYSCAN PROCESS ........................................................................................................... 17

11.4 READING KEYSCAN STATUS BY THE HOST ........................................................................ 18

11.5 MULTIPLE KEY PRESSES ................................................................................................... 19

12.0 Direct Key Operation .................................................................................................................... 20

12.1 DIRECT KEY INITIALIZATION ............................................................................................... 20

12.2 DIRECT KEY INITIALIZATION EXAMPLE ............................................................................... 21

13.0 PWM Timer ................................................................................................................................ 22

13.1 OVERVIEW OF PWM FEATURES ......................................................................................... 22

13.2 OVERVIEW ON PWM SCRIPT COMMANDS ........................................................................... 22

13.2.1 RAMP COMMAND ..................................................................................................... 22

13.2.2 SET_PWM COMMAND ............................................................................................... 22

13.2.3 GO_TO_START COMMAND ....................................................................................... 23

13.2.4 BRANCH COMMAND ................................................................................................. 23

13.2.5 TRIGGER COMMAND ................................................................................................ 23

13.2.6 END COMMAND ........................................................................................................ 23

14.0 LM8327 Register Set ................................................................................................................... 25

14.1 KEYBOARD REGISTERS AND KEYBOARD CONTROL ........................................................... 25

14.1.1 KBDSETTLE - Keypad Settle Time Register ................................................................... 25

14.1.2 KBDBOUNCE - Debounce Time Register ...................................................................... 25

14.1.3 KBDSIZE - Set Keypad Size Register ............................................................................ 25

14.1.4 KBDDEDCFG - Dedicated Key Register ........................................................................ 26

14.1.5 KBDRIS - Keyboard Raw Interrupt Status Register .......................................................... 26

14.1.6 KBDMIS - Keypad Masked Interrupt Status Register ....................................................... 27

14.1.7 KBDIC - Keypad Interrupt Clear Register ....................................................................... 27

14.1.8 KBDMSK - Keypad Interrupt Mask Register .................................................................... 28

14.1.9 KBDCODE0 - Keyboard Code Register 0 ....................................................................... 28

14.1.10 KBDCODE1 - Keyboard Code Register 1 ..................................................................... 28

14.1.11 KBDCODE2 - Keyboard Code Register 2 ..................................................................... 29

14.1.12 KBDCODE3 - Keyboard Code Register 3 ..................................................................... 29

14.1.13 EVTCODE - Key Event Code Register ......................................................................... 29

14.2 PWM TIMER CONTROL REGISTERS .................................................................................... 29

14.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers .............................................. 29

14.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers ................................. 30

14.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers ................................................... 30

www.national.com

4

14.2.4 TIMSWRES - PWM Timer Software Reset Registers ....................................................... 31

14.2.5 TIMRIS - PWM Timer Interrupt Status Register ............................................................... 31

14.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register .................................................. 32

14.2.7 TIMIC - PWM Timer Interrupt Clear Register .................................................................. 33

14.2.8 PWMWP - PWM Timer Pattern Pointer Register ............................................................. 33

14.2.9 PWMCFG - PWM Script Register (Two Byte) ................................................................. 34

14.3 INTERFACE CONTROL REGISTERS ..................................................................................... 35

14.3.1 I2CSA - I²C-Compatible ACCESS.bus Slave Address Register ......................................... 35

14.3.2 MFGCODE - Manufacturer Code Register ..................................................................... 35

14.3.3 SWREV - Software Revision Register ............................................................................ 35

14.3.4 SWRESET - Software Reset ........................................................................................ 35

14.3.5 RSTCTRL - System Reset Register .............................................................................. 35

14.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register ................................................. 36

14.3.7 CLKMODE - Clock Mode Register ................................................................................ 36

14.3.8 CLKCFG - Clock Configuration Register ........................................................................ 37

14.3.9 CLKEN - Clock Enable Register ................................................................................... 37

14.3.10 AUTOSLP - Autosleep Enable Register ....................................................................... 37

14.3.11 AUTOSLPTI - Auto Sleep Time Register ...................................................................... 38

14.3.12 IRQST - Global Interrupt Status Register ...................................................................... 38

14.4 GPIO FEATURE CONFIGURATION ....................................................................................... 39

14.4.1 GPIO Feature Mapping ............................................................................................... 39

14.4.2 IOCGF - Input/Output Pin Mapping Configuration Register ............................................... 39

14.4.3 IOPC0 - Pull Resistor Configuration Register 0 ............................................................... 40

14.4.4 IOPC1 - Pull Resistor Configuration Register 1 ............................................................... 40

14.4.5 IOPC2 - Pull Resistor Configuration Register 2 ............................................................... 41

14.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0 ................................................. 42

14.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0 .................................................. 42

14.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1 ................................................. 43

14.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1 .................................................. 43

14.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2 ............................................... 43

14.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2 ................................................ 44

14.5 GPIO DATA INPUT/OUTPUT ................................................................................................. 44

14.5.1 GPIOPDATA0 - GPIO Data Register 0 .......................................................................... 44

14.5.2 GPIOPDATA1 - GPIO Data Register 1 .......................................................................... 45

14.5.3 GPIOPDATA2 - GPIO Data Register 2 .......................................................................... 46

14.5.4 GPIOPDIR0 - GPIO Port Direction Register 0 ................................................................. 47

14.5.5 GPIOPDIR1 - GPIO Port Direction Register 1 ................................................................. 47

14.5.6 GPIOPDIR2 - GPIO Port Direction Register 2 ................................................................. 47

14.6 GPIO INTERRUPT CONTROL ............................................................................................... 48

14.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0 ........................................................ 48

14.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1 ........................................................ 48

14.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2 ........................................................ 48

14.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 ............................................... 48

14.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 ............................................... 49

14.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 ............................................... 49

14.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0 ......................................................... 49

14.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1 ......................................................... 49

14.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2 ......................................................... 50

14.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0 ................................................................ 50

14.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1 ................................................................ 50

14.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2 ................................................................ 50

14.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0 .................................................................. 51

14.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1 .................................................................. 51

14.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2 .................................................................. 51

14.7 GPIO INTERRUPT STATUS .................................................................................................. 52

14.7.1 GPIORIS0 - Raw Interrupt Status Register 0 .................................................................. 51

14.7.2 GPIORIS1 - Raw Interrupt Status Register 1 .................................................................. 52

14.7.3 GPIORIS2 - Raw Interrupt Status Register 2 .................................................................. 52

14.7.4 GPIOMIS0 - Masked Interrupt Status Register 0 ............................................................. 52

14.7.5 GPIOMIS1 - Masked Interrupt Status Register 1 ............................................................. 53

14.7.6 GPIOMIS2 - Masked Interrupt Status Register 2 ............................................................. 53

14.8 GPIO WAKE-UP CONTROL .................................................................................................. 53

14.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0 ..................................................................... 53

14.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1 ..................................................................... 53

14.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2 ..................................................................... 54

14.9 DIRECT KEY REGISTERS AND DIRECT KEY CONTROL ........................................................ 54

5

www.national.com

14.9.1 DEVTCODE - Direct Key Event Code Register ............................................................... 54

14.9.2 DBOUNCE - Direct Key Debounce Time Register ........................................................... 55

14.9.3 DIRECT0 - Direct Key Register 0 .................................................................................. 55

14.9.4 DIRECT1 - Direct Key Register 1 .................................................................................. 55

14.9.5 DIRECT2 - Direct Key Register 2 .................................................................................. 55

14.9.6 DIRECT3 - Direct Key Register 3 .................................................................................. 56

14.9.7 DKBDRIS - Direct Key Raw Interrupt Status Register ...................................................... 56

14.9.8 DKBDMIS - Direct Key Masked Interrupt Status Register ................................................. 56

14.9.9 DKBDIC - Direct Key Interrupt Clear Register ................................................................. 57

14.9.10 DKBDMSK - Direct Key Interrupt Mask Register ............................................................ 57

15.0 Absolute Maximum Ratings ........................................................................................................... 58

16.0 Electrical Characteristics ............................................................................................................... 58

17.0 Registers .................................................................................................................................... 61

17.1 REGISTER MAPPING .......................................................................................................... 61

17.1.1 Keyboard Registers .................................................................................................... 61

17.1.2 Direct Key Registers ................................................................................................... 61

17.1.3 PWM Timer Registers ................................................................................................. 62

17.1.4 System Registers ....................................................................................................... 63

17.1.5 Global Interrupt Registers ............................................................................................ 63

17.1.6 GPIO Registers .......................................................................................................... 63

18.0 Physical Dimensions .................................................................................................................... 69

www.national.com

6

6.0 Ordering Information

NSID

Spec

NOPB

Package Type

MICRO ARRAY

Package Method

1000 pieces tape & reel

3500 pieces tape & reel

LM8327JGR8

LM8327JGR8X

7.0 Signal Descriptions

7.1 DEVICE PIN FUNCTIONS

TABLE 1. KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS

Ball

Function 0

Function 1

Function 2

Function 3

Genio

Pin Count

Ball Name

DIRECT24

CLKIN

D2

Direct Keypad24

Clock In

1

D1

F3

Direct Keypad25

Interrupt

Genio

1

DIRECT25

IRQN

A4

F4

Supply Voltage

2

VCC

C1

E1

E2

ResetN

1

RESETN

SCL

Main I²C - Clk

Main I²C - Data

SDA

DIRECT0

KPX0

A6

A5

F1

F2

A2

B3

A3

B4

C6

C5

B6

B5

B2

A1

B1

C2

Direct Keypad0

Direct Keypad1

Direct Keypad2

Direct Keypad3

Direct Keypad4

Direct Keypad5

Direct Keypad6

Direct Keypad7

Direct Keypad8

Direct Keypad9

Direct Keypad10

Direct Keypad11

Direct Keypad12

Direct Keypad13

Direct Keypad14

Direct Keypad15

Keypad - I/O X0

Keypad - I/O X1

Keypad - I/O X2

Keypad - I/O X3

Keypad - I/O X4

Keypad - I/O X5

Keypad - I/O X6

Keypad - I/O X7

Keypad - I/O Y0

Keypad - I/O Y1

Keypad - I/O Y2

Keypad - I/O Y3

Keypad - I/O Y4

Keypad - I/O Y5

Keypad - I/O Y6

Keypad - I/O Y7

Genio

1

DIRECT1

KPX1

DIRECT2

KPX2

DIRECT3

KPX3

DIRECT4

KPX4

DIRECT5

KPX5

DIRECT6

KPX6

DIRECT7

KPX7

DIRECT8

KPY0

DIRECT9

KPY1

DIRECT10

KPY2

DIRECT11

KPY3

DIRECT12

KPY4

DIRECT13

KPY5

DIRECT14

KPY6

DIRECT15

KPY7

7

www.national.com

Ball

Function 0

Function 1

Function 2

Function 3

Pin Count

Ball Name

DIRECT16

KPY8

E3

Direct Keypad16

Keypad - I/O Y8

Genio

1

DIRECT17

KPY9

D5

E6

F6

E4

F5

E5

D6

Direct Keypad17

Direct Keypad18

Direct Keypad19

Direct Keypad20

Direct Keypad21

Direct Keypad22

Direct Keypad23

Keypad - I/O Y9

Keypad - I/O Y10

Keypad - I/O Y11

PWM output 0

PWM output 1

PWM output 2

Genio

1

DIRECT18

KPY10

DIRECT19

KPY11

Clockout

DIRECT20

PWM0

DIRECT21

PWM1

DIRECT22

PWM2

DIRECT23

GENIO1

C3

C4

D3

D4

Ground

TOTAL

4

GND

36

www.national.com

8

7.2 PIN CONFIGURATION AFTER RESET

Upon power-up or RESET the LM8327 will have defined

states on all pins. Table 2 provides a comprehensive overview

on the states of all functional pins.

TABLE 2. Pin Configuration after Reset

Pins

Pin States

DIRECT KEYPAD 0

DIRECT KEYPAD 1

DIRECT KEYPAD 2

DIRECT KEYPAD 3

DIRECT KEYPAD 4

DIRECT KEYPAD 5

DIRECT KEYPAD 6

DIRECT KEYPAD 7

DIRECT KEYPAD 8

DIRECT KEYPAD 9

DIRECT KEYPAD 10

DIRECT KEYPAD 11

DIRECT KEYPAD 12

DIRECT KEYPAD 13

DIRECT KEYPAD 14

DIRECT KEYPAD 15

DIRECT KEYPAD 16

DIRECT KEYPAD 17

DIRECT KEYPAD 18

DIRECT KEYPAD 19

DIRECT KEYPAD 20

DIRECT KEYPAD 21

DIRECT KEYPAD 22

DIRECT KEYPAD 23

DIRECT KEYPAD 24

DIRECT KEYPAD 25

Full Buffer mode input with an on-chip pull-up resistor enabled.

IRQN

Open Drain mode with no pull resistor enabled, driven low.

ꢀNOTE: The IRQN is driven low after Power-On Reset due to PORIRQ signal. The

value 0x01 must be written to the RSTINTCLR register (0x84) to release the IRQN

pin.

SCL

SDA

Open Drain mode with no pull resistor enabled.

9

www.national.com

8.0 Typical Application Setup

30124203

FIGURE 2. LM8327 in a Typical Setup with Standard Handset Keypad

8.1 FEATURES

•

External clock input for accurate PWM clock (not used).

Four host-programmable dedicated general-purpose

output pins (GPIOs:KPY4:7) supporting I/O-expansion

capabilities for host device.

Six host-programmable dedicated direct key connection

input pins (DIRECT 16:19, 23, 25) with wake-up

supporting I/O-expansion capabilities for host device.

The following features are supported with the application ex-

ample shown above:

8.1.1 Hardware

Hardware

•

4 x 8 keys and 8 Special Function (SF) keys for 40 keys.

ACCESS.bus interface for communication with a host

device.

8.1.2 Communication Layer

•

Versatile register-based command integration supported

from on-chip command interpreter.

Keypad event storage.

Individual PWM script file storage and execution control

for 3 PWM channels.

- communication speeds supported are: 100 kHz standard

mode and 400 kHz fast mode of operation.

•

Interrupt signal (IRQN) to indicate any keypad or hardware

interrupt events to the host.

Sophisticated PWM function block with 3 independent

channels to control color LED.

www.national.com

10

Halt mode is entered when no key-press event, key-release

event, or is detected for a certain period of time (by default,

1020 milliseconds). The mechanism for entering Halt mode is

always enabled in hardware, but the host can program the

period of inactivity which triggers entry into Halt mode using

the autosleep function. (See Table 52.)

9.0 Halt Mode

9.1 HALT MODE DESCRIPTION

The fully static architecture of the LM8327 allows stopping the

internal RC clock in Halt mode, which reduces power con-

sumption to the minimum level. Figure 3 shows an estimate

of the current in Halt mode at the maximum VCC (1.98V) from

25°C to +85°C.

9.2 ACCESS.BUS ACTIVITY

When the LM8327 is in Halt mode, only activity on the

ACCESS.bus interface that matches the LM8327 Slave Ad-

dress will cause the LM8327 to exit from Halt mode. However,

the LM8327 will not be able to acknowledge the first bus cycle

immediately following wake-up from Halt mode. It will respond

with a negative acknowledgement, and the host should then

repeat the cycle. A peripheral that is continuously active can

share the bus since this activity will not prevent the LM8327

from entering Halt mode.

30124204

FIGURE 3. Halt Current vs. Temperature at 1.98V

11

www.national.com

mission protocol. All functions can be controlled by configur-

ing one or multiple registers. Please refer to Section 14.0

LM8327 Register Set for the complete register set.

10.0 LM8327 Programming Interface

The LM8327 operation is controlled from a host device by a

complete register set, accessed via the I²C-compatible

ACCESS.bus interface. The ACCESS.bus communication is

based on a READ/WRITE structure, following the I²C trans-

10.1 ACCESS.BUS COMMUNICATION

Figure 4 shows a typical read cycle initiated by the host.

30124205

FIGURE 4. Master/Slave Serial Communication (Host to LM8327)

TABLE 3. Definition of Terms used in Serial Command Example

Term

S

Bits

Description

START Condition (always generated from the master device)

Slave address of LM8327 sent from the host

ADDRESS

7

This bit determines if the following data transfer is from master to slave (data write) or from slave

to master (data read).

0: Write

R/W

1

1: Read

An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge

status is actually provided from the slave and indicates to the master that the byte transfer was

successful.

ACK

REG

1

8

The first byte after sending the slave address is the REGISTER byte which contains the physical

address the host wants to read from or write to.

RS

Repeated START condition

DATA

8

1

The DATA field contains information to be stored into a register or information read from a register.

Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data

from a slave. The NACK status will actually be assigned from the master in order to signal the

end of a communication cycle transfer

NACK

P

STOP condition (always generated from the master device).

All actions associated with the non-shaded boxes in

Figure 4 are controlled from the master (host) device.

2. The host device wants to set a GENIO port, read from a

GENIO port, configure a GENIO port, and read the status

from a register or initialize any other function which is

supported from the LM8327. In case a GENIO shall be

read it will be most likely, that the LM8327 device will be

residing in “sleep mode”. In this mode the system clock

will be off to establish the lowest possible current

consumption. If the host device starts the communication

under this condition the LM8327 device will not be able

to acknowledge the first attempt of sending the slave

address. The LM8327 will wake up because of the

START condition but it can’t establish the internal timing

to scan the first byte received. The master device must

therefore apply a second attempt to start the

All actions associated with the shaded boxes in Figure 4 are

controlled from the slave (LM8327) device.

The master device can send subsequent REGISTER ad-

dresses separated by Repeated START conditions. A STOP

condition must be set from the master at the very end of a

communication cycle.

It is recommended to use Repeated START conditions in

multi-Master systems when sending subsequent REGISTER

addresses. This technique will make sure that the master de-

vice communicating with the LM8327 will not loose bus arbi-

tration.

communication with the LM8327 device.

10.1.1 Starting a Communication Cycle

There are two reasons for the host device to start communi-

cation to the LM8327:

1. The LM8327 device has set the IRQN line low in order to

signal a key - event or any other condition which

initializes a hardware interrupt from LM8327 to the host.

www.national.com

12

10.1.2 Communication Initialized from Host (Restart from

Sleep Mode)

30124206

FIGURE 5. Host Starts Communication While LM8327 is in Sleep Mode

•

In the timing diagram shown in Figure 5 the LM8327

resides in sleep mode. Since the LM8327 device can’t

acknowledge the slave address the host must generate a

STOP condition followed by a second START condition.

On the second attempt the slave address is being

acknowledged from the LM8327 device because it is in

active mode now.

The host can send different WRITE and/or READ

commands subsequently after each other.

The host must finally free the bus by generating a STOP

condition.

•

Normally the LM8327 will clock stretch after the

acknowledge bit is transmitted; however, there are some

conditions where the LM8327 will clock stretch between

the SDA Start bit and the first rising edge of SCL.

10.1.4 Auto Increment

In order to improve multi-byte register access, the LM8327

supports the auto increment of the address pointer.

•

A typical protocol access sequence to the LM8327 starts with

the I²C-compatible ACCESS.bus address, followed by REG,

the register to access (see Figure 4). After a REPEATED

START condition the host reads/writes a data byte from/to this

address location. If more than one byte is transmitted, the

LM8327 automatically increments the address pointer for

each data byte by 1. The address pointer keeps the status

until the STOP condition is received.

10.1.3 ACCESS.Bus Communication Flow

The LM8327 will only be driven in slave mode. The maximum

communication speed supported is Fast Mode (FS) which is

400 kHz. The device can be heavily loaded as it is processing

different kind of events caused from the human interface and

the host device. In such cases the LM8327 may temporarily

be unable to accept new commands and data sent from the

host device.

The LM8327 always uses auto increments unless otherwise

noted.

Please refer to Table 4 and Table 5 for the typical

ACCESS.bus flow of reading and writing multiple data bytes.

Please Note: “It is a legitimate measure of the slave device to

hold SCL line low in such cases in order to force the master

device into a waiting state!. It is therefore the obligation of the

host device to detect such cases. Typically there is a control

bit set in the master device indicating the Busy status of the

bus. As soon as the SCL line is released the host can continue

sending commands and data.”

10.1.5 Reserved Registers and Bits

The LM8327 includes reserved registers for future implemen-

tation options. Please use value 0 on a write to all reserved

register bits.

10.1.6 Global Call Reset

The LM8327 supports the Global Call Reset as defined in the

I²C Specification, which can be used by the host to reset all

devices connected to interface. The Global call reset is a sin-

gle byte ACCESS.bus/I²C write of data byte 0x06 to slave

address 0x00.

The Global Call Reset changes the I²C-compatible

ACCESS.bus Slave address of the LM8327 back to its default

value of 0x8A.

Further Remarks:

•

In systems with multiple masters it is recommended to

separate commands with Repeat START conditions

rather than sending a STOP - and another START -

condition to communicate with the LM8327 device.

•

Delays enforced by the LM8327 during very busy phases

of operation should typically not exceed a duration of 100

µsec.

13

www.national.com

TABLE 4. Multi-Byte Write with Auto Increment

I²C Com.

S

Step

1

Master/Slave

Value

Address Pointer

Comment

M

S

START condition

I²C-compatible ACCESS.bus Address

2

ADDR.

R/W

0x8A

0

3

Write

4

ACK

REG

ACK

DATA

ACK

DATA

ACK

P

Acknowledge

5

M

S

0xAA

0xAB

0xAC

Register Address, used as Address Pointer

Acknowledge

6

7

M

S

0x01

0

Write Data to Address in Pointer

Acknowledge, Address pointer incremented

Write Data to address 0xAB

Acknowledge, Address pointer incremented

STOP condition

8

9

M

S

0x05

0

10

11

M

TABLE 5. Multi-Byte Read with Auto Increment

I²C Com.

S

Step

1

Master/Slave

Value

Address Pointer

Comment

M

S

START condition

I²C-compatible ACCESS.bus Address

2

ADDR.

R/W

0x8A

0

3

Write

4

ACK

REG

ACK

RS

Acknowledge

5

M

S

0xAA

Register Address, used as Address pointer

Acknowledge

6

7

M

S

Repeated Start

I²C-compatible ACCESS.bus Address

8

ADDR.

R/W

0x8A

9

1

0

Read

10

11

12

13

14

15

ACK

DATA

ACK

DATA

NACK

P

0xAA

0xAB

0xAC

Acknowledge

S

0x01

0

Read Data from Address in Pointer

Acknowledge, Address Pointer incremented

Read Data from Address in Pointer

No Acknowledge, stops transmission

STOP condition

M

S

0x05

0

M

All non-bolded actions rows in Tables 4 and 5 are controlled from the master (host) device.

All highlighted rows in Tables 4 and 5 are controlled from the slave (LM8327) device.

www.national.com

14

11.0 Keyscan Operation

11.1 KEYSCAN INITIALIZATION

30124207

FIGURE 6. Keyscan Initialization

15

www.national.com

11.2 KEYSCAN INITIALIZATION EXAMPLE

•

Keypad matrix configuration is 8 rows x 12 columns.

Table 6 shows all the LM8327 register configurations to ini-

tialize keyscan:

TABLE 6. Keyscan Initialization Example

Access

Register name

Adress

Value

Comment

Type

byte

word

byte

word

byte

CLKEN

KBDSETTLE

KBDBOUNCE

KBDSIZE

KBDDEDCFG

IOCFG

0x8A

0x01

0x02

0x03

0x04

0xA7

0xAA

0xAC

0xAE

0x08

0x09

0x01

0x80

enable keyscan clock

set the keyscan settle time to 12 msec

0x80

set the keyscan debounce time to 12 msec

set the keyscan matrix size to 8 rows x 12 columns

configure KPX[7:2] and KPY[11:2] pins as keyboard matrix

write default value to enable all pins as keyboard matrix

configure pull-up resistors for KPX[7:0]

configure pull-down resistors for KPY[7:0]

configure pull-down resistors for KPY[11:8]

clear any pending interrupts

0x8C

0xFFFF

0x00

IOPC0

0xAAAA

0x5555

0x0055

0x03

IOPC1

IOPC2

KBDIC

KBDMSK

0x03

enable keyboard interrupts

www.national.com

16

11.3 KEYSCAN PROCESS

the device sets the RAW keyboard event interrupt REVTINT.

The RSINT interrupt is set anytime the keyboard status has

changed.

The LM8327 keyscan functionality is based on a specific

scanning procedure performed in a 4ms interval. On each

scan all assigned key matrix pins are evaluated for state

changes.

Depending on the interrupt masking for the keyboard events

(KBDMSK) and the masked interrupt handling (KBDMIS), the

pin IRQN will follow the IRQST.KBDIRQ status, which is set

as soon as one interrupt in KBDRIS is set.

In case a key event has been identified, the event is stored in

the key event FIFO, accessible via the EVTCODE register. A

key event can either be a key press or a key release. In ad-

dition, key presses are also stored in the KBDCODE[3:0]

registers. As soon as the EVTCODE FIFO includes a event,

Figure 7 shows the basic flow of a scanning process and

which registers are affected.

30124208

FIGURE 7. Example Keyscan Operation for

1 Key Press and Release

17

www.national.com

11.4 READING KEYSCAN STATUS BY THE HOST

host first reads the KBDCODE to get possible key press

events and afterwards reads the complete event list by read-

ing the EVTCODE register until all events are captured (0x7F

indicates end of buffer).

In order to keep track of the keyscan status, the host either

needs to regularly poll the EVTCODE register or needs to re-

act on the Interrupt signaled by the IRQN pin.

Reading KBDCODE clears the RSINT interrupt bit if all key-

boards events are emptied. In the same way, REVTINT is

cleared in case the EVTCODE FIFO reaches its empty state

on read.

Figure 8 gives an example on which registers to read to get

the keyboard events from the LM8327 and how they influence

the interrupt event registers. The example is based on the

assumption that the LM8327 has indicated the keyboard

event by the IRQN pin.

The event buffer content and the REVTINT and RELINT (lost

event) interrupt bits are also cleared if the KBDIC.EVTIC bit

is set.

Since the interrupt pin has various sources, the host first

checks the IRQST register for the interrupt source. If KBDIRQ

is set, the host can check the KBDMIS register to define the

exact interrupt source. KBDMIS contains the masked status

of KBDRIS and reflects the source for raising the interrupt pin.

The interrupt mask is defined by KBDMSK. The complete

status of all pending keyboard interrupts is available in the raw

interrupt register KBDRIS.

Interrupt bits in the masked interrupt register KBDMIS follow

the masked KBDRIS status.

In order to support efficient Multi-byte reads from EVTCODE,

the autoincrement feature is turned off for this register. There-

fore the host can continuously read the complete EVTCODE

buffer by sending one command.

After evaluating the interrupt source the host starts reading

the EVTCODE or KBDCODE register. In this example the

30124209

FIGURE 8. Example Host Reacting to

Interrupt for Keypad Event

www.national.com

18

11.5 MULTIPLE KEY PRESSES

KBDCODE3 accordingly. The four registers signal the last

multi-key press events.

The LM8327 supports up to four simultaneous key presses.

Any time a single key is pressed KBDCODE0 is set with the

appropriate key code. If a second key is pressed, the key is

stored in KBDCODE1 and the MULTIKEY flag of KBDCODE0

is set. Additional key presses are stored in KBDCODE2 and

All events are stored in parallel in the EVTCODE register for

the complete set of events.

All KBDCODE[3:0] registers are cleared on read.

30124210

FIGURE 9. Example Keyscan Operation for 2 Key Press Events

and 1 Key Release Event

19

www.national.com

12.0 Direct Key Operation

12.1 DIRECT KEY INITIALIZATION

30124213

FIGURE 10. Direct Key Initialization

www.national.com

20

12.2 DIRECT KEY INITIALIZATION EXAMPLE

Table 7 shows all the LM8327 register configurations to initialize direct keys.

•

Direct key configuration is for 26 direct keys.

TABLE 7. Direct Key Initialization Example

Register Name

CLKEN

Address

0x8A

0xE7

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xA7

0xAA

0xAC

0xAE

0xF2

0xF3

0xEC

0xED

0xEE

0xEF

Access Type

byte

Value

0x02

Comment

Enable direct key clock

DBOUNCE

GPIOIBE0

GPIOIBE1

GPIOIBE2

GPIOIEV0

GPIOIEV1

GPIOIEV2

GPIOIE0

GPIOIE1

GPIOIE2

IOCFG

byte

0x04

Set the keyscan debounce time to 12 msec.

Configure single key event detection for DK[7:0]

Configure single key event detection for DK[15:8]

Configure single key event detection for DK[23:16]

Configure press key event detection DK[7:0]

Configure press key event detection DK[15:8]

Configure press key event detection DK[23:16]

Disable GPI interrupts for DK[7:0]

byte

0x00

byte

0x00

byte

0x00

byte

0x00

byte

0x00

byte

0x00

byte

0x00

byte

0x00

Disable GPI interrupts for DK[15:8]

byte

0x00

Disable GPI interrupts for DK[23:16]

Write default value to enable all pins as direct keys

Configure pull-up resistors for DK[7:0]

Configure pull-up resistors for DK[15:8]

Configure pull-up resistors for DK[23:16]

Clear any pending interrupts

byte

0x00

IOPC0

word

byte

0xAAAA

0x01

IOPC1

IOPC2

DKBDIC

DKBDMSK

DIRECT0

DIRECT1

DIRECT2

DIRECT3

byte

0x00

Enable direct key and lost direct key interrupts

Enable pins as DK[7:0]

byte

0xFF

0x03

byte

Enable pins as DK[15:8]

byte

Enable pins as DK[23:16]

byte

Enable pins as DK[25:24]

21

www.national.com

•

The execution of any pre-programmed task is self-

sustaining and does not require further interaction from the

host.

64-byte script buffer for each PWM for up to 32

consecutive instructions.

13.0 PWM Timer

The LM8327 supports a timer module dedicated to smooth

LED control techniques (lighting controls).

•

The PWM timer module consists of three independent timer

units of which each can generate a PWM output with a fixed

period and automatically incrementing or decrementing vari-

able duty cycle. The timer units are all clocked with a slow

(32.768 kHz) clock whereas the interface operates with the

main system clock.

Direct addressing within script buffer to support multiple

PWM tasks in one buffer.

13.2 OVERVIEW ON PWM SCRIPT COMMANDS

The commands listed in Table 8 are dedicated to the slow

PWM timers.

13.1 OVERVIEW OF PWM FEATURES

Please note: The PWM Script commands are not part of the

command set supported by the LM8327 command inter-

preter. These commands must be transferred from the host

with help of the register-based command set.

•

Each PWM can establish fixed - or variable - duty-cycle

signal sequences on its output.

Each PWM can trigger execution of any pre-programmed

task on another PWM channel.

•

TABLE 8. PWM Script Commands

Command

RAMP

15

0

14

PRESCALE

1

13 12

11

10

9

8

7

6

5

4

3

2

1

0

STEPTIME

0

SIGN

INCREMENT

PWMVALUE

SET_PWM

GO_TO_

START

0

BRANCH

END

1

0

1

LOOPCOUNT

ADDR

STEPNUMBER

SENDTRIGGER

0

1

INT

WAITTRIGGER

X

TRIGGER

0

13.2.1 RAMP COMMAND

the direction of a RAMP (up or down). The STEPTIME field

and the PRESCALE bit determine the duration of one step.

Based on a 32.768 kHz clock, the minimum time resulting

from these options would be 0.49 milliseconds and the max-

imum time for one step would be 1 second.

A RAMP command will vary the duty cycle of a PWM output

in either direction (up or down). The INCREMENT field spec-

ifies the amount of steps for the RAMP. The maximum amount

of steps which can be executed with one RAMP Command is

126 which is equivalent to 50%. The SIGN bit field determines

TABLE 9. RAMP Command Bit Fields

15

14

13 12 11 10

9

8

7

6

5

4

3

2

1

0

PRESCALE

STEPTIME

SIGN

INCREMENT

TABLE 10. Description of Command Bit Fields of the RAMP Command

Bit or Field

PRESCALE

STEPTIME

SIGN

Value

Description

Divide the 32.768 kHz clock by 16

0

1

1 - 63

0

Divide the 32.768 kHz clock by 512

Number of prescaled clock cycles per step

Increment RAMP counter

1

Decrement RAMP counter

Number of steps executed by this instruction; a value of 0 functions as a

WAIT determined by STEPTIME.

INCREMENT

0 - 126

13.2.2 SET_PWM COMMAND

FULL SCALE (0% or 100%). A RAMP command following the

SET_PWM command will finally establish the desired duty

cycle on the PWM output.

The SET_PWM command does not allow generation of a

PWM output with a fixed duty cycle between 0% and 100%.

This command will set the starting duty cycle MIN SCALE or

TABLE 11. SET_PWM Command Bit Fields

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

DUTYCYCLE

www.national.com

22

TABLE 12. Description of Bit Fields of the SET_PWM Command

Bit or Field

Value

0

Description

Duty cycle is 0%.

DUTYCYCLE

255

Duty cycle is 100%.

13.2.3 GO_TO_START COMMAND

The GO_TO_START command jumps to the first command

in the script command file.

TABLE 13. GO_TO_START Command Bit Fields

15

14

13

12

11 10

9

8

7

6

5

4

3

2

1

0

13.2.4 BRANCH COMMAND

gives the option of looping for a specified number of repeti-

tions.

The BRANCH command jumps to the specified command in

the script command file. The BRANCH is executed with either

absolute or relative addressing. In addition, the command

Please note: Nested loops are not allowed.

TABLE 14. BRANCH Command Bit Fields

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

LOOPCOUNT

ADDR

STEPNUMBER

TABLE 15. Description of Command Bit Fields of the BRANCH Command

Bit or Field

Value

Description

Loop until a STOP PWM SCRIPT command is issued by the host.

Number of loops to perform.

0

1 - 63

0

LOOPCOUNT

ADDR

Absolute addressing

1

Relative addressing

Depending on ADDR:

STEPNUMBER

0 - 63

ADDR=0: Addr to jump to

ADDR=1: Number of backward steps

13.2.5 TRIGGER COMMAND

On trigger it will clear the trigger(s) and continue to the next

command.

Triggers are used to synchronize operations between PWM

channels. A TRIGGER command that sends a trigger takes

sixteen 32.768 kHz clock cycles, and a command that waits

for a trigger takes at least sixteen 32.768 kHz clock cycles.

When a trigger is sent, it is stored by the receiving channel

and can only be cleared when the receiving channel executes

a TRIGGER command that waits for the trigger.

A TRIGGER command that waits for a trigger (or triggers) will

stall script execution until the trigger conditions are satisfied.

TABLE 16. TRIGGER Command Bit Fields

10

WAITTRIGGER

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

1

SENDTRIGGER

0

TABLE 17. Description of Command Bit Fields

Field

Value

000xx1

000x1x

0001xx

000xx1

000x1x

0001xx

Description

Wait for trigger from channel 0

Wait for trigger from channel 1

Wait for trigger from channel 2

Send trigger to channel 0

WAITTRIGGER

SENDTRIGGER

Send trigger to channel 1

Send trigger to channel 2

13.2.6 END COMMAND

When the END command is executed, the PWM output will

be set to the level defined by PWMCFG.PWMPOL for this

channel. Also, the script counter is reset back to the beginning

of the script command buffer.

The END command terminates script execution. It will only

assert an interrupt to the host if the INT bit is set to “1”.

23

www.national.com

Please note: If a PWM channel is waiting for the trigger (last

executed command was "TRIGGER") and the script execu-

tion is halted then the "END" command can’t be executed

because the previous command is still pending. This is an

exception - in this case the IRQ signal will not be asserted.

TABLE 18. END Command Bit Fields

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

INT

0

TABLE 19. Description of Command Bit Fields of the END Command

Field

Value

Description

0

1

No interrupt will be sent.

Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.

INT

www.national.com

24

14.0 LM8327 Register Set

14.1 KEYBOARD REGISTERS AND KEYBOARD

CONTROL

Keyboard selection and control registers are mapped in the

address range from 0x01 to 0x10. This paragraph describes

the functions of the associated registers down to the bit level.

14.1.1 KBDSETTLE - Keypad Settle Time Register

TABLE 20. KBDSETTLE - Keypad Settle Time Register

Address Type Register Function

Register - Name

KBDSETTLE

0x01

R/W

Initial time for keys to settle, before the key-scan process is started.

Bit - Name

Bit

Default

Bit Function

The default value 0x80 : 0xBF sets a time target of 12 msec

Further time targets are as follows:

0xC0 - 0xFF: 16 msec

WAIT[7:0]

7:0

0x80

0x80 - 0xBF: 12 msec

0x40 - 0x7F: 8 msec

0x01 - 0x3F: 4 msec

0x00 : no settle time

14.1.2 KBDBOUNCE - Debounce Time Register

TABLE 21. KBDBOUNCE - Debounce Time Register

Register - Name

Address

Type

Register Function

KBDBOUNCE

0x02

R/W

Time between first detection of key and final sampling of key.

Bit - Name

Bit

Default

Bit Function

The default value 0x80 : 0xBF sets a time target of 12 msec.

Further time targets are as follows:

0xC0 - 0xFF: 16 msec

WAIT[7:0]

7:0

0x80

0x80 - 0xBF: 12 msec

0x40 - 0x7F: 8 msec

0x01 - 0x3F: 4 msec

0x00: no debouncing time

14.1.3 KBDSIZE - Set Keypad Size Register

TABLE 22. KBDSIZE - Set Keypad Size Register

Register - Name

Address

Type

Register Function

KBDSIZE

0x03

R/W

Defines the physical keyboard matrix size.

Bit - Name

Bit

Default

Bit Function

Number of rows in the keyboard matrix:

0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key

inputs if scanning is enabled by CLKEN.KBEN.

0x1: (illegal value)

ROWSIZE[3:0]

7:4

0x2

0x2 - 0x8: Number of rows in the matrix

Number of columns in the keyboard matrix:

0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key

inputs if scanning is enabled by CLKEN.KBEN

0x1: (illegal value)

COLSIZE[3:0]

3:0

0x2

0x2 - 0xC: Number of columns in the matrix

25

www.national.com

14.1.4 KBDDEDCFG - Dedicated Key Register

TABLE 23. KBDDEDCFG - Dedicated Key Register

Register - Name

Address

Type

Register Function

Defines if a key is used as a standard keyboard/GPIO pin or whether

it is used as dedicated key input.

KBDDEDCFG

0x04

R/W

Bit - Name

Bit

Default

Bit Function

Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2.

Bit=0: the dedicated key function applies.

ROW[7:2]

15:10

0x3F

Bit=1: no dedicated key function is selected. The standard GPIO

functionality applies according to register IOCFG or defined keyboard

matrix.

Each bit in COL [11:10] corresponds to ball KPY11 : KPY10.

Bit=0: the dedicated key function applies.

COL[11:10]

COL[9:2]

9:8

7:0

0x03

0xFF

Bit=1: no dedicated key function is selected. The standard GPIO

functionality applies according to register IOCFG or defined keyboard

matrix.

Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be

configured individually.

Bit=0: the dedicated key function applies.

Bit=1: no dedicated key function is selected. The standard GPIO

functionality applies according to register IOCFG or defined keyboard

matrix.

14.1.5 KBDRIS - Keyboard Raw Interrupt Status Register

TABLE 24. KBDRIS - Keyboard Raw Interrupt Status Register

Register - Name

Address

Type

Register Function

KBDRIS

0x06

R

Returns the status of stored keyboard interrupts.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:4

(reserved)

Raw event lost interrupt.

More than 8 keyboard events have been detected and caused the

event buffer to overflow. This bit is cleared by setting bit EVTIC of the

KBDIC register.

RELINT

3

2

0x0

Raw keyboard event interrupt.

At least one key press or key release is in the keyboard event buffer.

Reading from EVTCODE until the buffer is empty will clear this

interrupt.

REVTINT

0x0

Raw key lost interrupt indicates a lost key-code.

This interrupt is asserted when RSINT has not been cleared upon

detection of a new key press or key release, or when more than 4 keys

are pressed simultaneously.

RKLINT

RSINT

1

0

0x0

Raw scan interrupt.

Interrupt generated after keyboard scan, if the keyboard status has

changed.

www.national.com

26

14.1.6 KBDMIS - Keypad Masked Interrupt Status Register

TABLE 25. KBDMIS - Keypad Masked Interrupt Status Register

Register - Name

Address

Type

Register Function

Returns the status on masked keyboard interrupts after masking with

the KBDMSK register.

KBDMIS

0x07

R

Bit - Name

Bit

Default

Bit Functions

(reserved)

7:4

(reserved)

Masked event lost interrupt.

More than 8 keyboard events have been detected and caused the

event buffer to overflow. This bit is cleared by setting bit EVTIC of the

KBDIC register.

MELINT

3

2

0x0

Masked keyboard event interrupt.

At least one key press or key release is in the keyboard event buffer.

Reading from EVTCODE until the buffer is empty will clear this

interrupt.

MEVTINT

0x0

Masked key lost interrupt.

Indicates a lost key-code. This interrupt is asserted when RSINT has

not been cleared upon detection of a new key press or key release,

or when more than 4 keys are pressed simultaneously.

MKLINT

MSINT

1

0

0x0

Masked scan interrupt.

Interrupt generated after keyboard scan, if the keyboard status has

changed, after masking process.

14.1.7 KBDIC - Keypad Interrupt Clear Register

TABLE 26. KBDIC - Keypad Interrupt Clear Register

Register - Name

Address

Default

Register Function

KBDIC

0x08

W

Setting these bits clears Keypad active Interrupts.

Bit - Name

Bit

Default

Bit Function

Switches off scanning of special function (SF) keys, when keyboard

has no special function layout.

SFOFF

7

0: keyboard layout and SF keys are scanned

1: only keyboard layout is scanned, SF keys are not scanned

(reserved)

EVTIC

6:2

1

(reserved)

Clear event buffer and corresponding interrupts REVTINT and

RELINT by writing a 1 to this bit position.

Clear RSINT and RKLINT interrupt bits by writing a 1 to this bit

position.

KBDIC

0

27

www.national.com

14.1.8 KBDMSK - Keypad Interrupt Mask Register

TABLE 27. KBDMSK - Keypad Interrupt Mask Register

Register - Name

Address

Type

Register Function

Configures masking of keyboard interrupts. Masked interrupts do not

trigger an event on the Interrupt output.

In case the interrupt processes registers KBDCODE[3:0], MSKELINT

and MSKEINT should be set to 1. When the Event FIFO is processed,

MSKLINT and MSKSINT should be set. For keyboard polling

operations, all bits should be set and the polling operation consists of

reading out the EVTCODE.

KBDMSK

0x09

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

7:4

(reserved)

0: keyboard event lost interrupt RELINT triggers IRQ line

1: keyboard event lost interrupt RELINT is masked

0: keyboard event interrupt REVINT triggers IRQ line

1: keyboard event interrupt REVINT is masked

0: keyboard lost interrupt RKLINT triggers IRQ line

1: keyboard lost interrupt RKLINT is masked

0: keyboard status interrupt RSINT triggers IRQ line

1: keyboard status interrupt RSINT is masked

MSKELINT

MSKEINT

MSKLINT

MSKSINT

3

2

1

0

0x1

0x0

14.1.9 KBDCODE0 - Keyboard Code Register 0

Please note: Reading out all key code registers (KBDCODE0

to KBDCODE3) will automatically reset the keyboard scan in-

terrupt RSINT the same way as an active write access into bit

KBDIC of the interrupt clear register does. Reading 0x7F from

the KBDCODE0 register means that no key was pressed.

The key code detected by the keyboard scan can be read from

the registers KBDCODE0: KBDCODE3. Up to 4 keys can be

detected simultaneously. Each KBDCODE register includes

a bit (MULTIKEY) indicating if another key has been detected.

TABLE 28. KBDCODE0 - Keyboard Code Register 0

Register - Name

Address

Default

Register Function

KBDCODE0

0x0B

R

Holds the row and column information of the first detected key.

Bit - Name

MULTIKEY

Bit

7

Default

0x0

Bit Function

If this bit is 1 another key is available in KBDCODE1 register.

ROW index of detected key (0 to 7)

KEYROW[2:0]

KEYCOL[3:0]

6:4

3:0

0x7

0xF

Column index of detected (0 to 11, 12 for special function key).

14.1.10 KBDCODE1 - Keyboard Code Register 1

TABLE 29. KBDCODE1 - Keyboard Code Register 1

Register - Name

Address

Default

Register Function

KBDCODE1

0x0C

R

Holds the row and column information of the second detected key.

Bit - Name

MULTIKEY

Bit

7

Default

0x0

Bit Function

If this bit is 1 another key is available in KBDCODE2 register.

ROW index of detected key (0 to 7)

KEYROW[2:0]

KEYCOL[3:0]

6:4

3:0

0x7

0xF

Column index of detected key (0 to 11, 12 for special function key).

www.national.com

28

14.1.11 KBDCODE2 - Keyboard Code Register 2

TABLE 30. KBDCODE2 - Keyboard Code Register 2

Register - Name

Address

Default

Register Function

KBDCODE2

0x0D

R

Holds the row and column information of the third detected key.

Bit - Name

MULTIKEY

Bit

7

Default

0x0

Bit Function

If this bit is 1 another key is available in KBDCODE3 register.

ROW index of detected key (0 to 7)

KEYROW[2:0]

KEYCOL[3:0]

6:4

3:0

0x7

0xF

Column index of detected key (0 to 11, 12 for special function key).

14.1.12 KBDCODE3 - Keyboard Code Register 3

TABLE 31. KBDCODE3 - Keyboard Code Register 3

Register - Name

Address

Default

Register Function

KBDCODE3

0x0E

R

Holds the row and column information of the forth detected key.

Bit - Name

Bit

Default

Bit Function

If this bit is set to “1” then more than 4 keys are pressed

simultaneously.

MULTIKEY

7

0x0

KEYROW[2:0]

KEYCOL[3:0]

6:4

3:0

0x7

0xF

ROW index of detected key (0 to 7)

Column index of detected key (0 to 11, 12 for special function key).

14.1.13 EVTCODE - Key Event Code Register

TABLE 32. EVTCODE - Key Event Code Register

Register - Name

Address

Default

Bit Function

With this register a FIFO buffer is addressed storing up to 15

consecutive events.

Reading the value 0x7F from this address means that the FIFO buffer

is empty. See further details below.

EVTCODE

0x10

R

NOTE: Auto increment is disabled on this register. Multi-byte read will

always read from the same address.

Bit - Name

Bit

Default

Bit Function

This bit indicates, whether the keyboard event was a key press or a

key release event.

0: key was pressed

1: key was released

RELEASE

7

0x0

KEYROW[2:0]

KEYCOL[3:0]

6:4

3:0

0x7

0xF

Row index of key that is pressed or released.

Column index of key that is pressed (0...11, 12 for special function

key) or released.

14.2 PWM TIMER CONTROL REGISTERS

timer control registers are mapped in the range from 0x60 to

0x7F. This paragraph describes the functions of the associ-

ated registers down to the bit level.

The LM8327 provides three host-programmable PWM out-

puts useful for smooth LED brightness modulation. All PWM

14.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers

TABLE 33. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers

Register - Name

TIMCFG0

Address

0x60

Type

Register Function

This register configures interrupt masking and handles PWM start/

stop control of the associated PWM channel.

TIMCFG1

0x68

R/W

TIMCFG2

0x70

Bit - Name

(x = 0, 1 or 2)

Bit

Default

Bit Function

29

www.national.com

Register - Name

CYCIRQxMSK

(reserved)

Address

Type

0x0

Register Function

Interrupt mask for PWM CYCIRQx (see Table 37):

0: interrupt enabled

4

1: interrupt masked

3:0

0x0

(reserved)

14.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers

TABLE 34. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers

Register - Name

PWMCFG0

Address

0x61

Type

Register Function

This register defines interrupt masking and the output behavior for the

associated PWM channel.

PWMCFG1

0x69

R/W

PGEx is used to start and stop the PWM script execution.

PWMENx sets the PWM output to either reflect the generated pattern

or the value configured in PWMPOLx.

PWMCFG2

0x71

Bit - Name

(x = 0, 1 or 2)

Bit

Default

Bit Function

Mask for CDIRQ:

CDIRQxMSK

PGEx

3

0x0

0: CDIRQ enabled

1: CDIRQ disabled/masked

Pattern Generator Enable. Start/Stop PWM command processing for

this channel. Script execution is started always from beginning.

0: Pattern Generator disabled

2

0x0

1: Pattern Generator enabled

0: PWM disabled. PWM timer output assumes value programmed in

PWMPOL.

PWMENx

1

0

0x0

1: PWM enabled

Off-state of PWM output, when PWMEN=0.

0: PWM off-state is low

PWMPOLx

1: PWM off-state is high

14.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers

TABLE 35. TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers

Register - Name

Address

Type

Register Function

The registers determine the divider of the CLKIN external clock. The

resulting clock is only used for PWM generation. The value should

only be changed while PWM is stopped. Since all 3 PWM channels

use the same slow clock, TIMSCAL0 affects all 3 PWM channels.

TIMSCAL1 and TIMSCAL2 are directly linked to TIMSCAL0.

TIMSCAL0

TIMSCAL1

TIMSCAL2

0x62

0x6A

0x72

R/W

Bit - Name

Bit

Default

Bit Function

SCAL[7:0]

7:0

0x0

CLKIN is divided by (SCAL+1).

www.national.com

30

14.2.4 TIMSWRES - PWM Timer Software Reset Registers

TABLE 36. TIMSWRES - PWM Timer Software Reset Registers

Address Type Register Function

Register - Name

Reset control on all PWM timers.

A reset forces the pattern generator to fetch the first pattern and stops

it. Each reset stops all state-machines and timer.

Patterns stored in the pattern configuration register remain unaffected.

Interrupts on each timer are not cleared, they need to be cleared

writing into register TIMIC.

TIMSWRES

0x78

W

Bit - Name

Bit

Default

Bit Function

(reserved)

7:3

Software reset of timer 2.

SWRES2

SWRES1

SWRES0

2

1

0

0: no action

1: Software reset on timer 2, needs not to be written back to 0.

Software reset of timer 1.

0: no action

1: Software reset on timer 1, needs not to be written back to 0.

Software reset of timer 0.

0: no action

1: software reset on timer 0, needs not to be written back to 0.

14.2.5 TIMRIS - PWM Timer Interrupt Status Register

TABLE 37. TIMRIS - PWM Timer Interrupt Status Register

Register - Name

Address

Type

Register Function

This register returns the raw interrupt status from the PMW timers 0,

1 and 2.

CYCIRQx - Interrupt from the timers when PWM cycle is complete

(applies to the current PWM command residing in the active command

register of a PWM block).

TIMRIS

0x7A

R

CDIRQx - Interrupt from the pattern generator when PWM pattern

code is complete (applies to a completed task residing in the script

buffer of a PWM block).

Bit - Name

Bit

Default

0x0

Bit Functions

(reserved)

7:6

Raw interrupt status for CDIRQ timer2:

0: no interrupt pending

CDIRQ2

CDIRQ1

CDIRQ0

CYCIRQ2

CYCIRQ1

5

4

3

2

1

1: unmasked interrupt generated

Raw interrupt status for CDIRQ timer1:

0: no interrupt pending

0x0

1: unmasked interrupt generated

Raw interrupt status for CDIRQ timer0:

0: no interrupt pending

0x0

1: unmasked interrupt generated

Raw interrupt status for CYCIRQ timer2:

0: no interrupt pending

0x0

1: unmasked interrupt generated

Raw interrupt status for CYCIRQ timer1:

0: no interrupt pending

0x0

1: unmasked interrupt generated

31

www.national.com

Register - Name

Address

Type

Register Function

Raw interrupt status for CYCIRQ timer0:

0: no interrupt pending

CYCIRQ0

0

0x0

1: unmasked interrupt generated

14.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register

TABLE 38. TIMMIS - PWM Timer Masked Interrupt Status Register

Register - Name

Address

Type

Register Function

This register returns the masked interrupt status from the PMW timers

0,1 and 2. The raw interrupt status (TIMRIS) is masked with the

associated TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK

bits to get the masked interrupt status of this register.

CYCIRQ - Interrupt from the timers when PWM cycle is complete

(applies to the current PWM command residing in the active command

register of a PWM block).

TIMMIS

0x7B

R

CDIRQ - Interrupt from the pattern generator when PWM pattern code

is complete (applies to a completed task residing in the script buffer

of a PWM block).

Bit - Name

Bit

Default

Bit Function

(reserved)

7:6

(reserved)

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CDIRQ timer2:

0: no interrupt pending

CDIRQ2

CDIRQ1

5

4

3

2

1

0

0x0

1: interrupt generated

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CDIRQ timer1:

0: no interrupt pending

0x0

1: interrupt generated

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CDIRQ timer0:

0: no interrupt pending

CDIRQ0

1: interrupt generated

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CYCIRQ timer2:

0: no interrupt pending

CYCIRQ2

CYCIRQ1

CYCIRQ0

1: interrupt generated

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CYCIRQ timer1:

0: no interrupt pending

1: interrupt generated

Interrupt after masking, indicates active contribution to the interrupt

ball, when set. Status for CYCIRQ timer0:

0: no interrupt pending

1: interrupt generated

www.national.com

32

14.2.7 TIMIC - PWM Timer Interrupt Clear Register

TABLE 39. TIMIC - PWM Timer Interrupt Clear Register

Register - Name

Address

Type

Register Function

This register clears timer and pattern interrupts.

CYCIRQ - Interrupt from the timers when PWM cycle is complete

(applies to the current PWM command residing in the active command

register of a PWM block).

TIMIC

0x7C

W

CDIRQ - Interrupt from the pattern generator when PWM pattern code

is complete (applies to a completed task residing in the script buffer

of a PWM block).

Bit - Name

Bit

Default

Bit Function

(reserved)

7:6

Clears interrupt CDIRQ timer2:

0: no effect

CDIRQ2

CDIRQ1

5

4

3

2

1

0

1: interrupt is cleared. Does not need to be written back to 0

Clears interrupt CDIRQ timer1:

0: no effect

1: interrupt is cleared. Does not need to be written back to 0

Clears interrupt CDIRQ timer0:

0: no effect

CDIRQ0

1: interrupt is cleared. Does not need to be written back to 0

Clears interrupt CYCIRQ timer2:

0: no effect

CYCIRQ2

CYCIRQ1

CYCIRQ0

1: interrupt is cleared. Does not need to be written back to 0

Clears interrupt CYCIRQ timer1:

0: no effect

1: interrupt is cleared. Does not need to be written back to 0

Clears interrupt CYCIRQ timer0:

0: no effect

1: interrupt is cleared. Does not need to be written back to 0

14.2.8 PWMWP - PWM Timer Pattern Pointer Register

TABLE 40. PWMWP - PWM Timer Pattern Pointer Register

Register - Name

Address

Type

Register Function

Pointer to the pattern position inside the configuration register, which

will be overwritten by the next write access to be PWMCFG register.

NOTE: 1 pattern consist of 2 bytes and not the byte position (low or

high). It is incremented by 1 every time a full PWMCFG register access

(word) is performed.

PWMWP

0x7D

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

7

0x0

(reserved)

0 ≤ POINTER < 32 : timer0 patterns 0 to 31

32 ≤ POINTER < 64 : timer1 patterns 0 to 31

64 ≤ POINTER < 96 : timer2 patterns 0 to 31

96 ≤ POINTER < 128: not valid

POINTER[6:0]

6:0

0x0

33

www.national.com

14.2.9 PWMCFG - PWM Script Register (Two Byte)

TABLE 41. PWMCFG - PWM Script Register

Register - Name

Address

Type

Register Function

Two byte pattern storage register for a PWM script command indexed

by PWMWP. PWMWP is automatically incremented.

To be applied by two consecutive parameter bytes in one I²C Write

Transaction.

PWMCFG

0x7E

W

NOTE: Autoincrement is disabled on this register. Address will stay

at 0x7E for each word access.

Bit - Name

CMD[15:8]

CMD[7:0]

Bit

15:8

7:0

Default

Bit Function

High byte portion of a PWM script command.

Low byte portion of a PWM script command.

www.national.com

34

14.3 INTERFACE CONTROL REGISTERS

NOTE: I2CSA and MFGCODE use the same address. They

just differentiate in the access type:

The following section describes the functions of special con-

trol registers provided for the main controller.

•

Write - I2CSA

Read - MFGCODE

The manufacturer code MFGCODE and the software revision

number SWREV tell the main device which configuration file

has to be used for this device.

14.3.1 I2CSA - I²C-Compatible ACCESS.bus Slave Address Register

TABLE 42. I2CSA - I²C-Compatible ACCESS.bus Slave Address Register

Register - Name

Address

Type

Register Function

I²C-compatible ACCESS.bus Slave Address.

The address is internally applied after the next I²C STOP.

I2CSA

0x80

W

Bit - Name

SLAVEADDR[7:1]

(reserved)

Bit

7:1

0

Default

Bit Function

7-bit address field for the I²C-compatible ACCESS.bus slave address.

(reserved)

0x45

14.3.2 MFGCODE - Manufacturer Code Register

TABLE 43. MFGCODE - Manufacturer Code Register

Register - Name

Address

Type

Register Function

Manufacturer code of the LM8327.

MFGCODE

0x80

R

Bit - Name

Bit

Default

Bit Function

MFGBIT

7:0

0x00

8-bit field containing the manufacturer code.

14.3.3 SWREV - Software Revision Register

TABLE 44. SWREV - Software Revision Register

Register - Name

Address

Type

Register Function

Software revision code of the LM8327.

NOTE: Writing the SW revision with the inverted value triggers a reset

(see SWRESET).

SWREV

0x81

R

Bit - Name

Bit

Default

Bit Function

SWBIT

7:0

0xC4

8-bit field containing the SW Revision number.

14.3.4 SWRESET - Software Reset

TABLE 45. SWRESET - Software Reset Register

Register - Name

Address

Type

Register Function

Software reset.

NOTE: the reset is only applied if the supplied parameter has the

inverted value as SWBIT.

SWRESET

0x81

W

Reading this register provides the software revision (see Table 44).

Bit - Name

Bit

Default

Bit Function

SWBIT

7:0

Reapply inverted value for software reset.

14.3.5 RSTCTRL - System Reset Register

set). This will reset the slave address back to 0x8A. During

an active reset of a module, the LM8327 blocks the access to

the module registers. A read will return 0, write commands

are ignored.

This register allows to reset specific blocks of the LM8327.

For global reset of the I/OExpander the I²C command 'Gen-

eral Call reset' is used (see Section 10.1.6 Global Call Re-

35

www.national.com

TABLE 46. RSTCTRL - System Reset Register

Register - Name

Address

Type

Register Function

RSTCTRL

0x82

R/W

Software reset of specific parts of the LM8327.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:5

(reserved)

Interrupt controller reset. Does not change status on IRQN ball. Only

controls IRQ module register. Interrupt status read out is not possible

when this bit is set.

IRQRST

4

0x0

0: interrupt controller not reset

1: interrupt controller reset

Timer reset for Timers 0, 1, 2:

0: timer not reset

TIMRST

(reserved)

KBDRST

3

2

1

0x0

1: timer is reset

(reserved)

Keyboard interface reset:

0: keyboard is not reset

1: keyboard is reset

GENIO reset:

GPIRST

0

0x0

0: GENIO not reset

1: GENIO is reset.

14.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register

TABLE 47. RSTINTCLR - Clear NO Init/Power-On Interrupt Register

Register - Name

Address

Type

Register Function

This register allows to de-assert the POR/No Init Interrupt set every

time the device returns from RESET (either POR, HW or SW Reset),

the IRQN line is assigned active (low) and the IRQST.PORIRQ bit is

set.

RSTINTCLR

0x84

W

Bit - Name

Bit

Default

Bit Function

reserved

7:1

(reserved)

1: Clears the PORIRQ Interrupt signalled in IRQST register.

0: is ignored

IRQCLR

0

14.3.7 CLKMODE - Clock Mode Register

TABLE 48. CLKMODE - Clock Mode Register

Register - Name

Address

Type

Register Function

This register controls the current operating mode of the LM8327

device.

CLKMODE

0x88

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

7:2

(reserved)

Writing to 00 forces the device to immediately enter sleep mode,

regardless of any autosleep configuration. Reading this bit returns the

current operating mode, which should always be 01.

00: SLEEP Mode

MODCTL[1:0]

1:0

0x01

01: Operation Mode

1x: Future modes

www.national.com

36

14.3.8 CLKCFG - Clock Configuration Register

TABLE 49. CLKCFG - Clock Configuration Register

Register - Name

Address

Type

Register Function

Configures clock sources and power options of the device.

NOTE: Don't change while a PWM script is in progress.

CLKCFG

0x89

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

7

0x0

(reserved)

00: (reserved)

CLKSRCSEL[1:0]

(reserved)

6:5

4:0

0x2

0x0

01: use externally generated clock from CLKIN pin as PWM slow clock

1x: use internally generated PWM slow clock

(reserved)

14.3.9 CLKEN - Clock Enable Register

TABLE 50. CLKEN - Clock Enable Register

Register - Name

Address

Type

Register Function

Controls the clock to different functional units. It shall be used to

enable the functional blocks globally and independently.

CLKEN

0x8A

R/W

Bit - Name

Bit

Default

Bit Function

CLKOUT clock output enable:

00: CLKOUT clock disabled. Fixed to low level.

01: CLKOUT frequency = PWM slow clock frequency.

10: reserved

CLKOUTEN

7:6

0x0

11: reserved

(reserved)

TIMEN

5:3

2

(reserved)

PWM Timer 0, 1, 2 clock enable:

0: Timer 0, 1, 2 clock disabled

1: Timer 0, 1, 2 clock enabled.

0x0

Direct Key clock enable (starts/stops direct key scan):

0: Direct Key clock disabled

1: Direct Key clock enabled

DKBDEN*

KBDEN*

1

0

Keyboard clock enable (starts/stops key scan):

0: Keyboard clock disabled

1: Keyboard clock enabled

*Note: Only one of KBDEN or DKBDEN of CLKEN register can be set at a time, since Direct Key functions cannot be used at the same time as Keypad (Matrix).

Setting both bits to 1 at the same time will enable only Direct Key.

14.3.10 AUTOSLP - Autosleep Enable Register

TABLE 51. AUTOSLP - Autosleep Enable Register

Register - Name

Address

Type

Register Function

AUTOSLP

0x8B

R/W

This register controls the Auto Sleep function of the LM8327 device.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:1

(reserved)

Enables automatic sleep mode after a defined activity time stored in

the AUTOSLPTI register:

ENABLE

0

0x00

1: Enable entering auto sleep mode

0: Disable entering auto sleep mode

37

www.national.com

14.3.11 AUTOSLPTI - Auto Sleep Time Register

TABLE 52. AUTOSLPTI - Auto Sleep Time Register

Register - Name

Address

Type

Register Function

This register defines the activity time. If this time passes without any

processing events then the device enters into sleep-mode, but only if

AUTOSLP.ENABLE bit is set to 1.

AUTOSLPTIL

AUTOSLPTIH

0x8C

0x8D

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

15:11

(reserved)

Values of UPTIME[10:0] match to multiples of 4ms:

0x00: no autosleep, regardless if AUTOSLP.ENABLE is set

0x01: 4ms

UPTIME[10:8]

UPTIME[7:0]

10:8

7:0

0x00

0xFF

0x02: 8ms

0x7A: 500 ms

0xFF: 1020 ms (default after reset)

0x100: 1024 ms

0x7FF: 8188 ms

14.3.12 IRQST - Global Interrupt Status Register

TABLE 53. IRQST - Global Interrupt Status Register

Register - Name

Address

Type

Register Function

Returns the interrupt status from various on-chip function blocks. If

any of the bits is set and an IRQN line is configured, the IRQN line is

asserted active

IRQST

0x91

R

Bit - Name

Bit

Default

Bit Function

Supply failure on VCC.

Also power-on is considered as an initial supply failure. Therefore,

after power-on, the bit is set.

PORIRQ

7

0x1

0: no failure recorded

1: Failure, device was completely reset and requires re-programming.

Keyboard interrupt (further key selection in keyboard module):

KBDIRQ

6

0x0

0: inactive

1: active

Direct key interrupt (further key selection in direct key module):

0: inactive

1: active

DKBDIRQ

(reserved)

TIM2IRQ

5

4

3

(reserved)

Timer2 expiry (CDIRQ or CYCIRQ):

0x0

0: inactive

1: active

Timer1 expiry (CDIRQ or CYCIRQ):

TIM1IRQ

TIM0IRQ

GPIOIRQ

2

1

0

0: inactive

1: active

Timer0 expiry (CDIRQ or CYCIRQ):

0: inactive

1: active

GPIO interrupt (further selection in GPIO module):

0: inactive

1: active

www.national.com

38

14.4 GPIO FEATURE CONFIGURATION

14.4.1 GPIO Feature Mapping

direct key, keypad, GPIO or PWM usage is defined by the

following registers:

•

DIRECTn

The LM8327 has a flexible I/O structure which allows user to

dynamically assign different functionality to each ball. The

functionality of each ball is determined by the complete con-

figuration of the balls.

This register defines a ball as a direct key.

—

•

KBDSIZE and KBDDEDCFG

Both registers define a ball as either part of the keypad

matrix or as dedicated key input. These settings have

highest priority and will overwrite settings made in other

registers.

—

In general the following priority is given:

•

Direct Key

Keypad

GPIO

•

IOCFG

This register is used to define the usage of PWM[2:0]

and EXTIO if not configured to be part of the keymatrix,

to be used as GPIO.

—

PWM

With this, each ball will be available as keypad, GPIO, or PWM

unless it is specified to be a direct key. The configuration for

TABLE 54. Ball Configuration Options

BALL

Module connectivity

GPIOSEL

BALLCFG

0x3

0x0

GPIO[7:0]

GPIO[15:8]

GPIO16

GPIO17

GPIO18

GPIO19

PWM0

0x1

0x2

0x4

0x5

0x6

KPX[7:0]

KPY[7:0]

KPY8

not used

GPIO20

GPIO21

GPIO22

GPIO23

-

KPY9

KPY10

KPY11

PWM0

PWM1

PWM2

EXTIO

PWM1

PWM2

-

14.4.2 IOCGF - Input/Output Pin Mapping Configuration Register

TABLE 55. IOCGF - Input/Output Pin Mapping Configuration Register

Register - Name

Address

Type

Register Function

Configures usage of PWM[2:0] and EXTIO if not used as primary

function.

IOCFG

0xA7

W

Bit - Name

GPIOSEL

(reserved)

BALLCFG

Bit

7:4

3

Default

Bit Function

TBD

(reserved)

2:0

Select column to configure, see Table 54

39

www.national.com

14.4.3 IOPC0 - Pull Resistor Configuration Register 0

TABLE 56. IOPC0 - Pull Resistor Configuration Register 0

Address Type Register Function

Register - Name

IOPC0*

OxAA

R/W

Defines the pull resistor configuration for balls KPX[7:0].

Bit - Name

Bit

Default

Bit Function

Resistor enable for KPX7 ball:

00: no pull resistor at ball

KPX7PR[1:0]

15:14

13:12

11:10

9:8

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX6 ball:

00: no pull resistor at ball

KPX6PR[1:0]

KPX5PR[1:0]

KPX4PR[1:0]

KPX3PR[1:0]

KPX2PR[1:0]

KPX1PR[1:0]

KPX0PR[1:0]

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX5 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX4 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX3 ball:

00: no pull resistor at ball

7:6

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX2 ball:

00: no pull resistor at ball

5:4

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX1 ball:

00: no pull resistor at ball

3:2

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPX0 ball:

00: no pull resistor at ball

1:0

01: pull down resistor programmed

1x: pull up resistor programmed

* Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.4 IOPC1 - Pull Resistor Configuration Register 1

TABLE 57. IOPC1 - Pull Resistor Configuration Register 1

Register - Name

Address

Type

Register Function

IOPC1**

0xAC

R/W

Defines the pull resistor configuration for balls KPY[7:0].

Bit - Name

Bit

Default

Bit Function

Resistor enable for KPY7 ball:

00: no pull resistor at ball

KPY7PR[1:0]

15:14

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

www.national.com

40

Register - Name

Address

Type

Register Function

Resistor enable for KPY6 ball:

00: no pull resistor at ball

KPY6PR[1:0]

13:12

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY5 ball:

00: no pull resistor at ball

KPY5PR[1:0]

KPY4PR[1:0]

KPY3PR[1:0]

KPY2PR[1:0]

KPY1PR[1:0]

KPY0PR[1:0]

11:10

9:8

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY4 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY3 ball:

00: no pull resistor at ball

7:6

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY2 ball:

00: no pull resistor at ball

5:4

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY1 ball:

00: no pull resistor at ball

3:2

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY0 ball:

00: no pull resistor at ball

1:0

01: pull down resistor programmed

1x: pull up resistor programmed

** Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.5 IOPC2 - Pull Resistor Configuration Register 2

TABLE 58. IOPC2 - Pull Resistor Configuration Register 2

Register - Name

Address

Type

Register Function

Defines the pull resistor configuration for balls KPY[11:8], PWM[2:0],

EXTIO.

IOPC2***

0xAE

R/W

Bit - Name

Bit

Default

Bit Function

Resistor enable for EXTIO ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

EXTIO[1:0]

15:14

0x3

Resistor enable for PWM2 ball:

00: no pull resistor at ball

PWM2[1:0]

PWM1[1:0]

13:12

11:10

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for PWM1 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

41

www.national.com

Register - Name

Address

Type

Register Function

Resistor enable for PWM0 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

PWM0[1:0]

9:8

0x3

Resistor enable for KPY11 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

KPY11PR[1:0]

KPY10PR[1:0]

7:6

5:4

0x3

Resistor enable for KPY10 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY9 ball:

00: no pull resistor at ball

KPY9PR[1:0]

KPY8PR[1:0]

3:2

1:0

0x3

01: pull down resistor programmed

1x: pull up resistor programmed

Resistor enable for KPY8 ball:

00: no pull resistor at ball

01: pull down resistor programmed

1x: pull up resistor programmed

*** Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0

TABLE 59. GPIOOME0 - GPIO Open Drain Mode Enable Register 0

Register - Name

Address

Type

Register Function

Configures KPX[7:0] for Open Drain or standard output functionality.

The Open Drain drive source is configured by GPIOOMS0.

GPIOOME0

0xE0

R/W

Bit - Name

Bit

Default

Bit Function

Open Drain Enable on KPX[7:0]:

0: full buffer

KPX[7:0]ODE

7:0

0x0

1: open drain functionality

14.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0

TABLE 60. GPIOOMS0 - GPIO Open Drain Mode Select Register 0

Register - Name

Address

Type

Register Function

Configures the Open Drain drive source on KPX[7:0] if selected by

GPIOOME0.

GPIOOMS0

0xE1

R/W

Bit - Name

Bit

Default

Bit Function

0: Only NMOS transistor is active in output driver stage. Output can

be driven to gnd or Hi-Z.

KPX[7:0]ODM

7:0

0x0

1: Only PMOS transistor is active in output driver stage. Output can

be driven to VCC or Hi-Z.

www.national.com

42

14.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1

TABLE 61. GPIOOME1 - GPIO Open Drain Mode Enable Register 1

Register - Name

Address

Type

Register Function

Configures KPY[7:0] for Open Drain or standard output functionality.

The Open Drain drive source is configured by GPIOOMS1.

GPIOOME1

0xE2

R/W

Bit - Name

Bit

Default

Bit Function

Open Drain Enable on KPY[7:0]:

0: full buffer

KPY[7:0]ODE

7:0

0x0

1: open drain functionality

14.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1

TABLE 62. GPIOOMS1 - GPIO Open Drain Mode Select Register 1

Register - Name

Address

Type

Register Function

Configures the Open Drain drive source on KPY[7:0] if selected by

GPIOOME1.

GPIOOMS1

0xE3

R/W

Bit - Name

Bit

Default

Bit Function

0: Only NMOS transistor is active in output driver stage. Output can

be driven to GND or Hi-Z.

KPY[7:0]ODM

7:0

0x0

1: Only PMOS transistor is active in output driver stage. Output can

be driven to VCC or Hi-Z.

14.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2

TABLE 63. GPIOOME2 - GPIO Open Drain Mode Enable Register 2

Register - Name

Address

Type

Register Function

Configures KPY[11:8], PWM[2:0], EXTIO for Open Drain or standard

output functionality. The Open Drain drive source is configured by

GPIOOMS2.

GPIOOME2

0xE4

R/W

Bit - Name

Bit

Default

Bit Function

Open Drain Enable on EXTIO:

0: full buffer

EXTIOODM

7

0x0

1: open drain functionality

Open Drain Enable on PWM[2:0]:

0: full buffer

1: open drain functionality

PWM[2:0]ODM

KPY[11:8]ODE

6:4

3:0

0x0

Open Drain Enable on KPY[11:8]:

0: full buffer

1: open drain functionality

43

www.national.com

14.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2

TABLE 64. GPIOOMS2 - GPIO Open Drain Mode Select Register 2

Register - Name

Address

Type

Register Function

Configures the Open Drain drive source on KPY[11:8], PWM[2:],

EXTIO if selected by GPIOOME2.

GPIOOMS2

0xE5

R/W

Bit - Name

Bit

Default

Bit Function

0: only NMOS transistor is active in output driver stage. Output can be

driven to GND or Hi-Z.

1: only PMOS transistor is active in output driver stage. Output can be

driven to GND or Hi-Z.

EXTIOODM

7

0x0

PWM[2:0]ODM

KPY[11:8]ODM

6:4

3:0

0x0

same as above

14.5 GPIO DATA INPUT/OUTPUT

30124211

14.5.1 GPIOPDATA0 - GPIO Data Register 0

TABLE 65. GPIOPDATA0 - GPIO Data Register 0

Register - Name

Address

Type

Register Function

This register is used for data input/output of KPX[7:0]. Every data I/O is

masked with the associated MASK register.

If one of the I/Os is defined as output (see Table 68) values written to this

register are masked with MASK and then applied to the associated pin.

If one of the I/Os is defined as input (see Table 68) values read from this

register hold the masked input value of the associated pin.

GPIODATA0

0xC0

R/W

Bit - Name

Bit

Default

Bit Function

Mask Status for KPX7 when enabled as GPIO:

1: KPX7 enabled

MASK7

15

0x0

0: KPX7 disabled

Mask Status for KPX6 when enabled as GPIO:

1: KPX6 enabled

MASK6

MASK5

MASK4

MASK3

14

13

12

11

0x0

0: KPX6 disabled

Mask Status for KPX5 when enabled as GPIO:

1: KPX5 enabled

0: KPX5 disabled

Mask Status for KPX4 when enabled as GPIO:

1: KPX4 enabled

0: KPX4 disabled

Mask Status for KPX3 when enabled as GPIO:

1: KPX3 enabled

0: KPX3 disabled

www.national.com

44

Register - Name

Address

Type

Register Function

Mask Status for KPX2 when enabled as GPIO:

1: KPX2 enabled

MASK2

10

0x0

0: KPX2 disabled

Mask Status for KPX1 when enabled as GPIO:

1: KPX1 enabled

MASK1

MASK0

9

8

0x0

0: KPX1 disabled

Mask Status for KPX0 when enabled as GPIO:

1: KPX0 enabled

0: KPX0 disabled

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

7

6

5

4

3

2

1

0

0x0

Pin Status for KPX7 when enabled as GPIO.

Pin Status for KPX6 when enabled as GPIO.

Pin Status for KPX5 when enabled as GPIO.

Pin Status for KPX4 when enabled as GPIO.

Pin Status for KPX3 when enabled as GPIO.

Pin Status for KPX2 when enabled as GPIO.

Pin Status for KPX1 when enabled as GPIO.

Pin Status for KPX0 when enabled as GPIO.

14.5.2 GPIOPDATA1 - GPIO Data Register 1

TABLE 66. GPIOPDATA1 - GPIO Data Register 1

Register - Name

Address

Type

Register Function

This register is used for data input/output of KPY[7:0]. Every data I/O is

masked with the associated MASK register.

If one of the I/Os is defined as output (see Table 69) values written to this

register are masked with MASK and then applied to the associated pin.

If one of the I/Os is defined as input (see Table 69) values read from this

register hold the masked input value of the associated pin.

GPIODATA1

0xC2

R/W

Bit - Name

Bit

Default

Bit Function

Mask Status for KPY7 when enabled as GPIO:

1: KPY7 enabled

MASK15

15

0x0

0: KPY7 disabled

Mask Status for KPY6 when enabled as GPIO:

1: KPY6 enabled

MASK14

MASK13

MASK12

MASK11

MASK10

MASK9

14

13

12

11

10

9

0x0

0: KPY6 disabled

Mask Status for KPY5 when enabled as GPIO:

1: KPY5 enabled

0: KPY5 disabled

Mask Status for KPY4 when enabled as GPIO:

1: KPY4 enabled

0: KPY4 disabled

Mask Status for KPY3 when enabled as GPIO:

1: KPY3 enabled

0: KPY3 disabled

Mask Status for KPY2 when enabled as GPIO:

1: KPY2 enabled

0: KPY2 disabled

Mask Status for KPY1 when enabled as GPIO:

1: KPY1 enabled

0: KPY1 disabled

45

www.national.com

Register - Name

Address

Type

Register Function

Mask Status for KPY0 when enabled as GPIO:

1: KPY0 enabled

MASK8

8

0x0

0: KPY0 disabled

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

7

6

5

4

3

2

1

0

0x0

Pin Status for KPY7 when enabled as GPIO.

Pin Status for KPY6 when enabled as GPIO.

Pin Status for KPY5 when enabled as GPIO.

Pin Status for KPY4 when enabled as GPIO.

Pin Status for KPY3 when enabled as GPIO.

Pin Status for KPY2 when enabled as GPIO.

Pin Status for KPY1 when enabled as GPIO.

Pin Status for KPY0 when enabled as GPIO.

DATA8

14.5.3 GPIOPDATA2 - GPIO Data Register 2

TABLE 67. GPIOPDATA2 - GPIO Data Register 2

Register - Name

Address

Type

Register Function

This register is used for data input/output of KPY[11:8], PWM[2:0],

EXTIO. Every data I/O is masked with the associated MASK register.

If one of the I/Os is defined as output (see Table 70) values written to this

register are masked with MASK and then applied to the associated pin.

If one of the I/Os is defined as input (see Table 70) values read from this

register hold the masked input value of the associated pin.

GPIODATA2

0xC4

R/W

Bit - Name

Bit

Default

Bit Function

Mask Status for EXTIO when enabled as GPIO:

1: EXTIO enabled

MASK23

15

0x0

0: EXTIO disabled

Mask Status for PWM2 when enabled as GPIO:

1: PWM2 enabled

0: PWM2 disabled

MASK22

MASK21

MASK20

MASK19

14

13

12

11

0x0

Mask Status for PWM1 when enabled as GPIO:

1: PWM1 enabled

0: PWM1 disabled

Mask Status for PWM0 when enabled as GPIO:

1: PWM0 enabled

0: PWM0 disabled

Mask Status for KPY11 when enabled as GPIO:

1: KPY11 enabled

0: KPY11 disabled

Mask Status for KPY10 when enabled as GPIO:

1: KPY10 enabled

MASK18

MASK17

MASK16

10

9

0x0

0: KPY10 disabled

Mask Status for KPY9 when enabled as GPIO:

1: KPY9 enabled

0: KPY9 disabled

Mask Status for KPY8 when enabled as GPIO:

1: KPY8 enabled

8

0: KPY8 disabled

DATA23

DATA22

DATA21

DATA20

7

6

5

4

0x0

Pin Status for EXTIO when enabled as GPIO.

Pin Status for PWM2 when enabled as GPIO.

Pin Status for PWM1 when enabled as GPIO.

Pin Status for PWM0 when enabled as GPIO.

www.national.com

46

Register - Name

DATA19

Address

Type

0x0

Register Function

3

2

1

0

Pin Status for KPY11 when enabled as GPIO

Pin Status for KPY10 when enabled as GPIO.

Pin Status for KPY9 when enabled as GPIO.

Pin Status for KPY8 when enabled as GPIO.

DATA18

DATA17

DATA16

14.5.4 GPIOPDIR0 - GPIO Port Direction Register 0

TABLE 68. GPIOPDIR0 - GPIO Port Direction Register 0

Register - Name

Address

Type

Register Function

GPIODIR0

0xC6

R/W

Port direction for KPX[7:0].

Bit - Name

Bit

Default

Bit Function

Direction bits for KPX[7:0]:

0: input mode

KPX[7:0]DIR

7:0

0x00

1: output mode

14.5.5 GPIOPDIR1 - GPIO Port Direction Register 1

TABLE 69. GPIOPDIR1 - GPIO Port Direction Register 1

Register - Name

Address

Type

Register Function

GPIODIR1

0xC7

R/W

Port direction for KPY[7:0].

Bit - Name

Bit

Default

Bit Function

Direction bits for KPY[7:0]:

0: input mode

KPY[7:0]DIR

7:0

0x00

1: output mode

14.5.6 GPIOPDIR2 - GPIO Port Direction Register 2

TABLE 70. GPIOPDIR2 - GPIO Port Direction Register 2

Register - Name

Address

Type

Register Function

GPIODIR2

0xC8

R/W

Port direction for KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Direction bits for EXTIO:

0: input mode

EXTIODIR

7

0x0

1: output mode

Direction bits for PWM[2:0:]:

0: input mode

1: output mode

PWM[2:0]DIR

KPY[11:8]DIR

6:4

3:0

0x0

Direction bits for KPY[11:8]:

0: input mode

0x00

1: output mode

47

www.national.com

14.6 GPIO INTERRUPT CONTROL

14.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0

TABLE 71. GPIOIS0 - Interrupt Sense Configuration Register 0

Address Type Register Function

0xC9 R/W Interrupt type on KPX[7:0].

Register - Name

GPIOIS0

Bit - Name

Bit

Default

Bit Function

Interrupt type bits for KPX[7:0]:

KPX[7:0]IS

7:0

0x0

0: edge sensitive interrupt

1: level sensitive interrupt

14.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1

TABLE 72. GPIOIS1 - Interrupt Sense Configuration Register 1

Address Type Register Function

0xCA R/W Interrupt type on KPY[7:0].

Register - Name

GPIOIS1

Bit - Name

Bit

Default

Bit Function

Interrupt type bits for KPY[7:0]:

KPY[7:0]IS

7:0

0x0

0: edge sensitive interrupt

1: level sensitive interrupt

14.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2

TABLE 73. GPIOIS2 - Interrupt Sense Configuration Register 2

Address Type Register Function

0xCB R/W Interrupt type on KPY[11:8], PWM[2:0], EXTIO.

Register - Name

GPIOIS2

Bit - Name

Bit

Default

Bit Function

Interrupt type bits for EXTIO:

EXTIOIS

7

0x0

0: edge sensitive interrupt

1: level sensitive interrupt

Interrupt type bits for PWM[2:0:]:

0: edge sensitive interrupt

1: level sensitive interrupt

PWM[2:0]IS

KPY[11:8]IS

6:4

3:0

0x0

Interrupt type bits for KPY[11:8]:

0: edge sensitive interrupt

1: level sensitive interrupt

14.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0

TABLE 74. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0

Register - Name

Address

Type

Register Function

Defines whether an interrupt on KPX[7:0] is triggered on both edges

or on a single edge. See Table 77 for the edge configuration.

GPIOIBE0

0xCC

R/W

Bit - Name

Bit

Default

Bit Function

Interrupt both edges bits for KPX[7:0]:

0: interrupt generated at the active edge

1: interrupt generated after both edges

KPX[7:0]IBE

7:0

0x0

www.national.com

48

14.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1

TABLE 75. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1

Register - Name

Address

Type

Register Function

Defines whether an interrupt on KPY[7:0] is triggered on both edges

or on a single edge. See Table 78 for the edge configuration.

GPIOIBE1

0xCD

R/W

Bit - Name

Bit

Default

Bit Function

Interrupt both edges bits for KPY[7:0]:

0: interrupt generated at the configured edge

1: interrupt generated after both edges

KPY[7:0]IBE

7:0

0x0

14.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

TABLE 76. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

Register - Name

Address

Type

Register Function

Defines whether an interrupt on KPY[11:8], PWM[2:0], EXTIO is

triggered on both edges or on a single edge. See Table 79 for the edge

configuration.

GPIOIBE2

0xCE

R/W

Bit - Name

Bit

Default

Bit Function

Interrupt both edges bits for EXTIO:

0: interrupt generated at the active edge

1: interrupt generated after both edges

EXTIOIBE

7

0x0

Interrupt both edges bits for PWM[2:0:]:

0: interrupt generated at the active edge

1: interrupt generated after both edges

PWM[2:0]IBE

KPY[11:8]IBE

6:4

3:0

0x0

Interrupt both edges bits for KPY[11:8]:

0: interrupt generated at the active edge

1: interrupt generated after both edges

14.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0

TABLE 77. GPIOIEV0 - GPIO Interrupt Edge Select Register 0

Register - Name

Address

Type

Register Function

GPIOIEV0

0xCF

R/W

Select Interrupt edge for KPX[7:0].

Bit - Name

Bit

Default

Bit Function

Interrupt edge select from KPX[7:0]:

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

KPX[7:0]EV

7:0

0x0

14.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1

TABLE 78. GPIOIEV1 - GPIO Interrupt Edge Select Register 1

Register - Name

Address

Type

Register Function

GPIOIEV1

0xD0

R/W

Select Interrupt edge for KPY[7:0].

Bit - Name

Bit

Default

Bit Function

Interrupt edge select from KPY[7:0]:

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

KPY[7:0]EV

7:0

0x0

49

www.national.com

14.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2

TABLE 79. GPIOIEV2 - GPIO Interrupt Edge Select Register 2

Register - Name

Address

Type

Register Function

GPIOIEV2

0xD1

R/W

Select Interrupt edge for KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Interrupt edge select from EXTIO:

0: interrupt at low level or failig edge

1: interrupt at high level or rising edge

EXTIOEV

7

0x0

Interrupt edge select from PWM[2:0:]:

0: interrupt at low level or failig edge

1: interrupt at high level or rising edge

PWM[2:0]EV

KPY[11:8]EV

6:4

3:0

0x0

Interrupt edge select from KPY[11:8]:

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

14.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0

TABLE 80. GPIOIE0 - GPIO Interrupt Enable Register 0

Register - Name

Address

Type

Register Function

Enable/disable interrupts on KPX[7:0].

GPIOIE0

0xD2

R/W

Bit - Name

Bit

Default

Bit Function

Interrupt enable on KPX[7:0]:

KPX[7:0]IE

7:0

0x0

0: disable interrupt

1: enable interrupt

14.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1

TABLE 81. GPIOIE1 - GPIO Interrupt Enable Register 1

Register - Name

Address

Type

Register Function

GPIOIE1

0xD3

R/W

Enable/disable interrupts on KPY[7:0]

Bit - Name

Bit

Default

Bit Function

Interrupt enable on KPY[7:0]:

0: disable interrupt

KPY[7:0]IE

7:0

0x0

1: enable interrupt

14.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2

TABLE 82. GPIOIE2 - GPIO Interrupt Enable Register 2

Register - Name

Address

Type

Register Function

GPIOIE2

0xD4

R/W

Enable/disable interrupts on KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Interrupt enable on EXTIO:

0: disable interrupt

EXTIOIE

7

0x0

1: enable interrupt

Interrupt enable on PWM[2:0:]:

0: disable interrupt

PWM[2:0]IE

6:4

0x0

1: enable interrupt

www.national.com

50

Register - Name

Address

Type

Register Function

Interrupt enable on KPY[11:8]:

KPY[11:8]IE

3:0

0x0

0: disable interrupt

1: enable interrupt

14.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0

TABLE 83. GPIOIC0 - GPIO Clear Interrupt Register 0

Register - Name

Address

Type

Register Function

GPIOIC0

0xDC

W

Clears the interrupt on KPX[7:0].

Bit - Name

Bit

Default

Bit Function

Clear Interrupt on KPX[7:0].

0: no effect

KPX[7:0]IC

7:0

1: Clear corresponding interrupt

14.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1

TABLE 84. GPIOIC1 - GPIO Clear Interrupt Register 1

Register - Name

Address

Type

Register Function

GPIOIC1

0xDD

W

Clears the interrupt on KPY[7:0].

Bit - Name

Bit

Default

Bit Function

Clear Interrupt on KPY[7:0].

0: no effect

KPY[7:0]IC

7:0

1: Clear corresponding interrupt

14.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2

TABLE 85. GPIOIC2 - GPIO Clear Interrupt Register 2

Register - Name

Address

Type

Register Function

GPIOIC2

0xDE

W

Clears the interrupt on KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Clear interrupt on EXTIO:

0: no effect

EXTIOIC

7

1: Clear corresponding interrupt

Clear interrupt on PWM[2:0]:

0: no effect

1: Clear corresponding interrupt

PWM[2:0]IC

KPY[11:8]IC

6:4

3:0

Clear Interrupt on KPY[11:8]:

0: no effect

1: Clear corresponding interrupt

51

www.national.com

14.7 GPIO INTERRUPT STATUS

14.7.1 GPIORIS0 - Raw Interrupt Status Register 0

TABLE 86. GPIORIS0 - Raw Interrupt Status Register 0

Address Type Register Function

Raw interrupt status on KPX[7:0].

Register - Name

GPIORIS0

0xD6

Bit

R

Bit - Name

Default

Bit Function

Raw Interrupt status data on KPX[7:0]:

0: no interrupt condition at GPIO

1: interrupt condition at GPIO

KPX[7:0]RIS

7:0

0x0

14.7.2 GPIORIS1 - Raw Interrupt Status Register 1

TABLE 87. GPIORIS1 - Raw Interrupt Status Register 1

Register - Name

Address

Type

Register Function

Raw interrupt status on KPY[7:0].

GPIORIS1

0xD7

R

Bit - Name

Bit

Default

Bit Function

Raw Interrupt status data on KPY[7:0]:

0: no interrupt condition at GPIO

1: interrupt condition at GPIO

KPY[7:0]RIS

7:0

0x0

14.7.3 GPIORIS2 - Raw Interrupt Status Register 2

TABLE 88. GPIORIS2 - Raw Interrupt Status Register 2

Register - Name

Address

Type

Register Function

GPIORIS2

0xD8

R

Raw interrupt status on KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Raw Interrupt status data on EXTIO:

0: no interrupt condition at GPIO

1: interrupt at GPIO is active

EXTIORIS

7

0x0

Raw Interrupt status data on PWM[2:0]:

0: no interrupt condition at GPIO

1: interrupt at GPIO is active

PWM[2:0]RIS

KPY[11:8]RIS

6:4

3:0

0x0

Raw Interrupt status data on KPY[11:8]:

0: no interrupt condition at GPIO

1: interrupt condition at GPIO

14.7.4 GPIOMIS0 - Masked Interrupt Status Register 0

TABLE 89. GPIOMIS0 - Masked Interrupt Status Register 0

Register - Name

Address

Type

Register Function

Masked interrupt status on KPX[7:0].

GPIOMIS0

0xD9

R

Bit - Name

Bit

Default

Bit Function

Masked Interrupt status data on KPX[7:0]:

0: no interrupt contribution from GPIO

1: interrupt GPIO is active

KPX[7:0]MIS

7:0

0x0

www.national.com

52

14.7.5 GPIOMIS1 - Masked Interrupt Status Register 1

TABLE 90. GPIOMIS1 - Masked Interrupt Status Register 1

Address Type Register Function

Masked interrupt status on KPY[7:0].

Register - Name

GPIOMIS1

0xDA

Bit

R

Bit - Name

Default

Bit Function

Masked Interrupt status data on KPY[7:0]:

0: no interrupt contribution from GPIO

1: interrupt GPIO is active

KPY[7:0]MIS

7:0

0x0

14.7.6 GPIOMIS2 - Masked Interrupt Status Register 2

TABLE 91. GPIOMIS2 - Masked Interrupt Status Register 2

Register - Name

Address

Type

Register Function

GPIOMIS2

0xDB

R

Masked interrupt status on KPY[11:8], PWM[2:0], EXTIO.

Bit - Name

Bit

Default

Bit Function

Masked Interrupt status data on EXTIO:

0: no interrupt condition from GPIO

1: interrupt at GPIO is active

EXTIOMIS

7

0x0

Masked Interrupt status data on PWM[2:0]:

0: no interrupt condition from GPIO

1: interrupt at GPIO is active

PWM[2:0]MIS

KPY[11:8]MIS

6:4

3:0

0x0

Masked Interrupt status data on KPY[11:8]:

0: no interrupt contribution from GPIO

1: interrupt GPIO is active

14.8 GPIO WAKE-UP CONTROL

14.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0

TABLE 92. GPIOWAKE0 - GPIO Wake-Up Register 0

Register - Name

Address

Type

Register Function

Configures wake-up conditions for KPX[7:0].

GPIOWAKE0

0xE9

R/W

Each bit corresponds to a ball. When bit set, the corresponding ball

contributes to wakeup from auto sleep mode.

Bit - Name

Bit

Default

Bit Function

Wakeup enable on KPX[7:0]:

0: disable wakeup

KPX[7:0]WAKE

7:0

0x0

1: enable wakeup

14.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1

TABLE 93. GPIOWAKE1 - GPIO Wake-Up Register 1

Register - Name

Address

Type

Register Function

Configures wake-up conditions for KPY[7:0].

GPIOWAKE1

0xEA

R/W

Each bit corresponds to a ball. When bit set, the corresponding ball

contributes to wakeup from auto sleep mode.

Bit - Name

Bit

Default

Bit Function

Wakeup enable on KPX[7:0]:

0: disable wakeup

KPY[7:0]WAKE

7:00

0x0

1: enable wakeup

53

www.national.com

14.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2

TABLE 94. GPIOWAKE2 - GPIO Wake-Up Register 2

Register - Name

Address

Type

Register Function

Configures wake-up conditions for KPY[11:8], PWM[2:0}, EXTIO.

Each bit corresponds to a ball. When bit set, the corresponding ball

contributes to wakeup from auto sleep mode.

GPIOWAKE2

0xEB

R/W

Bit - Name

Bit

Default

Bit Function

Wakeup enable on EXTIO:

0: disable wakeup

EXTIOWAKE

7

0x0

1: enable wakeup

Wakeup enable on PWM[2:0]:

0: disable wakeup

1: enable wakeup

PWM[2:0]WAKE

KPY[11:8]WAKE

6:4

3:0

0x0

Wakeup enable on KPY[11:8]:

0: disable wakeup

1: enable wakeup

14.9 DIRECT KEY REGISTERS AND DIRECT KEY

CONTROL

Direct Key selection and control registers are mapped in the

address range from 0xE6 to 0xF3. This paragraph describes

the functions of the associated registers down to the bit level.

14.9.1 DEVTCODE - Direct Key Event Code Register

TABLE 95. DEVTCODE - Direct Key Event Code Register

Register - Name

Address

Type

Register Function

With this register a FIFO buffer is addressed storing up to 15

consecutive events.

Reading the value 0x3F from this address means that the FIFO buffer

is empty and a key is not pressed. Reading the value 0x1F form this

address means that the FIFO buffer is empty and a key is still pressed.

DKBDRIS.DREVTINT bit is cleared as soon as this FIFO reaches its

empty state. See further details below.

DEVTCODE

0xE6

R

NOTE: Auto increment is disabled on this register. Multi-byte read will

always read from the same address.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:6

(reserved)

This bit indicates whether the direct key event was a key press or a

key release event.

0: direct key was pressed

DKEYSTAT

DKEYCODE

5

0x0

1: direct key was released.

4:0

0x1F

Column index of key is pressed (0...24, 25 for Direct keys).

www.national.com

54

14.9.2 DBOUNCE - Direct Key Debounce Time Register

TABLE 96. DBOUNCE - Direct Key Debounce Time Register

Address Type Register Function

Register - Name

DBOUNCE

0xE7

R/W

Time between first detection of key and final sampling of key.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:5

(reserved)

De-bounce time for direct keys.

Values of DEBOUNCE[4:0] match to multiples of 3ms:

0x00: 0ms

0x01: 3ms

0x02: 6ms

0x03: 9ms

0x1F: 93 ms

DEBOUNCE

4:0

0x03

14.9.3 DIRECT0 - Direct Key Register 0

bits take priority over anything else. Direct key bits must be

cleared before IOCFG is accessed to set other functions for

the pins.

The direct key settings. If not enabled as a direct key, then

that pin follows the IOCFG and keypad registers. Direct Key

TABLE 97. DIRECT0 - Direct Key Register 0

Register - Name

Address

Type

Register Function

DIRECT0

0xEC

R/W

Enable Direct Key connections for DK[7:0].

Bit - Name

Bit

Default

Bit Function

1: Direct Key connection

0: Direct Key follows IOCFG and keypad registers.

DK[7:0]

7:0

0xFF

14.9.4 DIRECT1 - Direct Key Register 1

TABLE 98. DIRECT1 - Direct Key Register 1

Register - Name

Address

Type

Register Function

DIRECT1

0xED

R/W

Enable Direct Key connections for DK[15:8].

Bit - Name

Bit

Default

Bit Function

1: Direct Key connection

0: Direct Key follows IOCFG and keypad registers.

DK[15:8]

7:0

0xFF

14.9.5 DIRECT2 - Direct Key Register 2

TABLE 99. DIRECT2 - Direct Key Register 2

Register - Name

Address

Type

Register Function

DIRECT2

0xEE

R/W

Enable Direct Key connections for DK[23:16].

Bit - Name

Bit

Default

Bit Function

1: Direct Key connection

0: Direct Key follows IOCFG and keypad registers.

DK[23:16]

7:0

0xFF

55

www.national.com

14.9.6 DIRECT3 - Direct Key Register 3

TABLE 100. DIRECT3 - Direct Key Register 3

Register - Name

Address

Type

Register Function

DIRECT3

0xEF

R/W

Enable Direct Key connections for DK[25:24].

Bit - Name

Bit

Default

Bit Function

(reserved)

7:2

(reserved)

1: Direct Key connection

0: Direct Key follows IOCFG and keypad registers.

DK[25:24]

1:0

0x03

14.9.7 DKBDRIS - Direct Key Raw Interrupt Status Register

TABLE 101. DKBDRIS - Direct Key Raw Interrupt Status Register

Address Type Register Function

0xF0 Returns the status of stored direct key interrupts.

Register - Name

DKBDRIS

R

Bit - Name

Bit

Default

Bit Function

(reserved)

7:2

(reserved)

Raw event lost interrupt.

More than 8 direct key events have been detected and caused the

event buffer to overflow. This bit is cleared by setting bit DEVTIC of

the DKBDIC register.

DRELINT

1

0

0x0

Raw direct key event interrupt.

At least one direct key press or direct key release is in the direct key

event buffer. Reading from DEVTCODE until the buffer is empty will

automatically clear this interrupt.

DREVTINT

0x0

14.9.8 DKBDMIS - Direct Key Masked Interrupt Status Register

TABLE 102. DKBDMIS - Direct Key Masked Interrupt Status Register

Register - Name

Address

Type

Register Function

Returns the status of masked direct key interrupts after masking with

the DKBDMSK register.

DKBDMIS

0xF1

R

Bit - Name

Bit

Default

Bit Function

(reserved)

7:2

(reserved)

Masked event lost interrupt.

More than 8 direct key events have been detected and caused the

event buffer to overflow. This bit is cleared by setting bit DEVTIC of

the DKBDIC register.

DMELINT

1

0

0x0

Masked direct key event interrupt.

At least one direct key press or direct key release is in the direct key

event buffer. Reading from DEVTCODE until the buffer is empty will

automatically clear this interrupt.

DMEVTINT

0x0

www.national.com

56

14.9.9 DKBDIC - Direct Key Interrupt Clear Register

TABLE 103. DKBDIC - Direct Key Interrupt Clear Register

Address Type Register Function

Register - Name

DKBDIC

0xF2

W

Setting these bits clears direct key active interrupts.

Bit - Name

Bit

Default

Bit Function

(reserved)

7:1

(reserved)

Clear event buffer and corresponding interrupts DREVTINT and

DRELINT by writing a '1' to this bit position.

DEVTIC

0

14.9.10 DKBDMSK - Direct Key Interrupt Mask Register

TABLE 104. DKBDMSK - Direct Key Interrupt Mask Register

Register - Name

Address

Type

Register Function

Configures masking of direct key interrupts. Masked interrupts do not

trigger an event of the interrupt output.

DKBDMSK

0xF3

R/W

Bit - Name

Bit

Default

Bit Function

(reserved)

7:2

(reserved)

0: direct key event lost interrupt DRELINT triggers IRQ line

1: direct key event lost interrupt DRELINT is masked.

MSKELINT

MSKEINT

1

0

0x1

0: direct key event interrupt DREVTINT triggers IRQ line

1: direct key event interrupt DREVTINT is masked.

57

www.national.com

Maximum Input Current Without

Latchup

15.0 Absolute Maximum Ratings (Note

±100 mA

1)

ESD Protection Level

(Human Body Model)

(Machine Model)

(Charge Device Model)

2kV

200V

750V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Total Current into V_CCPin (Source)

Total Current out of GND Pin (Sink)

Storage Temperature Range

Supply Voltage (V_CC

)

100 mA

−65°C to +140°C

−0.3V to 2.2V

−0.2V to V_CC+0.2V

Voltage at Generic IOs

Voltage at Backdrive/Overvoltage

IOs

−0.3V to +4.25V

16.0 Electrical Characteristics

TABLE 105. DC ELECTRICAL CHARACTERISTICS

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

(Temperature: −40°C ≤ T_A≤ +85°C, unless otherwise specified)

Parameter

Conditions

Min

Typ

Max Units

Operating Voltage (V_CC

)

Core Supply Voltage

1.62

1.98

3.60

V

Maximum Input voltage for Backdrive/Overvoltage IOs

Internal Clock = ON, all internal functional

blocks running, No loads on pins,

V_CC= 1.8V, T_C= 1µs

Supply Current (I_DD) (Note 2, Note 3)

1.2

2.0

40

mA

T_A= 25°C

Sleep Mode HALT Current (I_HALT) (Note 4)

V_CC= 1.8V, T_A= 25°C

<9

1

µA

Internal Clock = OFF, no internal functional

blocks running

IDLE Current

Internal Clock = ON, no internal functional

blocks running

mA

TABLE 106. AC ELECTRICAL CHARACTERISTICS

(Temperature: −40°C ≤ T_A≤ +85°C)

Data sheet specification limits are guaranteed by design, test, or statistical analysis.

Parameter Conditions

System Clock Frequency

Min

Typ

Max

Units

MHz

ns

Internal RC

10.5

95

System Clock Period (mclk)

1.62V ≤ V_CC≤ 1.98V

Internal RC Oscillator (t_C)

0.95

μs

Internal RC Oscillator Frequency Variation

±7

%

ACCESS.bus Input Signals

Bus Free Time Between Stop and Start

Condition (t_BUFi) (Note 5)

16

SCL Setup Time (t_CSTOsi) (Note 5)

SCL Hold Time (t_CSTRhi) (Note 5)

SCL Setup Time (t_CSTRsi) (Note 5)

Data High Setup Time (t_DHCsi) (Note 5)

(Note 6)

Before Stop Condition

After Start Condition

8

2

Before Start Condition

Before SCL Rising Edge (RE)

mclk

Data Low Setup Time (t_DLCsi) (Note 5)

(Note 6)

Before SCL RE

2

SCL Low Time (t_SCLlowi) (Note 5)

SCL High Time (t_SCLhighi) (Note 5)

(Note 6)

After SCL Falling Edge (FE)

After SCL FE

12

SDA Hold Time (t_SDAhi) (Note 5)

SDA Setup Time (t_SDAsi) (Note 5)

(Note 6)

After SCL FE

0

2

Before SCL RE

www.national.com

58

Parameter

ACCESS.bus Output Signals

SDA Hold Time (t_SDAho) (Note 5)

Conditions

After SCL Falling Edge

Min

Typ

Max

Units

2

mclk

TABLE 107. GENERAL GPIO CHARACTERISTICS

Characteristics for all pins except CLKIN, IRQN/KPY11/PWM2, SDA, and SCL in GPIO mode.

Parameter

V_IH(Min. Input High Voltage)

V_IL(Max. Input Low Voltage)

Conditions

Min

Units

0.7xV_CC

V

0.3xV_CC

−16

V_CC= 1.62

I_Source

I_Sink

mA

V_OH= 0.7xV_CC

V_CC= 1.62

16

mA

V_OL= 0.3xV_CC

Allowable Sink current per pin (Note 7)

I_PU(Weak Pull-UP Current) (Note 8)

I_PD(Weak Pull-Down Current) (Note 8)

16

V_OUT= 0V

-30

30

-160

160

V_OUT= V_CC

µA

ns

GPIO output disabled

V_pin= 0 to V_CC

I_OZ(Input Leakage Current)

±2

15

t_Rise/Fall(Max. Rise and Fall times) (Note 5)

C_LOAD= 50 pF

TABLE 108. BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS

Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL

Parameter

V_IH(Min. Input High Voltage)

V_IL(Max. Input Low Voltage)

Conditions

Min

Typ

Max

Units

0.7xV_CC

V

0.3xV_CC

-6

V_CC= 1.62V

V_OH= 1.15V

I_Source

mA

V_CC= 1.62V

V_OL= 0.4V

I_Sink1(as GPIO)

I_Sink2(as ACCESS.bus)

I_Sink3(as ACCESS.bus)

12

3

V_CC= 1.62V

V_OL= 0.4V

V_CC= 1.62V

V_OL= 0.6V

4

mA

Allowable Sink current per pin (Note 7)

I_PU(Weak Pull-UP Current) (Note 8)

I_PD(Weak Pull-Down Current) (Note 8)

12

-40

40

V_OUT= 0V

-7

7

V_OUT= V_CC

GPIO output disabled

V_CC= 1.62V to 1.98V

V_pin= 0 to V_CC

µA

I_OZ1(Input Leakage Current) (Note 9)

±2

V_pin= V_CCto 3.6V

±10

0 ≤ V_CC≤ 0.5V

V_pin= 0 to 3.6V

I_OZ2(Input Backdrive Leakage Current)

±10

TABLE 109. BACKDRIVE/OVERVOLTAGE I/O AC CHARACTERISTICS

Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL

Parameter Conditions

Min

Typ

Max

Units

t_Rise/Fall

C_LOAD=50 pF @ 1MHz

70

(Max. Rise and Fall time) (Note 5)

ns

t_Fall

C_LOAD=10 pF to 100 pF

V_IHminto V_ILmax

10

120

(Max. Fall time) as ACCESS.bus (SDA, SCL

only) (Note 5)

59

www.national.com

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when

operating the device at absolute maximum ratings.

Note 2: Supply and IDLE current is measured with inputs connected to V_CCand outputs driven low but not connected to a load.

Note 3: Values are estimates. Values will be updated after characterization is completed.

Note 4: In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to V_CCand outputs driven low but not

connected to a load.

Note 5: Guaranteed by design, not tested.

Note 6: The ACCESS.bus interface implements and meets the timings necessary for interface to the I²C and SMBus protocols at logic levels. The bus drivers

have open-drain outputs for bidirectional operation. Due to Internal RC Oscillator Frequency Variation, this specification may not meet the AC timing and current/

voltage drive requirements of the full-bus specifications.

Note 7: The sum of all I/O sink/source current must not exceed the maximum total current into V_CCand out of GND as specified in the absolute maximum ratings.

Note 8: This is the internal weak pull-up (pull-down) current when driver output is disabled. If enabled, during receiving mode, this is the current required to switch

the input from one state to another.

Note 9: I_OZ1for CLKIN is max 60 µA if V_PIN> V_CCbecause the weak pull-down is enabled.

www.national.com

60

17.0 Registers

17.1 REGISTER MAPPING

17.1.1 Keyboard Registers

45), these registers are reset to 0x00 values by a module reset

using RSTCTRL.KBDRST and should be rewritten for desired

settings (see RSTCTRL - Section 14.3.5 RSTCTRL - System

Reset Register).

Table 110 shows the register map for keyboard functionality.

In addition to Global Call Reset (see Section 10.1.6 Global

Call Reset) or Software Reset using SWRESET (see Table

TABLE 110. Register Map for Keyboard Functionality

Register File

Address

ACCESS

Size

Default

value

Next RF

Address

Register Name

Description

Register Type

KBDSETTLE

KBDBOUNCE

Keypad Settle Time

0x01

0x02

R/W

byte

0x80

0x02

0x03

Keypad Debounce Time

Keypad Size

Configuration

KBDSIZE

0x03

R/W

byte

0x22

0x04

KBDDEDCFG0

KBDDEDCFG1

Keypad Dedicated Key 0

Keypad Dedicated Key 1

0x04

0x05

R/W

byte

0xFF

0x05

0x06

Keypad Raw Interrupt

Status

KBDRIS

KBDMIS

0x06

0x07

R

byte

0x00

0x07

0x08

Keypad Masked

Interrupt Status

KBDIC

Keypad Interrupt Clear

Keypad Interrupt Mask

Keypad Code 0

0x08

0x09

0x0B

0x0C

0x0D

0x0E

0x10

W

R

byte

0x09

0x0A

0x0C

0x0D

0x0E

0x0F

0x10

KBDMSK

0x0C

0x7F

KBDCODE0

KBDCODE1

KBDCODE2

KBDCODE3

EVTCODE

Keypad Code 1

Keypad Code 2

Keypad Code 3

Key Event Code

17.1.2 Direct Key Registers

set), these registers are reset to 0x00 values by a module

reset using RSTCTRL.KBDRST and should be rewritten for

desired settings (see RSTCTRL, Section 14.3.5 RSTCTRL -

System Reset Register).

Table 111 shows the register map for keyboard functionality

when using direct keys. In addition to Global Call Reset (see

Section 10.1.6 Global Call Reset) or Software Reset using

SWRESET (see Section 14.3.4 SWRESET - Software Re-

TABLE 111. Register Map for Direct Key Registers

Register File

Address

ACCESS

Size

Default

value

Next RF

Address

Register Name

DEVTCODE

DBOUNCE

Description

Register Type

Direct Key Event Code

0xE6

R

byte

0x3F

0xE6

Direct Key Debounce

Time

0xE7

R/W

byte

0x03

0xE8

DIRECT0

DIRECT1

DIRECT2

DIRECT3

Direct Key Config 0

Direct Key Config 1

Direct Key Config 2

Direct Key Config 3

0xEC

0xED

0xEE

0xEF

R/W

byte

0xFF

0x03

0xED

0xEE

0xEF

0xF0

Direct Key Raw

Interrupt Status

DKBDRIS

DKBDMIS

DKBDIC

0xF0

0xF1

0xF2

0xF3

R

byte

0x00

0xF1

0xF2

0xF3

0xF4

Direct Key Masked Int.

Status

Direct Key Interrupt

Clear

W

Direct Key Interrupt

Mask

DKBDMSK

R/W

0x03

61

www.national.com

17.1.3 PWM Timer Registers

Table 112 shows the register map for PWM Timer functionality. In addition to Global Call Reset (see Section 10.1.6 Global Call

Reset) or Software Reset using SWRESET (see Table 45), these registers are reset to default values by a module reset using

RSTCTRL.TIMRST (see Section 14.3.5 RSTCTRL - System Reset Register).

TABLE 112. Register Map for PWM Timer Functionality

Register File

Address

ACCESS

Size

Default

value

Next RF

Address

Register Name

Description

Register Type

PWM Timer

Configuration 0

TIMCFG0

0x60

R/W

byte

0x00

0x61

PWMCFG0

TIMSCAL0

PWM Configuration 0

0x61

0x62

R/W

byte

0x00

0x62

0x63

PWM Timer Prescaler 0

PWM Timer

Configuration 1

TIMCFG1

0x68

R/W

byte

0x00

0x69

PWMCFG1

TIMSCAL1

PWM Configuration 1

0x69

0x6A

R/W

byte

0x00

0x6A

0x6B

PWM Timer Prescaler 1

PWM Timer

Configuration 2

TIMCFG2

0x70

R/W

byte

0x00

0x71

PWMCFG2

TIMSCAL2

TIMSWRES

PWM Configuration 2

PWM Timer Prescaler 2

PWM Timer SW Reset

0x71

0x72

0x78

R/W

W

byte

0x00

0x72

0x73

0x79

PWM Timer Interrupt

Status

TIMRIS

0x7A

R

byte

0x00

0x7B

PWM Timer Masked Int.

Status

TIMMIS

TIMIC

0x7B

0x7C

0x7D

0x7E

R

W

byte

word

0x7C

0x7D

0x7E

0x7F

Timer Interrupt Clear

PWM Command Write

Pointer

PWMWP

PWMCFG

R/W

W

0x00

PWM Command Script

www.national.com

62

17.1.4 System Registers

TRL - System Reset Register). These registers can only be

reset to default values by a Global Call Reset (see Sec-

tion 10.1.6 Global Call Reset) or by a complete Software

Reset using SWRESET (seeTable 45).

Table 113 shows the register map for general system regis-

ters. These registers are not affected by any of the module

resets addressed by RSTCTRL (see Section 14.3.5 RSTC-

TABLE 113. Register Map for System Control Functionality

Register Name

Description

Register File

Address

Register Type

ACCESS

Size

Default

value

Next RF

Address

I²C Slave Address

Manufacturer Code

SW Revision

I2CSA

0x80

0x81

0x82

W

R

byte

0x8A

0x00

0xC4

0x81

0x82

0x83

MFGCODE

SWREV

R

SWRESET

RSTCTRL

SW Reset

W

System Reset

R/W

0x00

Clear No Init/Power On

Interrupt

RSTINTCLR

0x84

W

byte

0x85

CLKMODE

CLKCFG

Clock Mode

Clock Configuration

Clock Enable

0x88

0x89

0x8A

0x8B

0x8C

0xF4

R/W

byte

word

byte

0x01

0x40

0x89

0x8A

0x8B

0x8C

0x8D

0xF5

CLKEN

0x00

AUTOSLP

AUTOSLPTI

MMASTER

Auto Sleep Enable

Auto Sleep Time

Multi-Master Mode

0x00

0x00FF

0x00

17.1.5 Global Interrupt Registers

Table 45), these registers are reset to default values by a

module reset using RSTCTRL.IRQRST (see Section 14.3.5

RSTCTRL - System Reset Register).

Table 114 shows the register map for global interrupt func-

tionality. In addition to Global Call Reset (see Section 10.1.6

Global Call Reset) or Software Reset using SWRESET (see

TABLE 114. Register Map for Global Interrupt Functionality

Register Name

Description Register File Register Type ACCESS Size

Default

value

Next RF

Address

IRQST

Global Interrupt Status

0x91

R

byte

0x80

0x92

17.1.6 GPIO Registers

these registers are reset to 0x00 values by a module reset

using RSTCTRL.GPIRST and should be rewritten for desired

settings (see Section 14.3.5 RSTCTRL - System Reset Reg-

ister).

Table 115 shows the register map for GPIO functionality. In

addition to Global Call Reset (see Section 10.1.6 Global Call

Reset) or Software Reset using SWRESET (see Table 45),

TABLE 115. Register Map for GPIO Functionality

Register Name

Description

Register File Register Type ACCESS Size

Address

Default

value

Next RF

Address

I/O Pin Mapping

Configuration

IOCFG

IOPC0

IOPC1

IOPC2

0xA7

W

byte

word

0xA8

0xAB

0xAD

0xAF

Pull Resistor

Configuration 0

0xAA

0xAC

0xAE

R/W

0xFFFF

Pull Resistor

Configuration 1

Pull Resistor

Configuration 2

0xFFFF

0x00

GPIODATA0

GPIOMASK0

GPIODATA1

GPIOMASK1

GPIODATA2

GPIOMASK2

GPIODIR0

GPIO I/O Data 0

GPIO I/O Mask 0

GPIO I/O Data 1

GPIO I/O Mask 1

GPIO I/O Data 2

GPIO I/O Mask 2

GPIO I/O Direction 0

GPIO I/O Direction 1

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

R/W

W

byte

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

R/W

W

0x00

R/W

W

R/W

0x00

GPIODIR1

63

www.national.com

Register Name

Description

Register File

Address

Register Type ACCESS Size

Default

value

Next RF

Address

GPIODIR2

GPIOIS0

GPIOIS1

GPIOIS2

GPIO I/O Direction 2

GPIO Int Sense Config 0

GPIO Int Sense Config 1

GPIO Int Sense Config 2

0xC8

0xC9

0xCA

0xCB

R/W

byte

0x00

0xC9

0xCA

0xCB

0xCC

GPIO Int Both Edges

Config 0

GPIOIBE0

GPIOIBE1

GPIOIBE2

0xCC

0xCD

0xCE

R/W

byte

0x00

0xCD

0xCE

0xCF

GPIO Int Both Edges

Config 1

GPIO Int Both Edges

Config 2

GPIOIEV0

GPIOIEV1

GPIOIEV2

GPIOIE0

GPIO Int Edge Select 0

GPIO Int Edge Select 1

GPIO Int Edge Select 2

GPIO Interrupt Enable 0

GPIO Interrupt Enable 1

GPIO Interrupt Enable 2

GPIO Raw Int Status 0

GPIO Raw Int Status 1

GPIO Raw Int Status 2

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD6

0xD7

0xD8

R/W

R

byte

0x00

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD7

0xD8

0xD9

GPIOIE1

GPIOIE2

GPIORIS0

GPIORIS1

GPIORIS2

R

GPIO Masked Int Status

0

GPIOMIS0

GPIOMIS1

GPIOMIS2

0xD9

0xDA

0xDB

R

byte

0x00

0xDA

0xDB

0xDC

GPIO Masked Int Status

1

GPIO Masked Int Status

2

GPIOIC0

GPIOIC1

GPIOIC2

GPIO Interrupt Clear 0

GPIO Interrupt Clear 1

GPIO Interrupt Clear 2

0xDC

0xDD

0xDE

W

byte

0xDD

0xDE

0xDF

GPIO Open Drain Mode

Enable 0

GPIOOME0

GPIOOMS0

GPIOOME1

GPIOOMS1

GPIOOME2

GPIOOMS2

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

R/W

byte

0x00

0x08

0x00

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

GPIO Open Drain Mode

Select 0

GPIO Open Drain Mode

Enable 1

GPIO Open Drain Mode

Select 1

GPIO Open Drain Mode

Enable 2

GPIO Open Drain Mode

Select 2

GPIOWAKE0

GPIOWAKE1

GPIOWAKE2

GPIO Wakeup Enable 0

GPIO Wakeup Enable 1

GPIO Wakeup Enable 2

0xE9

0xEA

0xEB

R/W

byte

0x00

0xEA

0xEB

0xEC

www.national.com

64

65

www.national.com

66

67

www.national.com

68

18.0 Physical Dimensions inches (millimeters) unless otherwise noted

MICRO ARRAY Package

Order Number LM8327JGR8 NOPB or LM8327JGR8X NOPB

NS Package Number GRA36A

69

www.national.com

Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

www.national.com

Products

www.national.com/amplifiers

Design Support

www.national.com/webench

Amplifiers

WEBENCH® Tools

App Notes

Audio

www.national.com/audio

www.national.com/timing

www.national.com/adc

www.national.com/interface

www.national.com/lvds

www.national.com/power

www.national.com/appnotes

www.national.com/refdesigns

www.national.com/samples

www.national.com/evalboards

www.national.com/packaging

www.national.com/quality/green

www.national.com/contacts

www.national.com/quality

www.national.com/feedback

www.national.com/easy

Clock and Timing

Data Converters

Interface

Reference Designs

Samples

Eval Boards

LVDS

Packaging

Power Management

Green Compliance

Distributors

Switching Regulators www.national.com/switchers

LDOs

www.national.com/ldo

www.national.com/led

www.national.com/vref

www.national.com/powerwise

Quality and Reliability

Feedback/Support

Design Made Easy

Applications & Markets

Mil/Aero

LED Lighting

Voltage References

PowerWise® Solutions

www.national.com/solutions

www.national.com/milaero

www.national.com/solarmagic

www.national.com/training

Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors

PLL/VCO

www.national.com/tempsensors SolarMagic™

www.national.com/wireless

PowerWise® Design

University

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

Email: support@nsc.com

Tel: 1-800-272-9959

www.national.com


型号：	LM8327JGR8X
厂家：	TEXAS INSTRUMENTS
描述：	LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface LM8327移动I / O伴侣支持键盘扫描， I / O扩展，PWM和ACCESS总线主机接口
文件：	总72页 (文件大小：740K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM8327JGR8X [TI]

相关型号：

LM8328

LM8328TME

LM8328TMX

LM832M

LM832M/A+

LM832M/B+

LM832MX

LM832N

LM832N/A+

LM832N/B+

LM833

LM833