LM8330 [TI]
具有 GPIO、PWM 和 IEC61000 ESD 保护的 I2C 兼容键盘控制器;
| 型号： | LM8330 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 GPIO、PWM 和 IEC61000 ESD 保护的 I2C 兼容键盘控制器 控制器 |
| 文件： | 总55页 (文件大小：1228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM8330
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SNVS839A –JUNE 2012–REVISED MARCH 2013
LM8330 I2C-Compatible Keypad Controller with GPIO, PWM, and IEC61000 ESD Protection
Check for Samples: LM8330
1
FEATURES
–
Debounce Time for Reliable Key Event
Polling
2
•
KEY FEATURES
–
–
Configuration of General Purpose I/O Ports
–
–
–
Keypad Matrices of up to of 8 x 12 Keys,
Plus 8 Special Function (SF) Keys, for a
Full 104 Key Support.
Various Initialization Options (Keypad Size,
etc.)
•
KEY DEVICE FEATURES
Supports General-purpose I/O Expansion
on Pins Not Otherwise Used for Keypad or
PWM Output.
–
–
–
–
1.8V ±10% Single-supply Operation
On-chip Power-on Reset (POR)
−30°C to +85°C Temperature Range
Keypad Matrix and Dedicated Key Support:
–
–
16-Event Keycode Buffer
Robust IEC ESD Protection: ±8 kV Direct
Contact on KPX[7:0] and KPY[10:0] Pins
4-Event Multiple Key Storage Registers
–
–
Internal Oscillator, No External Clock
Required.
I2C-compatible ACCESS.bus Slave Interface
Standard (100 kHz) and Fast (400 kHz)
Modes:
–
25-pin DSBGA Package Size: 2 mm x 2 mm
x 0.6 mm (0.4 mm Pitch)
APPLICATIONS:
•
•
•
Mobile Phones
–
–
–
7-bit and 10-bit Addressing
Programmable Slave Address
(Default 7-bit 0x88, 10-bit 0x088)
Qwerty Keyboard
Universal Remote
DESCRIPTION
–
Three Host-programmable PWM Outputs
The LM8330 I/O - Expander and Keypad Controller is
a dedicated device designed to unburden a host
processor from scanning a matrix-addressed keypad
and to provide flexible and general purpose, host
–
–
–
Smooth LED Brightness Modulation
Dedicated 31-command Script Bugger
Register-based Command Interpreter
with Auto-increment Addressing
programmable
input/output
functions.
Three
independent Pulse Width Modulation (PWM) timer
outputs are provided for dynamic LED brightness
modulation.
–
–
Key Events, Errors, and Dedicated
Hardware Interrupts, Request Host Service
by Asserting an IRQ Output
It communicates with a host processor through an
I2C-compatible ACCESS.bus serial interface. It can
communicate in Standard (100 kHz) and Fast-Mode
(400 kHz) in slave Mode only.
Ultra-Low-Power Operation
–
–
–
Automatic HALT Mode: 1.5 µA (typ.)
Active Supply Current: 23 µA (typ.)
Configurable Wake-Up from HALT
Operation
All available input/output pins can alternately be used
as an input or an output in a keypad matrix or as a
host-programmable general-purpose input or output.
–
IEC61000-4-2 ESD Protection on KPX[7:0]
and KPY[10:0] pins
Any pin programmed as an input can also sense
hardware interrupts. The interrupt polarity (“high-to-
low” or “low-to-high” transition) is thereby
programmable.
–
–
ESD Glitch Filter on RESETN Input
External Reset for System Control
•
HOST-CONTROLLED FEATURES
The LM8330 follows a predefined register-based set
–
–
–
Reset Input for System Control
of commands. Upon startup (power-on)
a
PWM Scripting for Three PWM Outputs
configuration file must be sent from the host to set up
the hardware of the device.
Period of Inactivity That Triggers Entry into
HALT Mode
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LM8330
SNVS839A –JUNE 2012–REVISED MARCH 2013
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DESCRIPTION (CONTINUED)
The LM8330 is available in a 25-bump lead-free DSBGA package size 2.0 mm x 2.0 mm x 0.6 mm (0.4 mm
pitch).
The LM8330 has integrated ASIP (Application Specific Integrated Passives) on the KPX[7:0] and KPY[10:0] pins.
These pins are designed to tolerate IEC61000-4-2 level 4 ESD: ±8 kV direct contact.
LM8330 FUNCTION BLOCKS
1.8V (typ)
0.1 mF (required)
VCC
LM8330
SCL
SDA
Internal
OSC
ACCESS.bus
Main
processing
device
IRQN
RESETN
DIV
Command
Interpreter
32 kHz
Reference
Clock
Keypad
Matrix
Input/Output
Sleep Control
Key-Scan
Control
PWM
Generator
Wake-Up
Control
General Purpose
Inputs/Outputs
Input/Output
Expansion
ASIP ESD
Protection
PWM0
PWM2
NOTE: This diagram illustrates IO configuration 3 with IRQN enabled
PWM1
PACKAGE MARKING
1
2
3
4
5
A
B
C
D
E
Figure 1. LM8330 Pinout - Top View (balls underneath)
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SNVS839A –JUNE 2012–REVISED MARCH 2013
SIGNAL DESCRIPTIONS
Primary and Alternate Functions of All Device Pins
Ball
A3
D3
A4
A5
E1
D2
B4
B5
A1
A2
C1
D1
E4
E3
E2
D4
B2
B1
C2
B3
C4
D5
E5
C5
C3
Function 0(1)
Function 1(1)
Function 2(1)
Function 3(1)
Pin Count
Ball Name
RESETN
VCC
Reset Active Low Input
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
25
Supply Voltage
ACCESS.bus Clock
ACCESS.bus Data
SCL
SDA
Keypad-I/O X0
Keypad-I/O X1
Keypad-I/O X2
Keypad-I/O X3
Keypad-I/O X4
Keypad-I/O X5
Keypad-I/O X6
Keypad-I/O X7
Keypad-I/O Y0
Keypad-I/O Y1
Keypad-I/O Y2
Keypad-I/O Y3
Keypad-I/O Y4
Keypad-I/O Y5
Keypad-I/O Y6
Keypad-I/O Y7
Keypad-I/O Y8
Keypad-I/O Y9
Keypad-I/O Y10
Keypad-I/O Y11
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
KPX0
KPX1
KPX2
KPX3
KPX4
KPX5
KPX6
KPX7
KPY0
KPY1
KPY2
KPY3
KPY4
KPY5
KPY6
KPY7
KPY8
KPY9
KPY10
IRQN
GND
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
PWM2(2)
PWM1
PWM0
PWM2(2)
Interrupt
Ground
Total
(1) This table describes the alternate pin function and not the actual BALLCFG assignments. Refer to Table 49 for actual BALLCFG
Assignments.
(2) PWM2 functionality is mutually exclusive - one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of IOCFG.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC
)
−0.3V to 2.2V
−0.2V to VCC +0.2V
−0.3V to +.2.2V
+150°C
Voltage at Generic I/Os
Voltage at Backdrive I/Os
Junction Temperature
Storage Temperature Range
−40°C to +140°C
Lead Temperature (TL)
(Soldering, 10 sec.)
+260°C
2000V
200V
ESD Protection Level
Human Body Model:
Machine Model:
Charge Device Model:
Direct Contact (ASIP I/O only):
500V
IEC61000-4-2, 330Ω, 150 pF:
±8kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions,
see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
OPERATING RATINGS
Min
Max
1.98
Units
V
VCC Supply Voltage
Supply Noise
1.62
50
mVpp
Operating Ambient Temperature
−30°C to +85°C
DC ELECTRICAL CHARACTERISTICS
Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C,
VCC = 1.8V ±10%, unless otherwise specified
Symbol
Parameter
Operating Voltage
Conditions
Core Supply Voltage
Min
Typ
Max
Units
VCC
1.62
1.98
V
No load on any Output pin,
VCC = 1.8V, TA = 25°C
ICCDYN1
ICCDYN2
Active 8x7 Keypad matrix,
ACCESS.Bus frequency = 400 Khz,
No key pressed, PWM Inactive
23
30
(1)
Supply Current
No load on any Output pin, VCC = 1.8V, TA
= 25°C
µA
All GPIO Mode - outputs toggling,
ACCESS.Bus frequency = 400 Khz,
PWM Inactive
18
25
(2)
ICCHALT
Sleep Mode HALT Current
VCC = 1.8V, TA = 25°C
Internal Clock = OFF, no internal functional
blocks running
1.5
3.0
(1) Supply current is measured with inputs connected to VCC and outputs driven low but not connected to a load.
(2) In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to VCC and outputs
driven low but not connected to a load.
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SNVS839A –JUNE 2012–REVISED MARCH 2013
AC ELECTRICAL CHARACTERISTICS
Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C,
VCC = 1.8V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
1.62V ≤ VCC ≤ 1.98V
Min
Typ
64
Max
Units
KHz
μS
fOSC
tOSC
Internal Oscillator Frequency
Internal Oscillator Period
51.2
76.8
15.625
ACCESS.bus Signal Timing
fSCL
ACCESS.bus Clock Frequency
400
KHz
1.62V ≤ VCC ≤ 1.98V
tBUF
1.3
0.6
0.6
1.0
0.6
0.1
0.3
tCSTOsi
SCL Setup Time
SCL High Time
SCL Low Time
SCL Hold Time
SDA Setup Time
SDA Hold Time
Before Stop Condition
After SCL Rising Edge
After SCL Falling Edge
Repeated-Start Condition
Before SCL Rising Edge
After SCL Falling Edge
RESETN Timing
tSCLhigh
tSCLlow
tCSTRhi
tDHC
μS
tSDAhi
tSPIKE
RST Input Glitch Filter ()
0 < VIN < VDD
50
100
nS
GENERAL GPIO DC CHARACTERISTICS
Characteristics for pins KPX[7:0], KPY[10:0]. Datasheet min/max specification limits are specified by design, test, or statistical
analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
VIL
Min. Input High Voltage
0.65xVCC
V
0.35x
VCC
Max. Input Low Voltage
VCC = 1.62
VOH = 0.65xVCC
ISource
ISink
−4.5
mA
VCC = 1.62
VOL = 0.35xVCC
4.5
mA
mA
(1)
Allowable Sink Current per pin
Weak pullup Current
6.5
IPU
IPD
IOZ
VOUT = 0V
−160
30
−30
160
+1
Weak pulldown Current
Input Leakage Current
VOUT = VCC
µA
GPIO output disabled
−1
(1) The sum of all I/O sink/source current must not exceed 100 ma maximum total current into VCC and out of GND.
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BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS
Characteristics for pins RESETN, IRQN, SDA and SCL. Datasheet min/max specification limits are specified by design, test,
or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
VIL
0.65xVCC
RESETN, SCL, SDA
V
0.35xVC
C
VCC = 1.62V
VOH = 1.17V
ISource
ISink1
ISink2
ISink3
IRQN
IRQN
−16
VCC = 1.62V
VOL = 0.45V
16
3
mA
VCC = 1.62V
VOL = 0.4V
SDA
VCC = 1.62V
VOL = 0.6V
6
(1)
IPU
IPD
IRQN pin as GPIO11
IRQN pin as GPIO11
VOUT = 0V
−160
−30
(1)
VOUT = VCC
30
160
GPIO output disabled
1.62V ≤ VCC ≤ 1.98V
0 ≤ External pin voltage ≤ VCC
−1
+1
µA
µA
IOZ1
Input Leakage Current
GPIO output disabled
1.62V ≤ VCC ≤ 1.98V
0 ≤ External pin voltage ≤ 2.2V
−5
−5
+5
+5
0 ≤ VCC ≤ 0.5V
0 ≤ External pin voltage ≤ 2.2V
IOZ2
Input Backdrive Leakage Current
(1) This is the internal weak pullup (pulldown) current when driver output is disabled. If enabled, during receiving mode, this is the current
required to switch the input from one state to another.
BACKDRIVE I/O AC CHARACTERISTICS
Characteristics for pins SDA and SCL. Datasheet min/max specification limits are specified by design, test, or statistical
analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified.
Symbol
tRise/Fall
Parameter
Conditions
Min
Typ
Max
Units
(1)
Max. Rise and Fall time
CLOAD = 50 pF @ 1MHz
70
ns
Max. Fall Time ACCESS.bus,
SDA, SCL
CLOAD = 10 pF to 100 pF
VIHmin to VILmax
tFall
20
300
(1)
(1) Specified by design, not tested.
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SNVS839A –JUNE 2012–REVISED MARCH 2013
PIN CONFIGURATION AFTER RESET
Upon power-up or RESET the LM8330 will have defined states on all pins. The following table provides a
comprehensive overview of the states of all functional pins.
Pin Configuration after Reset
Pins
KPX0
KPX1
KPX2
KPX3
KPX4
KPX5
KPX6
KPX7
KPY0
KPY1
KPY2
KPY3
KPY4
KPY5
KPY6
KPY7
KPY8
KPY9
KPY10
IRQN
Pin States
Full Buffer mode with an on-chip pullup resistor enabled.
Full Buffer mode with an on-chip pulldown resistor enabled.
Open Drain mode with no pull resistor enabled, driven low.(1)
Open Drain mode with no pull resistor enabled.
SCL
SDA
(1) The IRQN is driven low after Power-On Reset due to PORIRQ signal. The value 0x01 must be written to the RSTINTCLR register (0x84)
to release the IRQN pin.
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TYPICAL APPLICATION SETUP
1.8V (typ)
0.1 mF (required)
VCC
SDA
KPY3
Main
processing
device
SCL
KPY2
IRQN/KPY11
RESETN
KPY1
KPY0
Up
Down
Sel
KPX0
KPX1
KPX2
KPX3
KPX4
KPX5
KPX6
KPX7
Left
Rght
LM8330
Soft
Lft
Soft
Rt
Genio12 Output
Send End
KPY4
KPY5
KPY6
KPY7
1
2
3
4
5
6
7
8
9
*
Genio13 Output
Genio14 Input
Genio15 Input
0
#
KPY8/PWM2
KPY9/PWM1
KPY10/PWM0
GND
Color
LED
Figure 2. LM8330 in a Typical Setup with Standard Handset Keypad
FEATURES
The following features are supported with the application example shown in example above:
Hardware
Hardware
•
•
4 x 8 keys and 8 Special Function (SF) keys for 40 keys.
ACCESS.bus interface for communication with a host device.
–
- Communication speeds supported are: 100 kHz and 400 kHz fast mode of operation.
•
•
•
•
Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host.
Sophisticated PWM function block with 3 independent channels to control color LED.
External reset input for system control.
Two host-programmable dedicated general-purpose output pins (GPIOs) supporting IO-expansion capabilities
for host device.
•
Two host-programmable dedicated general-purpose input pins with wake-up supporting IO-expansion
capabilities for host device.
Communication Layer
•
•
•
Versatile register-based command integration supported from on-chip command interpreter.
Keypad event storage.
Individual PWM script file storage and execution control for 3 PWM channels.
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SNVS839A –JUNE 2012–REVISED MARCH 2013
HALT MODE
HALT MODE DESCRIPTION
The fully static architecture of the LM8330 allows stopping the internal RC clock in Halt mode, which reduces
power consumption to the minimum level.
Halt mode is entered when no key-press event or key-release event is detected for a certain period of time (by
default, 1020 milliseconds). The mechanism for entering Halt mode is enabled by default and can be disabled
refer to Table 46. The period of inactivity which triggers entry into Halt mode using the auto-sleep function is
programmable refer to Table 47.
ACCESS.BUS ACTIVITY
When the LM8330 is in Halt mode an ACCESS.bus access to its Slave Address will not cause the LM8330 to
exit from Halt mode. All internal registers are available via ACCESS.bus while in HALT Mode. The LM8330 will
acknowledge all bus cycles to its Slave Address while in Halt mode and will not require the host to repeat the
cycle.
LM8330 PROGRAMMING INTERFACE
The LM8330 operation is controlled from a host device by a complete register set, accessed via the I2C-
compatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure,
following the I2C-compatible transmission protocol.
All functions can be controlled by configuring one or multiple registers. Configuration registers defined as word
ACCESS size must have the entire word written in a continuous ACCESS.bus data transfer for the values to take
effect. Reading write only registers will always return the value of 0. Please refer to and in LM8330 Registers for
the complete register set.
ACCESS.BUS COMMUNICATION
The LM8330 will only be driven in slave mode. The maximum communication speed supported is Fast Mode
(FS) which is 400 kHz. Figure 3 shows a typical 7-bit address Read cycle initiated by the host.
Figure 3. Master/Slave Serial Communication (Host to LM8330)
Table 1. Definition of Terms used in Serial Command Example
Term
S
Bits
7
Description
START Condition (always generated from the master device).
Slave address of LM8330 sent from the host (7-bit address mode).
ADDRESS
This bit determines if the following data transfer is from master to slave (data write) or from slave to
master (data read).
0: Write
R/W
1
1: Read
An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status
is actually provided from the slave and indicates to the master that the byte transfer was successful.
ACK
REG
1
8
The first byte after sending the slave address is the REGISTER byte which contains the physical address
the host wants to read from or write to.
RS
Repeated START condition.
DATA
8
1
The DATA field contains information to be stored into a register or information read from a register.
Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a
slave. The NACK status will actually be assigned from the master in order to signal the end of a
communication cycle transfer.
NACK
P
STOP condition (always generated from the master device).
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All actions associated with the non-shaded boxes in Figure 3 are controlled from the master (host) device.
All actions associated with the shaded boxes in Figure 3 are controlled from the slave (LM8330) device.
The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A
STOP condition must be set from the master at the very end of a communication cycle.
It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent
REGISTER addresses. This technique will make sure that the master device communicating with the LM8330
will not lose bus arbitration.
STARTING A COMMUNICATION CYCLE
There are two reasons for the host device to start communication to the LM8330:
1. The LM8330 device has set the IRQN line low in order to signal a key event or any other condition which
initializes a hardware interrupt from LM8330 to the host.
2. The host device wants to set a GPIO port, read from a GPIO port, configure a GPIO port, and read the status
from a register or initialize any other function which is supported from the LM8330. In case a GPIO shall be
read it will be most likely that the LM8330 device will be residing in “sleep mode”. In this mode the system
clock will be off to establish the lowest possible current consumption. If the host device starts the
communication under this condition, the LM8330 device will acknowledge the first byte if it matches its
programmed slave address.
AUTO INCREMENT
In order to improve multi-byte register access, the LM8330 supports the auto increment of the address pointer.
A typical read-access sequence to the LM8330 starts with the I2C-compatible ACCESS.bus address, followed by
the REG write of the register to access (see Figure 3). After a REPEATED START condition the host
reads/writes a data byte from/to this address location. The LM8330 automatically increments the address pointer
by one until a STOP condition is received. The LM8330 always uses auto increments unless otherwise noted.
Please refer to Table 2 and Table 3 for the typical ACCESS.bus flow of reading and writing multiple data bytes.
RESERVED REGISTERS AND BITS
The LM8330 includes reserved registers for future implementation options. Writing to the reserved locations is
not allowed and could result in abnormal device behavior.
GENERAL CALL RESET
The LM8330 does not support the Global Call Reset as defined in the NXP (Philips) I2C Specification UM10204
rev 0.3 from 2007.
DEVICE ID
The LM8330 does not support the Device ID as defined in the NXP (Philips) I2C Specification UM10204 rev 0.3
from 2007.
7-BIT and 10-BIT ADDRESSING MODES
The LM8330 supports both the 7-bit and 10-bit addressing modes as defined in the NXP (Philips) I2C
Specification UM10204 rev 0.3 from 2007. The default 7-bit slave address is 0x88, and the default 10-bit slave
address is 0x088.
NOTE
The upper three address bits in 10-bit mode are hard tied to 0.
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Table 2. Multi-Byte Write with Auto Increment
Step
1
Master/Slave
I2C Com.
Value
Address Pointer
Comment
M
M
M
S
S
START condition
2
ADDR
R/W
0x88
0
I2C-compatible ACCESS.bus Address
3
Write
4
ACK
REG
ACK
DATA
ACK
DATA
ACK
P
Acknowledge
5
M
S
0xAA
0xAA
0xAA
0xAA
0xAB
0xAB
0xAC
Register Address, used as Address Pointer
Acknowledge
6
7
M
S
0x01
0
Write Data to Address in Pointer
Acknowledge, Address pointer incremented
Write Data to address 0xAB
Acknowledge, Address pointer incremented
STOP condition
8
9
M
S
0x05
0
10
11
M
Table 3. Multi-Byte Read with Auto Increment
Step
1
Master/Slave
I2C Com.
Value
Address Pointer
Comment
M
M
M
S
S
START condition
2
ADDR
R/W
0x88
0
I2C-compatible ACCESS.bus Address
3
Write
4
ACK
REG
ACK
RS
Acknowledge
5
M
S
0xAA
0xAA
0xAA
0xAA
0xAA
Register Address, used as Address pointer
Acknowledge
6
7
M
M
M
S
Repeated Start
8
ADDR.
R/W
0x88
1
I2C-compatible ACCESS.bus Address
9
Read
10
11
12
13
14
15
ACK
DATA
ACK
DATA
NACK
P
0
0xAA
0xAA
0xAB
0xAB
0xAC
Acknowledge
S
0x01
0
Read Data from Address in Pointer
Acknowledge, Address Pointer incremented
Read Data from Address in Pointer
No Acknowledge, stops transmission
STOP condition
M
S
0x05
0
M
M
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KEYSCAN OPERATION
KEYSCAN INITIALIZATION
Figure 4. Keyscan Initialization
KEYSCAN INITIALIZATION EXAMPLE
Table 4 shows all the LM8330 register configurations to initialize keyscan:
•
Keypad matrix configuration is 8 rows x 8 columns.
Table 4. Keyscan Initialization Example
Register name
KBDSETTLE
KBDBOUNCE
KBDSIZE
KBDDEDCFG
IOCFG
adress
0x01
0x02
0x03
0x04
0xA7
0xAA
0xAC
0x08
0x09
0x8A
Access Type
byte
Value
0x80
Comment
Set the keyscan settle time to 12 msec.
byte
byte
word
byte
word
word
byte
byte
byte
0x80
0x88
Set the keyscan debounce time to 12 msec.
Set the keyscan matrix size to 8 rows x 8 columns.
0xFC3F
0xF8
Configure KPX[7:2] and KPY[7:2] pins as keyboard matrix.
Write default value to enable all pins as keyboard matrix.
Configure pullup resistors for KPX[7:0].
Configure pulldown resistors for KPY[7:0].
clear any pending interrupts.
IOPC0
0xAAAA
0x5555
0x03
IOPC1
KBDIC
KBDMSK
CLKEN
0x03
Enable keyboard interrupts.
0x01
Enable keyscan clock.
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KEYSCAN PROCESS
The LM8330 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On
each scan all assigned key matrix pins are evaluated for state changes.
In case a key event has been identified, the event is stored in the key event FIFO, accessible via the EVTCODE
register. A key event can either be a key press or a key release. In addition, key presses are also stored in the
KBDCODE[3:0] registers. As soon as the EVTCODE FIFO includes a event, the device sets the RAW keyboard
event interrupt REVTINT. The RSINT interrupt is set anytime the keyboard status has changed.
Depending on the interrupt masking for the keyboard events (KBDMSK) and the masked interrupt handling
(KBDMIS), the pin IRQN will follow the IRQST.KBDIRQ status, which is set as soon as one interrupt in KBDRIS
is set.
Figure 5 shows the basic flow of a scanning process and which registers are affected.
Figure 5. Example Keyscan Operation for
1 Key Press and Release
READING KEYSCAN STATUS BY THE HOST
In order to keep track of the keyscan status, the host either needs to regularly poll the IRQST register or needs
to react on the Interrupt signaled by the IRQN pin, in case the ball is configured for interrupt functionality. (See
GPIO FEATURE CONFIGURATION).
Figure 6 gives an example on which registers to read to get the keyboard events from the LM8330 and how they
influence the interrupt event registers. The example is based on the assumption that the LM8330 has indicated
the keyboard event by the IRQN pin.
Since the interrupt pin has various sources, the host first checks the IRQST register for the interrupt source. If
KBDIRQ is set, the host can check the KBDMIS register to define the exact interrupt source. KBDMIS contains
the masked status of KBDRIS and reflects the source for raising the interrupt pin. The interrupt mask is defined
by KBDMSK. The complete status of all pending keyboard interrupts is available in the raw interrupt register
KBDRIS.
After evaluating the interrupt source the host starts reading the EVTCODE or KBDCODE register. In this
example the host first reads the KBDCODE to get possible key press events and afterwards reads the complete
event list by reading the EVTCODE register until all events are captured (0x7F indicates end of buffer).
Reading KBDCODE clears the RSINT interrupt bit if all keyboards events are emptied. In the same way,
REVTINT is cleared in case the EVTCODE FIFO reaches its empty state on read.
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The event buffer content and the REVTINT and RELINT (lost event) interrupt bits are also cleared if the
KBDIC.EVTIC bit is set.
Interrupt bits in the masked interrupt register KBDMIS follow the masked KBDRIS status.
In order to support efficient Multi-byte reads from EVTCODE, the auto-increment feature is turned off for this
register. Therefore the host can continuously read the complete EVTCODE buffer by sending one command.
Figure 6. Example Host Reacting to
Interrupt for Keypad Event
MULTIPLE KEY PRESSES
The LM8330 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set
with the appropriate key code. If a second key is pressed, the key is stored in KBDCODE1 and the MULTIKEY
flag of KBDCODE0 is set. Additional key presses are stored in KBDCODE2 and KBDCODE3 accordingly. The
four registers signal the last multi key press events.
All events are stored in parallel in the EVTCODE register for the complete set of events.
All KBDCODE[3:0] registers are cleared on read.
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Figure 7. Example Keyscan Operation for 2 Key Press Events
and 1 Key Release Event
PWM TIMER
The LM8330 supports a timer module dedicated to smooth LED control techniques.
The Pulse Modulation Width (PWM) timer module consists of three independent timer units of which each can
generate a PWM output with a fixed period and automatically incrementing or decrementing variable duty cycle.
The timer units are all clocked with a slow (32 kHz) clock.
OVERVIEW OF PWM FEATURES
•
•
•
Each PWM can establish fixed - or variable - duty-cycle signal sequences on its output.
Each PWM can trigger execution of any pre-programmed task on another PWM channel.
The execution of any pre-programmed task is self-sustaining and does not require further interaction from the
host.
•
•
31-instruction script buffer for each PWM.
Direct addressing within script buffer to support multiple PWM tasks in one buffer.
OVERVIEW ON PWM SCRIPT COMMANDS
The commands listed in Table 5 are dedicated to the slow PWM timers.
NOTE
If the last address in the PWM script buffer is reached, and that command is not an END
command, an END command with INT & RST enabled will be forced and the PWM
operation will be terminated.Please note: The PWM Script commands are not part of the
command set supported by the LM8330 command interpreter. These commands must be
transferred from the host with help of the register-based command set.
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Table 5. PWM Script Commands
Command
RAMP
15
0
14
PRESCALE
1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STEPTIME
0
SIGN
INCREMENT
PWM VALUE
SET_PWM
GO_TO_
START
0
0
BRANCH
END
1
1
1
0
1
1
1
0
1
LOOPCOUNT
RST
WAITTRIGGER
ADDR
X
STEPNUMBER
INT
X
TRIGGER
SENDTRIGGER
0
RAMP Command
A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT
field specifies the amount of steps for the RAMP. The maximum amount of steps which can be executed with
one RAMP Command is 126 which is equivalent to 50%. The SIGN bit field determines the direction of a RAMP
(up or down). The STEPTIME field and the PRESCALE bit determine the duration of one step. Based on a 32
kHz clock, the minimum time resulting from these options would be 0.49 milliseconds and the maximum time for
one step would be 1 second.
Table 6. RAMP Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
PRESCALE
STEPTIME
SIGN
INCREMENT
Table 7. Description of Bit and Building Fields of the RAMP Command
Bit or Field
PRESCALE
STEPTIME
SIGN
Value
Description
0
Divide the 32 kHz clock by 16.
Divide the 32 kHz clock by 512.
1
1 - 63
0
Number of prescaled clock cycles per step.
Increment RAMP counter.
1
Decrement RAMP counter.
Number of steps executed by this instruction; a value of 0 functions as a WAIT
determined by STEPTIME.
INCREMENT
0 - 126
SET_PWM Command
The SET_PWM command does not allow generation of a PWM output with a fixed duty cycle between 0% and
100%. This command will set the starting duty cycle MIN SCALE or FULL SCALE (0% or 100%). A RAMP
command following the SET_PWM command will finally establish the desired duty cycle on the PWM output.
Table 8. SET_PWM Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
DUTYCYCLE
Table 9. Description of Bit and Building Fields of the SET_PWM Command
Bit or Field
Value
0
Description
Duty cycle is 0%.
DUTYCYCLE
255
Duty cycle is 100%.
GO_TO_START Ccommand
The GO_TO_START command jumps to the first command in the script command file.
Table 10. GO_TO_START Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
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BRANCH Command
The BRANCH command jumps to the specified command in the script command file. The branch is executed
with either absolute or relative addressing. In addition, the command gives the option of looping for a specified
number of repetitions.
NOTE
Nested loops are not allowed.
Table 11. BRANCH Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
LOOPCOUNT
ADDR
X
STEPNUMBER
Table 12. Description of Bit and Building Fields of the BRANCH Command
Bit or Field
Value
Description
Loop until a STOP PWM SCRIPT command is issued by the host.
Number of loops to perform.
0
1 - 63
0
LOOPCOUNT
Absolute addressing
ADDR
1
Relative addressing
Depending on ADDR:
STEPNUMBER
0 - 31
ADDR=0: Addr to jump to
ADDR=1: Number of backward steps
TRIGGER Command
Triggers are used to synchronize operations between PWM channels. A TRIGGER command that sends a
trigger takes sixteen 32 kHz clock cycles, and a command that waits for a trigger takes at least sixteen 32 kHz
clock cycles.
A TRIGGER command that waits for a trigger (or triggers) will stall script execution until the trigger conditions are
satisfied. On trigger it will clear the trigger(s) and continue to the next command.
When a trigger is sent, it is stored by the receiving channel and can only be cleared when the receiving channel
executes a TRIGGER command that waits for the trigger.
Table 13. TRIGGER Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
WAITTRIGGER
SENDTRIGGER
0
Table 14. Description of Bit and Building Fields
Field
Value
000xx1
000x1x
0001xx
000xx1
000x1x
0001xx
Description
Wait for trigger from channel 0
Wait for trigger from channel 1
Wait for trigger from channel 2
Send trigger to channel 0
WAITTRIGGER
SENDTRIGGER
Send trigger to channel 1
Send trigger to channel 2
END COMMAND
The END command terminates script execution. It will only assert an interrupt to the host if the INT bit is set to
'1'.
When the END command is executed, the PWM output will be set to the level defined by PWMCFG.PWMPOL
for this channel. Also, the script counter is reset back to the beginning of the script command buffer.
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NOTE
If a PWM channel is waiting for the trigger (last executed command was "TRIGGER"), and
the script execution is halted, then the "END" command can’t be executed because the
previous command is still pending. This is an exception - in this case the IRQ signal will
not be asserted.
Table 15. END Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
INT
RST
0
Table 16. Description of Bit and Building Fields of the END Command
Field
Value
Description
0
1
0
1
No interrupt will be sent.
INT
Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.
The PWM Output is set Low.
RST
The PWM Output is set according to PWMCFG.PWMPOL.
LM8330 REGISTER SET
KEYBOARD REGISTERS AND KEYBOARD CONTROL
Keyboard selection and control registers are mapped in the address range from 0x01 to 0x09. This paragraph
describes the functions of the associated registers down to the bit level.
KBDSETTLE - Keypad Settle Time Register
Table 17. KBDSETTLE - Keypad Settle Time Register
Register - Name
Address
Type
Register Function
Initial time for keys to settle, before the key-scan process is started. The
Keypad settle time will be imposed under the following conditions:
a. A wake-up event on the keypad input (if KBDEN=1)
b. The MODCTL register bit is written to transition from “halt” to
“operational” mode (if KBDEN=1).
KBDSETTLE
0x01
R/W
Bit - Name
Bit
Default
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec.
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00 : no settle time
KBDBOUNCE - Debounce Time Register
Table 18. KBDBOUNCE - Debounce Time Register
Register - Name
Address
Type
Register Function
KBDBOUNCE
0x02
R/W
Time between first detection of key and final sampling of key.
Bit - Name
Bit
Default
Bit Function
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Table 18. KBDBOUNCE - Debounce Time Register (continued)
Register - Name
Address
Type
Register Function
The default value 0x80 : 0xBF sets a time target of 12 msec.
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00: no debouncing time
KBDSIZE - Set Keypad Size Register
Table 19. KBDSIZE - Set Keypad Size Register
Register - Name
Address
Type
Register Function
KBDSIZE
0x03
R/W
Defines the physical keyboard matrix size.
Bit - Name
Bit
Default
Bit Function
Number of rows in the keyboard matrix:
0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN:
ROWSIZE[3:0]
7:4
3:0
0x2
0x1: (illegal value)
0x2 - 0x8: Number of rows in the matrix
Number of columns in the keyboard matrix:
0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN
COLSIZE[3:0]
0x2
0x1: (illegal value)
0x2 - 0xC: Number of columns in the matrix
KBDDEDCFG - Dedicated Key Register
Table 20. KBDDEDCFG - Dedicated Key Register
Register - Name
Address
Type
Register Function
Defines if a key is used as a standard keyboard/GPIO pin or whether it is
used as dedicated key input.
KBDDEDCFG
0x04
R/W
Bit - Name
Bit
Default
Bit Function
Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2.
Bit=0: the dedicated key function applies.
ROW[7:2]
15:10
9:8
0x3F
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [11:10] corresponds to ball KPY11 : KPY10.
Bit=0: the dedicated key function applies.
COL[11:10]
COL[9:2]
0x03
0xFF
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be
configured individually.
Bit=0: the dedicated key function applies.
7:0
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
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KBDRIS - Keyboard Raw Interrupt Status Register
Table 21. KBDRIS - Keyboard Raw Interrupt Status Register
Register - Name
Address
Type
Register Function
KBDRIS
0x06
R
Returns the status of stored keyboard interrupts.
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:4
Raw event lost interrupt.
More than 16 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
RELINT
REVTINT
RKLINT
3
2
1
0x0
0x0
0x0
Raw keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Raw key lost interrupt indicates a lost key-code.
This interrupt is asserted when RSINT has not been cleared upon
detection of a new key press or key release, or when more than 4 keys
are pressed simultaneously.
Raw scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed. Reading from KBDCODE until the buffer is empty will clear this
interrupt.
RSINT
0
0x0
KBDMIS - Keypad Masked Interrupt Status Register
Table 22. KBDMIS - Keypad Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
Returns the status on masked keyboard interrupts after masking with the
KBDMSK register.
KBDMIS
0x07
R
Bit - Name
Bit
Default
Bit Functions
(reserved)
(reserved)
7:4
Masked event lost interrupt.
More than 16 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
MELINT
MEVTINT
MKLINT
3
2
1
0x0
0x0
0x0
Masked keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Masked key lost interrupt.
Indicates a lost key-code. This interrupt is asserted when RSINT has not
been cleared upon detection of a new key press or key release, or when
more than 4 keys are pressed simultaneously.
Masked scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed, after masking process. Reading from KDBCODE until the buffer
is empty will clear this interrupt.
MSINT
0
0x0
KBDIC - Keypad Interrupt Clear Register
Table 23. KBDIC - Keypad Interrupt Clear Register
Register - Name
Address
Default
Register Function
KBDIC
0x08
W
Setting these bits clears Keypad active Interrupts
Bit - Name
Bit
Default
Bit Function
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Table 23. KBDIC - Keypad Interrupt Clear Register (continued)
Register - Name
Address
Default
Register Function
Switches off scanning of special function (SF) keys, when keyboard has
no special function layout:
SFOFF
7
0: keyboard layout and SF keys are scanned
1: only keyboard layout is scanned, SF keys are not scanned
(reserved)
(reserved)
6:2
Clear EVTCODE FIFO and corresponding interrupts REVTINT and
RELINT by writing a 1 to this bit position.
Note: Any key data in the EVTCODE FIFO will be lost when this bit is set;
it is the users responsibility to ensure that all key data is read prior to
asserting this bit. If a key is pressed while EVTIC is asserted/de-asserted
the EVTCODE FIFO will be updated with only the key release code when
the key is released.
EVTIC
KBDIC
1
0
Clear RSINT and RKLINT interrupt bits by writing a '1' to this bit position.
Note The KBDCODE registers are not cleared when setting this bit.
KBDMSK - Keypad Interrupt Mask Register
Table 24. KBDMSK - Keypad Interrupt Mask Register
Register - Name
Address
Type
Register Function
Configures masking of keyboard interrupts. Masked interrupts do not
trigger an event on the Interrupt output.
In case the interrupt processes registers KBDCODE[3:0], MSKELINT and
MSKEINT should be set to '1'. When the Event FIFO is processed,
MSKLINT and MSKSINT should be set. For keyboard polling operations,
all bits should be set and the polling operation consists of reading out the
IRQST.
KBDMSK
0x09
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:4
0: keyboard event lost interrupt RELINT triggers IRQ line
1: keyboard event lost interrupt RELINT is masked
0: keyboard event interrupt REVINT triggers IRQ line
1: keyboard event interrupt REVINT is masked
0: keyboard lost interrupt RKLINT triggers IRQ line
1: keyboard lost interrupt RKLINT is masked
0: keyboard status interrupt RSINT triggers IRQ line
1: keyboard status interrupt RSINT is masked
MSKELINT
MSKEINT
MSKLINT
MSKSINT
3
2
1
0
0x0
0x0
0x1
0x1
KEYBOARD CODE DETECT REGISTERS
The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3. Up to 4
keys can be detected simultaneously. Each KBDCODE register includes a bit (MULTIKEY) indicating if another
key has been detected.
NOTE
Reading out all key code registers (KBDCODE0 to KBDCODE3) will automatically reset
the keyboard scan interrupt RSINT the same way as an active write access into bit KBDIC
of the interrupt clear register does. Reading 0x7F from the KBDCODE0 register means
that no key was pressed.
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KBDCODE0 - Keyboard Code Register 0
Table 25. KBDCODE0 - Keyboard Code Register 0
Register - Name
Address
Default
Register Function
KBDCODE0
0x0B
R
Holds the row and column information of the first detected key.
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
If this bit is 1 another key is available in KBDCODE1 register.
ROW index of detected key (0 to 7).
KEYROW[2:0]
6:4
0x7
Column index of detected (0 to 11, 12 for special function key and 13 & 14
for dedicated KPY key).
KEYCOL[3:0]
3:0
0xF
KBDCODE1 - Keyboard Code Register 1
Table 26. KBDCODE1 - Keyboard Code Register 1
Register - Name
Address
Default
Register Function
KBDCODE1
0x0C
R
Holds the row and column information of the second detected key.
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
If this bit is 1 another key is available in KBDCODE2 register.
ROW index of detected key (0 to 7).
KEYROW[2:0]
6:4
0x7
Column index of detected key (0 to 11, 12 for special function key and 13
& 14 for dedicated KPY key).
KEYCOL[3:0]
3:0
0xF
KBDCODE2 - Keyboard Code Register 2
Table 27. KBDCODE2 - Keyboard Code Register 2
Register - Name
Address
Default
Register Function
KBDCODE2
0x0D
R
Holds the row and column information of the third detected key.
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
if this bit is 1 another key is available in KBDCODE3 register.
ROW index of detected key (0 to 7).
KEYROW[2:0]
6:4
0x7
Column index of detected key (0 to 11, 12 for special function key and 13
& 14 for dedicated KPY key).
KEYCOL[3:0]
3:0
0xF
KBDCODE3 - Keyboard Code Register 3
Table 28. KBDCODE3 - Keyboard Code Register 3
Register - Name
Address
Default
Register Function
KBDCODE3
0x0E
R
Holds the row and column information of the forth detected key.
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
if this bit is set to '1' then more than 4 keys are pressed simultaneously.
ROW index of detected key (0 to 7).
KEYROW[2:0]
6:4
0x7
Column index of detected key (0 to 11, 12 for special function key and 13
& 14 for dedicated KPY key).
KEYCOL[3:0]
3:0
0xF
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EVTCODE - Key Event Code Register
Table 29. EVTCODE - Key Event Code Register
Register - Name
Address
Default
Bit Function
With this register a FIFO buffer is addressed storing up to 15 consecutive
events.
Reading the value 0x7F from this address means that the FIFO buffer is
empty. See further details below.
EVTCODE
0x10
R
NOTE: Auto increment is disabled on this register. Multi-byte read will
always read from the same address.
Bit - Name
Bit
Default
Bit Function
This bit indicates whether the keyboard event was a key press or a key
release event:
RELEASE
7
0x0
0: key was pressed
1: key was released
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
Row index of key that is pressed or released.
Column index of detected key that is pressed (0 to 11, 12 for special
function key or and 13 & 14 for dedicated key) or released.
PWM TIMER CONTROL REGISTERS
The LM8330 provides three host-programmable PWM outputs useful for smooth LED brightness modulation. All
PWM timer control registers are mapped in the range from 0x60 to 0x7F. This paragraph describes the functions
of the associated registers down to the bit level.
TIMCFGx - PWM Timer 0, 1 and 2 Configuration Register
Table 30. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Register
Register - Name
TIMCFG0
Address
0x60
Type
Register Function
TIMCFG1
0x68
R/W
This register configures interrupt masking of the associated PWM channel.
TIMCFG2
0x70
Bit - Name
(x = 0, 1 or 2)
Bit
Default
Bit Function
Interrupt mask for PWM CYCIRQx (see register TIMRIS):
CYCIRQxMSK
(reserved)
4
0x0
0x0
0: interrupt enabled
1: interrupt masked
(reserved)
3:0
PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register
Table 31. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register
Register - Name
Address
Type
Register Function
This register defines interrupt masking and the output behavior for the
associated PWM channel.
PWMCFG0
0x61
PWMCFG1
0x69
R/W
PGEx is used to start and stop the PWM script execution.
PWMENx sets the PWM output to either reflect the generated pattern or
the value configured in PWMPOLx.
PWMCFG2
0x71
Bit - Name
(x = 0, 1 or 2)
Bit
Default
Bit Function
Mask for CDIRQ:
CDIRQxMSK
3
0x0
0: CDIRQ enabled
1: CDIRQ disabled/masked
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Table 31. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register (continued)
Register - Name
Address
Type
Register Function
Pattern Generator Enable. Start/Stop PWM command processing for this
channel. Script execution is started always from beginning.
0: Pattern Generator disabled
1: Pattern Generator enabled
PGEx
2
0x0
Notes:
1) This bit will be cleared when the PWM completes execution of END
command and END.RST = 1.
2) The PWM will complete execution of an active script command if this
bit is set to 0 by the host.
0: PWM disabled. PWM timer output assumes value programmed in
PWMPOL.
PWMENx
1
0
0x0
0x0
1: PWM enabled
Off-state of PWM output, when PWMEN = 0:
0: PWM off-state is low
PWMPOLx
1: PWM off-state is high
TIMSWRES - PWM Timer Software Reset Registers
Table 32. TIMSWRES - PWM Timer Software Reset Registers
Register - Name
Address
Type
Register Function
Reset control on all PWM timers.
A reset forces the pattern generator to fetch the first pattern and stops it.
Each reset stops all state-machines and timer.
TIMSWRES
0x78
W
Patterns stored in the pattern configuration register remain unaffected.
Interrupts on each timer are not cleared, they need to be cleared writing
into register TIMIC.
Bit - Name
Bit
Default
Bit Function
(reserved)
7:3
(reserved)
Software reset of timer 2:
SWRES2
SWRES1
SWRES0
2
1
0
0: no action
1: Software reset on timer 2, needs not to be written back to 0.
Software reset of timer 1
0: no action
1: Software reset on timer 1, needs not to be written back to 0.
Software reset of timer 0:
0: no action
1: software reset on timer 0, needs not to be written back to '0'.
TIMRIS - PWM Timer Interrupt Status Register
Table 33. TIMRIS - PWM Timer Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the raw interrupt status from the PWM timers 0,1 and
2.
CYCIRQx - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block).
TIMRIS
0x7A
R
CDIRQx - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
Default
Bit Functions
(reserved)
7:6
(reserved)
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Table 33. TIMRIS - PWM Timer Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Raw interrupt status for CDIRQ timer2:
CDIRQ2
CDIRQ1
5
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer1:
0: no interrupt pending
4
3
2
1
0
0x0
0x0
0x0
0x0
0x0
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer0:
0: no interrupt pending
CDIRQ0
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer2:
0: no interrupt pending
CYCIRQ2
CYCIRQ1
CYCIRQ0
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer1:
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer0:
0: no interrupt pending
1: unmasked interrupt generated
TIMMIS - PWM Timer Masked Interrupt Status Register
Table 34. TIMMIS - PWM Timer Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the masked interrupt status from the PWM timers 0, 1
and 2. The raw interrupt status (TIMRIS) is masked with the associated
TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK bits to get the
masked interrupt status of this register.
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
TIMMIS
0x7B
R
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
Default
Bit Function
(reserved)
7:6
(reserved)
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer2:
CDIRQ2
CDIRQ1
CDIRQ0
CYCIRQ2
5
4
3
2
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer1:
0x0
0x0
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer0:
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer2:
0: no interrupt pending
1: interrupt generated
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Table 34. TIMMIS - PWM Timer Masked Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer1:
CYCIRQ1
1
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer0:
CYCIRQ0
0
0x0
0: no interrupt pending
1: interrupt generated
TIMIC - PWM Timer Interrupt Clear Register
Table 35. TIMIC - PWM Timer Interrupt Clear Register
Register - Name
Address
Type
Register Function
This register clears timer and pattern interrupts.
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
TIMIC
0x7C
W
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:6
Clears interrupt CDIRQ timer2:
0: no effect
CDIRQ2
CDIRQ1
5
4
3
2
1
0
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer1:
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer0:
0: no effect
CDIRQ0
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer2:
0: no effect
CYCIRQ2
CYCIRQ1
CYCIRQ0
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer1:
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer0:
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
PWMWP - PWM Timer Pattern Pointer Register
Table 36. PWMWP - PWM Timer Pattern Pointer Register
Register - Name
Address
0x7D
Bit
Type
Register Function
Pointer to the pattern position inside the configuration register, which will
be overwritten by the next write access to be PWMCFG register.
PWMWP
R/W
NOTE: 1 pattern consists of 2 bytes and not the byte position (low or
high). It is incremented by 1 every time a full PWMCFG register access
(word) is performed.
Bit - Name
Default
Bit Function
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Table 36. PWMWP - PWM Timer Pattern Pointer Register (continued)
Register - Name
Address
Type
Register Function
(reserved)
7
0x0
(reserved)
0 ≤ POINTER < 32 : timer0 patterns 0 to 31
32 ≤ POINTER < 64 : timer1 patterns 0 to 31
64 ≤ POINTER < 96 : timer2 patterns 0 to 31
96 ≤ POINTER < 128: not valid
POINTER[6:0]
6:0
0x0
PWMCFG - PWM Script Register
Table 37. PWMCFG - PWM Script Register
Register - Name
Address
Type
Register Function
Two-byte pattern storage register for a PWM script command indexed by
PWMWP. PWMWP is automatically incremented.
To be applied by two consecutive parameter bytes in one I2C Write
Transaction.
PWMCFG
0x7E
W
NOTE: Auto-increment is disabled on this register. Address will stay at
0x7E for each word access.
Bit - Name
CMD[15:8]
CMD[7:0]
Bit
15:8
7:0
Default
Bit Function
High byte portion of a PWM script command
Low byte portion of a PWM script command
INTERFACE CONTROL REGISTERS
The following section describes the functions of special control registers provided for the main controller.
The manufacturer code MFGCODE and the software revision number SWREV tell the main device which
configuration file has to be used for this device.
NOTE
I2CSA and MFGCODE use the same address. They just differentiate in the access type:
•
•
Write - I2CSA
Read - MFGCODE
I2CSA - I2C-Compatible ACCESS.bus 10-Bit & 7-Bit Slave Address Register
Table 38. I2CSA - I2C-Compatible ACCESS.bus 10-Bit & 7-Bit Slave Address Register
Register - Name
Address
Type
Register Function
I2C-compatible ACCESS.bus Slave Address.
The address is internally applied after the next I2C STOP.
Bit Function
10-bit & 7-bit address field for the I2C-compatible ACCESS.bus slave
address (10-bit: upper three bits = 0).
I2CSA
0x80
W
Bit - Name
SLAVEADDR[7:1]
(reserved)
Bit
7:1
0
Default
0x44
(reserved)
MFGCODE - Manufacturer Code Register
Table 39. MFGCODE - Manufacturer Code Register
Register - Name
MFGCODE
Bit - Name
MFGBIT
Address
0x80
Bit
Type
R
Register Function
Manufacturer code of the LM8330.
Default
0x00
Bit Function
7:0
8-bit field containing the manufacturer code.
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SWREV - Software Revision Register
Table 40. SWREV - Software Revision Register
Register - Name
Address
Type
Register Function
Software revision code of the LM8330.
SWREV
0x81
R
NOTE: writing the SW revision with the inverted value triggers a reset (see
SWRESET - Software Reset).
Bit - Name
Bit
Default
Bit Function
SWBIT
7:0
0x84
8 - bit field containing the SW Revision number.
SWRESET - Software Reset
Table 41. SWRESET - Software Reset Register
Register - Name
Address
Type
Register Function
Software reset
NOTE: the reset is only applied if the supplied parameter has the inverted
SWRESET
0x81
W
value as SWBIT.
Reading this register provides the software revision (see SWREV -
Software Revision Register).
Bit - Name
Bit
Default
Bit Function
SWBIT
7:0
Reapply inverted value for software reset.
RSTCTRL - System Reset Register
This register allows resetting specific blocks of the LM8330. These bits are not self-clearing and must be written
to a value of '0' to release the block specific reset. All registers associated with the block specific reset will be
initialized to their default value. During an active reset of a module, the LM8330 will not block the access to the
module registers. A read will return the default value, write commands may or may not be ignored. (Refer to each
block-specific reset bit for additional details.)
Table 42. RSTCTRL - System Reset Register
Register - Name
RSTCTRL
Address
0x82
Bit
Type
R/W
Register Function
Software reset of specific parts of the LM8330.
Bit Function
Bit - Name
(reserved)
Default
7:5
(reserved)
Interrupt controller reset. Does not change status on IRQN ball. Only
controls IRQ module register. An interrupt status register read when this
bit is set will return a value of 0 even if there is an Interrupt Status bit set.
Pending interrupts will be accumulated and held until IRQRST bit is
released. Any interrupt can be cleared while IRQRST is active:
IRQRST
4
0x0
0: interrupt controller not reset
1: interrupt controller reset
Timer reset for Timers 0, 1, 2:
0: timer not reset
TIMRST
(reserved)
KBDRST
3
2
1
0x0
0x0
0x0
1: timer is reset
(reserved)
Keyboard interface reset:
0: keyboard is not reset
1: keyboard is reset
GPIO reset:
GPIRST
0
0x0
0: GPIO not reset
1: GPIO is reset.
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RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Table 43. RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Register - Name
Address
Type
Register Function
This register is used to clear the PORIRQ Interrupt. This interrupt is set
every time the device returns from RESET (either POR, HW or SW
Reset).
RSTINTCLR
0x84
W
Bit - Name
Bit
Default
Bit Function
reserved
7:1
(reserved)
1: Clears the PORIRQ Interrupt signalled in IRQST register.
0: is ignored
IRQCLR
0
CLKMODE - Clock Mode Register
Table 44. CLKMODE - Clock Mode Register
Register - Name
CLKMODE
Address
0x88
Bit
Type
R/W
Register Function
This register controls the current operating mode of the LM8330 device.
Bit - Name
Default
Bit Function
(reserved)
7:2
(reserved)
Writing to 00 forces the device to immediately enter sleep mode,
regardless of any auto-sleep configuration. Reading this bit returns the
current operating mode.
NOTE: Any active PWM Outputs will be turned off when the LM8330 is
transitioned from Operation Mode to Sleep Mode:
MODCTL[1:0]
1:0
0x01
00: SLEEP Mode
01: Operation Mode
1x: Future modes
CLKEN - Clock Enable Register
Table 45. CLKEN - Clock Enable Register
Register - Name
Address
Type
Register Function
Controls the clock to different functional units. It is used to enable the
functional blocks globally and independently.
CLKEN
0x8A
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:3
PWM Timer 0, 1, 2 clock enable:
0: Timer 0, 1, 2 clock disabled
1: Timer 0, 1, 2 clock enabled.
(reserved)
TIMEN
(reserved)
KBDEN
2
1
0
0x0
0x0
Keyboard clock enable (enables/disables key scan):
0: Keyboard clock disabled
1: Keyboard clock enabled
AUTOSLIP - Auto-sleep Enable Register
Table 46. AUTOSLIP - Auto-sleep Enable Register
Register - Name
AUTOSLP
Address
0x8B
Bit
Type
R/W
Register Function
This register controls the Auto-Sleep function of the LM8330 device.
Bit - Name
(reserved)
Default
Bit Function
7:1
(reserved)
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Table 46. AUTOSLIP - Auto-sleep Enable Register (continued)
Register - Name
Address
Type
Register Function
Enables automatic sleep mode after a defined activity time stored in the
AUTOSLPTI register:
ENABLE
0
0x00
1: Enable entering auto-sleep mode
0: Disable entering auto-sleep mode
AUTOSLPTI - Auto-Sleep Time Register
Table 47. AUTOSLPTI - Auto-Sleep Time Register
Register - Name
Address
Type
Register Function
This register defines the activity time. If this time passes without any
processing events then the device enters into sleep-mode, but only if
AUTOSLP.ENABLE bit is set to 1.
AUTOSLPTIL
AUTOSLPTIH
0x8C
0x8D
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
15:11
(reserved)
Values of UPTIME[10:0] match to multiples of 4ms:
0x00: no autosleep, regardless if AUTOSLP.ENABLE is set
0x01: 4ms
UPTIME[10:8]
UPTIME[7:0]
10:8
7:0
0x00
0xFF
0x02: 8ms
0x7A: 500 ms
0xFF: 1020 ms (default after reset)
0x100: 1024 ms
0x7FF: 8188 ms
IRQST - Interrupt Global Interrupt Status Register
Table 48. IRQST - Interrupt Global Interrupt Status Register
Register - Name
Address
Type
Register Function
Returns the interrupt status from various on-chip function blocks. If any of
the bits is set and an IRQN line is configured, the IRQN line is asserted
active.
IRQST
0x91
R
Bit - Name
Bit
Default
Bit Function
Supply failure on VCC.
Also power-on is considered as an initial supply failure. Therefore, after
power-on, the bit is set:
PORIRQ
7
0x1
0x0
0: no failure recorded
1: Failure - device was completely reset and requires re-programming.
Keyboard interrupt (further key selection in keyboard module):
KBDIRQ
(reserved)
TIM2IRQ
6
5:4
3
0: inactive
1: active
(reserved)
Timer2 expiry (CDIRQ or CYCIRQ):
0x0
0x0
0x0
0x0
0: inactive
1: active
Timer1 expiry (CDIRQ or CYCIRQ):
TIM1IRQ
TIM0IRQ
GPIOIRQ
2
1
0
0: inactive
1: active
Timer0 expiry (CDIRQ or CYCIRQ):
0: inactive
1: active
GPIO interrupt (further selection in GPIO module):
0: inactive
1: active
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GPIO FEATURE CONFIGURATION
GPIO Feature Mapping
The LM8330 has a flexible I/O structure which allows flexibility in the assignment of different functionality to each
ball. This flexibility is implemented in several registers that are used to configure the balls for function (Keypad
Matrix, Dedicated Key, GPIO, PWM, or Interrupt). Each ball can also be configured for direction, internal pull
resistor, and output buffer type (full, open drain, open source). The functionality of each ball is determined
according to the following configuration priority:
In general the following priority is given:
1. Keypad
2. GPIO/PWM/Interrupt
Each ball that is configured as part of a Keypad Matrix or Dedicated Keypad input will automatically configure the
ball direction, pull resistor and output buffer type. Any ball not configured as part of the keypad matrix will be
available as GPIO, PWM or interrupt output (IRQN) and must be configured accordingly.
The configuration for Keypad, PGIO, PWM, or interrupt usages is defined by the following register priority:
•
•
•
•
1st Priority: KBDSIZE
2nd Priority: KBDDEDCFG
3rd Priority: IOCFG
4th Priority: GPIODIR/GPIOME/GPIOMS/IOPC
When there is a conflict between any of these registers the ball will be configured according the priority above.
Below are several example programming conflicts and the resulting configuration.
•
If KBDSIZE selects 8x8 matrix, but KBDDEDCFG selects KPX2 as a Dedicated Input Key, the KBDSIZE
takes priority and the ball will be configured as a Keypad Matrix Input.
•
If KBDSIZE selects 8x8 matrix, but IOPC selects KPX[7:0] pins to have no pullup resistor enabled, the
KBDSIZE takes priority and the pullup resistors will automatically be enabled on all KPX[7:0] pins. Likewise,
the KPY[7:0] pins will be automatically configured to have no pullup or pulldown resistor enabled irregardless
of the settings in the IOPC registers since that behavior is required for Keyboard Matrix Outputs (i.e.
KBDSIZE has priority).
•
•
When there is a conflict between KBDSIZE settings and the GPIODIR, GPIOMS, or GPIOME settings,
KBDSIZE takes priority and the pins selected as Keyboard Matrix pins are automatically configured into the
proper direction, pullup/down configuration, and IO buffer configuration consistent with the required operation
as matrix pins.
If the IOCFG register selects a pin to be a PWM output, but the GPIODIR register selects the pin to be an
input, the IOCFG register takes priority and the pin will behave as a PWM output.
Table 49. Ball Configuration Options
Module connectivity
BALL
BALLCFG
0x3
GPIOSEL
0x0
0x1
0x2
0x4
0x5
0x6
0x7
KPX[7:0]
KPY[7:0]
X
X
Keypad Matrix or GPIO [7:0]
Keypad Matrix or GPIO [15:8]
KPY8/
0
1
X
-
-
-
KPY8/
GPIO16
PWM2(2)
KPY8
GPIO16
Reserved(1)
KPY9/
GPIO17
KPY9
PWM1
PWM0
KPY10/
GPIO18
KPY10
X
-
KPY11/
GPIO19
0
1
PWM2(2)
IRQN
IRQN
(1) BALLCFG 0x3 thru 0x7 are invalid and can result in indeterminate behavior.
(2) PWM2 functionality is mutally exclusive — one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of IOCFG.
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IOCGF - Input/Output Pin Mapping Configuration Register
Table 50. IOCGF - Input/Output Pin Mapping Configuration Register
Register - Name
IOCFG
Address
0xA7
Bit
Type
Register Function
Configures usage of KPY[11:8] if not used for Keypad. (Refer to Table 49
for appropriate BALLCFG setting.)
W
Bit - Name
(reserved)
Default
Bit Function
(reserved, set to
zero)
7:5
(reserved, set to zero)
Configures KPY11 as the IRQN output:
1= IRQN enabled
GPIOSEL
4
0 = BALLCFG Mapping
(reserved)
BALLCFG
3
(reserved, set to zero)
2:0
Select column to configure — refer to Table 49.
IOPC0 - Pull Resistor Configuration Register 0
Table 51. IOPC0 - Pull Resistor Configuration Register 0
Register - Name
IOPC0(1)
Address
OxAA
Bit
Type
R/W
Register Function
Defines the pull resistor configuration for balls KPX[7:0].
Bit Function
Bit - Name
Default
Resistor enable for KPX7 ball:
00: no pull resistor at ball
KPX7PR[1:0]
KPX6PR[1:0]
KPX5PR[1:0]
KPX4PR[1:0]
KPX3PR[1:0]
KPX2PR[1:0]
KPX1PR[1:0]
15:14
13:12
11:10
9:8
0x2
0x2
0x2
0x2
0x2
0x2
0x2
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX6 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX5 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX4 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX3 ball:
00: no pull resistor at ball
7:6
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX2 ball:
00: no pull resistor at ball
5:4
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPX1 ball:
00: no pull resistor at ball
3:2
01: pulldown resistor programmed
1x: pullup resistor programmed
(1) Written values of 0x2 and 0x3 will always be read back as 0x3.
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Table 51. IOPC0 - Pull Resistor Configuration Register 0 (continued)
Register - Name
Address
Type
Register Function
Resistor enable for KPX0 ball:
00: no pull resistor at ball
KPX0PR[1:0]
1:0
0x2
01: pulldown resistor programmed
1x: pullup resistor programmed
IOPC1 - Pull Resistor Configuration Register 1
Table 52. IOPC1 - Pull Resistor Configuration Register 1
Register - Name
IOPC1(1)
Address
0xAC
Bit
Type
R/W
Register Function
Defines the pull resistor configuration for balls KPY[7:0].
Bit Function
Bit - Name
Default
Resistor enable for KPY7 ball:
00: no pull resistor at ball
KPY7PR[1:0]
KPY6PR[1:0]
KPY5PR[1:0]
KPY4PR[1:0]
KPY3PR[1:0]
KPY2PR[1:0]
KPY1PR[1:0]
KPY0PR[1:0]
15:14
13:12
11:10
9:8
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
01 :pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY6 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY5 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY4 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY3 ball:
00: no pull resistor at ball
7:6
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY2 ball:
00: no pull resistor at ball
5:4
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY1 ball:
00: no pull resistor at ball
3:2
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY0 ball:
00: no pull resistor at ball
1:0
01: pulldown resistor programmed
1x: pullup resistor programmed
(1) Written values of 0x2 and 0x3 will always be read back as 0x3.
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IOPC2 - Pull Resistor Configuration Register 2
Table 53. IOPC2 - Pull Resistor Configuration Register 2
Register - Name
IOPC2(1)
Address
0xAE
Bit
Type
R/W
Register Function
Defines the pull resistor configuration for balls KPY[11:8].
Bit Function
Bit - Name
(reserved)
Default
0x5A
15:8
(reserved)
Resistor enable for KPY11 ball:
00: no pull resistor at ball
KPY11PR[1:0]
KPY10PR[1:0]
KPY9PR[1:0]
KPY8PR[1:0]
7:6
5:4
3:2
1:0
0x0
0x1
0x1
0x1
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY10 ball:
00: no pull resistor at ball
01 pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY9 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
Resistor enable for KPY8 ball:
00: no pull resistor at ball
01: pulldown resistor programmed
1x: pullup resistor programmed
(1) Written values of 0x2 and 0x3 will always be read back as 0x3.
GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Table 54. GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Register - Name
Address
Type
Register Function
Configures KPX[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS0.
GPIOOME0
0xE0
R/W
Bit - Name
Bit
Default
Bit Function
Open Drain Enable on KPX[7:0]:
0: full buffer
KPX[7:0]ODE
7:0
0x0
1: open drain functionality
GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Table 55. GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPX[7:0] if selected by
GPIOOME0.
GPIOOMS0
0xE1
R/W
Bit - Name
Bit
Default
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
KPX[7:0]ODM
7:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z.
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GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Table 56. GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Register - Name
GPIOOME1
Address
Type
Register Function
Configures KPY[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS1.
0xE2
R/W
Bit - Name
Bit
Default
Bit Function
Open Drain Enable on KPY[7:0]
0: full buffer
KPY[7:0]ODE
7:0
0x0
1: open drain functionality
GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Table 57. GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPY[7:0] if selected by
GPIOOME1.
GPIOOMS1
0xE3
R/W
Bit - Name
Bit
Default
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
KPY[7:0]ODM
7:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z.
GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Table 58. GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Register - Name
Address
Type
Register Function
Configures KPY[11:8] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS2.
GPIOOME2
0xE4
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:4
0x0
Open Drain Enable on KPY[11:8]:
0: full buffer
KPY[11:8]ODE
3:0
0x8
1: open drain functionality
Note: IRQN ball defaults to Open Drain Mode Enable after reset.
GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Table 59. GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPY[11:8] if selected by
GPIOOME2.
GPIOOMS2
0xE5
R/W
Bit - Name
Bit
Default
Bit Function
(reserved
7:4
(reserved)
0: Only nmos transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
KPY[11:8]ODM
3:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z.
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GPIO DATA INPUT/OUTPUT
GPIOPDATA0 - GPIO Data Register 0
Table 60. GPIOPDATA0 - GPIO Data Register 0
Register - Name
Address
Type
Register Function
This register controls GPIO Data & Mask on KPX[7:0].
If one I/O is defined as output (see Table 63), the values written to this
register are masked with MASK and then applied to the associated pin.
GPIODATA0
0xC0
R/W
Any I/O defined as an input (see Table 63) will return the value of the
associated pin regardless of the MASK value when read.
Bit - Name
Bit
Default
Bit Function
Mask Bits for KPX[7:0] when configured as GPIO Output:
1: output is not masked
KPX[7:0]MASK
15:8
0x0
0: output is masked (unchanged)
KPX[7:0] Pin State when configured as GPIO:
WRITE: Pin State = DATA if not Masked
READ: DATA = Current Pin State
KPX[7:0]
7:0
0xFC
GPIOPDATA1 - GPIO Data Register 1
Table 61. GPIOPDATA1 - GPIO Data Register 1
Register - Name
Address
Type
Register Function
This register controls GPIO Data & Mask on KPY[7:0].
If any I/O is defined as output (see Table 64), the value written to this
register are masked with MASK and then applied to the associated pin.
GPIODATA1
0xC2
R/W
Any I/O defined as an input (see Table 64) will return the value of the
associated pin regardless of the MASK value when read.
Bit - Name
Bit
Default
Bit Function
Mask Bits for KPY[7:0] when configured as GPIO Output:
1: output is not masked
KPY[7:0]MASK
15:8
0x0
0: output is masked (unchanged)
KPY[7:0] Pin State when configured as GPIO:
WRITE: Pin State = DATA if not Masked
READ: DATA = Current Pin State
KPY[7:0]
7:0
0x00
GPIOPDATA2 - GPIO Data Register 2
Table 62. GPIOPDATA2 - GPIO Data Register 2
Register - Name
GPIODATA2
Bit - Name
Address
0xC4
Bit
Type
Register Function
This register controls GPIO Data & Mask on KPY[11:8].
If any I/O is defined as an output (see Table 65) the value written to this
register is masked with MASK and then applied to the associated pin.
R/W
Any I/O defined as an input (see Table 65) will return the value of the
associated pin regardless of the MASK value when read.
Default
Bit Function
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Table 62. GPIOPDATA2 - GPIO Data Register 2 (continued)
Register - Name
Address
Type
Register Function
(reserved)
15:12
0x0
(reserved)
Mask Status for KPY[11:8] when enabled as GPIO:
1: Output is not masked
KPY[11:8]
11:8
0x0
0: Output is masked.
reserved
7:4
3:0
0x0
0x0
(reserved)
KPY [11:8] Pin State when configured as GPIO :
WRITE: Pin State = DATA if not Masked
READ: DATA = Current Pin State
KPY[11:8]DATA
GPIOPDIR0 - GPIO Port Direction Register 0
Table 63. GPIOPDIR0 - GPIO Port Direction Register 0
Register - Name
GPIODIR0
Address
Type
R/W
Register Function
0xC6
Port direction for KPX[7:0].
Bit - Name
Bit
Default
Bit Function
Direction bits for KPX[7:0]:
0: input mode
KPX[7:0]DIR
7:0
0x00
1: output mode
GPIOPDIR1 - GPIO Port Direction Register 1
Table 64. GPIOPDIR1 - GPIO Port Direction Register 1
Register - Name
GPIODIR1
Address
0xC7
Bit
Type
R/W
Register Function
Port direction for KPY[7:0]
Bit - Name
Default
Bit Function
Direction bits for KPY[7:0]:
0: input mode
KPY[7:0]DIR
7:0
0x00
1: output mode
GPIOPDIR2 - GPIO Port Direction Register 2
Table 65. GPIOPDIR2 - GPIO Port Direction Register 2
Register - Name
GPIODIR2
Address
Type
R/W
Register Function
0xC8
Bit
Port direction for KPY[11:8]:
Bit - Name
Default
Bit Function
(reserved)
7:4
(reserved)
Direction bits for KPY[11:8]
0: input mode
KPY[11:8]DIR
3:0
0x08
1: output mode
GPIO INTERRUPT CONTROL
GPIOIS0 - Interrupt Sense Configuration Register 0
Table 66. GPIOIS0 - Interrupt Sense Configuration Register 0
Register - Name
GPIOIS0
Address
0xC9
Bit
Type
R/W
Register Function
Interrupt type on KPX[7:0].
Bit - Name
Default
Bit Function
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Table 66. GPIOIS0 - Interrupt Sense Configuration Register 0 (continued)
Register - Name
Address
Type
Register Function
Interrupt type bits for KPX[7:0]:
KPX[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIS1 - Interrupt Sense Configuration Register 1
Table 67. GPIOIS1 - Interrupt Sense Configuration Register 1
Register - Name
GPIOIS1
Address
0xCA
Bit
Type
R/W
Register Function
Interrupt type on KPY[7:0]
Bit - Name
Default
Bit Function
Interrupt type bits for KPY[7:0]:
0: edge sensitive interrupt
1: level sensitive interrupt
KPY[7:0]IS
7:0
0x0
GPIOIS2 - Interrupt Sense Configuration Register 2
Table 68. GPIOIS2 - Interrupt Sense Configuration Register 2
Register - Name
GPIOIS2
Address
0xCB
Bit
Type
R/W
Register Function
Interrupt type on KPY[11:8]
Bit - Name
(reserved)
Default
Bit Function
7:4
(reserved)
Interrupt type bits for KPY[11:8]:
0: edge sensitive interrupt
1: level sensitive interrupt
KPY[11:8]IS
3:0
0x0
GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Table 69. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Register - Name
Address
0xCC
Bit
Type
Register Function
Defines whether an interrupt on KPX[7:0] is triggered on either edge or on
a single edge. See Table 72 for the edge configuration.
GPIOIBE0
R/W
Bit - Name
Default
Bit Function
Interrupt both edges bits for KPX[7:0]:
0: interrupt generated at the active edge
1: interrupt generated after either edge.
KPX[7:0]IBE
7:0
0x0
GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Table 70. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Register - Name
Address
0xCD
Bit
Type
Register Function
Defines whether an interrupt on KPY[7:0] is triggered on either edge or on
a single edge. See Table 73 for the edge configuration.
GPIOIBE1
R/W
Bit - Name
Default
Bit Function
Interrupt both edges bits for KPY[7:0]:
0: interrupt generated at the active edge.
1: interrupt generated after either edge.
KPY[7:0]IBE
7:0
0x0
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GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[11:8] was triggered on either edge or
on a single edge. See Table 74 for the edge configuration.
GPIOIBE2
0xCE
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved
7:4
Interrupt both edges bits for KPY[11:8]:
0: interrupt generated at the active edge.
1: interrupt generated after either edge.
KPY[11:8]IBE
3:0
0x0
GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Table 72. GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Register - Name
GPIOIEV0
Address
0xCF
Bit
Type
R/W
Register Function
Select Interrupt edge for KPX[7:0].
Bit - Name
Default
Bit Function
Interrupt edge select from KPX[7:0]:
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPX[7:0]EV
7:0
0xFF
GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Table 73. GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Register - Name
GPIOIEV1
Address
0xD0
Bit
Type
R/W
Register Function
Select Interrupt edge for KPY[7:0].
Bit - Name
Default
Bit Function
Interrupt edge select from KPY[7:0]:
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPY[7:0]EV
7:0
0xFF
GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Table 74. GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Register - Name
GPIOIEV2
Address
0xD1
Bit
Type
R/W
Register Function
Select Interrupt edge for KPY[11:8].
Bit - Name
(reserved)
Default
Bit Function
7:4
(reserved)
Interrupt edge select from KPY[11:8]:
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPY[11:8]EV
3:0
0xFF
GPIOIE0 - GPIO Interrupt Enable Register 0
Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0
Register - Name
GPIOIE0
Address
Type
R/W
Register Function
Enable/disable interrupts on KPX[7:0].
Bit Function
0xD2
Bit - Name
Bit
Default
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Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0 (continued)
Register - Name
Address
Type
Register Function
Interrupt enable on KPX[7:0]:
KPX[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
GPIOIE1 - GPIO Interrupt Enable Register 1
Table 76. GPIOIE1 - GPIO Interrupt Enable Register 1
Register - Name
GPIOIE1
Address
Type
R/W
Register Function
Enable/disable interrupts on KPY[7:0].
Bit Function
0xD3
Bit - Name
Bit
Default
Interrupt enable on KPY[7:0]:
0: disable interrupt
KPY[7:0]IE
7:0
0x0
1: enable interrupt
GPIOIE2 - GPIO Interrupt Enable Register 2
Table 77. GPIOIE2 - GPIO Interrupt Enable Register 2
Register - Name
GPIOIE2
Address
Type
R/W
Register Function
Enable/disable interrupts on KPY[11:8].
Bit Function
0xD4
Bit
Bit - Name
(reserved)
Default
7:4
(reserved)
Interrupt enable on KPY[11:8]:
0: disable interrupt
1: enable interrupt
KPY[11:8]IE
3:0
0x0
GPIOIC0 - GPIO Clear Interrupt Register 0
Table 78. GPIOIC0 - GPIO Clear Interrupt Register 0
Register - Name
GPIOIC0
Address
0xDC
Bit
Type
W
Register Function
Clears the interrupt on KPX[7:0].
Bit - Name
Default
Bit Function
Clear Interrupt on KPX[7:0]:
0: no effect
KPX[7:0]IC
7:0
1: Clear corresponding interrupt
GPIOIC1 - GPIO Clear Interrupt Register 1
Table 79. GPIOIC1 - GPIO Clear Interrupt Register 1
Register - Name
GPIOIC1
Address
0xDD
Bit
Type
W
Register Function
Clears the interrupt on KPY[7:0].
Bit - Name
Default
Bit Function
Clear Interrupt on KPY[7:0]:
0: no effect
KPY[7:0]IC
7:0
1: Clear corresponding interrupt
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GPIOIC2 - GPIO Clear Interrupt Register 2
Table 80. GPIOIC2 - GPIO Clear Interrupt Register 2
Register - Name
GPIOIC2
Address
0xDE
Bit
Type
W
Register Function
Clears the interrupt on KPY[11:8].
Bit Function
Bit - Name
(reserved)
Default
7:4
(reserved)
Clear Interrupt on KPY[11:8]:
0: no effect
KPY[11:8]IC
3:0
1: Clear corresponding interrupt
GPIO INTERRUPT STATUS
GPIORIS0 - Raw Interrupt Status Register 0
Table 81. GPIORIS0 - Raw Interrupt Status Register 0
Register - Name
GPIORIS0
Address
Type
R
Register Function
Raw interrupt status on KPX[7:0]
Bit Function
0xD6
Bit - Name
Bit
Default
Raw Interrupt status data on KPX[7:0]:
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPX[7:0]RIS
7:0
0x0
GPIORIS1 - Raw Interrupt Status Register 1
Table 82. GPIORIS1 - Raw Interrupt Status Register 1
Register - Name
GPIORIS1
Address
Type
R
Register Function
Raw interrupt status on KPY[7:0].
Bit Function
0xD7
Bit - Name
Bit
Default
Raw Interrupt status data on KPY[7:0]:
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPY[7:0]RIS
7:0
0x0
GPIORIS2 - Raw Interrupt Status Register 2
Table 83. GPIORIS2 - Raw Interrupt Status Register 2
Register - Name
GPIORIS2
Address
Type
R
Register Function
Raw interrupt status on KPY[11:8].
Bit Function
0xD8
Bit
Bit - Name
(reserved)
Default
7:4
(reserved)
Raw Interrupt status data on KPY[11:8]:
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPY[11:8]RIS
3:0
0x0
GPIOMIS0 - Masked Interrupt Status Register 0
Table 84. GPIOMIS0 - Masked Interrupt Status Register 0
Register - Name
GPIOMIS0
Address
0xD9
Bit
Type
R
Register Function
Masked interrupt status on KPX[7:0].
Bit - Name
Default
Bit Function
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Table 84. GPIOMIS0 - Masked Interrupt Status Register 0 (continued)
Register - Name
Address
Type
Register Function
Masked Interrupt status data on KPX[7:0]:
KPX[7:0]MIS
7:0
0x0
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIOMIS1 - Masked Interrupt Status Register 1
Table 85. GPIOMIS1 - Masked Interrupt Status Register 1
Register - Name
GPIOMIS1
Address
0xDA
Bit
Type
R
Register Function
Masked interrupt status on KPY[7:0].
Bit - Name
Default
Bit Function
Masked Interrupt status data on KPY[7:0]:
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
KPY[7:0]MIS
7:0
0x0
GPIOMIS2 - Masked Interrupt Status Register 2
Table 86. GPIOMIS2 - Masked Interrupt Status Register 2
Register - Name
GPIOMIS2
Address
0xDB
Bit
Type
R
Register Function
Masked interrupt status on KPY[11:8].
Bit Function
Bit - Name
Default
(reserved)
7:4
(reserved)
Masked Interrupt status data on KPY[11:8]:
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
KPY[11:8]MIS
3:0
0x0
GPIO WAKE-UP CONTROL
GPIOWAKE0 - GPIO Wake-Up Register 0
Table 87. GPIOWAKE0 - GPIO Wake-Up Register 0
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPX[7:0].
GPIOWAKE0
0xE9
R/W
Each bit corresponds to a ball. When a bit is set, the corresponding ball
contributes to wakeup from auto-sleep mode.
Bit - Name
Bit
Default
Bit Function
Wake up from auto sleep on KPY[7:0]
0: wake up from auto sleep disabled
1: wake up from auto sleep enabled
KPX[7:0]WAKE
7:0
0x0
GPIOWAKE1 - GPIO Wake-Up Register 1
Table 88. GPIOWAKE1 - GPIO Wake-Up Register 1
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[7:0].
GPIOWAKE1
0xEA
R/W
Each bit corresponds to a ball. When a bit is set, the corresponding ball
contributes to wakeup from auto-sleep mode.
Bit - Name
Bit
Default
Bit Function
Wake up from Auto sleep on KPY[7:0]
0: wake up from auto sleep disabled
1: wake up from auto sleep enabled
KPY[7:0]WAKE
7:0
0x0
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GPIOWAKE2 - GPIO Wake-Up Register 2
Table 89. GPIOWAKE2 - GPIO Wake-Up Register 2
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[11:8].
GPIOWAKE2
0xEB
R/W
Each bit corresponds to a ball. When a bit is set, the corresponding ball
contributes to wakeup from auto-sleep mode.
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Wake up from auto sleep on KPY[11:8]
0: wake up from auto sleep disabled
1: wake up from auto sleep enabled
KPY[11:8]WAKE
3:0
0x0
REGISTERS
REGISTER MAPPING
Registers defined as word access size must have both the lower and upper bytes written in one ACCESS.Bus
cycle before the internal register will be updated. If these registers are written as separate bytes, the value will be
discarded, and the internal register will be unchanged. Registers defined as byte access can be written
individually.
Keyboard Registers
shows the register map for keyboard functionality. In addition to RESET_N,POR or Software Reset using
SWRESET (see Table 41) or Software Reset using SWRESET (see Table 41), these registers are reset to
default values by a module reset using RSTCTRL.KBDRST and should be rewritten for desired settings (see
Table 42).
Register Map for Keyboard Functionality
Register File
Address
Next RF
Address
Register Name
KBDSETTLE
KBDBOUNCE
KBDSIZE
Description
Register Type
ACCESS Size
Default value
0x80
Keypad Settle
Time
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
R/W
R/W
R/W
R/W
R/W
R
byte
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Keypad Debounce
Time
byte
0x80
Keypad Size
Configuration
byte
0x22
Keypad Dedicated
Key 0
KBDDEDCFG0
KBDDEDCFG1
KBDRIS
byte
0xFF
Keypad Dedicated
Key 1
byte
0xFF
Keypad Raw
Interrupt Status
byte
0x00
Keypad Masked
Interrupt Status
KBDMIS
R
byte
0x00
Keypad Interrupt
Clear
KBDIC
W
byte
Keypad Interrupt
Mask
KBDMSK
R/W
byte
0x03
KBDCODE0
KBDCODE1
KBDCODE2
KBDCODE3
EVTCODE
Keypad Code 0
Keypad Code 1
Keypad Code 2
Keypad Code 3
Key Event Code
0x0B
0x0C
0x0D
0x0E
0x10
R
R
R
R
R
byte
byte
byte
byte
byte
0x7F
0x7F
0x7F
0x7F
0x7F
0x0C
0x0D
0x0E
0x0F
0x10
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PWM Timer Registers
shows the register map for PWM Timer functionality. In addition to RESET_N, POR and software reset using
SWRESET (see Table 41), these registers are reset to default values by a module reset using
RSTCTRL.TIMRST (see RSTCTRL - System Reset Register).
Register Map for PWM Timer Functionality
Register File
Address
Next RF
Address
Register Name
TIMCFG0
PWMCFG0
TIMCFG1
PWMCFG1
TIMCFG2
PWMCFG2
TIMSWRES
TIMRIS
Description
Register Type
ACCESS Size
Default value
0x00
PWM Timer
Configuration 0
0x60
0x61
0x68
0x69
0x70
0x71
0x78
0x7A
0x7B
0x7C
0x7D
0x7E
R/W
R/W
R/W
R/W
R/W
R/W
W
byte
0x61
0x62
0x69
0x6A
0x71
0x72
0x79
0x7B
0x7C
0x7D
0x7E
0x7F
PWM Configuration
0
byte
0x00
PWM Timer
Configuration 1
byte
0x00
PWM Configuration
1
byte
0x00
PWM Timer
Configuration 2
byte
0x00
PWM Configuration
2
byte
0x00
PWM Timer SW
Reset
byte
PWM Timer
Interrupt Status
R
byte
0x00
0x00
PWM Timer
Masked Int. Status
TIMMIS
R
byte
Timer Interrupt
Clear
TIMIC
W
byte
PWM Command
Write Pointer
PWMWP
R/W
W
byte
0x00
PWM Command
Script
PWMCFG
word
System Registers
shows the register map for general system registers. These registers are not affected by any of the module
resets addressed by RSTCTRL (see Table 42). These registers can only be reset to default values by a Global
Call Reset (see GENERAL CALL RESET) or by a complete Software Reset using SWRESET (see Table 41).
Register Map for System Control Functionality
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default value
Next RF
Address
I2C-compatible
ACCESS.bus Slave
Address
I2CSA
0x80
W
byte
0x88
0x81
MFGCODE
SWREV
Manufacturer Code
SW Revision
SW Reset
0x80
0x81
0x81
0x82
R
R
byte
byte
byte
byte
0x00
0x84
0x81
0x82
0x82
0x83
SWRESET
RSTCTRL
W
System Reset
R/W
0x00
Clear No Init/Power On
Interrupt
RSTINTCLR
0x84
W
byte
0x85
CLKMODE
CLKEN
Clock Mode
Clock Enable
0x88
0x8A
0x8B
0x8C
R/W
R/W
R/W
R/W
byte
byte
byte
word
0x00
0x00
0x89
0x8B
0x8C
0x8D
AUTOSLP
AUTOSLPTI
Auto-Sleep Enable
Auto-Sleep Time
0x00
0x00FF
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Global Interrupt Registers
shows the register map for global interrupt functionality. This register is reset to the default value by RESET_N,
POR or Software Reset using SWRESET (see Table 41). This register is not affected by a module reset using
RSTCTRL.IRQRST (see Table 42). Any interrupt that occurs while RSTCTRL.IRQRST is active will still be
captured.
Register Map for Global Interrupt Functionality
Register Name
IRQST
Description
Register File
Address
Register Type
ACCESS Size
Default value
Next RF
Address
Global Interrupt Status
0x91
R
byte
0x80
0x92
GPIO Registers
shows the register map for GPIO functionality. In addition to RESET_N, POR and software reset using
SWRESET (see Table 41), these registers are reset to default values by a module reset using
RSTCTRL.GPIRST (see Table 42).
Register Map for GPIO Functionality
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default value
Next RF
Address
I/O Pin Mapping
Configuration
IOCFG
IOPC0
IOPC1
IOPC2
0xA7
0xAA
0xAC
0xAE
W
byte
word
word
word
0xA8
0xAB
0xAD
0xAF
Pull Resistor
Configuration 0
R/W
R/W
R/W
0xAAAA
0x5555
Pull Resistor
Configuration 1
Pull Resistor
Configuration 2
0x5A15
0xFC
GPIODATA0
GPIOMASK0
GPIODATA1
GPIOMASK1
GPIODATA2
GPIOMASK2
GPIO I/O Data 0
GPIO I/O Mask 0
GPIO I/O Data 1
GPIO I/O Mask 1
GPIO I/O Data 2
GPIO I/O Mask 2
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
R/W
W
byte
byte
byte
byte
byte
byte
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
R/W
W
0x00
0x00
R/W
W
GPIO I/O
Direction 0
GPIODIR0
GPIODIR1
GPIODIR2
GPIOIS0
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0x00
0x00
0x08
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
GPIO I/O
Direction 1
GPIO I/O
Direction 2
GPIO Int Sense
Config 0
GPIO Int Sense
Config 1
GPIOIS1
GPIO Int Sense
Config 2
GPIOIS2
GPIO Int Both
Edges Config 0
GPIOIBE0
GPIOIBE1
GPIOIBE2
GPIOIEV0
GPIOIEV1
GPIO Int Both
Edges Config 1
GPIO Int Both
Edges Config 2
GPIO Int Edge
Select 0
GPIO Int Edge
Select 1
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Register Map for GPIO Functionality (continued)
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default value
Next RF
Address
GPIO Int Edge
Select 2
GPIOIEV2
GPIOIE0
0xD1
0xD2
0xD3
0xD4
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE9
0xEA
0xEB
R/W
R/W
R/W
R/W
R
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0x0F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xD2
GPIO Interrupt
Enable 0
0xD3
0xD4
0xD5
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xEA
0xEB
0xEC
GPIO Interrupt
Enable 1
GPIOIE1
GPIO Interrupt
Enable 2
GPIOIE2
GPIO Raw Int
Status 0
GPIORIS0
GPIORIS1
GPIORIS2
GPIOMIS0
GPIOMIS1
GPIOMIS2
GPIOIC0
GPIO Raw Int
Status 1
R
GPIO Raw Int
Status 2
R
GPIO Masked Int
Status 0
R
GPIO Masked Int
Status 1
R
GPIO Masked Int
Status 2
R
GPIO Interrupt
Clear 0
W
GPIO Interrupt
Clear 1
GPIOIC1
W
GPIO Interrupt
Clear 2
GPIOIC2
W
GPIO Open Drain
Mode Enable 0
GPIOOME0
GPIOOMS0
GPIOOME1
GPIOOMS1
GPIOOME2
GPIOOMS2
GPIOWAKE0
GPIOWAKE1
GPIOWAKE2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x08
0x00
0x00
0x00
0x00
GPIO Open Drain
Mode Select 0
GPIO Open Drain
Mode Enable 1
GPIO Open Drain
Mode Select 1
GPIO Open Drain
Mode Enable 2
GPIO Open Drain
Mode Select 2
GPIO Wakeup
Enable 0
GPIO Wakeup
Enable 1
GPIO Wakeup
Enable 2
REGISTER LAYOUT - Control Bits in LM8330 Registers
Register
Addr.
0x01
0x02
BIT 7
BIT 6
BIT 5
BIT 4
Wait[7:0]
Wait[7:0]
ROW-
BIT 3
BIT 2
BIT 1
BIT 0
KBDSETTLE
KBDBOUNCE
ROW-
SIZE3
ROW-
SIZE2
ROW-
SIZE1
COL-
SIZE3
COL-
SIZE2
COL-
SIZE1
COL-
SIZE0
KBDSIZE
0x03
SIZE0
COL6
ROW4
KBDDEDCFG0
KBDDEDCFG1
KBDRIS
0x04
0x05
0x06
COL9
COL8
COL7
COL5
ROW3
RELINT
COL4
ROW2
COL3
COL11
RKLINT
COL2
COL10
RSINT
ROW7
ROW6
ROW5
REVTINT
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REGISTER LAYOUT - Control Bits in LM8330 Registers (continued)
Register
KBDMIS
Addr.
0x07
0x08
0x09
0x0B
0x0C
0x0D
0x0E
0x10
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
MKLINT
EVTIC
BIT 0
MSINT
MELINT
MEVTINT
KBDIC
SFOFF
KBDIC
KBDMSK
MSKELINT
KEYCOL3
KEYCOL3
KEYCOL3
KEYCOL3
KEYCOL3
MSKEINT
KEYCOL2
KEYCOL2
KEYCOL2
KEYCOL2
KEYCOL2
MSKLINT
MSKSINT
KBDCODE0
KBDCODE1
KBDCODE2
KBDCODE3
EVTCODE
MULTIKEY KEYROW2 KEYROW1 KEYROW0
MULTIKEY KEYROW2 KEYROW1 KEYROW0
MULTIKEY KEYROW2 KEYROW1 KEYROW0
MULTIKEY KEYROW2 KEYROW1 KEYROW0
KEYCOL1 KEYCOL0
KEYCOL1 KEYCOL0
KEYCOL1 KEYCOL0
KEYCOL1 KEYCOL0
KEYCOL1 KEYCOL0
RELEASE
KEYROW2 KEYROW1 KEYROW0
CYCIRQ0-
MASK
TIMCFG0
PWMCFG0
TIMCFG1
PWMCFG1
TIMCFG2
PWMCFG2
0x60
0x61
0x68
0x69
0x70
0x71
START
CDIRQ0-
MASK
PGE
PGE
PGE
PWMEN
PWMEN
PWMEN
PWMPOL
START
CYCIRQ1-
MASK
CDIRQ1-
MASK
PWMPOL
START
CYCIRQ2-
MASK
CDIRQ2-
MASK
PWMPOL
TIMSWRES
TIMRIS
0x78
0x7A
0x7B
0x7C
0x7D
SWRES2
CICIRQ2
CICIRQ2
CICIRQ2
SWRES1
CICIRQ1
CICIRQ1
CICIRQ1
SWRES0
CICIRQ0
CICIRQ0
CICIRQ0
CDIRQ2
CDIRQ2
CDIRQ2
CDIRQ1
CDIRQ1
CDIRQ1
CDIRQ0
CDIRQ0
TIMMIS
TIMIC
CDIRQ0
PWMWP
0
PWMWP[6:0]
PWMCFG(Low
)
0x7E
0x7F
CMD[7:0]
CMD[15:8]
SLAVEADDR[7:1]
PWMCFG(Hig
h)
I2CSA
MFGCODE
SWREV
0x80
0x80
0x81
0x81
0x82
0x84
0x88
0x8A
0x8B
0
MFGBIT[7:0]
SWBIT[7:0]
SWBIT[7:0]
SWRESET
RSTCTRL
RSTINTCLR
CLKMODE
CLKEN
IRQRST
TIMRST
KBDRST
GPIRST
IRQCLR
MOD-CTL[1:0]
TIMEN
KBDEN
AUTOSLP
ENABLE
AUTOSLPTI
(Low)
0x8C
0x8D
UP-TIME [7:0]
UP-TIME [15:8]
AUTOSLPTI
(High)
IRQST
0x91
0xA7
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
PORIRQ
KBD1RQ
TIM2IRQ
IOCFGPM [7:0]
KPX2PR[1:0]
TIM1IRQ
TIM01RQ
GPIIRQ
IOCFG
IOPC0 (Low)
IOPC0 (High)
IOPC1 (Low)
IOPC1 (High)
IOPC2 (Low)
IOPC2 (High)
KPX3PR[1:0]
KPX1PR[1:0]
KPX0PR[1:0]
KPX7PR[1:0]
KPY3PR[1:0]
KPY7PR[1:0]
KPY11PR[1:0]
KPX6PR[1:0]
KPY2PR[1:0]
KPY6PR[1:0]
KPY10PR[1:0]
KPX5PR[1:0]
KPY1PR[1:0]
KPY5PR[1:0]
KPY9PR[1:0]
KPX4PR[1:0]
KPY0PR[1:0]
KPY4PR[1:0]
KPY8PR[1:0]
reserved
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REGISTER LAYOUT - Control Bits in LM8330 Registers (continued)
Register
GPIODATA0
GPIOMASK0
GPIODATA1
GPIOMASK1
GPIODATA2
GPIOMASK2
GPIODIR0
GPIODIR1
GPIODIR2
GPIOIS0
Addr.
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xE0
0xE1
0xE2
0xE3
BIT 7
DATA7
MASK7
DATA15
MASK15
BIT 6
DATA6
MASK6
DATA14
MASK14
BIT 5
DATA5
MASK5
DATA13
MASK13
BIT 4
DATA4
MASK4
DATA12
MASK12
BIT 3
BIT 2
BIT 1
BIT 0
DATA3
DATA2
DATA1
DATA0
MASK3
MASK2
MASK1
MASK0
DATA11
MASK11
DATA19
MASK19
KPX3DIR
KPY3DIR
KP11DIR
KPX3IS
DATA10
DATA10
DATA18
MASK18
KPX2DIR
KPY2DIR
KPY10DIR
KPX2IS
DATA9
DATA8
DATA9
DATA8
DATA17
MASK17
KPX1DIR
KPY1DIR
KPY9DIR
KPX1IS
KPY1IS
KPY9IS
KPX1IBE
KPY1IBE
KPY9IBE
KPX1EV
KPY1EV
KPY9IEV
KPX1IE
KPY1IE
KPY9IE
KPX1RIS
KPY1RIS
KPY9RIS
KPX1MIS
KPY1MIS
KPY9MIS
KPX1IC
KPY1IC
KPY9IC
DATA16
MASK16
KPX0DIR
KPY0DIR
KPY8DIR
KPX0IS
KPY0IS
KPY8IS
KPX0IBE
KPY0IBE
KPY8IBE
KPX0EV
KPY0EV
KPY8IEV
KPX0IE
KPY0IE
KPY8IE
KPX0RIS
KPY0RIS
KPY8RIS
KPX0MIS
KPY0MIS
KPY8MIS
KPX0IC
KPY0IC
KPY8IC
KPX7DIR
KPY7DIR
KPX6DIR
KPY6DIR
KPX5DIR
KPY5DIR
KPX4DIR
KPY4DIR
KPX7IS
KPY7IS
KPX6IS
KPY6IS
KPX5IS
KPY5IS
KPX4IS
KPY4IS
GPIOIS1
KPY3IS
KPY2IS
GPIOIS2
KPY11IS
KPX3IBE
KPY3IBE
KPY11IBE
KPX3EV
KPY3EV
KPY11IEV
KPX3IE
KPY10IS
KPX2IBE
KPY2IBE
KPY10IBE
KPX2EV
KPY2EV
KPY10IEV
KPX2IE
GPIOIBE0
GPIOIBE1
GPIOIBE2
GPIOIEV0
GPIOIEV1
GPIOIEV2
GPIOIE0
KPX7IBE
KPY7IBE
KPX6IBE
KPY6IBE
KPX5IBE
KPY5IBE
KPX4IBE
KPY4IBE
KPX7EV
KPY7EV
KPX6EV
KPY6EV
KPX5EV
KPY5EV
KPX4EV
KPY4EV
KPX7IE
KPY7IE
KPX6IE
KPY6IE
KPX5IE
KPY5IE
KPX4IE
KPY4IE
GPIOIE1
KPY3IE
KPY2IE
GPIOIE2
KPY11IE
KPX3RIS
KPY3RIS
KPY11RIS
KPX3MIS
KPY3MIS
KPY10IE
KPX2RIS
KPY2RIS
KPY10RIS
KPX2MIS
KPY2MIS
GPIORIS0
GPIORIS1
GPIORIS2
GPIOMIS0
GPIOMIS1
GPIOMIS2
GPIOIC0
KPX7RIS
KPY7RIS
KPX6RIS
KPY6RIS
KPX5RIS
KPY5RIS
KPX4RIS
KPY4RIS
KPX7MIS
KPY7MIS
KPX6MIS
KPY6MIS
KPX5MIS
KPY5MIS
KPX4MIS
KPY4MIS
KPY11MIS KPY10MIS
KPX7IC
KPY7IC
KPX6IC
KPY6IC
KPX5IC
KPY5IC
KPX4IC
KPY4IC
KPX3IC
KPY3IC
KPX2IC
KPY2IC
GPIOIC1
GPIOIC2
KPY11IC
KPX3ODE
KPY10IC
KPX2ODE
GPIOOME0
GPIOOMS0
GPIOOME1
GPIOOMS1
KPX7ODE
KPX6ODE
KPX5ODE
KPX4ODE
KPX1ODE KPX0ODE
KPX7ODM KPX6ODM KPX5ODM KPX4ODM KPX3ODM KPX2ODM KPX1ODM KPX0ODM
KPY7ODE KPY6ODE KPY5ODE KPY4ODE KPY3ODE KPY2ODE KPY1ODE KPY0ODE
KPY7ODM KPY6ODM KYY5ODM KPY4ODM KPY3ODM KPY2ODM KPY1ODM KPY0ODM
KPY11
ODE
KPY10
ODE
KPY9
ODE
KPY8
ODE
GPIOOME2
GPIOOMS2
GPIOWAKE0
GPIOWAKE1
GPIOWAKE2
0xE4
0xE5
0xE9
0xEA
0xEB
KPY11
ODM
KPY10
ODM
KPY9
ODM
KPY8
ODM
KPX7
WAKE
KPX6
WAKE
KPX5
WAKE
KPX4
WAKE
KPX3
WAKE
KPX2
WAKE
KPX1
WAKE
KPX0
WAKE
KPY7
WAKE
KPY6
WAKE
KPY5
WAKE
KPY4
WAKE
KPY3
WAKE
KPY2
WAKE
KPY1
WAKE
KPY0
WAKE
KPY11
WAKE
KPY10
WAKE
KPY9
WAKE
KPY8
WAKE
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SNVS839A –JUNE 2012–REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 45
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM8330TME/NOPB
LM8330TMX/NOPB
ACTIVE
ACTIVE
DSBGA
DSBGA
YFQ
YFQ
25
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-30 to 85
-30 to 85
8330
8330
3000 RoHS & Green
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM8330TME/NOPB
LM8330TMX/NOPB
DSBGA
DSBGA
YFQ
YFQ
25
25
250
178.0
178.0
8.4
8.4
2.08
2.08
2.08
2.08
0.76
0.76
4.0
4.0
8.0
8.0
Q1
Q1
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM8330TME/NOPB
LM8330TMX/NOPB
DSBGA
DSBGA
YFQ
YFQ
25
25
250
208.0
208.0
191.0
191.0
35.0
35.0
3000
Pack Materials-Page 2
MECHANICAL DATA
YFQ0025xxx
D
0.600
±0.075
E
TMD25XXX (Rev C)
D: Max = 2.04 mm, Min = 1.98 mm
E: Max = 2.04 mm, Min = 1.98 mm
4215084/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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