LM8342SDX/NOPB [TI]
具有非易失性存储器的可编程 TFT Vcom 校准器 | DSC | 10 | -40 to 85;
| 型号： | LM8342SDX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有非易失性存储器的可编程 TFT Vcom 校准器 | DSC | 10 | -40 to 85 光电二极管 商用集成电路 存储 |
| 文件： | 总24页 (文件大小：548K) |
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LM8342
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SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013
LM8342 Programmable TFT V Calibrator with Non-Volatile Memory
COM
Check for Samples: LM8342
1
FEATURES
DESCRIPTION
The LM8342 is an integrated combination of a non-
volatile register (7 bits EEPROM) and a DAC
controlled current source. Using the LM8342, the
VCOM calibration procedure is simplified by elimination
of the potentiometer adjustment task. This adjustment
task is currently performed at the factory using a
trimmer adjustment tool and visual inspection.
2
•
I2C Compatible Programmable DAC to Set the
Output Current
•
•
•
•
•
•
Ensured Monotonic DAC
Non-Volatile Memory to Hold the Setting
EEPROM in System Programmable
No External Programming Voltage Required
Maximum Interface Bus Speed is 400 kHz
SON-10 Package
The VCOM adjustment can be done electronically in
production, using the I2C compatible interface. The
factory operator can physically view the screen head-
on (frontal viewing) when performing this step, easing
manufacturing especially for large TFT panels.
APPLICATIONS
•
•
•
TFT Panel Factory Calibration
Digital Potentiometer
The VCOM level is typically at half AVDD (determined
by R1 and R2) and is buffered by the actual VCOM
driver. By controlling the level of IOUT, the VCOM level
can be tuned. The current level at the output of the
LM8342 is a fraction (1/128 to 128/128) of a
maximum current which is set by RSET and an analog
reference (AVDD). The actual fraction is determined
by the 7-bit DAC. As a result, the output current of
the LM8342 has a good temperature stability yielding
a very stable VCOM adjustment. Controlling the DAC
setting of the LM8342 is done via its I2C compatible
interface. The actual DAC setting is stored in a
volatile register. Using a “Write to EE” command the
data can be stored permanently in the embedded
EEPROM. At power on of the device, the EEPROM
data is copied to the volatile register, setting the DAC.
At any time, the data in the EEPROM can be
changed again via the I2C compatible interface.
Programmable Current Sink
Typical Application
V
DD
AV
DD
6
2
AV
DD
V
DD
15 kW
15 kW
15 kW
R1
V
COM
OUT
SDA
+
7
1
-
I
OUT
SCL
R2
8
LM8342
SCL-S
9
3
SET
CONTROLLER
WP
N
10
R
SET
WP
P
GND
4
5
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM8342
SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
SCL, SDA Pins
All Other Pins
4 kV
2.5 kV
Human Body Model
Machine Model
ESD Tolerance(2)
250V
VDD
5V
Supply and Reference Voltage
AVDD
20V
Storage Temperature Range
Junction Temperature(3)
−65°C to +150°C
+150°C
235°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Soldering Information
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and test conditions,
see the Electrical Characteristics tables.
(2) Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0Ω in series with 200 pF.
(3) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Operating Temperature Range(2)
−40°C to 85°C
2.25V to 3.6V
2.6V to 3.6V
4.5V to 18V
52°C/W
(3)
Digital Supply (VDD
)
Digital Supply (VDD) @ Programming
(3)
Analog Reference (AVDD
)
(4)
Package Thermal Resistance θJA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and test conditions,
see the Electrical Characteristics tables.
(2) Programming temperature range 0°C to 70°C .
(3) When AVDD is in the voltage range of 4.5V to 13V, the supply voltage VDD can be in 2.25V to 3.6V range. When AVDD is in the voltage
range from 13V to 18V, the supply voltage VDD is limited to the 2.6V to 3.6V range
(4) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
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SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013
Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ.
Boldface limits apply at the temperature extremes.(1)
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Supply and Reference Current
IDD
Supply Current
Analog Reference Current
40
8
62
13
μA
μA
AIDD
Control and Programming
Low Voltage
High Voltage
Input Current
Frequency
0.3 * VDD
V
0.7 * VDD
SCL, SDA
1
μA
kHz
V
400
WPP/WPN Low Level
WPP/WPN High Level
WPN Input Current
0.3 * VDD
0.7 * VDD
V
VIH = 3.0V(4)
100
150
5
µA
Ω
RON
SCL to SCL-S Switch Resistance
SDA/SCL Input Capacitance
pF
pF
SCL-S Input Capacitance
3
No Supply, VSDA
VSCL = 3.6V
,
SDA/SCL/SCL-S load current
1
μA
Programming Time
IDD @ Programming
Programming Cycles
Reading Cycles
See(5)
200
10
300
18
ms
mA
1000
10000
Output
Output Settling Time
Start-Up Time
95% of Final Value
10
30
μs
μs
VOUT
IOUT
VRSET
+ 0.5V
Output Voltage
AVDD
V
Adjustability
7
Bits
Differential Non-Linearity
Zero Scale Error
−1
−1
−4
5
1
1.5
4
AVDD = 10V,
VOUT = 5V
Output Current
LSB
Full Scale Error
Full Scale Range
100
1
μA
Voltage Drift VRSET
−1
LSB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) All limits are ensured by design or statistical analysis.
(3) Typical values represent the parametric norm at the time of characterization.
(4) On-Chip Pull Down Resistor of 30 kΩ.
(5) Programming temperature range 0°C to 70°C .
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CONNECTION DIAGRAM
1
2
3
4
5
10
9
OUT
SET
AV
SCL-S
DD
WP
8
SCL
SDA
N
P
DAP
WP
7
6
V
GND
DD
Figure 1. 10-Pin SON
Top View
PIN DESCRIPTIONS
Pin Name
OUT
Pin #
Function
1
2
3
Current sink output, adjustable in 128 steps. See Application Section for details.
Analog reference voltage input
AVDD
WPN
Write protect (input)
READ (I2C)
yes
WRITE→Reg
WRITE→EE
SCL Switch
WPN = Low
WPN = High
yes
yes
no
open
yes
yes
closed
WPP
GND
VDD
4
5
Inverted WPN (output)
Ground
6
Supply voltage
SDA
SCL
SCL-S
SET
DAP
7
I2C compatible serial data input/output
I2C compatible serial clock input
8
9
Switched SCL connection. Serial clock input when WPN is set to high
Maximum output current adjustment pin (see block diagram)
Left floating or connect to GND
10
4
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SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013
Block Diagram
V
AV
DD
DD
2
LM8342
6
EE
MEMORY
19R
OUT
1
2
SDA
SCL
I C COMPATIBLE
7
8
INTERFACE CONTROL
7 BITS
WP
REF
INPUT
+
-
DAC
SCL-S
SET
10
9
WP
N
R
3
4
5
GND
WP
P
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Typical Performance Characteristics
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IDD vs. VDD
IDD vs. Temperature
60
55
50
45
60
55
50
45
40
35
30
25
20
85°C
V
= 3.6V
DD
V
= 3.0V
DD
40
35
25°C
30
25
20
V
= 2.25V
DD
-40°C
-40
-15
10
35
60
85
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
DD
(V)
TEMPERATURE (°C)
Figure 2.
Figure 3.
AVDD Startup (Full Scale)
VDD Startup (Full Scale)
INTERMEDIATE STARTUP
CODE (MID SCALE)
R
R
= 10 kW
SET
= 40 kW
L
V
AV
DD
OUT
V
DD
V
OUT
0V
R
R
= 10 kW
SET
0V
= 40 kW
L
TIME (20 ms/DIV)
TIME (20 ms/DIV)
Figure 4.
Figure 5.
IOUT vs. RSET
IOUT vs. RSET
10000
1000
100
10
10000
1000
100
10
V
= 3.6V
DD
V
= 3V
DD
AV
DD
= 18V
V
= 2.25V
DD
AV
= 4.5V
DD
AV
DD
= 10V
AV
= 10V
= 5V
DD
V
OUT
1
0.1
1
0.1
1
10
100
1
10
100
R
(kW)
R
(kW)
SET
SET
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IOUT Current Step Negative (Full Scale)
IOUT Current Step Positive (Full Scale)
TIME (10 ms/DIV)
TIME (10 ms/DIV)
Figure 8.
Figure 9.
IOUT vs. VOUT
IOUT Error vs. VOUT
20
1
0.8
0.6
0.4
0.2
0
FULL SCALE
MID SCALE
18
16
14
12
10
8
ZERO SCALE
-0.2
-0.4
-0.6
-0.8
-1
MID SCALE
FULL SCALE
6
4
ZERO SCALE
2
0
0
2
4
6
8
10 12 14 16 18
1
2
3
4
5
6
7
8
9
10
V
V
(V)
OUT (V)
OUT
Figure 10.
Figure 11.
Differential Non-Linearity Error vs. DAC
(VOUT = 18V)
Gain & Offset Change vs. VOUT
0.3
5
4
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
V
= 18V
OUT
0.2
0.1
0
3
2
OFFSET CHANGE
1
-0.1
-0.2
-0.3
0
GAIN CHANGE
-1
18
2
6
10
14
0
16 32 48 64 80 96 112 128
DAC SETTING
V
(V)
OUT
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IOUT Error vs. VDD
IOUT Error vs. AVDD
0.02
0.015
0.01
0.2
0.15
0.1
FULL SCALE
FULL SCALE
ZERO SCALE
0.05
0
0.005
0
-0.005
-0.05
-0.1
-0.15
-0.2
MID SCALE
ZERO SCALE
MID SCALE
-0.01
-0.015
-0.02
2.25
2.5
2.75
V
3
3.25
3.5
5
7.5
10
15
17.5
20
12.5
AV (V)
(V)
DD
DD
Figure 14.
IOUT Error vs. Temperature
Figure 15.
Total Unadjusted Error vs. DAC
0.2
0.15
0.1
0.2
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
0
16 32 48 64 80 96 112 128
DAC SETTING
Figure 16.
Figure 17.
Integral Non-Linearity Error vs. DAC
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
16 32 48 64 80 96 112 128
DAC SETTING
Figure 18.
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Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
Differential Non-Linearity Error vs. DAC
0.2
RON vs. SCL-S Voltage
450
400
350
300
SCL VIA SERIES
RESISTOR 1.5 kW
0.15
0.1
CONNECTED TO V
DD
0.05
0
V
DD
= 2.25V
250
200
150
-0.05
-0.1
-0.15
-0.2
V
= 3.0V
DD
100
50
V
= 3.6V
DD
0
0
16 32 48 64 80 96 112 128
DAC SETTING
0
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
0.4
SCL-S VOLTAGE (V)
Figure 19.
Figure 20.
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APPLICATION SECTION
INTRODUCTION
The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits
EEPROM). Programming the register can be done using the I2C compatible interface. The LM8342 replaces the
potentiometer adjustment, and thereby simplifies the VCOM calibration procedure. With the LM8342, the factory
operator can physically view the screen head-on when performing this step, easing manufacturing especially for
large TFT panel sizes.
The following sections discuss the principle of operation of a TFT-LCD and, subsequently give a description of
how to use the LM8342, including the I2C compatible interface and control inputs. After this, two typical LM8342
configurations are presented. Subsequently an evaluation system is introduced, including a μC-board
programming using the I2C compatible interface. At the end of this application section board layout
recommendations are given.
PRINCIPLE OF OPERATION OF A TFT-LCD
This section offers a brief overview of the principle of operation of TFT-LCD’s. It gives a detailed description of
how information is presented on the display. Further an explanation of how data is written to the screen pixels
and how the pixels are selected is included.
TRANSMITTED LIGHT
POLARIZER
GLASS
TOP ITO
SUBSTRATE
PLATE
LIQUID CRYSTAL
BOTTOM ITO
MATERIAL
PLATE
V
PIXEL
± POLARITY
GLASS
SUBSTRATE
POLARIZER
LIGHT SOURCE
Figure 21. Individual LCD Pixel
Figure 21 shows a simplified illustration of an individual LCD pixel. The top and bottom plates of a pixel consist of
Indium-Tin Oxide (ITO), which is a transparent, electrically conductive material. ITO is at the inner surfaces of
two glass substrates that are the front and back glass panels of a TFT display. Sandwiched between two ITO
plates is an insulating material (liquid crystal). Liquid crystals alter the polarization of light, depending on how
much voltage (VPIXEL) is applied across the two plates. Polarizers are placed on the outer surfaces of the two
glass substrates. In combination with the liquid crystal, the polarizers create an electrically variable light filter that
modulates light transmitted from the back to the front of a display. A pixel’s bottom plate is at the backside of a
display where a light source is applied, and the top plate is at the front, facing the viewer. For most TFT displays,
a pixel transmits the greatest amount of light when VPIXEL ≤ ±0.5V, and it becomes less transparent as the
voltage increases with either positive or negative polarity.
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SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013
COLUMN DRIVERS
C
C
C
STRAY
STRAY
STRAY
V
V
V
COM
COM
COM
PIXEL
PIXEL
PIXEL
APPROX
/2
TFT-LCD PANEL
V
DD
V
BUFFER
COM
Figure 22. TFT Display
Figure 22 shows a simplified diagram of a TFT display, showing how individual pixels are connected to the row,
column and VCOM driver. Each pixel is represented by a capacitor with an NMOS transistor connected to its top
plate. Pixels in a TFT panel are arranged in rows and columns. Row lines are connected to the NMOS gates,
and column lines to the NMOS sources. The back plate of every pixel is connected to a common voltage called
VCOM. The voltage applied to the top plates (i.e. Gamma Voltage) controls the pixel brightness. The column
drivers supply this gamma voltage via the column lines, and ‘write’ this voltage to the pixels one row at a time.
This is accomplished by having the row drivers selecting an individual row of pixels when the column drivers
write the gamma voltage levels. The row drivers sequentially apply a large positive pulse (typically 25V to 35V) to
each row line. This turns on the NMOS transistors connected to an individual row, allowing voltage from the
column lines to be written to the pixels.
LM8342
V
COM
GAMMA CORRECTION CURVE
CALIBRATOR
LM8207
V
REF
V
COM
18 GAMMA BUFFER
COLUMN DRIVER
BUFFER
TIMING
CONTROL
MULTI
SOURCE
DC/DC
CONVERTER
& LDO
ROW
DRIVER
DISPLAY
Figure 23. TFT Panel Block Diagram
Figure 23 shows a block diagram of a TFT panel. The VCOM buffer supplies a common voltage (VCOM) to all the
pixels in a TFT panel. In general, VCOM is a DC voltage that is in the middle of the gamma voltage range. Screen
performance can be optimized by tuning the VCOM voltage in the calibration procedure. Using the LM8342, the
VCOM calibration procedure is simplified by elimination of the potentiometer adjustment task. This task is currently
performed at the factory using a trimmer adjustment tool and visual inspection, when using a stable reference
voltage and a potentiometer as a voltage divider to generate the VCOM voltage.
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PRINCIPLE OF OPERATION OF THE LM8342
The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits
EEPROM). Writing data can be done using the I2C compatible interface. Data can be written to a volatile register
and can also be stored in the non-volatile EEPROM. A simplified block diagram of the LM8342 is given in
Figure 24.
AV
DD
LM8342
OUT
I
OUT
2
I C COMPATIBLE BUS
DIGITAL/
ANALOG
CONVERTER
CONTROLLER
MEMORY
+
-
SET
SET
R
Figure 24. Block Diagram of the LM8342
The maximum output current of the LM8342 can be defined using an external resistor RSET in combination with
an analog reference voltage AVDD. This maximum current can be calculated using Equation 1.
AVDD
20
1
x
IOUT_MAX
=
RSET
(1)
The operating range for the output current is given in the Electrical Characteristics table. Variations of the voltage
reference AVDD or the external resistor RSET will affect this output current. Using a resistor with a low temperature
coefficient is recommended.
The relative value of IOUT with respect to the maximum current can be controlled digitally in 128 steps, using the
internal DAC. This results in an output current described by Equation 2.
DAC10 + 1
x
IOUT = IOUT_MAX
128
(2)
Using the serial interface bus the operator can store the DAC value in the LM8342s 7-bits volatile register
temporarily, or permanent in the EEPROM. During a start-up sequence the LM8342 will copy the contents of the
EEPROM to the register setting the DC value.
CONTROLLING THE DEVICE
The LM8342s current sink can be programmed using a serial interface bus. Additional functions (e.g. storing data
in the EEPROM) can be controlled in combination with external inputs. Table 1 shows the pins of the LM8342
and gives a short functional description.
Table 1. Pin Descriptions
Pin name
Function
SDA & SCL
(Serial interface bus)
The LM8342 output current can be controlled using the serial I2C compatible interface. This 2-
Wire interface uses a clock and a data signal. New values can be written to the memory, or the
current value can be read back from the device. The I2C compatible interface is discussed in
more detail in the next chapter.
AVDD
VDD
Analog reference voltage for the DAC.
Supply voltage for both the analog and digital circuitry.
SET
An external resistor RSET connected to the SET pin determines the maximum output current, see
Equation 1.
OUT
The output of the programmable current sink.
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Table 1. Pin Descriptions (continued)
Pin name
Function
SCL-S
WPN
For in-circuit PCB testing, the LM8342 can use the additional Switched SCL signal (SCL-S) input
for applying the SCL clock signal.
“Write Protect Not” (Input) has 2 functions:
1. Prohibits programming the EEPROM, when low or left floating (Internal a pull-down resistor is
connected) When WPN is set to a low level, only the volatile register is accessible. If WPN is set
to a high level also the EEPROM is accessible. Actual writing to the EEPROM or the register is
done using the “P-bit” in the serial communication.
2. WPN switches the SCL-S clock line. When WPN is set to a high level SCL-S is connected to
SCL. The operator should turn off the original SCL clock.
WPP
Write Protect Signal (Output). This is the inverted WPN signal.
I2C SERIAL INTERFACE BUS
The LM8342 supports an I2C compatible communication protocol, which is a bidirectional bus oriented
communication protocol. Any device that sends data on the bus is defined as a transmitter and the receiving
device as a receiver. The I2C compatible communication protocol uses 2 wires: SDA (Serial Data Line) and SCL
(Serial Clock Line). For both lines an external pull-up resistor, connected to the supply voltage, is required. The
device controlling the bus is known as the master, and the device or devices being controlled are the slaves.
Each device has its own specific address. The address of the LM8342 is 9EHEX. The master initiates the
communication and provides the clock. The LM8342 always operates as a slave. A typical system using an I2C
compatible interface bus is given in Figure 25.
V
DD
PULL-UP
RESISTORS
SDA
SCL
MASTER
LM8342
SLAVE B
SLAVE A
Figure 25. System Using an I2C compatible Bus
The LM8342 can be used in an I2C compatible system. All specifications of the LM8342, dealing with the
interface bus, are ensured by design. Except for the bus speed, which is specified in the Electrical
Characteristics table.
KEY ASPECT OF I2C COMPATIBLE COMMUNICATION
In this section a brief overview is presented, discussing the key aspect of I2C compatible communication.
Figure 26 shows the timing aspects of the I2C compatible serial interface.
START
SLAVE ADDRESS
R/W
A
DATA
A
STOP
1
0
0
1
1
1
1
D6 D5 D4 D3 D2 D1 D0
P
SCL
SDA
1
0
0
1
1
1
R/W
A
D6 D5 D4 D3 D2 D1 D0
P
A
1
START
STOP
Figure 26. Timing Diagram
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The timing diagram shows the major aspect of the communication protocol and represents a typical data stream.
In case a master wants to setup a data transfer, it tests if “the bus is busy.” If it is not busy, then the master
starts the data transfer by creating a “start data transfer” situation. Accordingly the corresponding receiver is
selected by sending the appropriate “slave address.” This receiver gives an “acknowledge” on recognizing its
address on the bus. The master continues the data transfer by sending the data stream. Again the receiver gives
an “acknowledge” after receipt. Depending on the amount of data the master will continue or create a “stop data
transfer” situation. Table 2 gives a more detailed description of the I2C compatible communication.
Table 2. Detailed Description of I2C compatible Communication Definitions
Bus not busy
The I2C compatible bus is not busy when both data (SDA) and clock (SCL) lines remain
HIGH. The controller can initiate data transfer only when the bus is not busy.
Start Data Transfer
Starting from an idle state (bus not busy) a START condition consists of a HIGH to
LOW transition of SDA while SCL is HIGH. All commands must start with a START
condition.
Slave address
After generating a start condition, the master transmits a 7-bit slave address. (The
LM8342 uses the 8th bit for selecting the R/W operation, but this does not affect the
address.) The address for the LM8342 is 9EHEX
.
R/W-bit
If the value of the R/W bit is HIGH, the data is read from the register of the LM8342.
Otherwise the current DAC setting is written to the LM8342.
Acknowledge
A receive device, when addressed, is obliged to generate an “acknowledge” after the
reception of each byte. The master generates an extra clock cycle that is associated
with this acknowledge bit. The receiver has to pull down the SDA line during the
acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of
SCL, with respect to the SCL timing specifications.
Data byte
P-bit
A data byte consists of 8 bits. 7 bits are used for the DAC setting of the LM8342. The
8th bit is known as the P-bit.
The function of the P-bit depends on the Read/Write operation (R/W-bit). During a Read
operation of the LM8342, the P-bit indicates the programming state of the EEPROM.
During a Write operation, the register or both the register and the EEPROM of the
LM8342 can be selected as destination. A more detailed description of the P-bit is given
in Table 3 .
Stop Data Transfer
A STOP condition consists of a LOW to HIGH transition of SDA while SCL is HIGH. All
operations must be ended with a STOP condition.
Table 3. P-bit Truth Table
Operation
P-bit
Description
Read
Read
1
0
Programming Ready
Programming Busy
(don’t turn off the device)
Write
Write
1
0
Register Write
EEPROM Write
The LM8342 can be used in I2C compatible systems with clock speeds of up to 400 kbps (Fast mode). For low
speed applications, an initial resistor value for the pull-up resistors is 15 kΩ is suitable. When increasing the
speed of the interface bus, the user should decrease the value of the pull-up resistors.
Typical Application
The following section discusses two typical applications for the LM8342. In the first application the LM8342 is
used as a programmable current sink, for example to drive a programmable bias generator. In the second
application the LM8342 is used to adjust the voltage level of a VCOM driver.
PROGRAMMABLE CURRENT SINK
As described in the “Principle of Operation of the LM8342” section the LM8342 basically operates as a
programmable current sink. Figure 27 shows a general current sink application.
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V
DD
6
2
AV
DD
V
DD
15 kW
15 kW
15 kW
OUT
SDA
1
7
I
OUT
SCL
8
LM8342
SCL-S
9
3
WP
N
SET
CONTROLLER
10
R
SET
WP
GND
P
4
5
Figure 27. Programmable Current Sink
The output current of the LM8342 can be calculated using Equation 3.
DAC10 + 1
AVDD
1
x
x
IOUT
=
20
RSET
128
(3)
DRIVING A VCOM LEVEL
Another typical application, given in Figure 28, is using the LM8342 to adjust the “voltage tap” of a resistive
voltage divider. The VCOM driver buffers the “voltage tap” in this application.
V
DD
AV
DD
6
2
AV
DD
V
DD
15 kW
15 kW
15 kW
R1
V
COM
OUT
SDA
+
7
1
-
I
OUT
SCL
R2
8
LM8342
SCL-S
9
3
SET
CONTROLLER
WP
N
10
R
SET
WP
P
GND
4
5
Figure 28. Typical Application Driving a VCOM Level
The voltage level of the VCOM driver, for a general setting of (DAC10) , is calculated using Equation 4.
«
∆
∆
≈
«
∆
∆
≈
∆
∆
«
≈
∆
∆
«
(DAC10 + 1) x R1
128 x RSET x 20
R2
1 -
VCOM = AVDD
x
x
≈
R1 + R2
(4)
For calibrating the VCOM level (see Figure 28) the tuning range of the design needs to be aligned to the required
VCOM tuning range (ΔVCOM). Figure 29 gives a graphical presentation of the desired voltage levels.
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AV
DD
VCOM_HIGH
D VCOM
V
MID
OPERATING V RANGE
COM
VCOM_LOW
GND
Figure 29. VCOM Voltage Levels
Assume the calibrator needs to cover the voltage range given in Equation 5.
D
VCOM = VCOM_HIGH œ VCOM_LOW
(5)
The limits of VCOM for DAC10 = 0 (high limit) and DAC10 = 127 (low limit) are given by:
«
≈
«
≈
R2
≈
R1 + R2
«
R1
≈
1 -
x
VCOM_HIGH = AVDD
x
128 x RSET x 20
«
(6)
(7)
«
≈
«
≈
R2
R1
≈
«
≈
1 -
x
VCOM_LOW = AVDD
x
R1 + R2
RSET x 20
«
Using Equation 5,Equation 6, and Equation 7 the value for resistors R1 and R2 can be obtained, resulting in
Equation 8 and Equation 9:
D
VCOM
40 x RSET
x
R1 =
D
AVDD
+
VCOM
(8)
and
40 x RSET x DVCOM
AVDD - DVCOM
R2 =
(9)
Table 4 gives an overview of resistor values for a typical value of AVDD, and 2 RSET values. All settings are for a
VCOM level at VMID = ½ AVDD, and a maximum variation of ΔVCOM
.
1
2
1
2
VMID
-
V
<
+
V
V
D
V
D
COM
<
MID
COM
COM
(10)
Table 4. Overview Resistor Values for Different RSET Settings at AVDD = 15V
AVDD = 15V (VCOM Level = 7.5 V)
RSET = 10 kΩ
RSET = 45 kΩ
ΔVCOM
R1
R2
ΔVCOM
R1
R2
(V)
(Ω)
(Ω)
(V)
(Ω)
(Ω)
±0.5
±1
25k
28.6k
61.5k
100k
146k
±0.5
±1
113k
212k
300k
379k
129k
277k
450k
655k
47.1k
66.7k
84.2k
±1.5
±2
±1.5
±2
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Table 4. Overview Resistor Values for Different RSET Settings at AVDD = 15V (continued)
±2.5
100k
114k
200k
267k
±2.5
±3
450k
514k
900k
1.2M
±3
EVALUATION SYSTEM
For the LM8342 a complete evaluation system is available, including two boards. Figure 30 gives a schematic
representation.
•
LM8342 Evaluation BoardThis board demonstrates the functionality of the LM8342 using the I2C compatible
interface for communication. The LM8342 can easily be demonstrated in 2 applications:
–
–
Programmable current sink
Programmable VCOM level driver
•
LM8342 Programmer BoardThis test board has dedicated functionality for communicating with the LM8342,
using the I2C compatible interface. This board can operate in two different modes:
–
Write mode: The digitized value of a potentiometer setting is written to the LM8342. The user can select
on the programmer board to write the data to the register or to store the data in the EEPROM.
–
Read mode: The board reads the stored values from the LM8342’s EEPROM and presents this data onto
a 3-digit display.
V
A
VDD
DD
2
BUFFERED
I C COMPATIBLE
V
COM
BUS
LM8342
EVALUATION
BOARD
LM8342
PROGRAMMER
BOARD
I
OUT
WP
N
WP
P
Figure 30. LM8342 Evaluation System
LAYOUT RECOMMENDATIONS
A proper layout is necessary for optimum performance of the LM8342. A low impedance and proper ground
plane (free of disturbances) is recommended, since a current of up to 10 mA can flow with HF contents during
programming. The traces from the GND pin to the ground plane should be as short as possible. It is
recommended to place decoupling capacitors close to the VDD and AVDD pins. Connections of these decoupling
capacitors to the ground plane should be short.
As SET is a sensitive input, crosstalk to that pin should be prevented. Special care should be taken when routing
the interface connections. The signals on the serial interface can be more than 60 dB larger than the equivalent
LSB at the SET input pin. Crosstalk between the interface bus and RSET results in disturbance of the output
current IOUT of the LM8342.
For applications requiring a low output current (using high values for RSET in combination with low DAC settings)
special attention should be paid to the parasitic capacitance (CPAR) parallel to RSET. For CPAR larger than tens of
pF, a small (<1 LSB) unwanted ripple at the output current might be obtained. It is recommended to place the
RSET resistor close to the LM8342, in combination with a good board layout to reduce this parasitic capacitance.
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM8342SD/NOPB
LM8342SDX/NOPB
ACTIVE
ACTIVE
WSON
WSON
DSC
DSC
10
10
1000 RoHS & Green
4500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
L8342
L8342
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM8342SD/NOPB
LM8342SDX/NOPB
WSON
WSON
DSC
DSC
10
10
1000
4500
178.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM8342SD/NOPB
LM8342SDX/NOPB
WSON
WSON
DSC
DSC
10
10
1000
4500
208.0
367.0
191.0
367.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
SDA10A (Rev A)
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