LM94CIMTX/NOPB_技术文档

LM94

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SNAS264C –APRIL 2006–REVISED MARCH 2013

LM94 TruTherm™ Hardware Monitor with PI Loop Fan Control for Server Management

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1

FEATURES

•

2-wire Serial Digital Interface, SMBus 2.0

Compliant

23

•

8-bit ΣΔ ADC

–

Supports Byte/block Read and Write

•

Monitors 16 Power Supplies

Selectable Slave Address (Tri-level Pin

Selects 1 of 3 Possible Addresses)

Monitors 4 Remote Thermal Diodes and 2

LM60

–

ALERT Output Supports Interrupt or

Comparator Modes

•

New TruTherm Technology Support for

Precision Thermal Diode Measurements

•

2.5V Reference Voltage Output

56-pin TSSOP Package

XOR-tree Test Mode

•

Internal Ambient Temperature Sensing

Programmable Autonomous Fan Control

Based on Temperature Readings with Fan

Boost Support

APPLICATIONS

•

Fan Boost Support on Tachometer Limit Error

Event

•

Servers

Fan Control Based on 13-step Lookup Table or

PI Control Loop or Combination of Both

Workstations

Multi-processor based equipment

•

PI Fan Control Loop Supports Tcontrol

Temperature Reading Digital Filters

KEY SPECIFICATIONS

•

Voltage Measurement Accuracy ... ±2% FS

(max)

0.5°C digital Temperature Sensor Resolution

0.0625°C Filtered Temperature Resolution for

Fan Control

•

Temperature Resolution ... 9-bits, 0.5°C

Temperature Sensor Accuracy ... ±2.5 °C (max)

Temperature Range:

•

2 PWM Fan Speed Control Outputs

4 Fan Tachometer Inputs

–

LM94 Operational ... 0°C to +85°C

Dual Processor Thermal Throttling (PROCHOT)

Monitoring

Remote Temp Accuracy ... 0°C to +125°C

•

Dual Dynamic VID Monitoring (6/7 VIDs per

processor) Supports VRD10.2/11

•

Power Supply Voltage ... +3.0V to +3.6V

Power Supply Current ... 1.6 mA

8 General Purpose I/Os:

DESCRIPTION

–

4 Can be Configured as Fan tachometer

Inputs

The LM94 hardware monitor has a two wire digital

interface compatible with SMBus 2.0. Using a ΣΔ

ADC, the LM94 measures the temperature of four

remote diode connected transistors as well as its own

die and 16 power supply voltages. The LM94 has

new TruTherm technology that supports precision

thermal diode measurements of processors on sub-

micron processes.

2 Can be Configured to Connect to

Processor THERMTRIP

2 are Standard GPIOs that Could be Used

to Monitor IERR Signal

•

2 General Purpose Inputs that Can be Used to

Monitor the 7th VID Signal for VRD11

Limit Register Comparisons of all Monitored

Values

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

I²C is a trademark of dcl_owner.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM94

SNAS264C –APRIL 2006–REVISED MARCH 2013

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Description

(continued)

To set fan speed, the LM94 has two PWM outputs that are each controlled by up to six temperature zones. The

fan-control algorithm can be based on a lookup table, PI (proportional/integral) control loop, or a combination of

both. The LM94 includes digital filters that can be invoked to smooth temperature readings for better control of

fan speed such that acoustical noise is minimized. The LM94 has four tachometer inputs to measure fan speed.

Limit and status registers for all measured values are included.

The LM94 builds upon the functionality of previous motherboard server management ASICs, such as the LM93.

It also adds measurement and control support for dynamic Vccp monitoring for VRD10/11 and PROCHOT. It is

designed to monitor a dual processor Xeon class motherboard with a minimum of external components.

Block Diagram

The block diagram of LM94 hardware is illustrated below. The hardware implementation is a single chip ASIC

solution.

RESET#

P1_PROCHOT

PROCHOT AND VRD_HOT

DETECT/CONTROL

LOGIC

P2_PROCHOT

P1_VRD_HOT

P2_VRD_HOT

Address Select

ALERT/XtestOut

SMBDAT

SERIAL BUS

INTERFACE

SMBCLK

P1_VID0/P1_VID7

P1_VID6

CONFIGURATION AND

IDENTIFICATION

REGISTERS

DYNAMIC VCCP MONITORING

P2_VID0/P2_VID7

P2_VID6

GPIO_0/TACH1

V

DD

STEPPING AND

DEVICE ID

REGISTERS

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

GPIO_4

GPIO_5

GPIO_6

3.3SBY (AD_IN 16)

AD_IN1(1.236V)/REMOTE1b+*

AD_IN2(1.236V)/REMOTE2b+*

FAN TACH/

GPIO/GPI

GPIO_7

ADDRESS POINTER

REGISTER

GPI8

GPI9

AD_IN3(1.236V)*

AD_IN4(1.6V)

AD_IN5(2V)

VALUE REGISTERS

LIMIT REGISTERS

VOLTAGE

REFERENCE

AD_IN6(2V)

AD_IN7(1.6V;P1_Vccp)

AD_IN8(1.6V;P2_Vccp)

INPUT

ATTENUATORS,

EXTERNAL DIODE

SIGNAL

CONDITIONING,

AND

AD_IN9(4.4V)

AD_IN10(6.67V)

HOST STATUS REGISTERS

BMC STATUS REGISTERS

8-Bit

SD ADC

AD_IN11(3.33V)

AD_IN12(2.625V)

AD_IN13(1.312V)

AD_IN14(1.312V)

PWM1

PWM2

ANALOG

MULTIPLEXER

FAN CONTROL

CONFIG REGISTERS,

LOOKUP TABLES,

and PI LOOP

PWM

FAN

CONTROL

TEMPERATURE

READING DIGITAL

FILTER

AD_IN15(1.236V)*

PARAMETERS

REMOTE1a+

REMOTE1-

SLEEP STATE CONTROL

AND MASK REGISTERS

REMOTE2a+

REMOTE2-

INTERNAL TEMP

SENSOR

GPI AND OTHER

MASK REGISTERS

V

REF

*Note: These pins may be used for ±12V with external

resistor dividers. The thevenin equivalent resistance at

the pin must be between 1k and 7k.

+

-

V

REF

(2.5V)

2

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SNAS264C –APRIL 2006–REVISED MARCH 2013

Application

Baseboard management of a dual processor server. Two LM94s may be required to manage a quad processor

board. The system diagram below shows a dual processor server

Figure 1. 2 Way Xeon Server Management

Alert

ICH

BMC, miniBMC

Sending

Device (ASD)

UART/NIC

EEPROM

2.5 V V

REF

SMBus

LM94

baseboard

temperature

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Connection Diagram

Top View

GPIO_0/TACH1

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

GPIO_4

1

2

3

4

5

6

7

8

9

P2_VID5

56

55

54

53

52

51

50

49

48

47

46

P2_VID4

P2_VID3

P2_VID2

P2_VID1

GPIO_5

P2_VID0/P2_VID7

P2_PROCHOT

P1_PROCHOT

P1_VID5

GPIO_6

GPIO_7

VRD1_HOT

VRD2_HOT

P2_VID6/GPI8

10

11

P1_VID4

P1_VID3

P1_VID6/GPI9

SMBDAT

12

13

P1_VID2

P1_VID1

45

44

SMBCLK

ALERT/XtestOut

RESET

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

P1_VID0/P1_VID7

PWM2

43

42

41

40

LM94

PWM1

AGND

GND

V

REF

Power 39

3.3V SB (AD_IN16)

Address Select

AD_IN15(1.236V)

AD_IN14(1.312V)

AD_IN13(1.312V)

AD_IN12(2.65V)

AD_IN11(3.3V)

AD_IN10(6.67V)

AD_IN9(4.4V)

AD_IN8(1.6V; P2_Vccp)

REMOTE1-

REMOTE1a+

REMOTE2-

38

37

36

35

34

33

32

31

30

29

REMOTE2a+

AD_IN1(1.236V)/REMOTE1b+

AD_IN2(1.236V)/REMOTE2b+

AD_IN3(1.236V)

AD_IN4(1.6V)

AD_IN5(2V)

AD_IN6(2V)

AD_IN7(1.6V; P1_Vccp)

Figure 2. 56 Pin TSSOP Package

See Package Number DGG0056A

Table 1. Pin Descriptions⁽¹⁾

Symbol

Pin No.

Type

Function

GPIO_0/TACH1

1

Digital I/O (Open-Drain) Can be configured as fan tach input or a general purpose open-drain digital

I/O.

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

2

3

4

5

Digital I/O (Open-Drain) Can be configured as fan tach input or a general purpose open-drain digital

I/O.

Digital I/O (Open-Drain) Can be configured as fan tach input or a general purpose open-drain digital

I/O.

Digital I/O (Open-Drain) Can be configured as fan tach input or a general purpose open-drain digital

I/O..

GPIO_4 /

P1_THERMTRIP

Digital I/O (Open-Drain) A general purpose open-drain digital I/O. Can be configured to monitor a

CPU's THERMTRIP signal to mask other errors. Supports TTL input logic

levels and AGTL compatible input logic levels.

GPIO_5 /

P2_THERMTRIP

6

7

8

Digital I/O (Open-Drain) A general purpose open-drain digital I/O. Can be configured to monitor a

CPU's THERMTRIP signal to mask other errors. Supports TTL input logic

levels and AGTL compatible input logic levels.

GPIO_6

GPIO_7

Digital I/O (Open-Drain) Can be used to detect the state of CPU1 IERR or a general purpose open-

drain digital I/O. Supports TTL input logic levels and AGTL compatible input

logic levels.

Digital I/O (Open-Drain) Can be used to detect the state of CPU2 IERR or a general purpose open-

drain digital I/O. Supports TTL input logic levels and AGTL compatible input

logic levels.

VRD1_HOT

VRD2_HOT

9

Digital Input

CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL

compatible input logic levels.

10

Digital Input

CPU2 voltage regulator HOT. Supports TTL input logic levels and AGTL

compatible input logic levels.

(1) The over-score indicates the signal is active low (“Not”).

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Table 1. Pin Descriptions⁽¹⁾(continued)

Symbol

Pin No.

Type

Function

P2_VID6/GPI8

11

Digital Input

CPU2 VID6 input. Could also be used as a general purpose input to trigger

an error event. Supports TTL input logic levels and AGTL compatible input

logic levels.

P1_VID6/GPI9

12

Digital Input

CPU1 VID6 input. Could also be used as a general purpose input to trigger

an error event. Supports TTL input logic levels and AGTL compatible input

logic levels.

SMBDAT

13

14

15

Digital I/O (Open-Drain) Bidirectional System Management Bus Data. Output configured as 5V

tolerant open-drain. SMBus 2.0 compliant.

SMBCLK

Digital Input

System Management Bus Clock. Driven by an open-drain output, and is 5V

tolerant. SMBus 2.0 Compliant.

ALERT/XtestOut

Digital Output (Open-

Drain)

Open-drain ALERT output used in an interrupt driven system to signal that an

error event has occurred. Masked error events do not activate the ALERT

output. When in XOR tree test mode, functions as XOR Tree output.

RESET

AGND

16

17

Digital I/O (Open-Drain) Open-drain reset output when power is first applied to the LM94. Used as a

reset for devices powered by 3.3V stand-by. After reset, this pin becomes a

reset input. See RESETS for more information. If this pin is not used,

connection to an external resistive pull-up is required to prevent LM94

malfunction.

GROUND Input

Analog Ground. Digital ground and analog ground need to be tied together at

the chip then both taken to a low noise system ground. A voltage difference

between analog and digital ground may cause erroneous results.

V_REF

18

19

Analog Output

2.5V used for external ADC reference, or as a V_REFreference voltage

This is the negative input (current sink) from both of the CPU1 thermal

REMOTE1−

Remote Thermal

Diode_1- Input (CPU 1 diodes. Connected to THERMDC pin of Pentium processor or the emitter of a

THERMDC)

diode connected MMBT3904 NPN transistor. Serves as the negative input

into the A/D for thermal diode voltage measurements. A 100 pF capacitor is

optional and can be connected between REMOTE1− and REMOTE1+.

REMOTE1a+

20

Remote Thermal

Diode_1+ I/O (CPU1

THERMDA1)

This is a positive connection to the first CPU1 thermal diode. Serves as the

positive input into the A/D for thermal diode voltage measurements. It also

serves as a current source output that forward biases the thermal diode.

Connected to THERMDA pin of Pentium processor or the base of a diode

connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and

can be connected between REMOTE1− and each REMOTE1+.

REMOTE2−

21

22

Remote Thermal

This is the negative input (current sink) from both of the CPU2 thermal

Diode_2 - Input (CPU2 diodes. Connected to THERMDC pins of Pentium processor or the emitter of

THERMDC)

a diode connected MMBT3904 NPN transistor. Serves as the negative input

into the A/D for thermal diode voltage measurements. A 100 pF capacitor is

optional and can be connected between REMOTE2− and each REMOTE2+.

REMOTE2a+

Remote Thermal

Diode_2 + I/O (CPU2

THERMDA1)

This is a positive connection to the first CPU2 thermal diode. Serves as the

positive input into the A/D for thermal diode voltage measurements. It also

serves as a current source output that forward biases the thermal diode.

Connected to THERMDA pin of Pentium processor or the base of a diode

connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and

can be connected between REMOTE2− and REMOTE2+.

AD_IN1/REMOTE1b+

AD_IN2/REMOTE2b+

AD_IN3

23

24

25

Analog Input (+12V1 or Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator. External

CPU1 THERMDA2)

attenuation resistors required such that 12V is attenuated to 0.927V for

nominal ¾ scale reading. This pin may also serve as the second positive

thermal diode input for CPU1.

Analog Input (+12V2 or Analog Input for +12V Rail 2 monitoring, for CPU2 voltage regulator. External

CPU2 THERMDA2)

attenuation resistors required such that 12V is attenuated to 0.927V for

nominal ¾ scale reading. This pin may also serve as the second positive

thermal diode input for CPU2.

Analog Input (+12V3)

Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation

resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale

reading.

AD_IN4

AD_IN5

26

27

Analog Input (FSB_Vtt) Analog input for 1.2V monitoring, nominal ¾ scale reading

Analog Input (3GIO /

PXH / MCH_Core)

Analog input for 1.5V monitoring, nominal ¾ scale reading

AD_IN6

28

Analog Input

(ICH_Core)

Analog input for 1.5V monitoring, nominal ¾ scale reading

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Table 1. Pin Descriptions⁽¹⁾(continued)

Symbol

Pin No.

Type

Function

AD_IN7 (P1_Vccp)

29

Analog Input

(CPU1_Vccp)

Analog input for +Vccp (processor voltage) monitoring.

Analog input for +3.3V monitoring, nominal ¾ scale reading

AD_IN8 (P2_Vccp)

30

Analog Input

(CPU2_Vccp)

AD_IN9

31

32

Analog Input (+3.3V)

Analog Input (+5V)

AD_IN10

Analog input for +5V monitoring silver box supply monitoring, nominal ¾

scale reading

AD_IN11

33

Analog Input

(SCSI_Core)

Analog input for +2.5V monitoring, nominal ¾ scale reading. This pin may

also be used to monitor an analog temperature sensor such as the LM60,

since readings from this input can be routed to the fan control logic.

AD_IN12

AD_IN13

AD_IN14

AD_IN15

34

35

36

37

Analog Input

(Mem_Core)

Analog input for +1.969V monitoring, nominal ¾ scale reading.

Analog input for +0.984V monitoring, nominal ¾ scale reading.

Analog input for +0.984V S/B monitoring, nominal ¾ scale reading.

Analog Input

(Mem_Vtt)

Analog Input

(Gbit_Core)

Analog Input (-12V)

Analog input for -12V monitoring. External resistors required to scale to

positive level. Full scale reading at 1.236V, , nominal ¾ scale reading. This

pin may also be used to monitor an analog temperature sensor such as the

LM60, since readings from this input can be routed to the fan control logic.

Address Select

38

39

3 level analog input

This input selects the lower two bits of the LM94 SMBus slave address.

3.3V SB (AD_IN16)

POWER (V_DD) +3.3V

standby power

V_DDpower input for LM94. Generally this is connected to +3.3V standby

power.

The LM94 can be powered by +3.3V if monitoring in low power states is not

required, but power should be applied to this input before any other pins.

This pin also serves as the analog input to monitor the 3.3V stand-by (SB)

voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100

pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF

should be closest to the power pin.

GND

40

GROUND

Digital Ground. Digital ground and analog ground need to be tied together at

the chip then both taken to a low noise system ground. A voltage difference

between analog and digital ground may cause erroneous results.

PWM1

41

42

43

44

45

46

47

48

49

50

51

52

53

Digital Output (Open-

Drain)

Fan control output 1.

PWM2

Digital Output (Open-

Drain)

Fan control output 2

P1_VID0/P1_VID7

P1_VID1

Digital Input

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P1_VID2

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P1_VID3

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P1_VID4

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P1_VID5

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P1_PROCHOT

P2_PROCHOT

P2_VID0/P2_VID7

P2_VID1

Digital I/O (Open-Drain) Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional

level shifter. Supports TTL input logic level.

Digital I/O (Open-Drain) Connected to CPU2 PROCHOT (processor hot) signal through a bidirectional

level shifter. Supports TTL input logic level.

Digital Input

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

P2_VID2

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

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Table 1. Pin Descriptions⁽¹⁾(continued)

Symbol

Pin No.

Type

Function

P2_VID3

P2_VID4

P2_VID5

54

Digital Input

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

55

56

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

Server Terminology

A/D

Analog to Digital Converter

ACPI

ALERT

ASF

BMC

BW

Advanced Configuration and Power Interface

SMBus signal to bus master that an event occurred that has been flagged for attention.

Alert Standard Format

Baseboard Management Controller

Bandwidth

DIMM

DP

Dual in line memory module

Dual-processor

ECC

FRU

FSB

FW

Error checking and correcting

Field replaceable unit

Front side bus

Firmware

Gb

Gigabit

GB

Gigabyte

Gbe

GPI

Gigabit Ethernet

General purpose input

General purpose I/O

Hardware

GPIO

HW

I²C

Inter integrated circuit (bus)

Local area network

LAN

LSb

LSB

LVDS

LUT

Mb

Least Significant Bit

Least Significant Byte

Low-Voltage Differential Signaling

Look-Up Table

Megabit

MB

Megabyte

MP

Multi-processor

MSb

MSB

MTBF

MTTR

NIC

Most Significant Bit

Most Significant Byte

Mean time between failures

Mean time to repair

Network Interface Card (Ethernet Card)

Operating system

OS

P/S

Power Supply

PCI

PCI Local Bus

PDB

POR

PS

Power Distribution Board

Power On Reset

Power Supply

SMBCLK and SMBDAT These signals comprise the SMBus interface (data and clock). See the SMBus Interface section for more

information.

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VRD

Voltage Regulator Down - regulates Vccp voltage for a CPU

Recommended Implementation

LM94

VID_CPU1(6:0)

VID_CPU2(6:0)

3.3V S/B

AD_IN16/

+3.3SB

P1_VID0

P1_VID1

P1_VID2

P1_VID3

P1_VID4

P1_VID5

P1_VID6

P2_VID0

+

100 pF

0.1 mF

10 mF

REF_2.5V

Vref

PWM1#

PWM2#

PWM1

PWM2

P2_VID1

P2_VID2

P2_VID3

P2_VID4

P2_VID5

P2_VID6

Fan Tach 1

Fan Tach 2

Fan Tach 3

Fan Tach 4

CPU1 ThermTrip#

CPU2 ThermTrip#

CPU1 IERR#

CPU2 IERR#

GPI/O_0

GPI/O_1

GPI/O_2

GPI/O_3

CPU1_PROCHOT#

P1_PROCHOT

P2_PROCHOT

CPU2_PROCHOT#

GPI/O_4

GPI/O_5

CPU1_THERMDA

CPU1_THERMDC

CPU2_THERMDA

CPU2_THERMDC

GPI/O_6

GPI/O_7

Remote1a+

Remote1-

Remote2a+

Remote2-

VRD1_HOT#

VRD2_HOT#

VRD1_HOT

VRD2_HOT

V

DD

13.7k

P12V_VRD1

P12V_VRD2

P12V_MEM

AD_IN1

AD_IN2

AD_IN3

AD_IN4

AD_IN5

AD_IN6

AD_IN7

AD_IN8

AD_IN9

AD_IN10

AD_IN11

AD_IN12

AD_IN13

10k

P1V2_VTT

P1V5_CORE

P1_VCCP

13.7k

1.15k

SB_RESET#

SMB ALERT#

RESET

ALERT /xTestout

1.15k

SMBCLK

SMBDAT

P2_VCCP

SMBCLK

SMBDAT

P3V3

P5V

P2V5

V

DD

P2V5_MEM

P1V25_VTT

P1V5SB_GB

5.76k

AD_IN14

AD_IN15

10k

P-12V

Address

Select

1.4k

3.3V S/B

A_GND

GND

Quiet System Ground

Figure 3. Recommended Implementation without Thermal Diode Connections

8

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THERM_DA1

THERM_DC1

Remote1a+

LM94

Remote1-

THERM_DC2

THERM_DA2

Remote1b+

Processor

Note: 100 pF cap across each thermal diode is optional and should be placed close to the LM94, if used. The

maximum capacitance between thermal diode pins is 300 pF.

Figure 4. Thermal Diode Recommended Implementation

Functional Description

The LM94 provides 16 channels of voltage monitoring, 4 remote thermal diode monitors, an internal/local

ambient temperature sensor, 2 PROCHOT monitors, 4 fan tachometers, 8 GPIOs, THERMTRIP monitor for

masking error events, 2 sets of 7 VID inputs, an ALERT output and all the associated limit registers on a single

chip, and communicates to the rest of the baseboard over the System Management Bus (SMBus). The LM94

also provides 2 PWM outputs and associated fan control logic for controlling the speed of system fans. There are

two sets of fan control logic, a lookup table and a PI (proportional/integral) loop controller. The lookup table and

PI controller are interactive, such that the fans run at the fastest required speed. Upon a temperature or fan tach

error event, the PWM outputs may be programmed such that they automatically boost to 100% duty cycle. A

timer is included that sets the minimum time that the fans are in the boost condition when activated by a fan tach

error.

The LM94 incorporates Texas Instruments' TruTherm technology for precision “Remote Diode” readings of

processors on 90nm process geometry or smaller. Readings from the external thermal diodes and the internal

temperature sensor are made available as an 9-bit two's-complement digital value with the LSb representing

0.5°C. Filtered temperature readings are available as a 12-bit two's-complement digital value with the LSb

representing 0.0625°C.

All but 4 of the analog inputs include internal scaling resistors. External scaling resistors are required for

measuring ±12V. The inputs are converted to 8-bit digital values such that a nominal voltage appears at ¾ scale

for positive voltages and ¼ scale for negative voltages. The analog inputs are intended to be connected to both

baseboard resident VRDs and to standard voltage rails supplied by a SSI compliant power supply.

The LM94 has logic that ties a set of dynamically moving VID inputs to their associated Vccp analog input for

real time window comparison fault determination. Voltage mapping for VRD10, VRD10 extended and VRD11are

supported by the LM94. When VRD10 mode is selected GPI8 and GPI9 can be used to detect external error

flags whose state is be reflected in the status registers.

Error events are captured in two sets of mirrored status registers (BMC Error Status Registers and Host Status

Registers) allowing two controllers access to the status information without any interference.

The LM94's ALERT output supports interrupt mode or comparator mode of operation. The comparator mode is

only functional for thermal monitoring.

The LM94 provides a number of internal registers, which are detailed in the Registers section of this document.

MONITORING CYCLE TIME

When the LM94 is powered up, it cycles through each temperature measurement followed by the analog

voltages in sequence, and it continuously loops through the sequence. The total monitoring cycle time is not

more than 100 ms, as this is the time period that most external micro-controllers require to read the register

values.

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Each measured value is compared to values stored in the limit registers. When the measured value violates the

programmed limit, a corresponding status bit in the B_Error and H_Error Status Registers is set.

The PROCHOT, tachometer and dynamic VID/Vccp monitoring is performed independently of the analog and

temperature monitoring cycle.

ΣΔ A/D INHERENT AVERAGING

The ΣΔ A/D architecture filters the input signal. During one conversion many samples are taken of the input

voltage and these samples are effectively averaged to give the final result. The output of the ΣΔ A/D is the

average value of the signal during the sampling interval. For a voltage measurement, the samples are

accumulated for 1.5 ms. For a temperature measurement, the samples are accumulated for 8.4 ms.

TEMPERATURE MONITORING

The LM94 remote diode target is the embedded thermal diode found in a Xeon class processor in 90nm

processes but can also work with any Intel based processor in 90nm or 65nm. The LM94 has an advanced

thermal diode input stage using TI's TruTherm technology that reduces the spread in ideality found in sub-micron

geometry thermal diodes. Internal analog filtering has been included in the thermal diode input stage thus

minimizing the need for external thermal diode filter capacitors. In addition a digital filter has been included for

the thermal diode temperature readings.

In some cases instead of using the embedded thermal diode, found on the Xeon processor, a diode connected

2N3904 transistor type can also be used. An example of this would be a MMBT3904 with its collector and base

tied to the thermal diode REMOTE+ pin and the emitter tied to the thermal diode REMOTE− pin. Since the

MMBT3904 is a surface mount device and has very small thermal mass, it measures the board temperature

where it is mounted. The ideality and series resistance varies for different diodes. Therefore the LM94 has

register support to allow calibration selection between a 2N3904 or a Xeon processor. The LM94 is optimized for

typical Intel processors on 90nm or 65nm process or 2N3904 transistor. Other transistor types may used but may

have additional error that can be can be corrected for by programming the appropriate Zone Adjustment Offset

register.

The LM94 acquires temperature data from four different sources:

•

4 external diodes (embedded in a processor or discrete)

1 internal diode (internal to the LM94)

2 analog temperature sensors, such as the LM60, that are connected to the AD_IN11 or AD_15 pins

a temperature value can be externally written into an LM94 register from the SMBus.

All of these values, although not necessarily simultaneously, can be used to control fans, compared against

limits, etc.

The temperature value registers are located at addresses 06h-09h, 50h–55h and 10h-23h. The temperature

sources are referred to as “zones” for convenience:

Zone

Description

Zone 1a

Zone 1b

Zone 2a

Zone 2b

Zone 3

Processor 1 remote diode 1

(REMOTE1a+, REMOTE1−)

Processor 1 remote diode 2

(REMOTE1b+, REMOTE1–)

Processor 2 remote diode 1

(REMOTE2a+, REMOTE2−)

Processor 2 remote diode 2

(REMOTE2b+, REMOTE2–)

Internal LM94 on-chip sensor or external LM60 analog sensor connected to AD_IN11; also accepts writes via

SMBus

Zone 4

External digital temperature value from SMBus write to register 53h or external LM60 analog sensor connected

to AD_IN15

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“Remote Diode” TruTherm Mode

The processor “remote thermal diode” is more correctly described as a transistor. The LM93 treated the “remote

diode” as a diode thus introducing inaccuracies. These inaccuracies have become more apparent as the

geometry of processors is shrinking. The LM94 can sense the “remote diode” using a new TruTherm technology

that treats the remote device as a transistor. The TruTherm Mode is more accurate for processors on 90nm and

smaller geometry. The LM94 still supports the old diode method and is callibrated for 2N3904 transistor type.

Temperature Data Format

Most of the temperature data for the LM94 is represented in three formats:

•

8-bit, two's complement byte with the LSb equal to 1.0ºC; this applies to temperature measurements as well

as any temperature limit registers and some configuration registers.

Temperature⁽¹⁾

+125°C

+25°C

Binary

Hex

7Dh

19h

01h

00h

FFh

E7h

C9h

81h

0111 1101

0001 1001

0000 0001

0000 0000

1111 1111

1110 0111

1100 1001

1000 0001

+1.0°C

0°C

−1.0°C

−25°C

−55°C

−127°C

(1) A value of 80h has a special meaning in the limit registers. It means that the temperature channel is masked. In addition, temperature

readings of 80h indicate thermal diode faults.

•

9–bit two's complement word with the LSb equal to 0.5°C; this applies to unfiltered temperature measurement

extended resolution value registers

Binary

Temperature

Hex

MSB

LSB

+125.5°C

+25.5°C

+0.5°C

0111 1101

0001 1001

0000 0000

1111 1111

1110 0111

1100 1001

1000 0001

1000 0000

0000 0000

1000 0000

7D 80h

19 80h

00 80h

00 00h

FF 80h

E7 80h

C9 80h

81 80h

0°C

−0.5°C

−25.5°C

−55.5°C

−127.5°C

•

12–bit two's complement word with the LSb equal to 0.0625°C; this applies to extended filtered temperature

measurement extended resolution value registers

Binary

Temperature

Hex

MSB

LSB

+125.0625°C

+25.0625°C

+1.0625°C

0°C

0111 1101

0001 1001

0000 0001

0000 0000

1111 1111

1110 0111

1100 1001

1000 0000

0001 0000

0000 0000

1111 0000

7D 10h

19 10h

01 10h

00 00h

FF F0h

E7 F0h

C9 F0h

80 F0h

−0.0625°C

−25.0625°C

−55.0625°C

−127.0625°C

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Some fan control configuration registers use four bits and have an unsigned binary format, please see the FAN

CONTROL configuration register descriptions for further details on this 4-bit format.

Thermal Diode Fault Status

The LM94 provides for indications of a fault (open or short circuit) with the remote thermal diodes. Before a

remote diode conversion is updated, the status of the remote diode is checked for an open or short circuit

condition. If such a fault condition occurs, a status bit is set in the status register. A short circuit is defined as the

diode pins connected to each other. When an open or short circuit is detected, the corresponding temperature

register is set to 80h.

EVENT ERRORS FOR FAN BOOST

Temperature boost error and tachometer error events can cause the fan control PWM output(s) to go to full on. A

boost temperature error event will cause both PWM outputs to go to full on, while a tachometer event can be

either bound to PWM1 or PWM2.

A fan boost temperature event occurs if any of the four temperature zones exceeds the temperature Fan Boost

Limit for that zone. Once a temperature has exceed the boost limit, it must drop to a value equal to the boost limit

minus the boost hysteresis before the boost condition is deactivated. The default setting for Zones 1 and 2 is

60°C and for Zones 3 and 4 it is 35°C.

The tachometer error boost function is enabled via the Tachometer Fan Boost Control register. Depending on the

setting of the tachometer to PWM binding bits one or both of the PWM outputs will go to 100% duty cycle upon

the detection of an unmasked Fan Tachometer Error Event. A Fan Tachometer Error event occurs when a

tachometer reading exceeds the value set in it's FAN Tach Limit register. Once the error event ends the PWM

output(s) will remain at 100% duty cycled for a time interval, Tach Boost Timeout, as programmed in the

Tachometer Fan Boost Control register. If the tachometer error event returns during the middle of the timout

interval the Tach Boost Timeout interval will be reset and restart once the error event ends.

VOLTAGE MONITORING

The LM94 contains inputs for monitoring voltages. Scaling is such that the correct value refers to approximately

3/4 scale or 192 decimal on all inputs, except the ±12V. Scaling is accomplished by using internal resistor

dividers, except for the ±12V. The typical input resistance of these inputs is 200 k ohms. Input voltages are

converted by an 8-bit Delta-Sigma (ΔΣ) A/D. The Delta-Sigma A/D architecture provides inherent filtering and

spike smoothing of the analog input signal.

The ±12V inputs must be scaled externally. A full scale reading is achieved when 1.236V is applied to these

inputs. For optimum performance the +12V should be scaled to provide a nominal ¾ full scale reading, while the

−12V should be scaled to provide a nominal ¼ scale reading. The thevenin resistance at the pin should be kept

between 1 kΩ and 7 kΩ.

The −12V monitoring is particularly challenging. It is required that an external offset voltage and external

resistors be used to bring the −12V rail into the positive input voltage region of the A/D input. It is suggested that

the supply rail for the LM94 device be used as the offset voltage. This voltage is usually derived from the P/S 5V

stand-by voltage rail via a ±1% accurate linear regulator. In this fashion we can always assume that the offset

voltage is present when the −12V rail is present as the system cannot be turned on without the 3.3V stand-by

voltage being present.

Table 2. Voltage vs Register Reading

Register

Reading

at

Nominal

Voltage

Register

Reading

at

Maximum

Voltage

Register

Reading

at

Minimum

Voltage

Absolute

Maximum

Range

Normal

Use

Nominal

Voltage

Maximum

Voltage

Minimum

Voltage

AD_IN1

AD_IN2

AD_IN3

AD_IN4

AD_IN5

+12V1

+12V2

+12V3

FSB_Vtt

3GIO

0.927V

1.20V

1.5V

C0h

1.236V

1.60V

2V

FFh

0V

00h

−0.3V to (V_DD+ 0.05V)

−0.3V to +6.0V

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Table 2. Voltage vs Register Reading (continued)

Register

Reading

at

Nominal

Voltage

Register

Reading

at

Maximum

Voltage

Register

Reading

at

Minimum

Voltage

Absolute

Maximum

Range

Normal

Use

Nominal

Voltage

Maximum

Voltage

Minimum

Voltage

AD_IN6

AD_IN7

ICH_Core

Vccp1

1.5V

1.20V

3.30V

5.0V

C0h

40h

C0h

2V

FFh

FAh

FFh

D1h

0V

3.0V

00h

AEh

−0.3V to +6.0V

−0.3V to +6.5V

−0.3V to +6.0V

−0.3V to (V_DD+ 0.05V)

−0.3V to +6.0V

1.60V

4.40V

6.667V

3.333V

2.625V

1.312V

1.236V

3.6V

AD_IN8

Vccp2

AD_IN9

+3.3V

AD_IN10

AD_IN11

AD_IN12

AD_IN13

AD_IN14

AD_IN15

AD_IN16

+5V

SCSI_Core

Mem_Core

Mem_Vtt

Gbit_Core

−12V

2.5V

1.969V

0.984V

0.309V

3.3V

+3.3V S/B

The nominal voltages listed in this table are only typical values. Voltage rails with different nominal voltages can

be monitored, but the register reading at the nominal value is no longer C0h. For example, a Mem_Core rail at

2.5V nominal could be monitored with AD_IN12, or a Mem_Vtt rail at 1.2V could be monitored with AD_IN13.

AD_IN16 is also the power pin of the LM94, therefore special limitations apply to this AD input. The specified

operational voltage range for the LM94 is 3.0V to 3.6V, therefore the voltage input to this pin is limited by this

restriction. Care should also be taken not to apply more than 6V to this pin to prevent catastrophic damage.

RECOMMENDED EXTERNAL SCALING RESISTORS FOR +12V POWER RAILS

The +12V inputs require external scaling resistors. The resistors need to scale 12V down to 0.927V.

R1

to AD_IN1-

V

IN

3

R2

Figure 5. Required External Scaling

Resistors for +12V Power Input

To calculate the required ratio of R1 to R2 use this equation:

R1 12

R2 0.927

=

- 1 = 11.04498

(1)

It is recommended that the equivalent thevenin resistance of the divider be between 1k and 7k to minimize errors

caused by leakage currents at extreme temperatures. The best values for the resistors are: R1=13.7 kΩ and

R2=1.15 kΩ. This yields a ratio of 11.94498, which has a +0.27% deviation from the theoretical. It is also

recommended that the resistors have ±1% tolerance or better.

Each LSB in the voltage value registers has a weight of 12V / 192 = 62.5 mV. To calculate the actual voltage of

the +12V power input, use the following equation:

V_IN= (8-bit value register code) x (62.5 mV)

(2)

RECOMMENDED EXTERNAL SCALING CIRCUIT FOR −12V POWER INPUT

The −12V input requires external resistors to level shift the nominal input voltage of −12V to +0.309V.

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R1

to

V

IN

AD_IN15

R2

3.3V

SB

±1%

+

-

Figure 6. Required External Level Shifting

Resistors for −12V Power Input

The +3.3V standby voltage is used as a reference for the level shifting. Therefore, the tolerance of this voltage

directly effects the accuracy of the −12V reading. To minimize ratio errors, a tolerance of better than ±1% should

be used. It is recommended that the equivalent thevenin resistance of the divider is between 1k and 7k to

minimize errors caused by leakage currents at extreme temperatures. To calculate the ratio of R1 to R2 use this

equation:

(V_IN- V_REF

)

R1

R2

- 1

=

(AD_IN - V_REF

)

(3)

where V_INis the nominal input voltage of −12V, V_REFis the reference voltage of +3.3V and AD_IN is the voltage

required at the AD input for a ¼ scale reading or 0.309V.

Therefore, for this case:

(-12 - 3.3)

R2 (0.309 - 3.3)

R1

- 1 = 4.11535

=

(4)

(5)

Using standard 1% resistor values for R1 of 5.76 kΩ and R2 of 1.4 kΩ yields an R1 to R2 ratio of 4.1143.

The input voltage V_INcan be calculated using the value register reading (VR) using this equation:

VR

+ 1) x [(1.236V x

256

R1

R2

V_IN

= (

) - 3.3V] + 3.3V

= (24.69 mV x VR) - 13.5771V

The table below summarizes the theoretical voltage values for value register readings near −12V.

Value Register

V_IN

% Δ from −12V

-10.0563

-9.8505

-9.6448

-9.4390

-9.2332

-9.0275

-8.8217

-8.6159

-8.4101

-8.2044

-7.9986

-7.7928

-7.5871

-7.3813

-7.1755

-6.9698

-6.7640

-6.5582

-6.3524

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

-13.2068

-13.1821

-13.1574

-13.1327

-13.1080

-13.0833

-13.0586

-13.0339

-13.0092

-12.9845

-12.9598

-12.9351

-12.9104

-12.8858

-12.8611

-12.8364

-12.8117

-12.7870

-12.7623

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Value Register

V_IN

% Δ from −12V

-6.1467

-5.9409

-5.7351

-5.5294

-5.3236

-5.1178

-4.9121

-4.7063

-4.5005

-4.2947

-4.0890

-3.8832

-3.6774

-3.4717

-3.2659

-3.0601

-2.8544

-2.6486

-2.4428

-2.2370

-2.0313

-1.8255

-1.6197

-1.4140

-1.2082

-1.0024

-0.7967

-0.5909

-0.3851

-0.1793

0.0264

0.2322

0.4380

0.6437

0.8495

1.0553

1.2610

1.4668

1.6726

1.8784

2.0841

2.2899

2.4957

2.7014

2.9072

3.1130

3.3188

3.5245

3.7303

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

-12.7376

-12.7129

-12.6882

-12.6635

-12.6388

-12.6141

-12.5894

-12.5648

-12.5401

-12.5154

-12.4907

-12.4660

-12.4413

-12.4166

-12.3919

-12.3672

-12.3425

-12.3178

-12.2931

-12.2684

-12.2438

-12.2191

-12.1944

-12.1697

-12.1450

-12.1203

-12.0956

-12.0709

-12.0462

-12.0215

-11.9968

-11.9721

-11.9474

-11.9228

-11.8981

-11.8734

-11.8487

-11.8240

-11.7993

-11.7746

-11.7499

-11.7252

-11.7005

-11.6758

-11.6511

-11.6264

-11.6018

-11.5771

-11.5524

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Value Register

V_IN

% Δ from −12V

3.9361

4.1418

4.3476

4.5534

4.7591

4.9649

5.1707

5.3765

5.5822

5.7880

5.9938

6.1995

6.4053

6.6111

6.8168

7.0226

7.2284

7.4342

7.6399

7.8457

8.0515

8.2572

8.4630

8.6688

8.8745

9.0803

9.2861

9.4919

9.6976

9.9034

10.1092

83

84

-11.5277

-11.5030

-11.4783

-11.4536

-11.4289

-11.4042

-11.3795

-11.3548

-11.3301

-11.3054

-11.2807

-11.2561

-11.2314

-11.2067

-11.1820

-11.1573

-11.1326

-11.1079

-11.0832

-11.0585

-11.0338

-11.0091

-10.9844

-10.9597

-10.9351

-10.9104

-10.8857

-10.8610

-10.8363

-10.8116

-10.7869

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

ADDING EXTERNAL SCALING RESISTORS TO OTHER ANALOG INPUTS

All analog inputs, except AD_IN1 through AD_IN3 and AD_IN15, include internal resistor dividers. Further scaling

of AD_IN4 through AD_IN14 inputs with external scaling resistors is possible if the errors due to the internal

dividers are accounted. The internal resistors, R_IN1 + R_IN2 shown in Figure 7, will present to the external divider

a minimum resistive load of 140 kΩ.

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LM94

AD_IN4 - AD_IN14

R1

V

IN

to ADC

R_IN

1

R2

R_IN

2

Figure 7.

DYNAMIC Vccp MONITORING USING VID

The AD_IN7 (CPU1 Vccp) and AD_IN8 (CPU2 Vccp) inputs are dynamically monitored using the P1_VIDx and

P2_VIDx inputs to determine the limits. The dynamic comparisons operate independently of the static

comparisons which use the statically programmed limits. The LM94 supports 3 different specifications for the

Voltage Regulator (VRM or VRD) used on motherboards with Intel CPUs with four different VID Modes of

operation. The Voltage Regulator Specifications supported are the VRD10/VRM10, VRD10.2 Extended and

VRD11/VRM11, and in this document they will be referred to as the VRD10, VRD10.2 and VRD11 specifications,

respectively.

According to the VRD 10 specification when a VID signal is ramping to a new value, it steps by one LSB at a

time, and one step occurs every 5 µs. In worse case, up to 20 steps may occur at once over 100 µs. The Vccp

voltage from the VRD has to settle to the new value within 50 µs of the last VID change. The LM94 expects that

the VID changes will not occur more frequently than every 5 µs in the VRD10 mode. Similarly the LM94 can

support the timing requirements of the VRD10.2 and VRD11 specifications.

The VID signals can be changed by the processor under program control, by internal thermal events or by

external control, like force PROCHOT.

The reference voltages selected by each value of the VID code can be found in the different VRM/VRD

specifications. Transient VID values caused by line-to-line skew are ignored by the LM94. See the VRM/VRD

specifications for the worst case line-to-line skew.

The LM94 averages the VID values over a sampling window to determine the average voltage that the VID input

was indicating during the sampling window. At the completion of a voltage conversion cycle the LM94 performs

limit comparisons based on average VID values and not instantaneous values. The upper limit is determined by

adding the upper limit offset to the average voltage indicated by VID. The lower limit is determined by subtracting

the lower limit offset from average voltage indicated by VID. If the AD_IN7 (or AD_IN8) voltage falls outside the

upper and lower limits, an error event is generated. Dynamic and static comparisons are performed once every

100 ms. The averaging time interval is 1.5 ms.

If at any time during the Vccp sampling window, the VID code indicates that the VRD/VRM should turn off its

output, the dynamic Vccp checking is disabled for that sample.

The comparison accuracy is ±25 mV, therefore the comparison limits must be set to include this error. Since the

Vccp voltage may be in the process of settling to a new value (due to a VID change), this settling should be

taken into account when setting the upper and lower limit offsets.

The LM94 has a limitation on the upper limit voltage for dynamic Vccp checking. The upper limit cannot exceed

1.5875V. If the sum of the voltage indicated by VID and the upper offset voltage exceed 1.5875, the upper limit

checking is disabled.

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Pins 11 and 12 have dual purpose. When VRD10 mode is selected they can be used as general purpose inputs

whose state is reflected the BMC and Host Error Status registers. In the other VRD modes they are used as a

VID6 input.

MONITORING ANALOG TEMPERATURE SENSORS

AD_IN11 and AD_IN15 readings can be routed to the fan control logic to facilitate the use of external

temperature sensors such as the LM60. When these inputs are used for temperature sensing the digital output

returned is in signed format, that is the MSb is inverted.

The following table lists critical parameters necessary for converting the binary data to temperature.

LM60

deg

/LSb

LM50

deg

/LSb

Full Scale

(code 256) V

254.5

code V

mV

/LSb

Input

V NOM

AD_

IN11

2.500

(¾ scale)

3.3333

1.2360

3.3138

1.2288

13.0

4.8

2.0833

1.3021

AD_

IN15

0.309

(¼ scale)

0.7725

0.4828

The following table lists the equations to use for converting the AD_IN11 or AD_IN15 Digital Value (DV) to a

temperature value.

Input

LM60 Equation

(DV + 95.44) × 2.0833

(DV + 40.18) × 0.7725

LM50 Equation

(DV + 89.60) × 1.3021

(DV + 24.44) × 0.4828

AD_IN11

AD_IN15

(6)

(8)

(7)

(9)

The following table lists the ideal values generated when using the LM60 at different temperatures.

AD_IN11 Reading

AD_IN15 Reading

LM60

Ideal

Vout

Temp

Signed

Decimal

Signed

Hex

Signed

Decimal

Signed

Hex

0

0.424

-95.44

-83

-81

-79

-76

-74

-71

-69

-67

-64

-62

-59

-57

-55

-52

-50

-47

-45

-43

-40

-38

-35

-33

A1

AD

AF

B1

B4

B6

B9

BB

BD

C0

C2

C5

C7

C9

CC

CE

D1

D3

D5

D8

DA

DD

DF

-40.18

-8

D8

F8

FF

5

25

0.5803

0.6115

0.6428

0.6740

0.7053

0.7365

0.7678

0.7990

0.8303

0.8615

0.8928

0.9240

0.9553

0.9865

1.0178

1.0490

1.0803

1.1115

1.1428

1.1740

1.2053

1.2365

30

-1

35

5

40

12

C

45

18

12

19

1F

25

2C

32

39

3F

46

4C

53

59

60

66

6D

73

7A

7F

50

25

55

31

60

37

65

44

70

50

75

57

80

63

85

70

90

76

95

83

100

105

110

115

120

125

130

89

96

102

109

115

122

127

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The following table lists the expected ideal digital values when using the LM50.

AD_IN11 Reading

AD_IN15 Reading

LM50

Ideal

Vout

Temp

Signed

Decimal

Signed

Hex

Signed

Decimal

Signed

Hex

0

0.5

-89.60

-70

-67

-63

-59

-55

-51

-47

-44

-40

-36

-32

-28

-24

-20

-17

-13

-9

A7

BA

BD

C1

C5

C9

CD

D1

D4

D8

DC

E0

E4

E8

EC

EF

F3

F7

FB

FF

3

-24.44

27

E8

1B

26

30

3A

45

4F

59

64

6E

79

7F

25

0.7500

0.8000

0.8500

0.9000

0.9500

1.0000

1.0500

1.1000

1.1500

1.2000

1.2500

1.3000

1.3500

1.4000

1.4500

1.5000

1.5500

1.6000

1.6500

1.7000

1.7500

1.8000

30

38

35

48

40

58

45

69

50

79

55

89

60

100

110

121

127

65

70

75

80

85

90

95

100

105

110

115

120

125

130

-5

-1

3

6

10

A

V_REFOUTPUT

V_REFis a fixed voltage to be used by an external VRD or as a voltage reference input for the BMC A/D inputs.

V_REFis 2.5V ±1%. There is internal current limit protection for the V_REFoutput in case it gets shorted to supply or

ground accidentally.

PROCHOT BACKGROUND INFORMATION

PROCHOT is an output from a processor that indicates that the processor has reached a predetermined

temperature trip point. At this trip point the processor can be programmed to lower its internal operating

frequency and/or lower its supply voltage by changing the value of the 6 bit VID that it supplies to the VRD. The

final VID setting and the rate at which it transitions to the new VID is programmable within the processor.

If PROCHOT is 100% throttled, it does not mean that the CPU is not executing, but it may mean that the CPU is

about to encounter a thermal trip if the processor temperature continues to rise.

PROCHOT is also an input to some processors so that an external controller can force a thermal throttle based

on external events.

PROCHOT is no longer asserted by the processor when the temperature drops below the predefined thermal trip

point.

Oscillation around the trip point is avoided by the processor by requiring that the temperature be above/below the

trip point for a predetermined period of time. A counter inside the processor is used to track this time and it has

to be incremented to a max count for an above temperature trip and decremented to zero when below the trip

temperature setting, to remove the trip.

The minimum time for PROCHOT assertion is time dependant on the FSB frequency. The minimum time that the

processor asserts PROCHOT is estimated to be 187 µs.

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PROCHOT MONITORING

PROCHOT monitoring applies to both the P1_PROCHOT and P2_PROCHOT inputs. Both inputs are monitored

in the same fashion, but the following description discusses a single monitor. (Px_PROCHOT represents both

P1_PROCHOT and P2_PROCHOT).

PROCHOT monitoring is meant to achieve two goals. One goal is to measure the percentage of time that

PROCHOT is asserted over a programmable time period. The result of this measurement can be read from an 8-

bit register where one LSB equals 1/256th of the PROCHOT Time Interval (0.39%). The second goal is to have a

status register that indicates, as a coarse percentage, the amount of time a processor has been throttled. This

second goal is required in order to communicate information over the NIC using ASF, i.e. status can be sent, not

values.

To achieve the first goal, the PROCHOT input is monitored over a period of time as defined by the PROCHOT

Time Interval Register. At the end of each time period, the 8-bit measurement is transferred to the Current

Px_PROCHOT register. Also at the end of each measurement period, the Current Px_PROCHOT register value

is moved to the Average Px_PROCHOT register by adding the new value to the old value and dividing the result

by 2. Note that the value that is averaged into the Average Px_PROCHOT register is not the new measurement

but rather the previous measurement. If the SMBus writes to the Current P1_PROCHOT (or Current

P2_PROCHOT) register, the capture cycle restarts for both monitoring channels (P1_PROCHOT and

P2_PROCHOT). Also note, that a strict average of two 8-bit values may result in Average Px_PROCHOT

reflecting a value that is one LSB lower than the Current Px_PROCHOT in steady state.

It should be noted that the 8-bit result has a positive bias of one half of an LSB. This is necessary because a

value of 00h represents that Px_PROCHOT was not asserted at all during the sampling window. Any amount of

throttling results in a reading of 01h.

The following table demonstrates the mapping for the 8-bit result:

8–Bit Result

Percentage Thottled

0

1

Exactly 0%

Between 0% and 0.39%

2

Between 0.39% and 0.78%

-

n

Between (n-1)/256 and n/256

-

253

254

255

Between 98.4% and 98.8%

Between 98.8% and 99.2%

Greater than 99.2%

To achieve the second goal, the LM94 has several comparators that compare the measured percentage reading

against several fixed and 1 variable value. The variable value is user programmable.

The result of these comparisons generates several error status bits described in the following table:

Status Description

Comparison Formula

PROCHOT was never de-asserted during monitoring interval.

193 ≤ measured value and not 100%

129 ≤ measured value < 193

100% Throttle

Greater than or equal to 75% and less than 100%

Greater than or equal to 50% and less than 75%

Greater than or equal to 25% and less than 50%

Greater than or equal to 12.5% and less than 25%

Greater than 0% and less than 12.5%

Greater than 0%

65 ≤ measured value < 129

33 ≤ measured value < 65

0 < measured value < 33

0 < measured value

Greater than user limit

user limit < measured value

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These status bits are reflected in the PROCHOT Error Status Registers. Each of the P1_PROCHOT and

P2_PROCHOT inputs is monitored independently, and each has its own set of status registers.

In S3 and S4/5 sleep states, the PROCHOT Monitoring function does not run. VRDx_Hot is disabled from

activating PROCHOT pins in S3 and S4/5. The Current Px_PROCHOT registers are reset to 00h and the

Average Px_PROCHOT registers hold their current state. Once the sleep state changes back to S0, the

monitoring function is restarted. After the first PROCHOT measurement has been made, the measurement is

written directly into the Current and Average Px_PROCHOT registers without performing any averaging.

Averaging returns to normal on the second measurement.

PROCHOT OUTPUT CONTROL

In some cases, it is necessary for the LM94 to drive the Px_PROCHOT outputs low. There are several conditions

that cause this to happen.

The LM94 can be told to logically short the two PROCHOT inputs together. When this is done, the LM94

monitors each of the Px_PROCHOT inputs. If any external device asserts one of the PROCHOT signals, the

LM94 responds by asserting the other PROCHOT signal until the first PROCHOT signal is de-asserted. This

feature should never be enabled if the PROCHOT signals are already being shorted by another means.

Whenever one of the VRDx_HOT inputs is asserted, the corresponding Px_PROCHOT pins are asserted by the

LM94. The response time is less than 10 µs. When the VRDx_HOT input is de-asserted, the Px_PROCHOT pin

is no longer asserted by the LM94. If the LM94 is configured to short the PROCHOT signals together, it always

asserts them together whenever either of the VRDx_HOT inputs is asserted. This response is disabled in sleep

states 3 and 4/5 and can be disabled through the PROCHOT Control register.

Software can manually program the LM94 to drive a PWM type signal onto P1_PROCHOT or P2_PROCHOT.

This is done via the PROCHOT Override register. See the description of this register for more details. Once

again, if the LM94 is configured to short the PROCHOT signals together, it always asserts them together

whenever this function is enabled.

FAN SPEED MEASUREMENT

The fan tach circuitry measures the period of the fan pulses by enabling a counter for two periods of the fan tach

signal. The accumulated count is proportional to the fan tach period and inversely proportional to the fan speed.

All four fan tach signals are measured within 1 second.

Fans in general do not over-speed if run from the correct voltage, so the failure condition of interest is under

speed due to electrical or mechanical failure. For this reason only low-speed limits are programmed into the limit

registers for the fans. It should be noted that, since fan period rather than speed is being measured, a fan tach

error event occurs when the measurement exceeds the limit value.

SMART FAN SPEED MEASUREMENT

If a fan's speed is varied using PWM drive of either of the fans power pins, the tachometer output of the fan is

corrupted. The LM94 includes smart tachometer circuitry that allows an accurate tachometer reading to be

achieved despite the signal corruption. In smart tach mode all four signals are measured within 4 seconds.

A smart tach capture cycle works according to the following steps:

1. Both PWM outputs are synchronized such that they activate simultaneously.

2. Both PWM output active times are extended for up to 50 ms.

3. The number of tach signal periods during the 50 ms interval are tracked:

a) If less than 1 period is sensed during the 50 ms extension the result returned is 3FFh.

b) After one period occurs the count for that period is memorized.

c) If during the 50 ms interval 2 periods do not occur, the tach value reported is the 1 period count multiplied

by 2.

d) If 2 periods do occur, the 2 period count is loaded into the value register and the 50 ms PWM extension is

terminated.

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The lowest two bits in each of the Fan Tach value registers are reserved. The smart tach feature takes

advantage of these bits. In normal tach mode, these bits return 00. In smart tach mode the two bits determine

the accuracy level of the reading. 11 is most accurate (2 periods used) and 10 is the least accurate (1 period

used). If less than 1 period occurred during the measurement cycle, the lower two bits are set to 10.

In smart fan tach mode, the TACH_EDGE field is honored in the LM94 Status/Control register. If only one edge

type is active, the measurement always uses that edge type (rising or falling). If both are active, the

measurement uses whichever edge type occurs first.

Typically the minimum RPM captured by smart fan tach mode is 900 RPM for a fan that produces two pulses per

revolution at about 50% duty cycle.

Inputs/Outputs

Besides all the pins associated with sensor inputs the LM94 has several pins that are assigned for other specific

functions.

ALERT OUTPUT

The ALERT output is an active-low open drain output signal. The ALERT output is used to signal a micro-

controller that one or more sensors have crossed their corresponding limit thresholds. This is generally not a fatal

event unless the micro-controller decides it to be.

If enabled, the ALERT output is asserted whenever any bit in any BMC Error Status register is set (with the

exception of the fixed PROCHOT threshold bits). By definition, when ALERT is enabled, it always matches the

inverse of the BMC_ERR bit in the LM94 Status/Control register. When the ALERT output is disabled, an alert

event can still be determined by reading the state of the BMC_ERR bit.

The ALERT functions like an interrupt. The LM94 does not support the SMBus ARA (Alert Response Address)

protocol.

ALERT is only de-asserted when there are no error status bits set in any BMC Error Status registers.

Alternatively, software can disable the ALERT output to cause it to de-assert. The ALERT output re-asserts once

enabled if any BMC Error Status register bits are still set.

The ALERT output also functions in comparator mode for thermal events, that is the ALERT output will be

asserted for unmasked thermal error events and will de-assert immediately when the error event ceases. The

operation of the ALERT output is controlled by the LM94 Configuration register.

Further information on how the ALERT output behaves can be found in MASKING, ERROR STATUS AND

ALERT.

RESET INPUT/OUTPUT

This pin acts as an active low reset output when power is applied to the LM94. It is asserted when the LM94 first

sees a voltage that exceeds the internal POR level on its +3.3V S/B V_DDinput. The internal registers of the LM94

are reset to their defaults when power is applied.

After this reset has completed, the RESET pin becomes an input. When an external device asserts RESET, the

LM94 clears the LOCK bit in the LM94 Configuration register. This feature allows critical registers to be locked

and provides a controlled mechanism to unlock them.

If the LM94 RESET is not used it must be tied high through an external resistive pull-up to prevent LM94

malfunction.

Within 10 µsec of asserting RESET externally, the Sleep State Control register shall be automatically set to S4/5.

This causes several error events to be masked according to the S4/5 masking definitions. Refer to the register

descriptions for more information. RESET may not be detected if it is asserted for less than 4 µsec.

PWM1 AND PWM2 OUTPUTS

The PWM outputs are used to control the speed of fans. The duty cycle of each output is automatically controlled

by the temperature of one or more temperature zones. They are also influenced by various other inputs and

registers. See FAN CONTROL for further information on the behavior of the PWM outputs.

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VRD1_HOT AND VRD2_HOT INPUTS

These inputs monitor the thermal sensor associated with each processor VRD on a baseboard. When one of the

inputs is activated, it indicates that the VRD has exceeded a predetermined temperature threshold. The LM94

responds by gradually increasing the duty cycle of any PWM outputs that are bound to the corresponding

processor and setting the appropriate error status bits. The corresponding PROCHOT signal is also asserted.

See the FAN CONTROL and the PROCHOT OUTPUT CONTROL for more information.

GPIO and GPI PINS

The LM94 has 8 GPIO pins than can act as either as general purpose inputs or outputs and 2 GPI pins that can

act as general purpose inputs. Each can be configured and controlled independently. When acting as an input

the pin can be masked to prevent it from setting a corresponding bit in the GPI Error status registers. Some of

these pins can also function as tachometer or VID inputs.

FAN TACH INPUTS

The fan inputs are Schmitt-Trigger digital inputs. Schmitt-Trigger input circuitry is included to accommodate slow

rise and fall times typical of fan tachometer outputs.

The maximum input signal range is 0V to +6.0V, even when V_DDis less than 5V. In the event that these inputs

are supplied from fan outputs, which exceed 0V to +6.0V, either resistive attenuation of the fan signal or diode

clamping must be included to keep inputs within an acceptable range, thereby preventing damage to the LM94.

Hot plugging fans can involve spikes on the Tach signals of up to 12V so diode protection or other circuitry is

required. For “Hot Plug” fans, external clamp diodes may be required for signal conditioning.

SMBus Interface

The SMBus is used to communicate with the LM94. LM94 SMBus interface lines are designed to be tolerant to

5V signalling. Necessary pull-ups are located on the baseboard. Care should be taken to ensure that only one

pull-up is used for each SMBus signal. The SMBus interface obeys the SMBus 2.0 protocols and signaling levels.

The SMBus interface of the LM94 does not load down the SMBus if no power is applied to the LM94. This allows

a module containing the LM94 to be powered down and replaced, if necessary.

SMBus ADDRESSING

Each time the LM94 is powered up, it latches the assigned SMBus slave address (determined by ADDR_SEL)

during the first valid SMBus transaction in which the first five bits of the targeted slave address match those of

the LM94 slave address. Once the address has been latched, the LM94 continues to use that address for all

future transactions until power is lost.

The address select input detects three different voltage levels and allows for up to 3 devices to exist in a system.

The address assignment is as follows:

Address Select Pin

(ADDR_SEL)

Slave Address

Assignment

High

V_DD/2

Low

01011 01

01011 10

01011 00

DIGITAL NOISE EFFECT ON SMBus COMMUNICATION

Noise coupling into the digital lines (greater than 150mV), overshoot greater than V_DDand undershoot less than

GND, may prevent successful SMBus communication with the LM94. SMBus No Acknowledge (NACK) is the

most common symptom, causing unnecessary traffic on the bus. Although, the SMBus maximum frequency of

communication is rather low (100 kHz max), care still needs to be taken to ensure proper termination within a

system with multiple parts on the bus and long printed circuit board traces. The LM94 includes on chip low-pass

filtering of the SMBCLK and SMBDAT signals to make it more noise immune. Minimize noise coupling by

keeping digital traces out of switching baseboard areas as well as ensuring that digital lines containing high

speed data communications cross at right angles to the SMBDAT and SMBCLK lines.

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GENERAL SMBus TIMING

The SMBus 2.0 specification defines specific conditions for different types of read and write operations but in

general the SMBus protocol operates as follows:

The master initiates data transfer by establishing a START condition, defined as a high to low transition on the

serial data line SMBDAT while the serial clock line SMBCLK remains high. This indicates that a data stream

follows. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8

bits. This consists of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data

transfer, i.e. whether data is written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low during the

high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for

data to be read from or written to it. If the R/W bit is a 0 then the master writes to the slave device. If the R/W bit

is a 1 the master reads from the slave device.

Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge bit.

Data transitions on the data line must occur during the low period of the clock signal and remain stable during

the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal.

If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the

slave device what to expect next. It may be an instruction, such as telling the slave device to expect a block

write, or it may simply be a register address that tells the slave where subsequent data is to be written.

Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a

slave device during a read operation. Before doing a read operation, it is necessary to do a write operation to tell

the slave what sort of read operation to expect and/or the address from which data is to be read.

When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will

allow the data line to go high during the 10th clock pulse to assert a STOP condition. In READ mode, the slave

drives the data not the master. For the bit in question, the slave is looking for an acknowledge and the master

doesn't drive low. This is known as ‘No Acknowledge’. The master then takes the data line low during the low

period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.

Note, a repeated START may be given only between a write and read operation that are in succession.

SMBus ERROR SAFETY FEATURES

To provide a more robust SMBus interface, the LM94 incorporates a timeout feature for both SMBCLK and

SMBDAT. If either signal is low for a long period of time (see SMBus AC specs), the LM94 SMBus state machine

reverts to the idle state and waits for a START signal. Large block transfers of all zeros should be avoided if the

SMBCLK is operating at a very low frequency to avoid accidental timeouts. Pulling the Reset pin low does not

reset the SMBus state machine. If the LM94 SMBDAT pin is low during a system reset, the LM94’s state

machine timeouts and resets automatically. If the LM94’s SMBDAT pin is high during a system reset, the first

assertion of a start by the master resets the LM94’s interface state machine.

Although it is a violation of the SMBus specification, in some cases a START or STOP signal occurs in the

middle of a byte transfer instead of coming after an acknowledge bit. If this occurs, only a partial byte was

transferred. If a byte was being written, it is aborted and the partial byte is not committed. If a byte was being

read from a read-to-clear register, the register is not cleared.

SERIAL INTERFACE PROTOCOLS

The LM94 contains volatile registers, the registers occupy address locations from 00h to EFh.

Data can be read and written as a single byte, a word, or as a block of several bytes. The LM94 supports the

following SMBus/I²C transactions/protocols:

—

Send Byte

Write Byte

Write Word

SMBus Write Block

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—

I²C Block Write

Read Byte

Read Word

SMBus Read Block

SMBus Block-Write Block-Read Process Call

I²C Block Read

In addition to these transactions the LM94 supports a few extra items and also has some behavior that must be

defined beyond the SMBus 2.0 specification. No other SMBus 2.0 transactions are supported (PEC, ARA etc.).

The SMBus specification defines several protocols for different types of read and write operations. The ones

used in the LM94 are discussed below. The following abbreviations are used in the diagrams:

S

— START

P

— STOP

R

W

A

/A

— READ

— WRITE

— ACKNOWLEDGE

— NO ACKNOWLEDGE

Address Incrementing

The established base address does not increment. Repeatedly reading without re-establishing a new base

address returns data from the same address each time. I²C read transactions can use this information and skip

reestablishing the base address, when only one master is used. One exception to this rule exists when a block

write and block read is used to emulate a block write/read process call. This is detailed later, see the SMBus

Block-Write Block-Read Process Call description.

Block Command Code Summary

Block command codes control the block read and write operations of the LM94 as summarized in the following

table:

Command Code Name

Block Write Command

Value

F0h

Description

SMBus Block Write Command Code

SMBus Block Write/Read Process Call

Block Read Command

Fixed Block 0

F1h

F2h

Fixed Block Read Command Code: address

40h, size 8 bytes

Fixed Block 1

Fixed Block 2

Fixed Block 3

Fixed Block 4

Fixed Block 5

Fixed Block 6

Fixed Block 7

Fixed Block 8

F3h

F4h

F5h

F6h

F7h

F8h

F9h

FAh

Fixed Block Read Command Code: address

48h, size 8 bytes

Fixed Block Read Command Code: address

50h, size 6 bytes

Fixed Block Read Command Code: address

56h, size 16 bytes

Fixed Block Read Command Code: address

67h, size 4 bytes

Fixed Block Read Command Code: address

6Eh, size 8 bytes

Fixed Block Read Command Code: address

78h, size 12 bytes

Fixed Block Read Command Code: address

90h, size 32 bytes

Fixed Block Read Command Code: address

B4h, size 8 bytes

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Command Code Name

Value

Description

Fixed Block 9

FBh

Fixed Block Read Command Code: address

C8h, size 8 bytes

Fixed Block 10

Fixed Block 11

FCh

FDh

Fixed Block Read Command Code: address

D00h, size 16 bytes

Fixed Block Read Command Code: address

E5h, size 9 bytes

Write Operations

The LM94 supports the following SMBus write protocols.

Write Byte

In this operation the master device sends an address byte and one data byte to the slave device, as follows:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a command code (register address).

5. The slave asserts ACK.

6. The master sends the data byte.

7. The slave asserts ACK.

8. The master asserts a STOP condition to end the transaction.

1

2

3

4

5

6

7

8

S

Slave

Address

W

A

Register

Address

A

Data

Byte

A

P

Write Word

In this operation the master device sends an address byte and two data bytes to the slave device, as follows:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a command code (register address).

5. The slave asserts ACK.

6. The master sends the low data byte.

7. The slave asserts ACK.

8. The master sends the high data byte.

9. The slave asserts ACK.

10. The master asserts a STOP condition to end the transaction.

1

2

3

4

5

6

7

8

9

10

P

S

Slave

Address

W

A

Register

Address

A

Data Byte

Low

A

Data Byte

High

A

SMBus Write Block to Any Address

The start address for a block write is embedded in this transaction. In this operation the master sends a block of

data to the slave as follows:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a command code that tells the slave device to expect a block write. The LM94 command

code for a block write is F0h.

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5. The slave asserts ACK.

6. The master sends a byte that tells the slave device how many data bytes it will send (N). The SMBus

specification allows a maximum of 32 data bytes to be sent in a block write.

7. The slave asserts ACK.

8. The master sends data byte 1, the starting address of the block write.

9. The slave asserts ACK after each data byte.

10. The master sends data byte 2.

11. The slave asserts ACK.

12. The master continues to send data bytes and the slave asserts ACK for each byte.

13. The master asserts a STOP condition to end the transaction.

1

2

3

4

5

6

7

8

9

10

11

A

∼

12

13

P

S

Slave

Address

W

A

Command

F0h

(Block

Write)

A

Byte

Count

(N)

A

Data

Byte 1

(Start

A

Data

Byte 2

Data

Byte N

A

Address)

Special Notes

1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM94 but are

ignored.

2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.

3. The Byte Count field is ignored by the LM94. The master device may send more or less bytes and the LM94

accepts them.

4. The SMBus specification requires that block writes never exceed 32 data bytes. Meeting this requirement

means that only 31 actual data bytes can be sent (the register address counts as one byte). The LM94 does

not care if this requirement is met.

I²C™ Block Write

In this transaction the master sends a block of data to the LM94 as follows:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends the starting address of the block write.

5. The slave asserts ACK after each data byte.

6. The master sends data byte 1.

7. The slave asserts ACK.

8. The master continues to send data bytes and the slave asserts ACK for each byte.

9. The master asserts a STOP condition to end the transaction

1

2

3

4

5

6

7

8

9

S

Slave Address

W

A

Register

Address

A

Data

Byte 1

A

∼

Data

Byte N

A

P

Special Notes:

1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM94 but are

ignored.

2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.

Read Operations

The LM94 uses the following SMBus read protocols.

Read Byte

In the LM94, the read byte protocol is used to read a single byte of data from a register. In this operation the

master device receives a single byte from a slave device, as follows:

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1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a register address.

5. The slave asserts an ACK.

6. The master sends a Repeated START.

7. The master sends the slave address followed by the read bit (high).

8. The slave asserts an ACK.

9. The master receives a data byte and asserts a NACK.

10. The master asserts a STOP condition and the transaction ends.

1

2

3

4

5

6

7

8

9

10

P

S

Slave

Address

W

A

Register

Address

A

S

Slave

Address

R

A

Data

Byte

/A

Read Word

In the LM94, the read word protocol is used to read two bytes of data from a register or two consecutive

registers. In this operation the master device reads two bytes from a slave device, as follows:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a register address.

5. The slave asserts an ACK.

6. The master sends a Repeated START.

7. The master sends the slave address followed by the read bit (high).

8. The slave asserts an ACK.

9. The master receives the Low data byte and asserts an ACK.

10. The master receives the High data byte and asserts a NACK.

11. The master asserts a STOP condition and the transaction ends.

1

2

3

4

5

6

7

8

9

10

11

P

S

Slave

Address

W

A

Register

Address

A

S

Slave

Address

R

A

Data

Byte Low

A

Data

Byte High

/A

SMBus Block-Write Block-Read Process Call

This transaction is used to read a block of data from the LM94. Below is the sequence of events that occur in this

transaction:

1. The master device asserts a START condition.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK.

4. The master sends a command code that tells the slave device to expect a block read (F1h) and the slave

asserts ACK.

5. The master sends the Byte Count for this write which is 2 and the slave asserts ACK.

6. The master sends the Start Register Address for the block read and the slave asserts the ACK.

7. The master sends the Byte Count (1-32) for the block read processes call and the slave asserts ACK.

8. The master asserts a repeat START condition.

9. The master sends the 7-bit slave address followed by the read bit (high).

10. The slave asserts ACK.

11. The master receives a byte count data byte that tells it how many data bytes will received. This field reflects

the number of bytes requested by the Byte Count transmitted to the LM94. The SMBus specification allows a

maximum of 32 data bytes to be received in a block read. Then master asserts ACK.

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12. The master receives byte 1 and then asserts ACK.

13. The master receives byte 2 and then asserts ACK.

14. The master receives N-3 data bytes, and asserts ACK for each one.

15. The master receives data byte N and asserts a NACK.

16. The master asserts a STOP condition to end the transaction.

1

2

3

4

5

6

7

8

9

10

A

∼

S

Slave

Address

W

A

Block

Read

Command

Code (F1h)

A

Byte

Count

(2h)

A

Start

Register

Address

A

Byte

A

S

Slave

Address

R

Count

(1–20h)

(N)

∼

11

12

13

14

15

/A

16

Byte

A

Data

Byte 1

A

Data

Byte 2

A

∼

Data

Byte N

P

Count

(1–20h)

(N)

Special Notes:

1. The LM94 returns 00h when address locations outside of normal address space are read.

2. Block reads do not wrap around from address FFh to 00h

3. If the master acknowledges more bytes that it requested, the LM94 continues to supply data until the master

does not acknowledge a byte.

4. If the master does not acknowledges a byte to prematurely abort a block read, the LM94 gets off the bus to

allow the master to issue a STOP signal.

Simulated SMBus Block-Write Block-Read Process Call

Alternatively, if the master cannot support an SMBus Block-Write Block-Read process call, it can be emulated by

two transactions (a block write followed by a block read). This should only be done in a single master system,

since in a dual master system collisions can occur that corrupt the data and transaction. Below is the sequence

of events for these transactions:

1. The master issues a START to start this transaction.

2. The master sends the 7-bit slave address followed by a write bit (low).

3. The slave asserts the ACK.

4. The master sends the Block Read command code (F1h) and the slave asserts the ACK.

5. The master sends the Byte Count (2h) for this transaction and the slave asserts the ACK.

6. The master sends the Start Register Address and the slave asserts the ACK.

7. The master sends the Byte Count (1-20h) for the Block-Read Process Call and the slave asserts the ACK.

8. The master sends a STOP to end this transaction.

9. The master sends a START to start this transaction.

10. The master sends the 7-bit slave address followed by a write bit (low) and the slave asserts the ACK.

11. The master sends the Block Read Command code (F1h) and the slave asserts the ACK.

12. The master sends a repeat START.

13. The master sends the 7-bit slave address followed by a read bit (high) and the slave asserts the ACK.

14. The master receives Byte Count (this matches the size sent by the master in step 7) and asserts the ACK.

15. The master receives Data Byte 1 and asserts the ACK.

16. The master receives Data Byte 2 and asserts the ACK.

17. The master receives N-3 data bytes, and asserts ACK for each one.

18. The master receives the last data byte and asserts a NACK.

19. The master issues a STOP to end this transaction.

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1

2

3

4

5

6

7

8

9

10

∼

S

Slave

Address

W

A

Block

Read

Command

Code

A

Byte

Count

(2h)

A

Start

Register

Address

A

Byte

A

P

S

Slave

Address

W

A

Count

(1–20h)

(N)

(F1h)

∼

11

12 13

Slave

Address

14

15

16

17

16

Block

Read

Command

Code

A

S

R

A

Byte

A

Data

Byte 1

A

Data

Byte 2

A

∼

Data

Byte N

/A

P

Count

(1–20h)

(N)

(F1h)

Special Notes:

1. Steps 9 through 19 can be repeated to read another block of data. The address auto-increments such that

the next block starts where the last block left off. The size returned by the LM94 is the same each time.

2. The LM94 returns 00h when address locations outside of normal address space are read.

3. Block reads do not wrap around from address FFh to 00h

4. If the master acknowledges more bytes that it requested, the LM94 continues to supply data until the master

does not acknowledge a byte.

5. If the master does not acknowledges a byte to prematurely abort a block read, the LM94 gets off the bus to

allow the master to issue a STOP signal.

6. After a block read is finished, the base address of the LM94 is updated to point to the byte just beyond the

last byte read.

SMBus Fixed Address Block Reads

Block reads can be performed from pre-defined addresses. A special command code has been reserved for each

pre-defined address. See the Block Command Code Summary for more details on the command codes. Below is

the sequence of events that occur for this type of block read:

1. The master sends a START to start this transaction.

2. The master sends the 7-bit slave address followed by a write bit (low).

3. The slave asserts an ACK.

4. The master sends a Fixed Block Command Code (F2h-FDh) and the slave asserts an ACK.

5. The master sends a repeated START.

6. The master sends the 7-bit slave address followed by a read bit (high).

7. The slave asserts an ACK.

8. The master receives the Byte Count (depends on the Fixed Block Command Code used) and asserts an

ACK.

9. The master receives the first data byte and asserts an ACK.

10. The master continues to receive data bytes and asserting an ACK.

11. The master receives the last data byte.

12. The master asserts a NACK.

13. The master issues a STOP to end this transaction.

1

2

3

4

5

6

7

8

9

10 11

Data

Byte N

12 13

/A

S

Slave

Address

W

A

Fixed

Block

Command

Code

A

S

Slave

Address

R

A

Byte

Count

(N)

A

Data

Byte 1

A

∼

P

(F2h–FDh)

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Special Notes:

1. The LM94 returns 00h when address locations outside of normal address space are read.

2. Block reads do not wrap around from address FFh to 00h.

3. If the master acknowledges more bytes that it requested, the LM94 continues to supply data until the master

does not acknowledge a byte.

4. If the master does not acknowledges a byte to prematurely abort a block read, the LM94 gets off the bus to

allow the master to issue a STOP signal.

I²C Block Reads

The LM94 supports I²C block reads. The following sequence of events occur in this transaction:

1. The master sends a START to start this transaction .

2. The master send 7-bit slave address followed by a write bit (low).

3. The slave asserts an ACK.

4. The master sends the register address and the slave asserts an ACK.

5. The master sends a repeated START.

6. The master sends the 7-bit slave address followed by a read bit (high).

7. The slave asserts an ACK.

8. The master receives Data Byte 1 and asserts an ACK.

9. The master continues to receive bytes and asserting an ACK for each byte received.

10. The master receives the last byte.

11. The master asserts a NACK.

12. The master issues a STOP.

1

2

3

4

5

6

7

8

9

∼

10

11 12

/A

S

Slave

Address

W

A

Register

Address

A

S

Slave

Address

R

A

Data

Byte 1

A

Data

Byte 2

A

Data

Byte N

P

Special Notes:

1. The LM94 returns 00h when address locations outside of normal address space are read.

2. Block reads do not wrap around from address FFh to 00h.

3. If the master acknowledges more bytes that it requested, the LM94 continues to supply data until the master

does not acknowledge a byte.

4. If the master does not acknowledges a byte to prematurely abort a block read, the LM94 gets off the bus to

allow the master to issue a STOP signal.

READING AND WRITING 16-BIT REGISTERS

Whenever the low byte of a 16-bit register is read, the high byte is frozen. After the high byte is read, it is

unfrozen. This ensures that the entire 16-bit value is read properly and the high byte matches with the low byte.

If the low byte of a different 16-bit register is read, the currently frozen high byte is unfrozen and the high byte of

the new 16-bit register is frozen. In a system with two SMBus masters, it is very important that only one master

reads any 16-bit registers at a time. One possible method to achieve this would involve using 16-bit SMBus

reads (instead of two separate 8-bit reads) to read 16-bit registers.

Whenever the low byte of a 16-bit register is written, the write is buffered and does not take effect until the

corresponding high byte is written. If the low byte of a different 16-bit register is written, the previously buffered

low byte of the first register is discarded. If a device attempts to write the high byte of a 16-bit register, and the

corresponding low byte was not written (or was discarded), then the LM94 will NACK the byte.

Using The LM94

POWER ON

The LM94 generates a power on reset signal on RESET when power is applied for the first time to the part.

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RESETS

Upon power up, the RESET output is asserted when the voltage on the power supply crosses the power-on-reset

threshold level (see the Electrical Characteristics). The RESET output is open-drain and should be used with an

external pull-up resistor connected to V_DD. Once the power on reset has completed, the RESET pin becomes an

input and 10 µs after assertion of RESET the LOCK bit in the LM94 Configuration register shall be cleared. In

addition, 10 µs after assertion of RESET the sleep control register shall be automatically set to S4/S5. This

causes several error events to be masked according to the S4/S5 masking definitions. Since the RESET pin

becomes an active input, it must not be left floating at any time as this may cause the LM94 to drift into S4/S5

and thus have unpredictable behavior. RESET must be asserted for more than 4µs in order to ensure detection.

Power

On Reset

External

Reset

Register Types

Factory regs

x

BMC Error Status regs

Host Error Status regs

Value regs

Limit regs

x

Setup regs

x

LM94 Configuration Lock Bit

LM94 Configuration GMSK Bit

Sleep Mask

x

x (reset)

x

Sleep State Control

Other Mask regs

x

All other registers are not effected by power on reset or external reset.

ADDRESS SELECTION

LM94 is designed to be used primarily in dual processor server systems that may require only one monitoring

device.

If multiple LM94 devices are implemented in a system, they must have unique SMBus slave addresses. See the

SMBus ADDRESSING for more information.

The board designer may apply a 10 kΩ pull-down and/or pull-up resistors to ground and/or to 3.3V SB V_DDon

the ADDR_SEL pin. The LM94 is designed to work with resistors of 5% tolerance for the case where two

resistors are required. Upon the first SMBus communication to the part, the LM94 assigns itself an SMBus

address according to the ADDR_SEL input.

Address

Select

Board

Implementation

SMBus

Address

less-than 10% of V_DD

Pulled to ground through a 10 kΩ resistor

0101 100b

0101 110b

≈ V_DD/2

10 kΩ (5%) Resistor to 3.3V SB V_DDand to

Ground

greater-than 90% of V_DD

Pulled to 3.3V SB V_DDthrough a 10 kΩ

0101 101b

resistor

DEVICE SETUP

BIOS executes the following steps to configure the registers in the LM94. All steps may not be necessary if

default values are acceptable.

Set limits and parameters (not necessarily in this order):

•

Set up Fan control

Set up PWM temperature bindings

Set fan tach limits

Set fan boost temperature and hysteresis

Set the VRD_HOT and PROCHOT PWM ramp control rate

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•

Enable Smart Tach Mode and Tachometer Input to PWM binding (required with PWM drive of fan ground or

power pins)

•

Set the temperature absolute limits

Set the temperature hysteresis values

Set temperature filtered or unfiltered usage

Set the Zone Adjustment Offset temperature

Set the PROCHOT override and time interval values

Set the PROCHOT user limit

Enable THERMTRIP masking of error events (if GPIO4 and GPIO5 are used as THERMTRIP inputs)

Set voltage sensor limits and hysteresis

Set the Dynamic Vccp offset limits

Set the Sleep State control and mask registers

Set Other Mask Registers (GPI Error, VRDx_HOT, and Dynamic Vccp limit checking)

Set start bit to select user values and unmask error events

Set the sleep state to 0

Set Lock bit to lock the limit and parameter registers (optional)

ROUND ROBIN VOLTAGE/TEMPERATURE CONVERSION CYCLE

The LM94 monitoring function is started as soon as the part is powered up. The LM94 performs a “round robin”

sampling of the inputs, in the order shown below. Each cycle of the round robin is completed in less than 100

ms.

The results of the sampling and conversions can be found in the value registers and are available at any time.

Channel #

Input

Typical Assignment

Internal Temperature Reading

3

1

Temp Zone 3

Temp Zone 1a

Temp Zone 1b

Temp Zone 2a

Temp Zone 2b

AIN1

Remote Diode 1a Temp Reading

Remote Diode 1b Temp Reading (if selected)

2

Remote Diode 2a Temp Reading

Remote Diode 2b Temp Reading (if selected)

4

+12V1 (if selected)

+12V2 (if selected)

+12V3

5

AIN2

6

AIN3

7

AIN4

FSB_Vtt

8

AIN5

3GIO/PXH/MCH_Core

ICH_Core

9

AIN6

10

11

12

13

14

15

16

17

18

19

AIN7

CPU_1Vccp

CPU2_Vccp

3.3V

AIN8

AIN9

AIN10

+5V

AIN11

SCSI_Core

Mem_Core

Mem_Vtt

AIN12

AIN13

AIN14

GBIT_Core

−12V

AIN15

AIN16

3.3V SB V_DDSupply Rail

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ERROR STATUS REGISTERS

The LM94 contains several error status registers for the BMC side, and duplicated error status registers for the

Host side. These registers are used to reflect the state of all the possible error conditions that the LM94 monitors.

The BMC/Host Error Status registers hold a set bit until the event is cleared by software, even if the condition

causing the error event goes away.

To clear a bit in the Error Status registers, a ‘1’ has to be written to the specific bit that is required to be cleared.

If the event that caused the error is no longer active then the bit is cleared.

Clearing a bit in a BMC Error Status register does not clear the corresponding bit in the Host Error Status

register or vise versa.

ASF Mode

Error Status registers function allow the LM94 to act as a legacy sensor (6.1.2 of ASF spec DSP0114 rev 2) and

to easily connect to the SMBus of an ASF capable NIC chip.

The LM94 can be placed into ASF mode by setting the appropriate bit in the LM94 Status/Control register. Once

this bit is set, the BMC Error Status registers become read-to-clear. Writing a ‘1’ to clear a particular bit is also

allowed in ASF mode. The Host Error Status registers are not effected by ASF mode.

MASKING, ERROR STATUS AND ALERT

Masking is always applied to bits in the HOST and BMC Error Status registers. If an event is masked, the

corresponding error bit in the HOST or BMC Error Status registers is prevented from ever being set. As a result,

this prevents the event from ever causing ALERT to be asserted. Masking an event does not clear its associated

Error Status bit if it is currently set.

Voltage errors are masked by writing a high voltage limit value of FFh. This is the default high limit for all

voltages.

Temperature errors are masked by writing a high temperature limit value of 80h. This is the default high limit for

all temperatures. Masking a temperature channel masks both temperature errors and diode fault errors.

The GPI Mask register allows GPI errors to be masked. Any bits that are set in this register mask events for the

corresponding GPIO_x pin.

User PROCHOT status is not really an error but it can be used to notify the user of processor throttling past a

preset USER limit. A user limit of FFh acts as the mask for this register. Error bits associated with the predefined

PROCHOT thresholds cannot be masked. It is important to note though, that these error bits do not cause

BMC_ERR, HOST_ERR, or ALERT to be asserted under any condition.

Fan tach errors are masked if the tach limit for the given tach is set to FFh .

GPI errors and VRDx_HOT errors can be masked by setting the appropriate bit in the GPI and Miscellaneous

Error Mask registers.

When the LM94 powers up, the ALERT output is disabled. The ALERT output can be enabled by setting the

ALERT_EN bit in the LM94 Configuration register.

In addition the manual masking options, the LM94 also masks some errors depending on the sleep state of the

system. The sleep state of the system is communicated to the LM94 by writing to the Sleep State Control

register. Some types of error events are always masked in certain sleep modes. Some types of error events are

optionally masked in certain sleep modes if their sleep mask register bit is set. Refer to the register descriptions

for more information.

LAYOUT AND GROUNDING

Analog components such as voltage dividers should be physically located as close as possible to the LM94. See

PCB Layout for Minimizing Noise for thermal diode layout recommendations.

The LM94 bypass capacitors, the parallel combination of 100 pF, 10 µF (electrolytic or tantalum) and 0.1 µF

(ceramic) bypass capacitors must be connected between power pin (pin 39) and ground, and should be located

as close as possible to the LM94. The 100 pF capacitor should be placed closest to the power pin.

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THERMAL DIODE APPLICATION

To measure temperature external to the LM94, use a remote discrete diode to sense the temperature of external

objects or ambient air. The temperature of a discrete diode is affected, and often dominated, by the temperature

of its leads.

Most silicon diodes do not lend themselves well to this application. It is recommended that a MMBT3904

transistor type base emitter junction be used with the collector tied to the base.

Figure 8. Thermal Diode Temperature vs. LM94 Temperature Reading

125

100

_

75

_

50

_

25

_

0_

25

_

50

_

100

_

125

_

75

DIODE TEMPERATURE (°C)

DIODE NON-IDEALITY

Diode Non-Ideality Factor Effect on Accuracy

When a transistor is connected as a diode, the following relationship holds for variables V_BE, T and I_F:

V_BE

h x V_t

I_F= I_Sx e

where:

V_t=

-1

(10)

(11)

k T

q

•

q = 1.6×10⁻¹⁹Coulombs (the electron charge),

T = Absolute Temperature in Kelvin

k = 1.38×10⁻²³joules/K (Boltzmann's constant),

η is the non-ideality factor of the process the diode is manufactured on,

I_S= Saturation Current and is process dependent,

I_f= Forward Current through the base emitter junction

V_BE= Base Emitter Voltage drop

In the active region, the -1 term is negligible and may be eliminated, yielding the following equation

V_be

hV_t

e

I_F= I_S

(12)

In Equation 12, η and I_Sare dependant upon the process that was used in the fabrication of the particular diode.

By forcing two currents with a well controlled ratio(I_F2/I_F1) and measuring the resulting voltage difference, it is

possible to eliminate the I_Sterm. Solving for the forward voltage difference yields the relationship:

I_F2

I_F1

K x T

q

DV_BE= h x

x ln

(13)

35

Solving Equation 13 for temperature yields:

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DV_BEx q

T =

I_F2

h x k x ln

I_F1

(14)

Equation 14 holds true when a diode connected transistor such as the MMBT3904 is used. When this “diode”

equation is applied to an integrated diode such as a processor transistor with its collector tied to GND as shown

in Figure 9 it will yield a wide non-ideality spread. This wide non-ideality spread is not due to true process

variation but due to the fact that Equation 14 is an approximation.

TruTherm technology uses the transistor equation, Equation 15, which is a more accurate representation of the

topology of the thermal diode found in an FPGA or processor.

DV_BEx q

T =

I_C2

h x k x ln

I_C1

(15)

Intel^®

PROCESSOR

I_E= I_F

100 pF

1

2

3

4

D1a+

D1-

I_R

D2a+

D2-

I_C

LM94

I_F

Q1

MMBT3904

I_R

Figure 9. Thermal Diode Current Paths

TruTherm should only be enabled when measuring the temperature of a transistor integrated as shown in the

processor of Figure 9, because Equation 15 only applies to this topology.

Calculating Total System Accuracy

The voltage seen by the LM94 also includes the I_FR_Svoltage drop of the series resistance. The non-ideality

factor, η, is the only other parameter not accounted for and depends on the diode that is used for measurement.

Since ΔV_BEis proportional to both η and T, the variations in η cannot be distinguished from variations in

temperature. Since the non-ideality factor is not controlled by the temperature sensor, it will directly add to the

inaccuracy of the sensor. For the Pentium D processor on 65nm process, Intel specifies a +4.06%/−0.89%

variation in η from part to part when the processor diode is measured by a circuit that assumes diode equation,

Equation 14, as true. As an example, assume a temperature sensor has an accuracy specification of ±2.5°C at a

temperature of 75 °C (348 Kelvin) and the processor diode has a non-ideality variation of +4.06%/−0.89%. The

resulting system accuracy of the processor temperature being sensed will be:

T_ACC= ± 2.5°C + (+4.06% of 348 K) = +16.6 °C

(16)

and

T_ACC= ± 2.5°C + (−0.89% of 348 K) = −5.6 °C

(17)

TruTherm technology uses the transistor equation, Equation 15, resulting in a non-ideality spread that truly

reflects the process variation which is very small. The transistor equation non-ideality spread is ±0.4% for the

Pentium D processor on 65nm process. The resulting accuracy when using TruTherm technology improves to:

T_ACC= ±2.5°C + (±0.4% of 348 K) = ± 3.9 °C

(18)

The next error term to be discussed is that due to the series resistance of the thermal diode and printed circuit

board traces. The thermal diode series resistance is specified on most processor data sheets. For the Pentium D

processor on 65 nm process, this is specified at 4.52Ω typical. The LM94 accommodates the typical series

resistance of the Pentium D processor on 90 nm process. The error that is not accounted for is the spread of the

Pentium's series resistance, that is 2.79Ω to 6.24Ω or ±1.73Ω. The equation to calculate the temperature error

due to series resistance (T_ER) for the LM94 is simply:

T_ER= R_PCBx 0.62°C/ W

(19)

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Solving Equation 19 for R_PCBequal to ±1.73Ω results in the additional error due to the spread in the series

resistance of ±1.07°C. The spread in error cannot be canceled out, as it would require measuring each individual

thermal diode device. This is quite difficult and impractical in a large volume production environment.

Equation 19 can also be used to calculate the additional error caused by series resistance on the printed circuit

board. Since the variation of the PCB series resistance is minimal, the bulk of the error term is always positive

and can simply be cancelled out by subtracting it from the output readings of the LM94.

Compensating for Different Non-Ideality

In order to compensate for the errors introduced by non-ideality, the temperature sensor is calibrated for a

particular processor. Texas Instruments' temperature sensors are always calibrated to the typical non-ideality and

series resistance of a given processor type. The LM94 is calibrated for two non-ideality factors and series

resistance values thus supporting the MMBT3904 transistor and the Pentium D processor on 65nm process

without the requirement for additional trims. For most accurate measurements TruTherm mode should be turned

on when measuring the Pentium D processor on the 65nm process the error introduced by the false non-ideality

spread (see Diode Non-Ideality Factor Effect on Accuracy). When a temperature sensor calibrated for a

particular processor type is used with a different processor type, additional errors are introduced.

Temperature errors associated with non-ideality of different processor types may be reduced in a specific

temperature range of concern through use of software calibration. Typical non-ideality specification differences

cause a gain variation of the transfer function, therefore the center of the temperature range of interest should be

the target temperature for calibration purposes. The following equation can be used to calculate the temperature

correction factor (T_CF) required to compensate for a target non-ideality differing from that supported by the LM94.

T_CF= [(η_S−η_Processor) ÷ η_S] × (T_CR+ 273 K)

(20)

where

•

η_S= LM94 non-ideality for accuracy specification

η_T= target thermal diode typical non-ideality

T_CR= center of the temperature range of interest in °C

The correction factor of Equation 20 should be directly added to the temperature reading produced by the LM94.

For example when using the LM94, with the 3904 mode selected, to measure a AMD Athlon processor, with a

typical non-ideality of 1.008, for a temperature range of 60 °C to 100 °C the correction factor would calculate to:

T_CF=[(1.003−1.008)÷1.003]×(80+273) =−1.75°C

(21)

Therefore, 1.75°C should be subtracted from the temperature readings of the LM94 to compensate for the

differing typical non-ideality target.

PCB Layout for Minimizing Noise

In the following guidelines, Remote+ and Remote -− refer to the REMOTE1a+, Remote 1b+, REMOTE1−,

REMOTE2a+, Remote2b+ and REMOTE2− pins.

In a noisy environment, such as a power supply, layout considerations are very critical. Noise induced on traces

running between the remote temperature diode sensor and the LM94 can cause temperature conversion errors.

The following guidelines should be followed:

1. Place a 0.1 µF and 100 pF LM94 power bypass capacitors as close as possible to the V_DDpin, with the

100pF capacitor being the closest. Place 10 µF capacitor in the near vicinity of the LM94 power pin.

2. Place a 100 pF capacitor as close as possible to the LM94 thermal diode Remote+ and Remote− pins. Make

sure the traces to the 100 pF capacitor are matched and as short as possible. This capacitor is required to

minimize high frequency noise error.

3. Thermal diodes that share one Remote− pin must have a separate trace from the LM94 Remote− pin run to

each diode cathode. Do not "daisy chain" these connections.

4. Ideally, the LM94 should be placed within 10 cm of the thermal diode pins with the traces being as straight,

short and identical as possible. Trace resistance of 1Ω can cause as much as 1°C of error.

5. Diode traces should be surrounded by a GND guard ring to either side, above and below, if possible. This

GND guard should not be between the Remote+ and Remote− lines. In the event that noise does couple to

the diode lines, it would be ideal if it is coupled to both identically, i.e. common mode. That is, equally to the

Remote+ (D+) and Remote−(D-) lines. (See figure below):

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Figure 10. Recommended Diode Trace Layout

6. Avoid routing diode traces in close proximity to any power supply switching or filtering inductors.

7. Avoid running diode traces close to or parallel to high speed digital and bus lines. Diode traces should be

kept at least 2 cm apart from the high speed digital traces.

8. If it is necessary to cross high speed digital traces, the diode traces and the high speed digital traces should

cross at a 90 degree angle.

9. The ideal place to connect the LM94’s GND pin is as close as possible to the Processors GND associated

with the sense diode. In the case of two processors pick a node in between the two that has the least noise.

10. Leakage current between Remote+ and GND should be kept to a minimum. Error in the diode temperature

reading may reach 0.4°C with 30 nA of leakage current. Keeping the printed circuit board as clean as

possible minimizes leakage current. The residue from some freeze spray can induce high leakage current.

FAN CONTROL

Automatic Fan Control Methods

The LM94 fan speed control method is optimized for fan noise reduction, fan power efficiency, fan reliability and

minimum cost. The PWMx outputs can be filtered using an external switching regulator type output stage that

provides 5V to 12V DC for fan power. A high PWM frequency is required to minimize the size and cost of the

inductor and other components used in the output stage. The PWM outputs of the LM94 can operate up to 22.5

kHz with a variable step size depending on the fan control mode of operation. The LM94 supports LUT (Lookup

Table) and PI (Proportional Integral) fan control methods. These methods can function interactively or

independently as controlled by the PWM binding registers. Figure 11 shows the high level block diagram for

these fan control methods. The mapping/binding of the temperature zones to the LUTs is completely

independent of the PI loops. The temperature zones can be first independently bound to the LUTs and/or PI

loops then each LUT or PI loop can be bound to either PWM Output. The LUT parameters are independent of

the temperature zone binding. The PI loop controller is a proportional-integral feedback controller. It generates a

9-bit PWM duty cycle and uses temperature feedback from the processor thermal zones (Zones 1 and 2). The

PWM output controls the airflow over the processors and thus the temperature of the processors is adjusted by

the PI loop to maintain the hottest temperature reading between the values Tcontrol and Tcontrol - hysteresis.

The LM94 supports 2 processors and each processor can have two thermal sub-zones. The hottest of each

processor temperature is reported to the Zone selectors and PI loop inputs. Each processor has an independent

Tcontrol setting.

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T control 1

T control 2

-

+

PI

Binding

PI Fan Control

T Zone 1a

T Zone 1b

Hottest of

T Zone 1a or T

Zone 1b

Zone 1&3

Selector

LUT 1

LUT 2

LUT 3

LUT 4

Selector

T Zone 2a

T Zone 2b

Hottest of

T Zone 2a or T

Zone 2b

PWM 1

PWM

Binding

Zone 2&4

Selector

T Zone 3

AD_IN11

Zone 1&3

Selector

Int. Temp.

PWM 2

T Zone 4

AD_IN15

Ext. Temp.

Zone 2&4

Selector

Figure 11. LUT and PI controller high level block diagram

LUT Fan Control Duty Cycles

Several registers in the LM94 use 4-bit values to represent a duty cycle. All of them use a common mapping that

associates the 4-bit value with a duty cycle. The 4-bit values correspond also with the 14 steps of the auto fan

control algorithm. The mapping is shown below. This applies for PWM outputs running at the default 22.5 kHz

(high) frequency.

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22.5 kHz (High Frequency)

4-Bit Value

Step

Duty Cycle

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

0.00%

1

2

25.00%

31.25%

37.50%

43.75%

50.00%

56.25%

62.50%

68.75%

75.00%

81.25%

87.50%

93.75%

100.00%

Reserved

3

4

5

6

7

8

9

10

11

12

13

—

Alternate LUT PWM Mapping

The PWM output can operate at lower frequencies, instead of the default 22.5 kHz. The lower frequencies can

be enabled through the PWMx Control 4 registers. Operating in the lower frequency mode, enables an alternate

mapping of step numbers to duty cycle. This effects the auto fan control and all LM94 registers that describe a

duty cycle using a 4-bit value. This alternate mapping can also be enable when using the default 22.5 kHz PWM

frequency.

The alternate LUT PWM duty cycle mapping is listed in the following table:

Alternate LUT

Duty Cycle

4-Bit Value

LUT Step

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

0%

1

2

25.00%

28.57%

32.14%

35.71%

39.29%

42.86%

46.43%

50.00%

53.57%

57.14%

71.43%

85.71%

100.00%

Reserved

3

4

5

6

7

8

9

10

11

12

13

—

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Fan Control Priorities

The automatic fan control is not the only function that influences PWM duty cycle. There are several other

functions that influence the PWM duty cycle. All the functions can be classified into several categories:

Category #

Category Name

1

2

3

4

5

6

PWM to 100% conditions

VRDx_HOT ramp-up/ramp-down

PROCHOT ramp-up/ramp-down function

Manual PWM Override

Fan Spin-Up Control

Automatic Fan Control Algorithm

The ultimate PWM duty cycle that is chosen can be described by the following formula:

If (Manual PWM Override is active)

PWM = max(1,2,3,4)

Else

PWM = max(1,2,3,5,6)

So in general, categories 1, 2 and 3 are always active. In addition to that, either category 4 or categories 5 and 6

are active depending on whether manual override is enabled. In this sense the manual override, when enabled,

replaces category 5 and 6.

PWM to 100% Conditions

There are several conditions that cause the duty cycles of all PWM outputs to immediately get set to 100%. They

are:

1. any of the four temperature zones exceed the programmed Fan Boost Limit setting but has not yet cooled

down enough to drop below the hysteresis point

2. a tachometer reading exceeds its limit

3. the OVRID bit is set in the LM94 Status/Control

VRDx_HOT Ramp-Up/Ramp-Down

This function causes the duty cycle of the PWM outputs to gradually increase over time if VRD1_HOT or

VRD2_HOT are asserted.

When VRDx_HOT is asserted, the ramp function is enabled. The enabling process involves two steps:

1. The current duty cycle being requested by other PWM functions is memorized.

2. The ramp function immediately adds one PWM duty cycle step to the memorized value and requests this

duty cycle.

Once the function is enabled, it gradually adds additional duty cycle steps every X milliseconds whenever

VRDx_HOT is asserted (X is programmable via the PWM Ramp Control register). If VRDx_HOT remains

asserted for a long enough time, the duty cycle eventually reaches 100%.

Whenever VRDx_HOT is de-asserted, the ramp function begins to ramp down by subtracting one PWM duty

cycle step every X milliseconds. If VRDx_HOT is currently de-asserted, and the ramp function is less than to the

PWM duty cycle being requested by other functions, the ramp function is disabled.

As long as the function is enabled, it continues to ramp up or ramp down depending on the state of VRDx_HOT.

The ramp enabling process described above can only re-occur after the ramp function has been disabled. Rapid

assertion/de-assertion of VRDx_HOT does not trigger the enabling process unless VRDx_HOT was de-asserted

long enough for the ramp function to disable itself.

This ramp function operates independently for VRD1_HOT and VRD2_HOT. In addition, the ramp function only

applies to the PWM(s) that are bound to one or two VRDx_HOT inputs. Depending on the bindings, it is possible

that up to four independent ramp functions are active at any given moment:

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PWM1/VRD1

PWM1/VRD2

PWM2/VRD1

PWM2/VRD2

If a PWM is bound to both VRD1_HOT and VRD2_HOT, then two ramp functions are active for that PWM output.

In this case the duty cycle that is used is the maximum of the two ramp functions.

PROCHOT Ramp-Up/Ramp-Down

This function is very similar to the VRDx_HOT ramp-up/ramp-down function. The PWM duty cycle ramps up in

the same fashion whenever the PROCHOT measurement exceeds the user programmed threshold. Once a new

PROCHOT measurement is made that no longer exceeds the user limit, the PWM will begin to ramp down.

Just as with the VRDx_HOT ramp function, the PROCHOT ramp function uses independent bindings to

determine which PWM outputs should be effected by each PROCHOT input (P1_PROCHOT or P2_PROCHOT).

If a PWM is bound to both P1_PROCHOT and P2_PROCHOT, two PROCHOT ramp functions could be active at

the same time. In this case the duty cycle that is used is the maximum of the two ramp functions.

Manual PWM Override

When a PWM channel is configured for manual PWM override, software can manually control the PWM duty

cycle. There are some PWM control functions that could still cause the duty cycle to be higher than the manual

setting. See the Fan Control Priorities for details.

Fan Spin-Up Control

All of the other PWM control functions are combined to produce a final duty cycle that is actually used for the

PWM output. If this final value changes from zero to a non-zero value, the Fan Spin-Up Control function is

triggered. Once triggered, the Fan Spin-Up Control requests the programmed duty cycle for a programmed

period of time.

XOR TREE TEST

An XOR tree is provided in the LM94 for Automated Test Equipment (ATE) board level connectivity testing. This

allows the functionality of all digital inputs to be tested in a simple manner and any pins that are non-functional or

shorted together to be identified. When the test mode is enabled by setting the ‘XEN’ bit in the XOR Test

register, the part enters XOR test mode.

Table 3. The following signals are included in the XOR test tree:

Px_VIDy

GPIO_x

PWMx

Px_PROCHOT

VRDx_HOT

GPIx

RESET

Since the test mode is XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK

should not be included in the test tree.

Figure 12. Example of XOR Test Tree (not showing all signals)

P1_VID0

P1_VID1

P1_VID2

P1_VID3

P1_VID4

VRD2_Hot

GPI_8

xTestOut

GPI_9

RESET

To properly implement the XOR TREE test on the PCB, no pins listed in the tree should be connected directly to

power or ground. If a pin needs to be configured as a permanent low, such as a GPI, it should be connected to

ground through a low value resister such as 10 kΩ, to allow the ATE (Automatic Test Equipment) to drive it high.

When generating test waveforms, a typical propagation delay of 500 ns through the XOR tree should be allowed

for.

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Registers

REGISTER WARNINGS

In most cases, reserved registers and register bits return zero when read. This should not be relied upon, since

reserved registers can be used for future expansion of the LM94 functions.

Some registers have “N/D” for their default value. This means that the power-up default of the register is not

defined. In the case of value registers, care should be taken to ensure that software does not read a value

register until the associated measurement function has acquired a measurement. This applies to temperatures,

voltages, fan RPM, and PROCHOT monitoring.

REGISTER SUMMARY TABLE

Table 4. Register Key

Term

Description

N/D

N/A

R

Not Defined

Not Applicable

Read Only

R/W

RWC

Read or Write

Read or Write to Clear

Lock

Register Name

Address Default

Description

FACTORY REGISTERS

x

XOR Test

SMBus Test

Reserved

00h

01h

00h

00

Used to set the XOR test tree mode

SMBus read/write test register

02h-04h N/D

“REMOTE DIODE” MODE SELECT

Transistor Mode Select

x

05h

00h

Selects Diode Mode (default) or Transistor Mode for “Remote Diode”

measurements

VALUE REGISTER SECTION 1

Zone 1b (CPU1 Diode b) Temp

Zone 2b (CPU2 Diode b) Temp

06h

07h

08h

00h

Measured value of remote thermal diode temperature channel 1b

Measured value of remote thermal diode temperature channel 2b

Filtered value of remote thermal diode temperature channel 1b

Zone 1b (CPU1 Diode b) Filtered

Temp

Zone 2b (CPU2 Diode b) Fitlered

Temp

09h

00h

Filtered value of remote thermal diode temperature channel 2b

PWM1 8-bit Duty Cycle Value

PWM2 8-bit Duty Cycle Value

0Ah

0Bh

00h

8- bit value of the PWM1 duty cycle.

8-bit value of the PWM2 duty cycle

HIGH RESOLUTION PWM OVERIDE REGISTERS

x

PWM1 Duty Cycle Override (low byte) 0Ch

PWM1 Duty Cycle Override (high byte) 0Dh

PWM2 Duty Cycle Override (low byte) 0Eh

PWM2 Duty Cycle Override (high byte) 0Fh

00h

Lower byte of the high resolution PWM1 duty cycle register

Upper byte of the high resolution PWM1 duty cycle register

Lower byte of the high resolution PWM2 duty cycle register

Upper byte of the high resolution PWM2 duty cycle register

EXTENDED RESOLUTION TEMPERATURE VALUE REGISTERS

Z1a_LSB

Z1a_MSB

Z1b_LSB

Z1b_MSB

Z2a_LSB

10h

11h

12h

13h

14h

00h

Zone 1a (CPU1) extended resolution unfiltered temperature value

register, least-significant byte

Zone 1a (CPU1) extended resolution unfiltered temperature value

register, most-significant byte

Zone 1b (CPU1) extended resolution unfiltered temperature value

register, least-significant-byte

Zone 1b (CPU1) extended resolution unfiltered temperature value

register, most-significant byte

Zone 2a (CPU2) extended resolution unfiltered temperature value

register, least-significant-byte

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Lock

Register Name

Address Default

Description

Z2a_MSB

Z2b_LSB

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

00h

Zone 2a (CPU2) extended resolution unfiltered temperature value

register, most-significant byte

Zone 2b (CPU2) extended resolution unfiltered temperature value

register, least-significant-byte

Z2b_MSB

Z1a_F_LSB

Zone 2b (CPU2) extended resolution unfiltered temperature value

register, most-significant byte

Zone 1a (CPU1) extended resolution filtered temperature value

register, least-significant byte

Z1a_F_MSB

Z1b_F_LSB

Z1b_F_MSB

Z2a_F_LSB

Z2a_F_MSB

Z2b_F_LSB

Z2b_F_MSB

Z3_LSB

Zone 1a (CPU1) extended resolution filtered temperature value

register, most-significant byte

Zone 1b (CPU1) extended resolution filtered temperature value

register, least-significant-byte

Zone 1b (CPU1) extended resolution filtered temperature value

register, most-significant byte

Zone 2a (CPU2) extended resolution filtered temperature value

register, least-significant-byte

Zone 2a (CPU2) extended resolution filtered temperature value

register, most-significant byte

Zone 2b (CPU2) extended resolution filtered temperature value

register, least-significant-byte

Zone 2b (CPU2) extended resolution filtered temperature value

register, most-significant byte

Zone 3 (Internal) extended resolution temperature value register,

least-significant byte

Z3_MSB

Zone 3 (Internal) extended resolution temperature value register,

least-significant byte

Z4_LSB

Zone 4 (External Digital) extended resolution temperature value

register, most-significant byte

Z4_MSB

Zone 4 (External Digital) extended resolution temperature value

register, least-significant byte

Reserved

24h-30h N/D

PI LOOP AND FAN CONTROL SETUP REGISTERS

x

Temperature Source Select

PWM Filter Settings

31h

32h

00h

Selects the temperature source for some temperature zones.

Sets the IIR filter coefficients for the PWM outputs for low resolution

sources

x

PWM1 Filter Shutoff Threshold

PWM2 Filter Shutoff Threshold

PI/LUT Fan Control Bindings

33h

34h

35h

36h

00h

30h

00h

PWM1 Filter Shutoff Threshold

PWM2 Filter Shutoff Threshold

PI/LUT fan control binding configuration

PI Controller Minimum PWM and Hysteresis settings

PI Controller Minimum PWM and

Hysteresis

x

Zone 1 Tcontrol

Zone 2 Tcontrol

Zone 1 Toff

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

00h

80h

00h

Zone 1 (CPU1) PI Controller Target Temperature (Tcontrol)

Zone 2 (CPU2) PI Controller Target Temperature (Tcontrol)

Zone 1 (CPU1) PI Controller Off Temperature (Toff)

Zone 2 (CPU2) PI Controller Off Temperature (Toff)

PI controller proportional coefficient

Zone 2 Toff

P Coefficient

I Coefficient

PI controller integral coefficient

PI Exponents

PI controller coefficient exponents

DEVICE IDENTIFICATION REGISTERS

Manufacturer ID

3Eh

3Fh

01h

79h

Contains manufacturer ID code

Version/Stepping

Contains code for major and minor revisions

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Lock

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Register Name

Address Default

Description

BMC ERROR STATUS REGISTERS

B_Error Status 1

40h

41h

42h

43h

44h

45h

46h

47h

00h

BMC error status register 1

BMC error register 2

BMC error register 3

BMC error register 4

B_Error Status 2

B_Error Status 3

B_Error Status 4

B_P1_PROCHOT Error Status

B_P2_PROCHOT Error Status

B_GPI Error Status

BMC error register for P1_PROCHOT

BMC error register for P2_PROCHOT

BMC error register for GPIs

B_Fan Error Status

BMC error register for Fans

HOST ERROR STATUS REGISTERS

H_Error Status 1

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

00h

HOST error status register 1

HOST error register 2

H_Error Status 2

H_Error Status 3

HOST error register 3

H_Error Status 4

HOST error register 4

H_P1_PROCHOT Error Status

H_P2_PROCHOT Error Status

H_GPI Error Status

H_Fan Error Status

VALUE REGISTERS SECTION 2

Zone 1a (CPU1) Temp

Zone 2a (CPU2) Temp

Zone 3 (Internal) Temp

Zone 4 (External Digital) Temp

Zone 1a (CPU1) Filtered Temp

Zone 2a (CPU2) Filtered Temp

AD_IN1 Voltage

HOST error register for P1_PROCHOT

HOST error register for P2_PROCHOT

HOST error register for GPIs

HOST error register for Fans

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

00h

N/D

Measured value of remote thermal diode temperature channel 1a

Measured value of remote thermal diode temperature channel 2a

Measured temperature from on-chip sensor

Measured temperature from external temperature sensor

Filtered value of remote thermal diode temperature channel 1a

Filtered value of remote thermal diode temperature channel 2a

Measured value of AD_IN1

AD_IN2 Voltage

Measured value of AD_IN2

AD_IN3 Voltage

Measured value of AD_IN3

AD_IN4 Voltage

Measured value of AD_IN4

AD_IN5 Voltage

Measured value of AD_IN5

AD_IN6 Voltage

Measured value of AD_IN6

AD_IN7 Voltage

Measured value of AD_IN7

AD_IN8 Voltage

Measured value of AD_IN8

AD_IN9 Voltage

Measured value of AD_IN9

AD_IN10 Voltage

Measured value of AD_IN10

AD_IN11 Voltage

Measured value of AD_IN11

AD_IN12 Voltage

Measured value of AD_IN12

AD_IN13 Voltage

Measured value of AD_IN13

AD_IN14 Voltage

Measured value of AD_IN14

AD_IN15 Voltage

Measured value of AD_IN15

AD_IN16 Voltage

Measured value of AD_IN16 (V_DD3.3V S/B)

Reserved

66h

N/D

Current P1_PROCHOT

Average P1_PROCHOT

Current P2_PROCHOT

Average P2_PROCHOT

67h

68h

69h

6Ah

00h

Measured P1_PROCHOT throttle percentage

Average P1_PROCHOT throttle percentage

Measured P2_PROCHOT throttle percentage

Average P2_PROCHOT throttle percentage

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Register Name

Address Default

Description

GPI State

6Bh

00h

Current GPIO state

P1_VID

P2_VID

6Ch

6Dh

00h

Current VID value of Processor 1

Current VID value of Processor 2

FAN Tach 1 LSB

FAN Tach 1 MSB

FAN Tach 2 LSB

FAN Tach 2 MSB

FAN Tach 3 LSB

FAN Tach 3 MSB

FAN Tach 4 LSB

FAN Tach 4 MSB

6Eh

6Fh

70h

71h

72h

73h

74h

75h

00h

Measured FAN Tach 1 LSB

Measured FAN Tach 1 MSB

Measured FAN Tach 2 LSB

Measured FAN Tach 2 MSB

Measured FAN Tach 3 LSB

Measured FAN Tach 3 MSB

Measured FAN Tach 4 LSB

Measured FAN Tach 4 MSB

Reserved

76h-77h N/D

TEMPERATURE LIMIT REGISTERS

Zone 1 (CPU1) Low Temp

78h

79h

7Ah

7Bh

80h

Low limit for external thermal diode temperature channel 1 (D1)

measurement

Zone 1 (CPU1) High Temp

Zone 2 (CPU2) Low Temp

Zone 2 (CPU2) High Temp

High limit for external thermal diode temperature channel 1 (D1)

measurement

Low limit for external thermal diode temperature channel 2 (D2)

measurement

High limit for external thermal diode temperature channel 2 (D2)

measurement

Zone 3 (Internal) Low Temp

7Ch

7Dh

7Eh

7Fh

80h

Low limit for local temperature measurement

High limit for local temperature measurement

Low limit for external digital temperature sensor

High limit for external digital temperature sensor

Zone 3 (Internal) High Temp

Zone 4 (External Digital) Low Temp

Zone 4 (External Digital) High Temp

x

Fan Boost Temp Zone 1

Fan Boost Temp Zone 2

Fan Boost Temp Zone 3

Fan Boost Temp Zone 4

Zone1 and Zone 2 Hysteresis

Zone 3 and Zone 4 Hysteresis

80h

81h

82h

83h

84h

85h

3Ch

23h

00h

Zone 1 (CPU1) fan boost temperature

Zone 2 (CPU2) fan boost temperature

Zone 3 (Internal) fan boost temperature

Zone 4 (External Digital) fan boost temperature

Zone 1 and Zone 2 hysteresis for limit comparisons

Zone 3 and Zone 4 hysteresis for limit comparisons

Reserved

86h-8Dh N/D

ZONE 1b and 2b TEMPERATURE READING ADJUSTMENT REGISTERS

Zone 1b Temp Adjust

8Eh

00h

Allows all Zone 1b temperature measurements to be adjusted by a

programmable offset.

Zone 2b Temp Adjust

8Fh

00h

Allows all Zone 2b temperature measurements to be adjusted by a

programmable offset.

OTHER LIMIT REGISTERS

AD_IN1 Low Limit

90h

91h

92h

93h

94h

00h

FFh

00h

FFh

00h

Low limit for analog input 1 measurement

High limit for analog input 1 measurement

Low limit for analog input 2 measurement

High limit for analog input 2 measurement

Low limit for analog input 3 measurement

AD_IN1 High Limit

AD_IN2 Low Limit

AD_IN2 High Limit

AD_IN3 Low Limit

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Register Name

Address Default

Description

AD_IN3 High Limit

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

A1h

A2h

A3h

A4h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

High limit for analog input 3 measurement

AD_IN4 Low Limit

AD_IN4 High Limit

AD_IN5 Low Limit

AD_IN5 High Limit

AD_IN6 Low Limit

AD_IN6 High Limit

AD_IN7 Low Limit

AD_IN7 High Limit

AD_IN8 Low Limit

AD_IN8 High Limit

AD_IN9 Low Limit

AD_IN9 High Limit

AD_IN10 Low Limit

AD_IN10 High Limit

AD_IN11 Low Limit

AD_IN11 High Limit

AD_IN12 Low Limit

AD_IN12 High Limit

AD_IN13 Low Limit

AD_IN13 High Limit

AD_IN14 Low Limit

AD_IN14 High Limit

AD_IN15 Low Limit

AD_IN15 High Limit

AD_IN16 Low Limit

AD_IN16 High Limit

Low limit for analog input 4 measurement

High limit for analog input 4 measurement

Low limit for analog input 5 measurement

High limit for analog input 5 measurement

Low limit for analog input 6 measurement

High limit for analog input 6 measurement

Low limit for analog input 7 measurement

High limit for analog input 7 measurement

Low limit for analog input 8 measurement

High limit for analog input 8 measurement

Low limit for analog input 9 measurement

High limit for analog input 9 measurement

Low limit for analog input 10 measurement

High limit for analog input 10 measurement

Low limit for analog input 11 measurement

High limit for analog input 11 measurement

Low limit for analog input 12 measurement

High limit for analog input 12 measurement

Low limit for analog input 13 measurement

High limit for analog input 13 measurement

Low limit for analog input 14 measurement

High limit for analog input 14 measurement

Low limit for analog input 15 measurement

High limit for analog input 15 measurement

Low limit for analog input 16 measurement

High limit for analog input 16 measurement

P1_PROCHOT User Limit

P2_PROCHOT User Limit

B0h

B1h

FFh

User settable limit for P1_PROCHOT

User settable limit for P2_PROCHOT

Vccp1 Limit Offsets

Vccp2 Limit Offsets

B2h

B3h

17h

VID offset values for window comparator for CPU1 Vccp (AD_IN7)

VID offset values for window comparator for CPU2 Vccp (AD_IN8)

FAN Tach 1 Limit LSB

FAN Tach 1 Limit MSB

FAN Tach 2 Limit LSB

FAN Tach 2 Limit MSB

FAN Tach 3 Limit LSB

FAN Tach 3 Limit MSB

FAN Tach 4 Limit LSB

FAN Tach 4 Limit MSB

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

FCh

FFh

FCh

FFh

FCh

FFh

FCh

FFh

FAN Tach 1 Limit LSB

FAN Tach 1 Limit MSB

FAN Tach 2 Limit LSB

FAN Tach 2 Limit MSB

FAN Tach 3 Limit LSB

FAN Tach 3 Limit MSB

FAN Tach 4 Limit LSB

FAN Tach 4 Limit MSB

SETUP REGISTERS

Special Function Control 1

BCh

00h

Controls the hysteresis for voltage limit comparisons. Also selects

filtered or unfiltered temperature usage for temperature limit

comparisons and fan control.

Special Function Control 2

GPI / VID Level Control

BDh

BEh

00h

Enables smart tach detection. Also selects 0.5°C or 1.0°C resolution

for fan control.

x

Control the input threshold levels for the P1_VIDx, P2_VIDx and

GPIO_x inputs.

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Register Name

PWM Ramp Control

Address Default

Description

x

BFh

00h

Controls the ramp rate of the PWM duty cycle when VRDx_HOT is

asserted, as well as the ramp rate when PROCHOT exceeds the user

threshold.

x

Fan Boost Hysteresis (Zones 1/2)

Fan Boost Hysteresis (Zones 3/4)

Zones 1/2 Spike Smoothing Control

LUT 1/2 MinPWM and Hysteresis

C0h

C1h

C2h

C3h

44h

00h

Fan Boost Hysteresis for zones 1 and 2

Fan Boost Hysteresis for zones 3 and 4

Configures Spike Smoothing for zones 1 and 2

Controls MinPWM and hysteresis setting for LUT 1 and 2 auto-fan

control

x

LUT 3/4 MinPWM and Hysteresis

GPO

C4h

C5h

00h

Controls MinPWM and hysteresis setting for LUT 3 and 4 auto-fan

control

Controls the output state of the GPIO pins

PROCHOT Control

C6h

C7h

00h

11h

Controls assertion of P1_PROCHOT or P2_PROCHOT

PROCHOT Time Interval

Configures the time window over which the PROCHOT inputs are

measured

x

PWM1 Control 1

PWM1 Control 2

PWM1 Control 3

PWM1 Control 4

C8h

C9h

CAh

CBh

00h

Controls PWM control source bindings.

Controls PWM override and output polarity

Controls PWM spin-up duration and duty cycle

Frequency control for PWM1.

x

PWM2 Control 1

PWM2 Control 2

PWM2 Control 3

PWM2 Control 4

CCh

CDh

CEh

CFh

00h

Controls PWM control source bindings.

Controls PWM override and output polarity

Controls PWM spin-up duration and duty cycle

Frequency control for PWM2

x

LUT 1 Base Temperature

LUT 2 Base Temperature

LUT 3 Base Temperature

LUT 4 Base Temperature

D0h

D1h

D2h

D3h

00h

Base temperature to which look-up table offset is applied for LUT 1

Base temperature to which look-up table offset is applied for LUT 2

Base temperature to which look-up table offset is applied for LUT 3

Base temperature to which look-up table offset is applied for LUT 4

x

Step 2 Temp Offset

Step 3 Temp Offset

Step 4 Temp Offset

Step 5 Temp Offset

Step 6 Temp Offset

Step 7 Temp Offset

Step 8 Temp Offset

Step 9 Temp Offset

Step 10 Temp Offset

Step 11 Temp Offset

Step 12 Temp Offset

Step 13 Temp Offset

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

00h

Step 2 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 3 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 4 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 5 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 6 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 7 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 8 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 9 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 10 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 11 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 12 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 13 LUT 1/2 and LUT 3/4 Offset Temperatures

TACH to PWM Binding

Tach Boost Control

E0h

E1h

00h

3Fh

Controls the tachometer input to PWM output binding

Controls the fan boost function upon a tach error

x

LM94 Status/Control

LM94 Configuration

E2h

E3h

00h

Gives Master error status, ASF reset control and Max PWM control

Configures various outputs and provides START bit

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Register Name

Address Default

Description

SLEEP STATE CONTROL AND MASK REGISTERS

Sleep State Control

S1 GPI Mask

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

03h

FFh

0Fh

FFh

0Fh

07h

FFh

07h

Used to communicate the system sleep state to the LM94

Sleep state S1 GPI error mask register

S1 Fan Mask

Sleep state S1 fan tach error mask register

Sleep state S3 GPI error mask register

S3 GPI Mask

S3 Fan Mask

Sleep state S3 fan tach error mask register

Sleep state S3 temperature or voltage error mask register

Sleep state S4/5 GPI error mask register

S3 Temperature/Voltage Mask

S4/5 GPI Mask

S4/5 Temperature/Voltage Mask

OTHER MASK REGISTERS

GPI Error Mask

Sleep state S4/5 temperature or voltage error mask register

ECh

EDh

FFh

3Fh

Error mask register for GPI faults

Miscellaneous Error Mask

Error mask register for VRDx_HOT, GPI, and dynamic Vccp limit

checking.

ZONE 1a AND 2a TEMPERATURE READING ADJUSTMENT REGISTERS

Zone 1a Temp Adjust

EEh

00h

Allows all Zone 1a temperature measurements to be adjusted by a

programmable offset

Zone 2a Temp Adjust

EFh

00h

Allows all Zone 2a temperature measurements to be adjusted by a

programmable offset

BLOCK COMMANDS

Block Write Command

Block Read Command

Fixed Block 0

F0h

F1h

F2h

F3h

F4h

F5h

F6h

F7h

F8h

F9h

FAh

FBh

FCh

FDh

N/A

SMBus Block Write Command Code

SMBus Block Write/Read Process call

Fixed block code address 40h, size 8 bytes

Fixed block code address 48h, size 8 bytes

Fixed block code address 50h, size 6 bytes

Fixed block code address 56h, size 16 bytes

Fixed block code address 67h, size 4 bytes

Fixed block code address 6Eh, size 8 bytes

Fixed block code address 78h, size 12 bytes

Fixed block code address 90h, size 32 bytes

Fixed block code address B4h, size 8 bytes

Fixed block code address C8h, size 8 bytes

Fixed block code address D0h, size 16 bytes

Fixed block code address E5h, size 9 bytes

Fixed Block 1

Fixed Block 2

Fixed Block 3

Fixed Block 4

Fixed Block 5

Fixed Block 6

Fixed Block 7

Fixed Block 8

Fixed Block 9

Fixed Block 10

Fixed Block 11

Reserved

FEh-FFh N/A

Reserved for future commands

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FACTORY REGISTERS 00h–04h

Register 00h XOR Test

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

R/W

XOR Test

RES

XEN

00h

Sleep

Masking

Bit Name R/W Default

Description

0

XEN R/W

0

The LM94 incorporates an XOR tree test mode. When the test mode is enabled by setting

this bit, the part enters XOR test mode. Clearing this bit brings the part out of XOR test

mode.

N/A

7:1

RES

R

0

Reserved

N/A

Register 01h SMBus Test

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

R/W

SMBus

Test

7

6

5

4

3

2

1

0

00h

This register can be used to verify that the SMBus can read and write to the device without effecting any

programmed settings.

“REMOTE DIODE” MODE SELECT

Register 05h Remote-Diode Transistor Mode Select

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

R/W

Transistor

Mode

RES

P2b_T_E P2a_T_E P1b_T_E P1a_T_E

00h

N

Select

Bit

Name

R/W

Description

0

1

P1a_T_EN

P1b_T_EN

P2a_T_EN

P2b_T_EN

RES

R/W

R

If set, Processor 1 Remote-Diode “a” Transistor Mode enabled.

If set, Processor 1 Remote-Diode “b” Transistor Mode enabled.

If set, Processor 2 Remote-Diode “a” Transistor Mode enabled.

If set, Processor 2 Remote-Diode “b” Transistor Mode enabled.

Reserved

2

3

7:4

VALUE REGISTERS SECTION 1

Registers 06-07h and 50–53h Unfiltered Temperature Value Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1b

(CPU1)

Temp

06h

07h

50h

R

7

6

5

4

3

2

1

0

00h

Zone 2b

(CPU2)

Temp

7

6

5

4

3

2

1

0

Zone 1a

(CPU1)

Temp

50

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Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 2a

(CPU2)

Temp

51h

52h

R

7

6

5

4

3

2

1

0

00h

Zone 3

(Internal)

Temp

7

6

5

4

3

2

1

0

00h

Zone 4

(External

Digital)

Temp

53h

R/W

Zones 1 and 2 are all automatically updated by the LM94. The Zone 3 (Internal) Temp and Zone 4 (External

Digital) Temp registers may be written by an external SMBus device or can be assigned to AD_IN11 and

AD_IN15, respectively.

The temperature registers for zones 1 and 2 will return a value of 80h if the remote diode pins are not

implemented by the board designer or are not functioning properly.

Registers 08–09h and 54–55h Filtered Temperature Value Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1b

(CPU1)

Filtered

Temp

08h

09h

54h

55h

R

7

6

5

4

3

2

1

0

00h

Zone 2b

(CPU2)

Filtered

Temp

7

6

5

4

3

2

1

0

Zone 1a

(CPU1)

Filtered

Temp

Zone 2a

(CPU2)

Filtered

Temp

These registers reflect the temperature of zones 1 and 2 after the spike smoothing filter has been applied.

The characteristics of the filtering can be adjusted by using the Zones 1/2 Spike Smoothing Control register.

Register 0Ah and 0Bh PWM1 and PWM2 8-bit Duty Cycle Value

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ah

0Bh

R

PWM1

Duty

Cycle

Value

7

6

5

4

3

2

1

0

00h

PWM2

Duty

7

6

5

4

3

2

1

0

00h

Cycle

Value

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These registers report the current duty cycle being driven on the PWM1 or PWM2 outputs. It is the upper 8 bits

of the 9-bit PWM value. It reflects the maximum duty cycle of any low-resolution or high-resolution PWM sources

bound to the PWM1 or PWM2 outputs.

PWM Duty Cycle Overide Registers

Register 0Ch PWM1 Duty Cycle Override (low byte)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ch

R/W

PWM1 Duty Cycle

Override (low byte)

PWM1_

DC[0]

PWM1_

EN_Hres

_Over

RES

00h

Bit

5:0

6

Name

R/W

Description

Reserved

RES

R

PWM1_EN_Hres_Over

R/W

When this bit is set, high-resolution override for PWM1 is enabled. When this

bit is set, PWM1 will run at the programmed duty cycle: PWM1_DC[8:0]/256 *

100%; values over 100h are reserved.

7

PWM1_DC[0]

R/W

When this bit is set, bit [0] of the override duty cycle for PWM1 is set.

If manual PWM1 override is enabled in this register, all other PWM1 bindings are disabled except for the 100%

override in the LM94 Status Control register (E2h).

Register 0Dh PWM1 Duty Cycle Override (high byte)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Dh

R/W

PWM1 Duty Cycle

Override (high

byte)

PWM1_DC[8:1]

00h

These bits set the upper 8-bits of the 9-bit override duty cycle value for PWM1.

Register 0Eh PWM2 Duty Cycle Override (low byte)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Eh

R/W

PWM 2 Duty

Cycle Override

(low byte)

PWM2_ PWM2_

RES

00h

DC[0]

EN_Hres

_Over

Bit

5:0

6

Name

RES

R/W

R

Description

Reserved

PWM2_EN_Hres_Over

R/W

When this bit is set, high-resolution override for PWM2 is enabled. When this

bit is set, PWM2 will run at the programmed duty cycle: PWM2_DC[8:0]/256 *

100%; values over 100h are reserved.

7

PWM2_DC[0]

R/W

When this bit is set, bit [0] of the override duty cycle for PWM2 is set.

If manual PWM 2 override is enabled in this register, all other PWM 2 bindings are disabled except for the 100%

override in the LM94 Status Control register (E2h).

Register 0Fh PWM2 Duty Cycle Override (high byte)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Fh

R/W

PWM2 Duty Cycle

Override (high

byte)

PWM2_DC[8:1]

00h

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These bits set the upper 8-bits of the 9-bit override duty cycle value for PWM2.

EXTENDED RESOLUTION VALUE REGISTERS

Registers 10h - 17h Zone 1 (CPU1) and Zone 2 (CPU2) Extended Resolution Unfiltered Temperature Value

Registers, Most and Least Significant Bytes

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

10h

11h

R

Z1a_LSB

Z1a_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 11h is a mirror of register Zone 1a (CPU1) Temp at address 50h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

12h

13h

R

Z1b_LSB

Z1b_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 13h is a mirror of register Zone 1b (CPU1) Temp at address 06h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

14h

15h

R

Z2a_LSB

Z2a_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 15h is a mirror of register Zone 2a (CPU2) Temp at address 51h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

16h

17h

R

Z2b_LSB

Z2b_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 17h is a mirror of register Zone 2b (CPU2) Temp at address 07h.

Registers 18h – 1Fh Zone 1 (CPU1) and Zone 2 (CPU2) Extended Resolution Filtered Value Registers,

Most and Least Significant Bytes

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

18h

19h

R

Z1a_F_LSB

Z1a_F_MSB

0.5

0.25

64

0.125

32

0.0625

16

0

8

0

4

0

2

0

1

00h

Sign

Register 19h is a mirror of register Zone 1a (CPU1) Filtered Temp at address 54h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Ah

1Bh

R

Z1b_F_LSB

Z1b_F_MSB

0.5

0.25

64

0.125

32

0.0625

16

0

8

0

4

0

2

0

1

00h

Sign

Register 1Bh is a mirror of register Zone 1b (CPU1) Filtered Temp at address 08h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Ch

1Dh

R

Z2a_F_LSB

Z2a_F_MSB

0.5

0.25

64

0.125

32

0.0625

16

0

8

0

4

0

2

0

1

00h

Sign

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Register 1Dh is a mirror of register Zone 2a (CPU2) Filtered Temp at address 55h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Eh

1Fh

R

Z2b_F_LSB

Z2b_F_MSB

0.5

0.25

64

0.125

32

0.0625

16

0

8

0

4

0

2

0

1

00h

Sign

Register 1Fh is a mirror of register Zone 2b (CPU2) Filtered Temp at address 09h.

Registers 20h – 23h Zone 3 and Zone 4 Extended Resolution Value Registers, Most and Least Significant

Bytes

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

20h

21h

R/W

Z3_LSB

Z3_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 21h is a mirror of register Zone 3 (Internal) Temp at address 52h.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

22h

23h

R/W

Z4_LSB

Z4_MSB

0.5

0

8

0

4

0

2

0

1

00h

Sign

64

32

16

Register 23h is a mirror of register Zone 4 (External Digital) Temp at address 53h.

PI LOOP FAN CONTROL SETUP REGISTERS

Register 31h Internal/External Temperature Source Select

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

31h

R/W

Internal/ External

Temperature Source

Select

RES

INT_

WR_E

Z2bE

Z1bE

EXT_

AD15

INT_

AD11

00h

Bit

Name

R/W

Description

0

INT_ADC11

R/W

When this bit is set, the Internal Temperature Register (Zone 3) will be

automatically updated with the value from the ADC_IN11 Voltage Value

register minus 128 by inverting the MSb. Subtraction of 128 or inverting the

MSb is required since the data in the temperature register is a signed value.

When this bit is cleared the Internal Temperature Register (Zone 3) will be

automatically updated with the internal temperature reading from the LM94’s

internal thermal diode. All functions related to the Internal Temperature

Register value are affected by this bit (LUTs, Temperature Boost, etc.)

1

EXT_ADC15

When this bit is set, the External Digital Temperature register (Zone 4) will

become read-only and will be automatically updated from the ADC_IN15

Voltage Value register minus 128 by inverting the MSb. Subtraction of 128 or

inverting the MSb is required since the data in the temperature registers are

signed. When this bit is cleared the External Digital Temperature register is

writable and must be updated over the SMBus by software. All functions

related to the External Digital Temperature register are affected by this bit

(LUTs, Temperature Boost, etc.)

2

3

4

Z1bE

Z2bE

R/W

When this bit is set, pin 23 is enabled as a Remote 1b input. When this bit is

cleared pin 23 is set as a AD_IN1 input.

When this bit is set, pin 24 is enabled as a Remote 2b input. When this bit is

cleared pin 24 is set as a AD_IN2 input.

INT_WR_E

When this bit is set, the Internal Temperature Value register may be updated

by an external SMBus write. All automatic updates of the Internal

Temperature Value register will cease.

7:3

RES

R

Reserved

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Register 32h PWM Filter Settings

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

32h

R/W

PWM_Filter

RES

FC_PWM2[2:0]

RES

FC_PWM1[2:0]

00h

Bit

2:0

3

Name

FC_PWM1[2:0]

RES

R/W

R

Description

Sets the filter coefficient for the IIR filter on PWM1 low resolution sources.

Reserved

6:4

7

FC_PWM2[2:0]

RES

R/W

R

Sets the filter coefficient for the IIR filter on PWM2 low resolution sources.

Reserved

FC_PWM1[2:0] or FC_PWM2[2:]

95% Settling Time Interval

000

001

010

011

100

101

110

111

Filter bypassed

0.098s

0.237s

0.510s

1.056s

2.147s

4.328s

8.689s

Register 33h PWM1 Filter Shutoff Threshold

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

33h

R/W

PWM1_Filter

Shut_Thresh

PWM1_SHUT_DC[4:0]

RES

00h

Bit

2:0

7:3

Name

RES

R/W

R

Description

Reserved

PWM1_SHUT_DC[4:0]

R/W

Sets the filter shutoff threshold. The actual duty cycle threshold is 3.15%

times this value. If the PWM filter is disabled the shutdown threshold is also

disabled. The shutdown threshold allows the PWM1 output to be turned off

for duty cycles less than the programmed value.

Bit [7:3]

9-bit Threshold

Corresponding Duty Cycle

0

1

2

0

8

0.000%

3.125%

6.25%

16

·

29

30

31

232

240

248

90.625%

93.750%

96.875%

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Register 34h PWM2 Filter Shutoff Threshold

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

34h

R/W

PWM2_Filter

Shut_Thresh

PWM2_SHUT_DC[4:0]

RES

00h

Bit

2:0

7:3

Name

RES

R/W

R

Description

Reserved

PWM2_SHUT_DC[4:0]

R/W

Sets the filter shutoff threshold. The actual duty cycle threshold is 3.15%

times this value. If the PWM filter is disabled the shutdown threshold is also

disabled. The shutdown threshold allows the PWM1 output to be turned off

for duty cycles less than the programmed value.

Bit [7:3]

9-bit Threshold

Corresponding Duty Cycle

0

1

2

0

8

0.000%

3.125%

6.25%

16

·

29

30

31

232

240

248

90.625%

93.750%

96.875%

Register 35h PI/LUT Fan Control Bindings

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

35h

R/W

Fan Control

Bindings

LUT4

_Z2

LUT3

_Z1

LUT2

_Z2

LUT1

_Z1

PWM2

_PI

PWM1

_PI

PI_Z2

PI_Z1

30h

Bit

Name

R/W

Description

0

PI_Z1

R/W

When this bit is set, the PI controller is bound to the P1 temperature (zone 1).

This also changes the available filtering options for the P1 temperature.

1

PI_Z2

R/W

When this bit is set, the PI controller is bound to the P2 temperature (zone 2).

This also changes the available filtering options for the P2 temperature zone.

2

3

4

PWM1_PI

PWM2_PI

LUT1_Z1

R/W

When this bit is set, the PWM1 output is bound to the PI controller.

When this bit is set, the PWM2 output is bound to the PI controller.

When this bit is set, LUT1 will use the P1 temperature (zone 1) instead of the

Internal temperature (zone 3).

5

6

7

LUT2_Z2

LUT3_Z1

LUT4_Z2

R/W

When this bit is set, LUT2 will use the P2 temperature (zone2) instead of the

External Digital temperature (zone 4).

When this bit is set, LUT3 will use the P1 temperature (zone1) instead of the

Internal temperature (zone 3).

When this bit is set, LUT4 will use the P2 temperature (zone 2) instead of the

External Digital temperature (zone 4).

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Register 36h PI Controller Minimum PWM and Hysteresis

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

36h

R/W

PI MinPWM and

Hyst

PI_MinPWM[3:0]

PI_Hyst[3:0]

00h

Bit

3:0

7:4

Name

R/W

Description

PI_Hyst[3:0]

R/W

Sets the hysteresis for the PI Loop fan controller in 0.5°C steps up to 7.5°C.

PI_MinPWM[3:0]

Defines the minimum PWM output for the PI Loop fan controller in 6.25%

steps up to 93.75%.

PI_Hyst[3:0]

Hysteresis (°C)

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

PI_MinPWM[3:0]

Minimum Duty Cycle

0.00%

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

6.25%

12.5%

18.75%

25.00%

31.25%

37.50%

43.75%

50.00%

56.25%

62.50%

68.75%

75.00%

81.25%

87.5%

93.75%

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Registers 37h and 38h Zone 1 and 2 PI Controller Target Temperature (Tcontrol)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

37h

38h

R/W

Zone 1 Tcontrol

Zone 2 Tcontrol

7

6

5

4

3

2

1

0

00h

Same format as temperature value register for Zone 1 and Zone 2. The PWM output controls the airflow over the

processors and thus the temperature of the processors is adjusted by the PI loop to maintain the hottest Zone 1

or Zone 2 temperature reading between their respective values for Tcontrol and Tcontrol - hysteresis. Intel

specifies an optimum Tcontrol temperature for some of it's processors that can be found in the MSR register

space.

Register 39h and 3Ah Zone 1 and 2 PI Fan Control Off Temperature (Toff)

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

39h

3Ah

R/W

Z1 Toff

Z2 Toff

7

6

5

4

3

2

1

0

80h

Same format as temperature value register for Zone 1 and Zone 2. When these registers are set to 80h, the Toff

function is disabled. Toff is the temperature at which the PI control loop output is forced to zero duty cycle.

Register 3Bh Proportional Coefficient

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Bh

R/W

P Coefficient

7

6

5

4

3

2

1

0

00h

Register 3Ch Integral Coefficient

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Ch

R/W

I Coefficient

7

6

5

4

3

2

1

0

00h

Register 3Dh PI Coefficient Exponents

Register

Address

Read/

Write

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Dh

R/W

PI Exponents

RES

PCE[1:0]

ICE[1:0]

00h

Bit

1:0

2:3

7:4

Name

ICE[1:0]

PCE[1:0]

RES

R/W

R

Description

PI controller integral coefficient exponent (2-bit signed value)

PI controller proportional coefficient exponent (2-bit signed value)

Reserved

ICE[1:0]

10b

Integral Exponent

-2

-1

0

11b

00b

01b

1

PCE[1:0]

10b

Proportional Exponent

-2

-1

0

11b

00b

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PCE[1:0]

Proportional Exponent

01b

1

DEVICE IDENTIFICATION REGISTERS (3Eh-3Fh)

Register 3Eh Manufacturer ID

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Eh

R

Manufact

urer ID

0

01h

The Manufacturer ID register contains the manufacturer identification number. This number is assigned by Texas

Instruments and is a method for uniquely identifying the part manufacturer.

Register 3Fh Version/Stepping

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Fh

R

Version/S

tepping

VER[3:0]

STP[3:0]

79h

0

1

0

1

The four least significant bits of the Version/Stepping register [3:0] contain the current stepping of the LM94

silicon. The four most significant bits [7:4] reflect the LM94 version number. The LM94 has a fixed version

number of 0111b wich matches the LM93, since the LM94 is closely related to the LM93. To differentiat the

LM94 from the LM93 for the first stepping of LM94 this register reads 01111000b. For the second stepping of the

LM94, this register reads 01111001b and so on. It is incrementally increased for future versions for the silicon.

The final released silicon has a stepping of 9h therefore this register reads 79h.

The register is used by application software to identify which device in the family of hardware monitoring ASICs

has been implemented in the given system. Based on this information, software can determine which registers to

read from and write to. Application software may use the current stepping to implement work-a-rounds for bugs

found in a specific silicon stepping.

BMC ERROR STATUS REGISTERS 40h–47h

The B_Error Status Registers contain several bits that each represent a particular error event that the LM94 can

monitor. The LM94 sets a given bit whenever the corresponding error event occurs. The BMC_ERR bit in the

LM94 Status/Control register is also set if any bit in the BMC Error Status registers is set. If enabled, ALERT is

also asserted anytime BMC_ERR is set. The exception to this is the fixed threshold error status bits in the

PROCHOT Error Status registers. They have no influence on BMC_ERR or ALERT.

Once a bit is set in the BMC Error Status registers, it is not automatically cleared by the LM94 if the error event

goes away. Each bit must be cleared by software. If software attempts to clear a bit while the error condition still

exists, and the error is unmasked, the bit does not clear. If the error is masked, the bit can be cleared even if the

error condition still exists.

If the LM94 is in ASF mode, the BMC Error Status registers are both read-to-clear and write-one-to-clear. When

not in ASF mode, the registers are only write-one-to-clear.

Each register described in this section has a column labeled Sleep Masking. This column describes which error

events are masked in various sleep states. The sleep state of the system is communicated to the LM94 by

writing to the Sleep State Control register. If a sleep state in this column has a ‘*’ next to it, it denotes that the

error event is optionally masked in that sleep mode, depending on the Sleep State Mask registers.

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Register 40h B_Error Status 1

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_Error

Status 1

VRD2

_ERR

VRD1

_ERR

ZN4_

ERR

ZN3_

ERR

ZN2_

ERR

ZN1_

ERR

40h

RWC

RES

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

ZN1_ERR

ZN2_ERR

RWC This bit is set when any zone 1 temperature has fallen outside its associated

temperature limits.

S3*, S4/5*

none

RWC This bit is set when any zone 2 temperature has fallen outside its associated

temperature limits.

ZN3_ERR

ZN4_ERR

RWC This bit is set when the zone 3 temperature has fallen outside the zone 3

temperature limits.

RWC This bit is set when the zone 4 temperature has fallen outside the zone 4

temperature limits.

none

4

5

VRD1_ERR

VRD2_ERR

RES

RWC This bit is set when the VRD1_HOT input has been asserted.

RWC This bit is set when the VRD2_HOT# input has been asserted.

S3, S4/5

N/A

7:6

R

Reserved

Register 41h B_Error Status 2

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_Error

Status 2

ADIN8

_ERR

ADIN7

_ERR

ADIN6

_ERR

ADIN5

_ERR

ADIN4

_ERR

ADIN3

_ERR

ADIN2

_ERR

ADIN1

_ERR

41h

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

AD1_ERR

AD2_ERR

RWC This bit is set when the AD_IN1 voltage has fallen outside the range defined by the

AD_IN1 Low Limit and the AD_IN1 High Limit registers.

S3, S4/5

RWC This bit is set when the AD_IN2 voltage has fallen outside the range defined by the

AD_IN2 Low Limit and the AD_IN2 High Limit registers.

S3, S4/5

AD3_ERR

AD4_ERR

AD5_ERR

AD6_ERR

AD7_ERR

AD8_ERR

RWC This bit is set when the AD_IN3 voltage has fallen outside the range defined by the

AD_IN3 Low Limit and the AD_IN3 High Limit registers.

RWC This bit is set when the AD_IN4 voltage has fallen outside the range defined by the

AD_IN4 Low Limit and the AD_IN4 High Limit registers.

RWC This bit is set when the AD_IN5 voltage has fallen outside the range defined by the

AD_IN5 Low Limit and the AD_IN5 High Limit registers.

RWC This bit is set when the AD_IN6 voltage has fallen outside the range defined by the

AD_IN6 Low Limit and the AD_IN6 High Limit registers.

RWC This bit is set when the AD_IN7 voltage has fallen outside the range defined by the

AD_IN7 Low Limit and the AD_IN7 High Limit registers.

RWC This bit is set when the AD_IN8 voltage has fallen outside the range defined by the

AD_IN8 Low Limit and the AD_IN8 High Limit registers.

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Register 42h B_Error Status 3

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_Error

Status 3

ADIN16

_ERR

ADIN15

_ERR

ADIN14

_ERR

ADIN13

_ERR

ADIN12

_ERR

ADIN11

_ERR

ADIN10

_ERR

ADIN9

_ERR

42h

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

AD9_ERR

RWC This bit is set when the AD_IN9 voltage has fallen outside the range defined by the

AD_IN9 Low Limit and the AD_IN9 High Limit registers.

S3, S4/5

AD10_ERR

AD11_ERR

AD12_ERR

AD13_ERR

AD14_ERR

AD15_ERR

AD16_ERR

RWC This bit is set when the AD_IN10 voltage has fallen outside the range defined by

the AD_IN10 Low Limit and the AD_IN10 High Limit registers.

S3, S4/5

RWC This bit is set when the AD_IN11 voltage has fallen outside the range defined by

the AD_IN11 Low Limit and the AD_IN11 High Limit registers.

RWC This bit is set when the AD_IN12 voltage has fallen outside the range defined by

the AD_IN12 Low Limit and the AD_IN12 High Limit registers.

S3*, S4/5*

S3, S4/5

none

RWC This bit is set when the AD_IN13 voltage has fallen outside the range defined by

the AD_IN13 Low Limit and the AD_IN13 High Limit registers.

RWC This bit is set when the AD_IN14 voltage has fallen outside the range defined by

the AD_IN14 Low Limit and the AD_IN14 High Limit registers.

RWC This bit is set when the AD_IN15 voltage has fallen outside the range defined by

the AD_IN15 Low Limit and the AD_IN15 High Limit registers.

RWC This bit is set when the AD_IN16 voltage has fallen outside the range defined by

the AD_IN16 Low Limit and the AD_IN16 High Limit registers.

Register 43h B_Error Status 4

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_Error

Status 4

D2a_

ERR

D1a_

ERR

DV_DDP2 DV_DDP1

GPI9

_ERR

GPI8

_ERR

D2b

_ERR

D1b

_ERR

43h

RWC

00h

_ERR

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

D1b_ERR

D2b_ERR

GPI8

RWC Diode Fault Error

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE1b+ and

REMOTE1− pins.

RWC Diode Fault Error

S3*, S4/5*

S3, S4/5

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE2b+ and

REMOTE2− pins.

RWC SCSI Fuse Error

This bit is set if GPI8 has been asserted. Enabled only when VID mode is set to

VRD 10.

GPI9

RWC SCSI Fuse Error

This bit is set if GPI9 has been asserted. Enabled only when VID mode is set to

VRD 10.

DV_DDP1_ERR

DV_DDP2_ERR

D1a_ERR

D2a_ERR

RWC Dynamic Vccp Limit Error.

This bit is set if AD_IN7 (P1_Vccp) did not match the requested voltage as

reported by P1_VID[7:0].

RWC Dynamic Vccp Limit Error.

This bit is set if AD_IN8 (P2_Vccp) did not match the requested voltage as

reported by P1_VID[7:0].

RWC Diode Fault Error

This bit is set if there is an open or short circuit on the REMOTE1a+ and

REMOTE1− pins.

RWC Diode Fault Error

This bit is set if there is an open or short circuit on the REMOTE2a+ and

REMOTE2− pins.

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Register 44h B_P1_PROCHOT Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_P1_PR

OCHOT

Error

TMAX

PH1

_ERR

44h

RWC

T100

T75

T50

T25

T12

T0

00h

Status

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

T0

RWC Set when P1_PROCHOT has had a throttled event. This bit is set for any amount

of PROCHOT throttling >0%.

S3, S4/5

T12

T25

T50

T75

T100

RWC Set when P1_PROCHOT has throttled greater than or equal to 0.39% but less than

12.5%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 12.5% but less than

25%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 25% but less than

50%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 50% but less than

75%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 75% but less than

100%.

6

7

TMAX

RWC Set when P1_PROCHOT has throttled 100%.

S3, S4/5

PH1_ERR

RWC Set when P1_PROCHOT has throttled more than the user limit.

The PH1_ERR bit is the only bit in this register that will set BMC_ ERR in the LM94 Status/Control register.

Register 45h B_P2_PROCHOT Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_P2_PR

OCHOT

Error

TMAX

PH2

_ERR

45h

RWC

T100

T75

T50

T25

T12

T0

00h

Status

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

T0

RWC Set when P2_PROCHOT has had a throttled event. This bit is set for any amount

of PROCHOT throttling >0%.

S3, S4/5

T12

T25

T50

T75

T100

RWC Set when P2_PROCHOT has throttled greater than or equal to 0.0% but less than

12.5%.

S3, S4/5

RWC Set when P2_PROCHOT has throttled greater than or equal to 12.5% but less than

25%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 25% but less than

50%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 50% but less than

75%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 75% but less than

100%.

6

7

TMAX

RWC Set when P2_PROCHOT has throttled 100%.

S3, S4/5

PH2_ERR

RWC Set when P2_PROCHOT has throttled more than the user limit.

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The PH2_ERR bit is the only bit in this register that will set BMC_ ERR in the LM94 Status/Control register.

Register 46h B_GPI Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_GPI

Error

Status

GPI6

_ERR

GPI7

_ERR

GPI5

_ERR

GPI4

_ERR

GPI3

_ERR

GPI2

_ERR

GPI1

_ERR

GPI0

_ERR

46h

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

GPI0_ERR

GPI1_ERR

GPI2_ERR

GPI3_ERR

GPI4_ERR

GPI5_ERR

GPI6_ERR

GPI7_ERR

RWC This bit is set whenever GPIO0 is driven low (unless masked via the GPI Error

Mask register).

S1*, S3*, S4/5*

RWC This bit is set whenever GPIO1 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO2 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO3 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO4 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO5 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO6 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO7 is driven low (unless masked via the GPI Error

Mask register).

Register 47h B_Fan Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

B_Fan

Error

Status

FAN4

_ERR

FAN3

_ERR

FAN2

_ERR

FAN1

_ERR

47h

RWC

RES

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

FAN1_ERR

FAN2_ERR

FAN3_ERR

FAN4_ERR

RES

RWC This bit is set when the Fan Tach 1 value register is above the value set in the Fan

Tach 1 Limit register.

S1*, S3*, S4/5

N/A

RWC This bit is set when the Fan Tach 2 value register is above the value set in the Fan

Tach 2 Limit register.

2

RWC This bit is set when the Fan Tach 3 value register is above the value set in the Fan

Tach 3 Limit register.

3

RWC This bit is set when the Fan Tach 4 value register is above the value set in the Fan

Tach 4 Limit register.

7:4

R

Reserved

HOST ERROR STATUS REGISTERS

The Host Error Status Registers contain several bits that each represent a particular error event that the LM94

can monitor. The LM94 sets a given bit whenever the corresponding error event occurs. The HOST_ERR bit in

the LM94 Status/Control register also sets if any bit in the Host Error Status registers is set. The exception to this

is the fixed threshold error status bits in the PROCHOT Error Status registers. They have no influence on

HOST_ERR.

Once a bit is set in the Host Error Status registers, it is not automatically cleared by the LM94 if the error event

goes away. Each bit must be cleared by software. If software attempts to clear a bit while the error condition still

exists, the bit does not clear.

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Software must specifically write a 1 to any bits it wishes to clear in the Host Error Status registers (write-one-to-

clear).

Each register described in this section has a column labeled Sleep Masking. This column describes which error

events are masked in various sleep states. The sleep state of the system is communicated to the LM94 by

writing to the Sleep State Control register. If a sleep state in this column has a ‘*’ next to it, it denotes that the

error event is optionally masked in that sleep mode, depending on the Sleep State Mask registers.

Register 48h H_Error Status 1

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_Error

Status 1

VRD2

_ERR

VRD1

_ERR

ZN4_

ERR

ZN3_

ERR

ZN2_

ERR

ZN1_

ERR

48h

RWC

RES

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

ZN1_ERR

ZN2_ERR

RWC This bit is set when any zone 1 temperature has fallen outside its associated

temperature limits.

S3*, S4/5*

RWC This bit is set when any zone 2 temperature has fallen outside its associated

temperature limits.

S3*, S4/5*

none

ZN3_ERR

ZN4_ERR

RWC This bit is set when the zone 3 temperature has fallen outside the zone 3

temperature limits.

RWC This bit is set when the zone 4 temperature has fallen outside the zone 4

temperature limits.

none

4

5

VRD1_ERR

VRD2_ERR

RES

RWC This bit is set when the VRD1_HOT input has been asserted.

RWC This bit is set when the VRD2_HOT# input has been asserted.

S3, S4/5

N/A

7:6

R

Reserved

Register 49h H_Error Status 2

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_Error

Status 2

ADIN8

_ERR

ADIN7

_ERR

ADIN6

_ERR

ADIN5

_ERR

ADIN4

_ERR

ADIN3

_ERR

ADIN2

_ERR

ADIN1

_ERR

49h

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

AD1_ERR

AD2_ERR

RWC This bit is set when the AD_IN1 voltage has fallen outside the range defined by the

AD_IN1 Low Limit and the AD_IN1 High Limit registers.

S3, S4/5

RWC This bit is set when the AD_IN2 voltage has fallen outside the range defined by the

AD_IN2 Low Limit and the AD_IN2 High Limit registers.

S3, S4/5

AD3_ERR

AD4_ERR

AD5_ERR

AD6_ERR

AD7_ERR

AD8_ERR

RWC This bit is set when the AD_IN3 voltage has fallen outside the range defined by the

AD_IN3 Low Limit and the AD_IN3 High Limit registers.

RWC This bit is set when the AD_IN4 voltage has fallen outside the range defined by the

AD_IN4 Low Limit and the AD_IN4 High Limit registers.

RWC This bit is set when the AD_IN5 voltage has fallen outside the range defined by the

AD_IN5 Low Limit and the AD_IN5 High Limit registers.

RWC This bit is set when the AD_IN6 voltage has fallen outside the range defined by the

AD_IN6 Low Limit and the AD_IN6 High Limit registers.

RWC This bit is set when the AD_IN7 voltage has fallen outside the range defined by the

AD_IN7 Low Limit and the AD_IN7 High Limit registers.

RWC This bit is set when the AD_IN8 voltage has fallen outside the range defined by the

AD_IN8 Low Limit and the AD_IN8 High Limit registers.

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Register 4Ah H_Error Status 3

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_Error

Status 3

ADIN16

_ERR

ADIN15

_ERR

ADIN14

_ERR

ADIN13

_ERR

ADIN12

_ERR

ADIN11

_ERR

ADIN10

_ERR

ADIN9

_ERR

4Ah

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

AD9_ERR

RWC This bit is set when the AD_IN9 voltage has fallen outside the range defined by the

AD_IN9 Low Limit and the AD_IN9 High Limit registers.

S3, S4/5

AD10_ERR

AD11_ERR

AD12_ERR

AD13_ERR

AD14_ERR

AD15_ERR

AD16_ERR

RWC This bit is set when the AD_IN10 voltage has fallen outside the range defined by

the AD_IN10 Low Limit and the AD_IN10 High Limit registers.

S3, S4/5

RWC This bit is set when the AD_IN11 voltage has fallen outside the range defined by

the AD_IN11 Low Limit and the AD_IN11 High Limit registers.

RWC This bit is set when the AD_IN12 voltage has fallen outside the range defined by

the AD_IN12 Low Limit and the AD_IN12 High Limit registers.

S3*, S4/5*

S3, S4/5

none

RWC This bit is set when the AD_IN13 voltage has fallen outside the range defined by

the AD_IN13 Low Limit and the AD_IN13 High Limit registers.

RWC This bit is set when the AD_IN14 voltage has fallen outside the range defined by

the AD_IN14 Low Limit and the AD_IN14 High Limit registers.

RWC This bit is set when the AD_IN15 voltage has fallen outside the range defined by

the AD_IN15 Low Limit and the AD_IN15 High Limit registers.

RWC This bit is set when the AD_IN16 voltage has fallen outside the range defined by

the AD_IN16 Low Limit and the AD_IN16 High Limit registers.

Register 4Bh H_Error Status 4

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_Error

Status 4

D2a_

ERR

D1a_

ERR

DV_DDP2 DV_DDP1

GPI9

_ERR

GPI8

_ERR

D2b

_ERR

D1b

_ERR

4Bh

RWC

00h

_ERR

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

D1b_ERR

D2b_ERR

GPI8

RWC Diode Fault Error

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE1b+ and

REMOTE1− pins.

RWC Diode Fault Error

S3*, S4/5*

S3, S4/5

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE2b+ and

REMOTE2− pins.

RWC SCSI Fuse Error

This bit is set if GPI8 has been asserted. Enabled only when VID mode is set to

VRD 10.

GPI9

RWC SCSI Fuse Error

This bit is set if GPI9 has been asserted. Enabled only when VID mode is set to

VRD 10.

DV_DDP1_ERR

DV_DDP2_ERR

D1a_ERR

D2a_ERR

RWC Dynamic Vccp Limit Error.

This bit is set if AD_IN7 (P1_Vccp) did not match the requested voltage as

reported by P1_VID[7:0].

RWC Dynamic Vccp Limit Error.

This bit is set if AD_IN8 (P2_Vccp) did not match the requested voltage as

reported by P1_VID[7:0].

RWC Diode Fault Error

This bit is set if there is an open or short circuit on the REMOTE1a+ and

REMOTE1− pins.

RWC Diode Fault Error

This bit is set if there is an open or short circuit on the REMOTE2a+ and

REMOTE2− pins.

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Register 4Ch H_P1_PROCHOT Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_P1_PR

OCHOT

Error

TMAX

PH1_ER

R

4Ch

RWC

T100

T75

T50

T25

T12

T0

00h

Status

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

T0

RWC Set when P1_PROCHOT has had a throttled event. This bit is set for any amount

of PROCHOT throttling >0%.

S3, S4/5

T12

T25

T50

T75

T100

RWC Set when P1_PROCHOT has throttled greater than or equal to 0.00% but less than

12.5%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 12.5% but less than

25%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 25% but less than

50%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 50% but less than

75%.

RWC Set when P1_PROCHOT has throttled greater than or equal to 75% but less than

100%.

6

7

TMAX

RWC Set when P1_PROCHOT has throttled 100%.

S3, S4/5

PH1_ERR

RWC Set when P1_PROCHOT has throttled more than the user limit.

The PH1_ERR bit is the only bit in this register that will set HOST_ ERR in the LM94 Status/Control register.

Register 4Dh B_P2_PROCHOT Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_P2_PR

OCHOT

Error

TMAX

PH2_ER

R

4Dh

RWC

T100

T75

T50

T25

T12

T0

00h

Status

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

T0

RWC Set when P2_PROCHOT has had a throttled event. This bit is set for any amount

of PROCHOT throttling >0%.

S3, S4/5

T12

T25

T50

T75

T100

RWC Set when P2_PROCHOT has throttled greater than or equal to 0.00% but less than

12.5%.

S3, S4/5

RWC Set when P2_PROCHOT has throttled greater than or equal to 12.5% but less than

25%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 25% but less than

50%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 50% but less than

75%.

RWC Set when P2_PROCHOT has throttled greater than or equal to 75% but less than

100%.

6

7

TMAX

RWC Set when P2_PROCHOT has throttled 100%.

S3, S4/5

PH2_ERR

RWC Set when P2_PROCHOT has throttled more than the user limit.

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The PH2_ERR bit is the only bit in this register that will set HOST_ ERR in the LM94 Status/Control register.

Register 4Eh H_GPI Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_GPI

Error

Status

GPI6

_ERR

GPI7

_ERR

GPI5

_ERR

GPI4

_ERR

GPI3

_ERR

GPI2

_ERR

GPI1

_ERR

GPI0

_ERR

4Eh

RWC

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

2

3

4

5

6

7

GPI0_ERR

GPI1_ERR

GPI2_ERR

GPI3_ERR

GPI4_ERR

GPI5_ERR

GPI6_ERR

GPI7_ERR

RWC This bit is set whenever GPIO0 is driven low (unless masked via the GPI Error

Mask register).

S1*, S3*, S4/5*

RWC This bit is set whenever GPIO1 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO2 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO3 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO4 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO5 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO6 is driven low (unless masked via the GPI Error

Mask register).

RWC This bit is set whenever GPIO7 is driven low (unless masked via the GPI Error

Mask register).

Register 4Fh H_Fan Error Status

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H_Fan

Error

Status

FAN4

_ERR

FAN3

_ERR

FAN2

_ERR

FAN1

_ERR

4Fh

RWC

RES

00h

Sleep

Masking

Bit

Name

R/W

Description

0

1

FAN1_ERR

FAN2_ERR

FAN3_ERR

FAN4_ERR

RES

RWC This bit is set when the Fan Tach 1 value register is above the value set in the Fan

Tach 1 Limit register.

S1*, S3*, S4/5

N/A

RWC This bit is set when the Fan Tach 2 value register is above the value set in the Fan

Tach 2 Limit register.

2

RWC This bit is set when the Fan Tach 3 value register is above the value set in the Fan

Tach 3 Limit register.

3

R

This bit is set when the Fan Tach 4 value register is above the value set in the Fan

Tach 4 Limit register.

7:4

R

Reserved

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VALUE REGISTERS

Registers 50–53h Unfiltered Temperature Value Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1b

(CPU1)

Temp

06h

07h

50h

51h

52h

R

7

6

5

4

3

2

1

0

00h

Zone 2b

(CPU2)

Temp

7

6

5

4

3

2

1

0

Zone 1a

(CPU1)

Temp

Zone 2a

(CPU2)

Temp

Zone 3

(Internal)

Temp

Zone 4

(External

Digital)

Temp

53h

R/W

7

6

5

4

3

2

1

0

00h

Zones 1 and 2 are all automatically updated by the LM94. The Zone 3 (Internal) Temp and Zone 4 (External

Digital) Temp registers may be written by an external SMBus device or can be assigned to AD_IN11 and

AD_IN15, respectively.

The temperature registers for zones 1 and 2 will return a value of 80h if the remote diode pins are not

implemented by the board designer or are not functioning properly.

Registers 54–55h Filtered Temperature Value Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1b

(CPU1)

Filtered

Temp

08h

09h

54h

55h

R

7

6

5

4

3

2

1

0

00h

Zone 2b

(CPU2)

Filtered

Temp

7

6

5

4

3

2

1

0

Zone 1a

(CPU1)

Filtered

Temp

Zone 2a

(CPU2)

Filtered

Temp

These registers reflect the temperature of zones 1 and 2 after the spike smoothing filter has been applied.

The characteristics of the filtering can be adjusted by using the Zones 1/2 Spike Smoothing Control register.

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Register 56–65h A/D Channel Voltage Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

7

Bit 6

6

Bit 5

5

Bit 4

4

Bit 3

3

Bit 2

2

Bit 1

1

Bit 0

0

AD_IN1

Voltage

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

R

N/D

AD_IN2

Voltage

7

6

5

4

3

2

1

0

N/D

AD_IN3

Voltage

7

6

5

4

3

2

1

0

AD_IN4

Voltage

7

6

5

4

3

2

1

0

AD_IN5

Voltage

7

6

5

4

3

2

1

0

AD_IN6

Voltage

7

6

5

4

3

2

1

0

AD_IN7

Voltage

7

6

5

4

3

2

1

0

AD_IN8

Voltage

7

6

5

4

3

2

1

0

AD_IN9

Voltage

7

6

5

4

3

2

1

0

AD_IN10

Voltage

7

6

5

4

3

2

1

0

AD_IN11

Voltage

7

6

5

4

3

2

1

0

AD_IN12

Voltage

7

6

5

4

3

2

1

0

AD_IN13

Voltage

7

6

5

4

3

2

1

0

AD_IN14

Voltage

7

6

5

4

3

2

1

0

AD_IN15

Voltage

7

6

5

4

3

2

1

0

AD_IN16

Voltage

7

6

5

4

3

2

1

0

The voltage reading registers reflect the current voltage of the LM94 voltage monitoring inputs. Voltages are

presented in the registers at ¾ full scale for the nominal voltage. Therefore, at nominal voltage, each register

reads C0h.

Register 67h Current P1_PROCHOT

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Current

P1_PRO

CHOT

67h

R

7

6

5

4

3

2

1

0

00h

This is the value of the PROCHOT percentage active time for Processor 1 at the end of each PROCHOT

monitoring interval as set by the PROCHOT Time Interval register. Writing to this register does not effect the

register contents, but does restart the capture cycle for both PROCHOT channels (P1_PROCHOT and

P2_PROCHOT). A register value of one represents anything greater than 0% but less than 0.39% of active time.

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Register Value (Decimal)

Percentage Active Time

0

1

2

0%

0.39%

0.78%

•

n

n/256*100

99.60%

255

Register 68h Average P1_PROCHOT

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Average

P1_PRO

CHOT

68h

R

7

6

5

4

3

2

1

0

00h

This is the average percentage active time of P1_PROCHOT. It is the result of adding the contents of this

register to the contents of the Current P1_PROCHOT register and dividing the result by 2. The update occurs at

the same time that the Current P1_PROCHOT register gets updated. A register value of one represents anything

greater than 0% but less than 0.39% of active time.

Register 69h Current P2_PROCHOT

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Current

P2_PRO

CHOT

69h

R

7

6

5

4

3

2

1

0

00h

This is the value of the PROCHOT percentage active time for Processor 2 at the end of each PROCHOT

monitoring interval as set by the PROCHOT Time Interval register. Writing to this register does not effect the

register contents, but does restart the capture cycle for both PROCHOT channels (P1_PROCHOT and

P2_PROCHOT). A register value of one represents anything greater than 0% but less than 0.39% of active time.

Register Value (Decimal)

Percentage Active Time

0

1

2

0%

0.39%

0.78%

•

n

n/256*100

99.60%

255

Register 6Ah Average P2_PROCHOT

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Average

P2_PRO

CHOT

6Ah

R

7

6

5

4

3

2

1

0

00h

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This is the average percentage active time of P2_PROCHOT. It is the result of adding the contents of this

register to the contents of the Current P2_PROCHOT register and dividing the result by 2. The update occurs at

the same time that the Current P2_PROCHOT register gets updated. A register value of one represents anything

greater than 0% but less than 0.39% of active time.

Register 6Bh Current GPI State

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6Bh

R

GPI State

GPI7

GPI6

GP15

GPI4

GPI3

GPI2

GPI1

GPI0

00h

Bit

0

Name

Read/Write

Description

GPI0

GPI1

GPI2

GPI3

GPI4

GPI5

GPI6

GPI7

R

1 if GPIO_0 input is LOW, not latched

1 if GPIO_1 input is LOW, not latched

1 if GPIO_2 input is LOW, not latched

1 if GPIO_3 input is LOW, not latched

1 if GPIO_4 input is LOW, not latched

1 if GPIO_5 input is LOW, not latched

1 if GPIO_6 input is LOW, not latched

1 if GPIO_7 input is LOW, not latched

1

2

3

4

5

6

7

Register 6Ch P1_VID

This register has four possible mappings described in the table. The mapping is determined by the VID mode as

selected in the Special Function Control 2 register at address BDh. See the Special Function Control 2 register

description for further details.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RES (0)

P1_VID[5:0] for VRD 10 mode (functions same as LM93)

P1_VID[6:0] for VRD 10.2 Extended mode

00h

RES (0)

6Ch

R

P1_VID

P1_VID[6:0] for VRD 11 , Mode 1 (most commonly used mode for VRD11)

P1_VID[7:1] for VRD 11, Mode 2

RES (0)

Table 5. VRD 10 mode

Bit

Name

Read/Write

Description

5:0

P1_VID[5:0]

R

Processor 1 VID status.

Reports the current state of the P1_VID5 through P1_VID0 pins. This register

will only be updated if P1_VID signals remain stable for at least 600 ns.

7:6

RES

R

Reserved and will always report 0.

Table 6. VRD 10.2 Extended mode

Bit

Name

Read/Write

Description

6:0

P1_VID[6:0]

R

Processor 1 VID status.

Reports the current state of the P1_VID6 through P1_VID0 pins. This register

will only be updated if P1_VID signals remain stable for at least 600 ns.

7

RES

R

Reserved and will always report 0.

Table 7. VRD 11 Mode 1

Bit

Name

Read/Write

Description

6:0

P1_VID[6:0]

R

Processor 1 VID status. This mode is the recommended mode for support of

VRD11.

Reports the current state of the P1_VID6 through P1_VID0 pins. This register

will only be updated if P1_VID signals remain stable for at least 600 ns.

7

RES

R

Reserved and will always report 0.

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Table 8. VRD 11 Mode 2

Bit

0

Name

RES

Read/Write

Description

Reserved and will always report 0.

R

7:1

P1_VID[7:1]

Processor 1 VID status. This mode is supplied for future experimentation and

will require additional hardware in order to support both VRD11 and VRD10

specifications.

Reports the current state of the P1_VID7 through P1_VID1 pins. This register

will only be updated if P1_VID signals remain stable for at least 600 ns.

Register 6Dh P2_VID

This register has four possible mappings described in the table. The mapping is determined by the VID mode as

selected in the Special Function Control 2 register at address BDh. See the Special Function Control 2 register

description for further details.

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RES (0)

P2_VID[5:0] for VRD 10 mode (functions same as LM93)

P2_VID[6:0] for VRD 10.2 Extended mode

00h

RES (0)

6Dh

R

P2_VID

P2_VID[6:0] for VRD 11 , Mode 1 (most commonly used mode for VRD11)

P2_VID[7:1] for VRD 11, Mode 2

RES (0)

Table 9. VRD 10 mode

Bit

Name

Read/Write

Description

5:0

P2_VID[5:0]

R

Processor 2 VID status.

Reports the current state of the P2_VID5 through P2_VID0 pins. This register

will only be updated if P2_VID signals remain stable for at least 600 ns.

7:6

RES

R

Reserved and will always report 0.

Table 10. VRD 10.2 Extended mode

Bit

Name

Read/Write

Description

6:0

P2_VID[6:0]

R

Processor 2 VID status.

Reports the current state of the P2_VID6 through P2_VID0 pins. This register

will only be updated if P2_VID signals remain stable for at least 600 ns.

7

RES

R

Reserved and will always report 0.

Table 11. VRD 11 Mode 1

Bit

Name

Read/Write

Description

6:0

P2_VID[6:0]

R

Processor 2 VID status. This mode is the recommended mode for support of

VRD11.

Reports the current state of the P2_VID6 through P2_VID0 pins. This register

will only be updated if P2_VID signals remain stable for at least 600 ns.

7

RES

R

Reserved and will always report 0.

Table 12. VRD 11 Mode 2

Bit

0

Name

RES

Read/Write

Description

Reserved and will always report 0.

R

7:1

P2_VID[7:1]

Processor 2 VID status. This mode is supplied for future experimentation and

will require additional hardware in order to support both VRD11 and VRD10

specifications.

Reports the current state of the P2_VID7 through P2_VID1 pins. This register

will only be updated if P2_VID signals remain stable for at least 600 ns.

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Register 6E–75h Fan Tachometer Readings

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

TACH1[5:0]

TACH1[13:6]

TACH2[5:0]

TACH2[13:6]

TACH3[5:0]

TACH3[13:6]

TACH4[5:0]

TACH4[13:6]

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fan Tach 1

LSB

T1ST[1:0]

6Eh

6Fh

70h

71h

72h

73h

74h

75h

R

00h

Fan Tach 1

MSB

00h

Fan Tach 2

LSB

T2ST[1:0]

T3ST[1:0]

T4ST[1:0]

Fan Tach 2

MSB

Fan Tach 3

LSB

Fan Tach 3

MSB

Fan Tach 4

LSB

Fan Tach 4

MSB

The 14-bit fan tach readings indicate the number of 22.5 kHz clock periods that occurred during two full periods

of the tachometer input signal. Most fans produce two tachometer pulses per full revolution. These registers must

be updated at least once every second.

The fan tachometer reading registers must always return an accurate fan tachometer measurement, even when

a fan is disabled or non-functional. 3FFFh indicates that the fan is stalled, not spinning fast enough to measure,

or the tachometer input is not connected to a valid signal.

If the pulses per revolution of the fan is known, the RPM can be calculated with the following equation:

RPM= 22500 cycles/sec * 60 sec/min * 2 pulses / COUNT cycles / PULSES_PER_REV

where:

PULSES_PER_REV = the number of pulses that the fan produces per revolution

COUNT = The 14-bit value read from the tach register

Bit

Name

Read/Write

Description

1:0

T1ST[1:0], T2ST[1:0],

T3ST[1:0], T4ST[1:0]

R

Two bits for each tachometer reading that report the state of the fan control

circuitry used to acquire a reading. See table below for further clarification.

7:2

7:0

TACH1[5:0], TACH2[5:0],

TACH3[5:0], TACH4[5:0]

R

Least significant bit field of tachometer reading.

TACH1[13:6], TACH2[13:6],

TACH3[13:6], TACH4[13:6]

Most significant bit fielf of tachometer reading.

T1ST[1:0], T2ST[1:0],

State of Fan Control Circuitry

T3ST[1:0], or T4ST[1:0]

00

01

10

11

Normal Mode (Smart Tach Mode disabled)

Reserved

Smart Tach Mode 1, less accurate with most stable Fan RPM

Smart Tach Mode 2, most accurate with least stable Fan RPM

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LIMIT REGISTERS

Registers 78–7Fh Temperature Limit Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Processo

r 1

78h

79h

7Ah

7Bh

R/W

(Zone1)

Low

Temp

7

6

5

4

3

2

1

0

80h

Processo

r 1

(Zone1)

High

7

6

5

4

3

2

1

0

Temp

Processo

r 2

(Zone2)

Low

Temp

Processo

r 2

(Zone2)

High

Temp

Internal

(Zone3)

Low

7Ch

7Dh

R/W

7

6

5

4

3

2

1

0

80h

Temp

Internal

(Zone3)

High

Temp

External

Digital

(Zone4)

Low

7Eh

7Fh

R/W

7

6

5

4

3

2

1

0

80h

Temp

External

Digital

(Zone4)

High

Temp

If an external temperature input or the internal temperature sensor either exceeds the value set in the high limit

register or falls below the value set in the low limit register, the corresponding bit in the B_ and H_Error Status 1

register is set automatically by the LM94. For example, if the temperature read from the Remote1− and

Remote1+ inputs exceeds the Processor (Zone1) High Temp register limit setting, the ZN1_ERR bit in both

B_Error Status 1 and H_Error Status 1 registers is set. The temperature limits in these registers is represented

as 8 bit, 2’s complement, signed numbers in Celsius.

If any high temp limit register is set to 80h then the B_ and H_Error Status register bit for that temperature

channel is masked.

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Registers 80–83h Fan Boost Temperature Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fan

Boost

Temp

Zone 1

80h

81h

82h

83h

R/W

7

6

5

4

3

2

1

0

3Ch

Fan

Boost

Temp

Zone 2

7

6

5

4

3

2

1

0

3Ch

23h

Fan

Boost

Temp

Zone 3

Fan

Boost

Temp

Zone 4

If any thermal zone exceeds the temperature set in the Fan Boost Limit register, both of the PWM outputs are set

to 100%. The fan boost function takes precedence over low-resolution manual override. High-resolution manual

overide takes priority over the fan boost function. This is a safety feature that attempts to cool the system if there

is a potentially catastrophic thermal event. If set to 7Fh and the fan control temperature resolution is 1°C, the

feature is disabled.

Default = 60°C = 3Ch for zones 1 and 2

Default = 35°C = 23h for zones 3 and 4

The temperature has to fall the number of degrees specified in the Fan Boost Hysteresis registers, below this

temperature to cause the PWM outputs to return to normal operation. The fan boost function can be disabled by

setting the associated register to 80h.

Register 84h Zone1, and Zone2 Hysteresis for Limit Comparisons

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Limit

Comparis

on

HC1

84h

R/W

Hysteresi

s

HC2

00h

(Zones

1/2)

Bit

Name

R/W

Description

3:0

HC1

R/W

Sets the limit comparison hysteresis for zone 1 for both the High and Low limits. The

hysteresis can be set from 0°C to 15°C and has 1°C resolution.

7:4

HC2

R/W

Sets the limit comparison hysteresis for zone 2 for both the High and Low limits. The

hysteresis can be set from 0°C to 15°C and has 1°C resolution.

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Register 85h Zone3 and Zone4 Hysteresis for Limit Comparisons

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Limit

Comparis

on

HC3

85h

R/W

Hysteresi

s

HC4

00h

(Zones

3/4)

Bit

Name

R/W

Description

3:0

HC3

R/W

Sets the limit comparison hysteresis for zone 3 for both the High and Low limits. The

hysteresis can be set from 0°C to 15°C and has 1°C resolution.

7:4

HC4

R/W

Sets the limit comparison hysteresis for zone 4 for both the High and Low limits.The

hysteresis can be set from 0°C to 15°C and has 1°C resolution.

Registers 8E–8Fh Zone 1b and Zone 2b Temperature Reading Adjustment Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1b

Temp

Adjust

8Eh

8Fh

R/W

RES

Z1b_ADJUST[5:0]

Z2b_ADJUST[5:0]

00h

Zone 2b

Temp

RES

Adjust

Bit

Name

R/W

Description

5:0

Z1b_ADJUST[5:0] or

Z2b_ADJUST[5:0]

R/W

6-bit signed 2’s complement offset adjustment. This value is added to zone 1b or

zone 2b temperature measurements as they are made. All LM94 registers and

functions behave as if the resulting temperature was the true measured

temperature. This register allows offset adjustments from +31°C to −32°C in 1°C

steps.

7:6

RES

R

Reserved

Registers 90–AFh Voltage Limit Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AD_IN1

Low Limit

90h

91h

92h

93h

94h

95h

96h

97h

98h

R/W

7

6

5

4

3

2

1

0

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

AD_IN1

High Limit

AD_IN2

Low Limit

AD_IN2

High Limit

AD_IN3

Low Limit

AD_IN3

High Limit

AD_IN4

Low Limit

AD_IN4

High Limit

AD_IN5

Low Limit

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Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

7

Bit 6

6

Bit 5

5

Bit 4

4

Bit 3

3

Bit 2

2

Bit 1

1

Bit 0

0

AD_IN5

High Limit

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

A1h

A2h

A3h

A4h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

R/W

FFh

AD_IN6

Low Limit

7

6

5

4

3

2

1

0

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

AD_IN6

High Limit

7

6

5

4

3

2

1

0

AD_IN7

Low Limit

7

6

5

4

3

2

1

0

AD_IN7

High Limit

7

6

5

4

3

2

1

0

AD_IN8

Low Limit

7

6

5

4

3

2

1

0

AD_IN8

High Limit

7

6

5

4

3

2

1

0

AD_IN9

Low Limit

7

6

5

4

3

2

1

0

AD_IN9

High Limit

7

6

5

4

3

2

1

0

AD_IN10

Low Limit

7

6

5

4

3

2

1

0

AD_IN10

High Limit

7

6

5

4

3

2

1

0

AD_IN11

Low Limit

7

6

5

4

3

2

1

0

AD_IN11

High Limit

7

6

5

4

3

2

1

0

AD_IN12

Low Limit

7

6

5

4

3

2

1

0

AD_IN12

High Limit

7

6

5

4

3

2

1

0

AD_IN13

Low Limit

7

6

5

4

3

2

1

0

AD_IN13

High Limit

7

6

5

4

3

2

1

0

AD_IN14

Low Limit

7

6

5

4

3

2

1

0

AD_IN14

High Limit

7

6

5

4

3

2

1

0

AD_IN15

Low Limit

7

6

5

4

3

2

1

0

AD_IN15

High Limit

7

6

5

4

3

2

1

0

AD_IN16

Low Limit

7

6

5

4

3

2

1

0

AD_IN16

High Limit

7

6

5

4

3

2

1

0

FFh as the high limit acts as a mask for that voltage sensor and so prevents this channel from being able to set

the associated error status bit in the B_ or H_ Error Status registers, for both high and low limit errors.

If a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the

voltage low limit register, the corresponding bit is set automatically by the LM94 in the B_ and H_Error Status

registers.

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Register B0–B1h PROCHOT User Limit Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P1_PRO

CHOT

User

B0h

B1h

R/W

7

6

5

4

3

2

1

0

FFh

Limit

P2_PRO

CHOT

User

7

6

5

4

3

2

1

0

Limit

These registers allow a user limit to be set for the PROCHOT monitoring function. If the corresponding Current

Px_PROCHOT register exceeds this value, the PH1_ERR or PH2_ERR bit is set in the corresponding Host and

BMC error status registers. A value of FFh acts as a mask and prevents the error status bits from being set.

Register Value (Decimal)

Threshold Percentage

0

1

2

0%

0.39%

0.78%

•

n

n/256*100

99.60%

255

Register B2–B3h Dynamic Vccp Limit Offset Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vccp1

Limit

Offsets

B2h

B3h

R/W

UPPER_OFFSET1

UPPER_OFFSET2

LOWER_OFFSET1

LOWER_OFFSET2

17h

Vccp2

Limit

Offsets

These offsets are used to determine the upper and lower limits of the dynamic Vccp window comparator. These

offsets are added or subtracted from the value selected by the VID bits.

LOWER_OFFSET1 or

Lower Offset

LOWER_OFFSET2

0h

1h

2h

3h

- -

25 mV

50 mV

75 mV

100 mV

- -

Ch

Dh

Eh

Fh

325 mV

350 mV

375 mV

400 mV

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UPPER_OFFSET1 or

UPPER_OFFSET2

Upper Offset

0h

1h

2h

3h

∼ ∼

Dh

Eh

Fh

12.5 mV

25 mV

37.5 mV

50 mV

∼ ∼

175 mV

187.5 mV

200 mV

Register B4–BBh Fan Tach Limit Registers

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fan Tach

1

Limit LSB

RES

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

R/W

TLIMIT1[5:0]

FCh

Fan Tach

1

Limit

MSB

TLIMIT1[13:6]

FFh

FCh

FFh

FCh

FFh

FCh

FFh

Fan Tach

2

Limit LSB

TLIMIT2[5:0]

RES

Fan Tach

2

Limit

MSB

TLIMIT2[13:6]

Fan Tach

3

Limit LSB

TLIMIT3[5:0]

Fan Tach

3

Limit

MSB

TLIMIT1[13:6]

Fan Tach

4

Limit LSB

TLIMIT4[5:0]

Fan Tach

4

Limit

MSB

TLIMIT4[13:6]

If a tachometer reading exceeds its limit (as defined by these registers) the corresponding bit is set in the Host

and BMC Error Status registers. The fan tachometer readings can be associated with a particular PWM output,

but the tach errors are not automatically masked when a PWM is at 0% or set to level that causes the fan RPM

to be below the limit purposely. In order to prevent false errors, care needs to be taken to make sure that the Fan

Tach Limits are properly set. Errors are never generated for a fan if its limit is set to 3FFFh.

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SETUP REGISTERS

Register BCh Special Function Control 1 (Voltage Hysteresis and Fan Control Filter Enable)

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Special

Function

Control 1

FCFE2

LCFE2

LCFE1

VH

BCh

R/W

RES

FCFE1

00h

Bit

Name

R/W

Description

2:0

VH

R/W

Voltage hysteresis control. This determines the amount of hysteresis to be applied to all

voltage limit comparisons. It applies to both high and low limits. One LSB equals one A/D

count, so the actual voltage represented by one LSB depends on the voltage channel.

3

4

5

LCFE1

LCFE2

FCFE1

Limit Comparison Filter Enable. Setting this bit causes limit comparisons for temperature

zone 1a and 1b to use the filtered (spike smoothed) temperature instead of the unfiltered

temperature.

Limit Comparison Filter Enable. Setting this bit causes limit comparisons for temperature

zone 2a and 2b to use the filtered (spike smoothed) temperature instead of the unfiltered

temperature.

Fan Control Filter Enable. Setting this bit causes fan control functions for zone 1a and 1b

(including fan boost) to use the filtered (spike smoothed) temperature instead of the

unfiltered temperature. This includes the PI Loop controller, LUT, and temperature fan

boost functions.

6

7

FCFE2

RES

R/W

R

Fan Control Filter Enable. Setting this bit causes fan control functions for zone 2a and 2b

(including fan boost) to use the filtered (spike smoothed) temperature instead of the

unfiltered temperature. This includes the PI Loop controller, LUT, and temperature fan

boost functions.

Reserved

In order for the LCFE1, LCFE2, FCFE1 and FCFE2 bits to work correctly, the ZN1E and ZN2E bits in the Zones

1/2 Spike Smoothing Control register (at address C2h) should be cleared.

Application Note: If hysteresis for voltage limit comparisons is non-zero, special care needs to be taken when

changing the voltage limit registers while a voltage error condition exists. If software relaxes the voltage limits in

an attempt to prevent an error condition, it may be necessary to relax the limits by an amount greater than the

hysteresis value and wait several milliseconds before attempting to clear the error status bit for the given voltage

channel. Once the error status bit has been cleared, the desired limit(s) can be programmed.

Register BDh Special Function Control 2 (Smart Tach Mode Enable, Fan Control Temperature

Resolution Control and VID Mode Select)

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Special

Function

Control 2

LT12

_RS

STE4

STE3

STE2

STE1

LT34

_RS

BDh

R/W

VID_MODE[1:0]

00h

Bit

0

Name

R/W

Description

STE1

STE2

STE3

STE4

Enable Smart Tach for Tach 1

Enable Smart Tach for Tach 2

Enable Smart Tach for Tach 3

Enable Smart Tach for Tach 4

1

2

3

4

LT12_RS

When this bit is set, the LUT1 and LUT2 fan controls will use 0.5°C. The resolution

of the LUT offsets and hysteresis settings are affected by this bit. These bits apply

to the fan control offset registers, fan control hysteresis registers, and boost

hysteresis registers.

5

LT34_RS

R/W

When this bit is set, the LUT3 and LUT4 fan controls will use 0.5°C. The resolution

of the LUT offsets and hysteresis settings are affected by this bit.

7:6

VID_MODE[1:0]

These bits select the VID mode which determines how the VID code is handled by

the P1_VID and P2_VID value registers and the dynamic Vccp monitoring.

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Table 13. VID Mode Select Bit Description

VID_MODE[1:0]

VID Mode

Comments

00

01

10

VRD10

Supports the VRD10 specification from Intel and is backwards compatible with

the LM93 dynamic Vccp monitoring circuitry. This mode has a voltage range of

0.8375V to 1.600V with 12.5mV resolution and supports 6 VID bits/pins.

VRD10.2 Extended

VRD11 Mode 1

Supports the VRD10.2 Extended specification from Intel. This mode has a

voltage range of 0.83125V to 1.600V with 6.25mV resolution and supports 7 VID

bits/pins.

Supports the VRD11 specification from Intel. This mode has a voltage range of

0.83125V to 1.600V with 6.25mV resolution and supports 7 VID bits/pins (VID6-

VID0). It assumes VID7 is 0. This is the recommended mode of operation for

support of VRD10 and VRD11 without requiring additional hardware.

11

VRD11 Mode 2

Supports the VRD11 specification from Intel. This mode has a voltage range of

0.0375V to 1.600V with 12.5mV resolution and supports 7 VID bits/pins (VID7-

VID1). It assumes VID0 is 0. This mode measures voltage levels below

0.83125V for VRD11, but will require additional hardware to simultaneously

support VRD10 operation.

Application Note: Enabling Smart Tach mode is not supported while either PWM output is configured for 22.5

kHz. The behavior of the part is undefined if this configuration is programmed. Register E0h Special Function

TACH to PWM Binding must be setup when Smart Tach modes are enabled.

Register BEh GPI/VID Level Control

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPI/VID

Level

Control

GPI6

_LVL

GPI4

_LVL

GPI9

_LVL

GPI8

_LVL

P2_VID

_LVL

P1_VID

_LVL

GPI7

_LVL

GPI5

_LVL

BEh

R/W

00h

Bit

0

Name

R/W

Description

P1_VID_LVL

P2_VID_LVL

GPI8_LVL

GPI9_LVL

GPI4_LVL

GPI5_LVL

GPI6_LVL

GPI7_LVL

If set, P1_VIDx inputs use alternate lower V_IHand V_ILlevels.

If set, P2_VIDx uses alternate lower V_IHand V_ILlevels.

1

2

When in VRD10 mode, if set, GPI_8 input uses alternate lower V_IHand V_ILlevels.

3

When in VRD10 mode, if set, GPI_9 input will use alternate lower V_IHand V_ILlevels.

If set, GPIO4 input will use alternate lower V_IHand V_ILlevels

If set, GPIO5 input will use alternate lower V_IHand V_ILlevels

If set, GPIO6 input will use alternate lower V_IHand V_ILlevels

If set, GPIO7 input will use alternate lower V_IHand V_ILlevels

4

5

6

7

See the DC Electrical Characteristics for exact V_IHand V_ILlevels.

Register BFh PWM Ramp Control

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM

Ramp

Control

VRD_RAMP

BFh

R/W

PH_RAMP

00h

Bit

Name

R/W

Description

3:0

VRD_RAMP

R/W

Sets the time delay between ramp steps for the VRDx_HOT ramp up/ramp down

PWM function.

7:4

PH_RAMP

R/W

Sets the time delay between ramp steps for the Px_PROCHOT ramp up/ramp down

PWM function.

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If the time delay between steps is set to 0 ms, the PWM duty cycle goes immediately to 100% instead of ramping

up gradually.

VRD_RAMP

or PH_RAMP

Time Delay between

Ramp Steps

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

0 ms

50 ms

100 ms

150 ms

200 ms

250 ms

300 ms

350 ms

400 ms

450 ms

500 ms

550 ms

600 ms

650 ms

700 ms

750 ms

Register C0h Fan Boost Hysteresis (Zones 1/2)

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fan

Boost

Hysteresi

s

H1

C0h

R/W

H2

44h

(Zones

1/2)

Bit

3:0

7:4

Name

R/W

Description

H1

H2

Sets the fan boost hysteresis for Zone 1a and 1b, has 1°C resolution.

Sets the fan boost hysteresis for zone 2a and 2b, has 1°C resolution.

If the temperature zone is above fan boost temperature and then drops below the fan boost temperature, the

following occurs: the PWM output remains at 100% until the temperature goes a certain amount below the fan

boost temperature. These hysteresis registers control this amount and can be set anywhere from 0°C to 15°C

(unsigned).

Register C1h Fan Boost Hysteresis (Zones 3/4)

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fan

Boost

Hysteresi

s

H3

C1h

R/W

H4

44h

(Zones

3/4)

Bit

3:0

7:4

Name

R/W

Description

H3

H4

Sets the fan boost hysteresis for zone 3 and has 1°C resolution.

Sets the fan boost hysteresis for zone 4 and has 1°C resolution.

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If the temperature zone is above fan boost temperature and then drops below the fan boost temperature, the

following occurs: the PWM output remains at 100% until the temperature goes a certain amount below the fan

boost temperature. These hysteresis registers control this amount and can be set anywhere from 0°C to 15°C

(unsigned).

Register C2h Zones 1/2 Spike Smoothing Control

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zones 1/2

Spike

ZN2

ZN1E

ZN1

C2h

R/W

Smoothin

g

ZN2E

00h

Control

Bit

2:0

3

Name

R/W

Description

ZN1

Configures the spike smoothing characteristics for zone 1a and 1b

ZN1E

When set, the filtered temperature for zone 1a and 1b is used for both limit checking

and auto-fan control instead of the unfiltered temperature. Even when this bit is

cleared, the filtered temperature can be read by software from the filtered

temperature register.

6:4

7

ZN2

R/W

Configures the spike smoothing characteristics for zone 2a and 2b

ZN2E

When set, the filtered temperature for zone 2a and 2b is used for both limit checking

and auto-fan control instead of the unfiltered temperature. Even when this bit is

cleared, the filtered temperature can be read by software from the filtered

temperature register.

If all the REMOTE1 or REMOTE2 pins are connected to a processor or chipset, instantaneous temperature

spikes may be sampled by the LM94. If these spikes are not ignored, the PWM outputs may cause the fans to

turn on prematurely and produce unpleasant noise. Also, false error events may occur. For this reason, any zone

that is connected to a chipset or processor may need spike smoothing enabled. The spike smoothing provides

additional filtering above and beyond any ΣΔ A/D inherent averaging.

When spike smoothing is enabled, the temperature reading registers still reflect the current value of the

temperature—not the filtered value. Only the filtered temperature registers reflect the filtered value.

ZN1 or ZN2

Spike Smoothed Over

11.8 seconds

7.0 seconds

0h

1h

2h

3h

4h

5h

6h

7h

4.4 seconds

3.0 seconds

1.6 seconds

0.8 seconds

0.6 seconds

0.4 seconds

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Register C3h LUT 1/2 MinPWM and Hysteresis

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LUT 1/2

MinPWM

and

LUT_FC_TH12

C3h

R/W

MinPWM12

00h

Hysteresi

s

Bit

Name

R/W

Description

3:0

LUT_FC_TH12

MinPWM12

R/W

This field sets the amount of hysteresis (in degrees C) that is used by the auto-fan

control for LUT 1 and 2. This should be set greater than 0 to avoid unwanted

oscillation between two steps in the look-up table. The resolution of this field is

controlled by Special Function Control 2 register bit 4.

7:4

R/W

This field determines the duty cycle that the auto-fan control requests for LUT 1 and

2 if the temperature for the given zone falls below the programmed base

temperature for the assigned LUT. This field accepts 16 possible values 13 of which

are mapped to duty cycles according the table in the Auto-Fan Control section LUT

Fan Control Duty Cycles.

Register C4h LUT 3/4 MinPWM and Hysteresis

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LUT 3/4

MinPWM

and

LUT_FC_TH34

C4h

R/W

MinPWM34

00h

Hysteresi

s

Bit

Name

R/W

Description

3:0

LUT_FC_TH34

MinPWM34

R/W

This field sets the amount of hysteresis (in degrees C) that is used by the auto-fan

control for LUT 3 and 4. This should be set greater than 0 to avoid unwanted

oscillation between two steps in the look-up table. The resolution of this field is

controlled by Special Function Control 2 register bit 5.

7:4

R/W

This field determines the duty cycle that the auto-fan control requests for LUT 3 and

4 if the temperature for the given zone falls below the programmed base

temperature for the assigned LUT. This field accepts 16 possible values 13 of which

are mapped to duty cycles according the table in the Auto-Fan Control section LUT

Fan Control Duty Cycles.

Register C5h GPO

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C5h

R/W

GPO

GPO7

GPO6

GPO5

GPO4

GPO3

GPO2

GPO1

GPO0

00h

Bit

Name

R/W

Description

0

GPO0

GPO1

GPO2

GPO3

GPO4

GPO5

R/W

If set, GPIO_0 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_0 is being used as an input.

1

2

3

4

5

R/W

If set, GPIO_1 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_1 is being used as an input.

If set, GPIO_2 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_2 is being used as an input.

If set, GPIO_3 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_3 is being used as an input.

If set, GPIO_4 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_4 is being used as an input.

If set, GPIO_5 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_5 is being used as an input.

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Bit

Name

R/W

Description

6

GPO6

R/W

If set, GPIO_6 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_6 is being used as an input.

7

GPO7

R/W

If set, GPIO_7 will be pulled low. If cleared, the output is not pulled low. This bit

should be 0 if GPIO_7 is being used as an input.

Register C6h PROCHOT Control

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PROCHO

T

Override

FORCE P2_VRD2 P1_VRD1

_P2 _DIS _DIS

PHT_DC

FORCE

_P1

C6h

R/W

00h

Bit

3:0

4

Name

R/W

Description

PHT_DC

PROCHOT duty cycle select.

P1_VRD1_DIS

When this bit is set by software, P1_PROCHOT will not be asserted when P1_VRD_HOT

is asserted.

5

6

7

P2_VRD2_DIS

FORCE_P1

FORCE_P2

R/W

When this bit is set by software, P2_PROCHOT will not be asserted when P2_VRD_HOT

is asserted.

When this is set by software, P1_PROCHOT will be asserted by the LM94 with the duty

cycle selected by PHT_DC.

When this is set by software, P2_PROCHOT will be asserted by the LM94 with the duty

cycle selected by PHT_DC.

Note that if the P1P2_PROCHOT bit is set to short the Px_PROCHOT pins together, both Px_PROCHOT

outputs will be driven together, even if only one of the FORCE_Px bits is set.

The period of the PWM signal driven on Px_PROCHOT is 3.56 ms (80 internal 22.5 kHz clocks). The asserted

time can be increased in 5 clock increments. 5 clocks is about 220 µs and would represent 6.25% percent

throttled.

Possible settings for PHT_DC:

PHT_DC

0h

Asserted Period

5 clocks

1h

10 clocks

15 clocks

20 clocks

25 clocks

30 clocks

35 clocks

40 clocks

45 clocks

50 clocks

55 clocks

60 clocks

65 clocks

70 clocks

75 clocks

80 clocks

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

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Register C7h PROCHOT Time Interval

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PROCHO

T

Time

P1_TI

C7h

R/W

P2_TI

11h

Interval

Bit

3:0

7:4

Name

R/W

Description

P1_TI

P2_TI

Sets the monitoring interval for P1_PROCHOT

Sets the monitoring interval for P2_PROCHOT

Possible settings for P1_TI and P2_TI:

Monitoring Time Interval

(seconds)

P1_TI or P2_TI

0h

1h

0.73

1.46

2.9

2h

3h

5.8

4h

11.7

23.3

46.6

93.2

186

5h

6h

7h

8h

9h

372

Ah–Fh

Reserved

Note that changing this value while PROCHOT measurements are running may cause the monitoring circuit to

produce a erroneous value. To avoid alerts and invalid B_Px_PROCHOT or B_Px_PROCHOT Error Status

values, only change this value while the chip is programmed for S3 or S4/5.

Register C8h PWM1 Control 1

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM1

Control 1

VRD1

PH2

PH1

LUT4

LUT3

LUT2

LUT1

C8h

R/W

VRD2

00h

Bit

0

Name

R/W

Description

LUT1

LUT2

LUT3

LUT4

PH1

If set, PWM1 will be bound to LUT 1.

1

If set, PWM1 will be bound to LUT 2.

2

If set, PWM1 will be bound to LUT 3.

3

If set, PWM1 will be bound to LUT 4.

4

If set, PWM1 will be bound to P1_PROCHOT.

If set, PWM1 will be bound to P2_PROCHOT.

If set, PWM1 will be bound to VRD1_HOT1.

If set, PWM1 will be bound to VRD1_HOT2.

5

PH2

6

VRD1

VRD2

7

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This register can bind PWM1 to several different control sources. The temperature zones control the PWM duty

cycle using the table lookup function. The Px_PROCHOT and VRDx_HOT inputs control the PWM using the

ramp up/ramp down functions. If multiple control sources are bound to PWM1, the largest duty cycle being

requested will be used.

Register C9h PWM1 Control 2

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM1

Control 2

PPL

EPPL

INV

OVR

C9h

R/W

OVR_DC

00h

Bit

0

Name

R/W

Description

OVR

INV

When set, enables manual duty cycle override for PWM1.

1

Invert PWM1 output. When 0, 100% duty cycle corresponds to the PWM output

continuously HIGH. When 1, 100% duty cycle corresponds to the PWM output

continuously LOW.

2

3

EPPL

PPL

R/W

Enable PROCHOT PWM1 lock. When set, this bit causes bound PROCHOT events

on PWM1 to trigger PPL (bit [3]). When cleared, PPL never gets set.

PROCHOT PWM1 lock. When set, this bit indicates that PWM1 is currently being

held at 100% because a bound PROCHOT event occurred while EPPL (bit [2]) was

set. This bit is cleared by writing a zero. Clearing this bit allows the fans to return to

normal operation. This bit is not locked by the LOCK bit in the LM94 Configuration

register.

7:4

OVR_DC

R/W

This field sets the duty cycle that will be used by PWM1 whenever manual low

resolution override mode is active. This field accepts 16 possible values that are

mapped to duty cycles according the table in the FAN CONTROL section. Whenever

this register is read, it returns the duty cycle that is currently being used by PWM1

regardless of whether override mode is active or not. The value read may not match

the last value written if another control source is requesting a greater duty cycle.

This field always returns 0h when the PWM1 spin up cycle is active.

Register CAh PWM1 Control 3

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

SU_DUR[2:0]

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM1

Control 3

SU_DUR[

3]

SU_DC

CAh

R/W

00h

Bit

Name

SU_DC

R/W

Description

3:0

R/W

This field sets the duty cycle that will be used whenever PWM1 experiences a Spin-

Up cycle. This field accepts 16 possible values that are mapped to duty cycles

according the table in the LUT Fan Control Duty Cycles section. Setting this field to

0h will effectively disable Spin-Up.

4

SU_DUR[3]

R/W

Most significant bit that sets the Spin-up duration for PWM1.

7:0

SU_DUR[2:0]

Least significant bits that set the Spin-Up duration for PWM1 least significant bits.

Bits 7:4 configure the spin-up duration. When the duty cycle of PWM1 changes from zero to a non-zero value,

the spin-up sequence is activated for the specified amount of time. The available settings are defined according

to this table:

SU_DUR[3] (Bit 4)

SU_DUR[2:0] (Bits[7:5])

Spin-Up Time

Spin-up disabled

100 ms

0

0h

1h

2h

3h

4h

5h

6h

250 ms

400 ms

700 ms

1s

2 s

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SU_DUR[3] (Bit 4)

SU_DUR[2:0] (Bits[7:5])

Spin-Up Time

0

1

7h

0h

1h

2h

3h

4h

5h

6h

7h

4 s

6 s

8 s

10 s

12 s

14 s

16 s

18 s

20 s

Register CBh PWM1 Control 4

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM1

Control 4

RES

HF_LUT

_MAP

FREQ1

CBh

R/W

RES

00h

Bit

Name

FREQ1

R/W

Description

2:0

R/W

PWM1 frequency control. Setting this value controls the frequency of the PWM1

output according to the table below.

3

HF_LUT_MAP

R/W

Selects between two different maps for the PWM duty cycle assignment in the LUT

when the PWM frequency is set to 22.5kHz. All 4 LUTs, VRD ramp, PROCHOT

ramp, spin-up and low-resolution overide will be affected by this bit. When this bit is

set the LUT duty cycle assignment will increment 6.25% steps starting at 25%.

When this bit is cleared the duty cycle mapping will match the Low Frequency table.

This bit has no effect when the PWM frequency is set to anything other than

22.5kHz and the low PWM frequency mapping will be used.

7:4

RES

R

Reserved

Frequency of

PWM1 (Hz)

FREQ1

0h

1h

2h

3h

4h

5h

6h

7h

22500

96

84

72

60

48

36

12

Table 14. LUT 1-4 Duty Cycle Assignment with PWM Frequency=22.5kHz as Controlled by the

HF_LUT_MAP bit.

LUT Duty Cycle Assignments when HF_LUT_MAP='1'

LUT Duty Cycle Assignments when HF_LUT_MAP='0'

(Low PWM Frequency Mapping)

LUT Step

Duty Cycle (%)

25

LUT Step

Duty Cycle (%)

25

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

31.25

37.5

28.57

32.14

35.71

39.29

42.86

46.43

50

43.75

50

56.25

62.25

68.75

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Table 14. LUT 1-4 Duty Cycle Assignment with PWM Frequency=22.5kHz as Controlled by the

HF_LUT_MAP bit. (continued)

LUT Duty Cycle Assignments when HF_LUT_MAP='1'

LUT Duty Cycle Assignments when HF_LUT_MAP='0'

(Low PWM Frequency Mapping)

9

75

9

53.57

57.14

71.43

85.71

100

10

11

12

13

81.25

87.5

93.75

100

10

11

12

13

Register CCh PWM2 Control 1

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

VRD2

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LUT1

PWM2

Control 1

VRD1

PH2

PH1

LUT4

LUT3

LUT2

CCh

R/W

00h

Bit

0

Name

R/W

Description

LUT1

LUT2

LUT3

LUT4

PH1

If set, PWM2 will be bound to LUT 1.

1

If set, PWM2 will be bound to LUT 2.

2

If set, PWM2 will be bound to LUT 3.

3

If set, PWM2 will be bound to LUT 4.

4

If set, PWM2 will be bound to P1_PROCHOT.

If set, PWM2 will be bound to P2_PROCHOT.

If set, PWM2 will be bound to VRD1_HOT.

If set, PWM2 will be bound to VRD2_HOT.

5

PH2

6

VRD1

VRD2

7

This register can bind PWM2 to several different control sources. The temperature zones control the PWM duty

cycle using the table lookup function. The Px_PROCHOT and VRDx_HOT inputs control the PWM using the

ramp up/ramp down functions. If multiple control sources are bound to PWM2, the largest duty cycle being

requested will be used.

Register CDh PWM2 Control 2

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM2

Control 2

PPL

EPPL

INV

OVR

CDh

R/W

OVR_DC

00h

Bit

0

Name

R/W

Description

OVR

INV

When set, enables manual duty cycle override for PWM2.

1

Invert PWM1 output. When 0, 100% duty cycle corresponds to the PWM output

continuously HIGH. When 1, 100% duty cycle corresponds to the PWM output

continuously LOW.

2

3

EPPL

PPL

R/W

Enable PROCHOT PWM2 lock. When set, this bit causes bound PROCHOT events

on PWM2 to trigger PPL (bit [3]). When cleared, PPL never gets set.

PROCHOT PWM2 lock. When set, this bit indicates that PWM2 is currently being

held at 100% because a bound PROCHOT event occurred while EPPL (bit [2]) was

set. This bit is cleared by writing a zero. Clearing this bit allows the fans to return to

normal operation. This bit is not locked by the LOCK bit in the LM94 Configuration

register.

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Bit

Name

R/W

Description

7:4

OVR_DC

R/W

This field sets the duty cycle that will be used by PWM2 whenever manual low

resolution override mode is active. This field accepts 16 possible values that are

mapped to duty cycles according the table in the FAN CONTROL section. Whenever

this register is read, it returns the duty cycle that is currently being used by PWM2

regardless of whether override mode is active or not. The value read may not match

the last value written if another control source is requesting a greater duty cycle.

This field always returns 0h when the PWM2 spin up cycle is active.

Register CEh PWM2 Control 3

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

SU_DUR[2:0]

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM2

Control 3

SU_DUR[

3]

SU_DC

CEh

R/W

00h

Bit

Name

SU_DC

R/W

Description

3:0

R/W

This field sets the duty cycle that used whenever PWM2 experiences a Spin-Up

cycle. This field accepts 16 possible values that are mapped to duty cycles

according the table in the Auto-Fan Control section LUT Fan Control Duty Cycles.

Setting this field to 0h effectively disables Spin-Up.

4

SU_DUR[3]

R/W

Most significant bit that sets the spin-up duration for PWM2

Least significant bits that set the Spin-Up duration for PWM2.

7:5

SU_DUR[2:0]

Bits 7:4 configure the spin-up duration. When the duty cycle of PWM2 changes from zero to a non-zero value,

the spin-up sequence is activated for the specified amount of time. The available settings are defined according

to this table:

SU_DUR[3] (Bit 4)

SU_DUR[2:0] (Bits[7:5])

Spin-Up Time

0

1

0h

1h

2h

3h

4h

5h

6h

7h

0h

1h

2h

3h

4h

5h

6h

7h

Spin-up disabled

100 ms

250 ms

400 ms

700 ms

1s

2 s

4 s

6 s

8 s

10 s

12 s

14 s

16 s

18 s

20 s

90

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Register CFh PWM2 Control 4

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PWM2

Control 4

RES

HF_LUT

_MAP

FREQ2

CFh

R/W

RES

00h

Bit

Name

FREQ2

R/W

Description

2:0

R/W

PWM2 frequency control. Controls the frequency of the PWM2 output in the same

fashion as FREQ1 in the PWM1 Control 4 register.

3

HF_LUT_MAP

R/W

Selects between two different maps for the PWM duty cycle assignment in the LUT

when the PWM frequency is set to 22.5kHz. All 4 LUTs, VRD ramp, PROCHOT

ramp, spin-up, and low-resolution override will be affected by this bit. When this bit

is cleared the LUT duty cycle assignment will increment 6.25% steps starting at

25%. When this bit is set the duty cycle mapping will match the Low Frequency

table. This bit has no effect when the PWM frequency is set to anything other than

22.5kHz and the low PWM frequency mapping will be used.

7:4

RES

R

Reserved

Frequency of

PWM1 (Hz)

FREQ1

0h

1h

2h

3h

4h

5h

6h

7h

22500

96

84

72

60

48

36

12

Table 15. LUT 1-4 Duty Cycle Assignment with PWM Frequency=22.5kHz as Controlled by the

HF_LUT_MAP bit.

LUT Duty Cycle Assignments when HF_LUT_MAP='1'

LUT Duty Cycle Assignments when HF_LUT_MAP='0'

(Low PWM Frequency Mapping)

LUT Step

Duty Cycle (%)

25

LUT Step

Duty Cycle (%)

25

1

2

1

2

31.25

37.5

28.57

32.14

35.71

39.29

42.86

46.43

50

3

4

43.75

50

4

5

6

56.25

62.25

68.75

75

6

7

8

9

53.57

57.14

71.43

85.71

100

10

11

12

13

81.25

87.5

10

11

12

13

93.75

100

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Register D0h–D3h LUT 1 to 4 Base Temperatures

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LUT 1

Base

Temperat

ure

D0h

D1h

D2h

D3h

R/W

7

6

5

4

3

2

1

0

00h

LUT 2

Base

Temperat

ure

7

6

5

4

3

2

1

0

LUT 3

Base

Temperat

ure

LUT 4

Base

Temperat

ure

The value in this register is used as the base in the temperature calculation for the auto fan control look-up table.

These registers use the standard temperature format (8-bit signed data). The look-up table contains the

temperature offsets. The offsets are added to the base temperature to determine the true temperature to be used

for each table entry for auto fan control.

Register D4h–DFh Lookup Table Steps—LUT 1/2 and LUT 3/4 Offset Temperature

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Step 2

Temp

Offset

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

R/W

LUT3/4_STEP2

LUT3/4_STEP3

LUT3/4_STEP4

LUT3/4_STEP5

LUT3/4_STEP6

LUT3/4_STEP7

LUT3/4_STEP8

LUT3/4_STEP9

LUT3/4_STEP10

LUT3/4_STEP11

LUT3/4_STEP12

LUT1/2_STEP2

LUT1/2_STEP3

LUT1/2_STEP4

LUT1/2_STEP5

LUT1/2_STEP6

LUT1/2_STEP7

LUT1/2_STEP8

LUT1/2_STEP9

LUT1/2_STEP10

LUT1/2_STEP11

LUT1/2_STEP12

00h

Step 3

Temp

Offset

Step 4

Temp

Offset

Step 5

Temp

Offset

Step 6

Temp

Offset

Step 7

Temp

Offset

Step 8

Temp

Offset

Step 9

Temp

Offset

Step 10

Temp

Offset

Step 11

Temp

Offset

Step 12

Temp

Offset

92

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Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Step 13

Temp

DFh

R/W

LUT3/4_STEP13

LUT1/2_STEP13

00h

Offset

There are two look up tables of 13 steps (12 offsets), one for LUT 1 and 2 the other for LUT 3 and 4. Each 8-bit

offset register contains the offset temperature for LUT 1 and 2 as well as the offset temperature for LUT 3 and 4.

The format for the offsets is a 4-bit unsigned value, and one LSB is either 1°C or 0.5°C. The offset resolution is

controlled by LT34_RS and LT12_RS bits found in the Special Function Control 2 register (at address BDh).

Therefore, the offset range is variable as well and is either 15°C to 0°C or 7.5°C to 0°C.

See the FAN CONTROL section for information on how the base temperature/lookup table should be used for

controlling the PWM output(s).

Register E0h Special Function TACH to PWM Binding

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Special

Function

TACH to

PWM

T4P1

T3P2

T3P1

T2P2

T2P1

T1P2

T1P1

E0h

R/W

T4P2

00h

Binding

Bit

0

Name

R/W

Description

T1P1

T1P2

T2P1

T2P2

T3P1

T3P2

T4P1

T4P2

If set, TACH1 is bound to PWM1.

If set, TACH1 is bound to PWM2.

If set, TACH2 is bound to PWM1.

If set, TACH2 is bound to PWM2.

If set, TACH3 is bound to PWM1.

If set, TACH3 is bound to PWM2.

If set, TACH4 is bound to PWM1.

If set, TACH4 is bound to PWM2.

1

2

3

4

5

6

7

If a TACH channel is bound to a PWM channel, TACH errors on that channel are automatically masked when the

bound PWM is at 0% duty cycle or performing spin-up. Behavior is undefined if a TACH channel is bound to both

PWM outputs. This register must be setup when Smart Tach Mode is enabled in register BDh, Special Function

Control 2, and when Tach Boost is enabled in register E1h, Tachometer Fan Boost Cotrol.

Register E1h Tachometer Fan Boost Control Register

Register Read/

Default

Value

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

E1h

R/W

Tach Fan Boost Control

RES

TBS

TBT[5:0]

3Fh

Lock

X

Bit

Name

R/W

Description

5:0

TBT[5:0]]

R/W

TACH error fan boost enable timeout. Set to 63 (3Fh) to disable the

TACH error fan boost feature (default). Values other than 63 enable

the TACH error fan boost feature and set the timeout according to

the following table.

6

7

TBS

RES

TACH boost status: When set, this bit indicates that the TACH error

boost has been triggered and is currently requesting 100% PWM. If

bits [5:0] are configured for an infinite timeout, and the TACH error(s)

have ceased, then writing a zero to this bit will un-trigger the TACH

boost. If TACH error boost is disabled, this bit always returns a 0.

R

Reserved

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Table 16. Timeout Assignments for TBT[5:0]

TBT[5:0]

Timeout/Function

0

1

0

3

·

N

N * 32 * 0.091 sec

60

61

62

63

175

178

Infinite setting (software must clear bit 6 of this register to reset)

Disabled

Register E2h LM94 Status Control

Register Read/

Address Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LM94 Status/

Control

BMC

_ERR

HOST

_ERR

TACH_EDGE

GPI5_A GPI4_AM

M

ASF

OVRID

E2h

R/W

00h

Lock

X

Bit

0

Name

OVRID

ASF

R/W

Description

If this bit is set, all PWM outputs go to 100% duty cycle.

1

If this bit is set, BMC error registers support ASF, i.e. reset on read. When

not in ASF mode, a write “1” is required to clear the bits in the BMC error

status registers.

2

GPI4_AM

R/W

GPI4 Auto Mask Enable

If this bit is set, an error event on GPI4 causes all other error events to be

masked.

The BMC Error Status registers do not reflect any new error events until the

GPI4_ERR bit is cleared in the B_GPI Error Status register. The HOST Error

Status registers do not reflect any new error events until the GPI4_ERR bit

is cleared in the H_GPI Error Status register.

If a CPU_THERMTRIP signal is connected to GPIO4, this ensures that

unwanted error events do not fire once CPU_THERMTRIP is asserted.

3

5:4

6

GP15_AM

R/W

R

GPI5 Auto Mask Enable

This bit works exactly the same as GPI4_AM, but applies to GPI5.

TACH_EDGE

HOST_ERR

BMC_ERR

This field determines what type of edges are used for measuring fan tach

pulses. This effects all four tachometer inputs.

This bit gets set if any error bit is set in any of the Host Error Status registers

(H_).

7

R

This bit gets set if any error bit is set in any of the BMC Error Status

registers (B_). When this bit is set, ALERT are asserted if enabled.

Edge Type Used for

Tachometer Measurements

TACH_EDGE

0h

1h

2h

3h

Either rising or falling edges may be used.

Rising edges only

Falling edges only

Reserved

94

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Register E3h LM94 Configuration

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LM94

Configura READY

tion

RES

ALERT_

COMP_E PROCHO

P1P2_

ALERT

_EN

GMSK

LOCK

START

E3h

R/W

00h

N

T

Lock

x

Bit

Name

R/W

Description

0

START

R/W

When this bit is 0, the LM94 operates in basic mode. All error events are

masked. The auto fan control algorithm is disabled. Both PWMs are set to

0%. All monitoring functions are active and the value registers are updated.

Once this bit is set, error events are no longer globally masked, and the

auto-fan control algorithm is enabled. Fan boost uses the programmed

values.

It is expected that all limit and setup registers are set by BIOS or application

software prior to setting this bit.

X

1

2

LOCK

R/W

Setting this bit locks all registers and register bits that are indicated as

lockable. Lockable registers have an “x” in the Lock column of their

description. This register is locked once it is set. This bit can only be cleared

by an external device asserting RESET.

GMSK

Global Mask

When this bit is set by software, all error events are masked. Setting this bit

does not effect any other mask registers or value registers.

3

4

ALERT_EN

R/W

When this bit is set, the ALERT output is enabled. If this bit is cleared, the

ALERT output is disabled.

P1P2_

PROCHOT

In some configurations it may be required to have both processors throttling

at the same rate. When this bit is set, the LM94 connects P1_PROCHOT to

P2_PROCHOT. If P1_PROCHOT and P2_PROCHOT are already shorted

by some other means, this bit should NOT be set. Doing so would cause

both PROCHOT signals to be stuck low until this bit is cleared.

5

ALERT_

COMP_EN

R/W

When this bit is set the ALERT output will function in the thermal comparator

mode. In the thermal comparator mode ALERT will be asserted only for

unmasked thermal error events. ALERT will be de-assserted immediately

when the error event ceases.

6

7

RES

R/W

R

Reserved

READY

The LM94 sets this bit automatically after valid data has been collected for

all temperatures and voltages. Software should not use any temperature or

voltage values until this bit has been set.

SLEEP STATE CONTROL AND MASK REGISTERS

Register E4h Sleep State Control

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sleep

State

SB

E4h

R/W

RES

03h

Control

Bit

Name

R/W

Description

1:0

SB

R/W

Sleep State Control. Setting this field tells the LM94 which sleep state the system is

in. Several error events are masked depending on the state of this field.

7:2

RES

R

Reserved

SB

Description

00

Sleep state = S0

Do not mask errors.

01

Sleep state = S1

Mask errors according to S1 mask registers and standard S1 masking.

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SB

Description

10

Sleep state = S3

Mask errors according to S3 mask registers and standard S3 masking.

11

Sleep state = S4/5

Mask errors according to S4/5 mask registers and standard S4/5 masking.

This mode is activated automatically if the RESET input is asserted.

Register E5h S1 GPI Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S1 GPI

Mask

GPI7_S1 GPI6_S1 GPI5_S1 GPI4_S1 GPI3_S1 GPI2_S1 GPI1_S1 GPI0_S1

E5h

R/W

FFh

_MSK

Bit

0

Name

R/W

Description

GPI0_S1_MSK

GPI1_S1_MSK

GPI2_S1_MSK

GPI3_S1_MSK

GPI4_S1_MSK

GPI5_S1_MSK

GPI6_S1_MSK

GPI7_S1_MSK

If set, GPI0 errors are masked in S1 sleep state.

If set, GPI1 errors are masked in S1 sleep state.

If set, GPI2 errors are masked in S1 sleep state.

If set, GPI3 errors are masked in S1 sleep state.

If set, GPI4 errors are masked in S1 sleep state.

If set, GPI5 errors are masked in S1 sleep state.

If set, GPI6 errors are masked in S1 sleep state.

If set, GPI7 errors are masked in S1 sleep state.

1

2

3

4

5

6

7

Register E6h S1 Tach Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TACH4_ TACH3_ TACH2_ TACH1_

S1 Tach

Mask

E6h

R/W

RES

S1

0Fh

_MSK

Bit

0

Name

R/W

Description

TACH1_S1_MSK

TACH2_S1_MSK

TACH3_S1_MSK

TACH4_S1_MSK

RES

R/W

R

If set, Tach1 errors are masked in S1 sleep state.

If set, Tach2 errors are masked in S1 sleep state.

If set, Tach3 errors are masked in S1 sleep state.

If set, Tach4 errors are masked in S1 sleep state.

Reserved

1

2

3

7:4

Register E7h S3 GPI Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S3 GPI

Mask

GPI7_S3 GPI6_S3 GPI5_S3 GPI4_S3 GPI3_S3 GPI2_S3 GPI1_S3 GPI0_S3

E7h

R/W

FFh

_MSK

Bit

0

Name

R/W

Description

GPI0_S3_MSK

GPI1_S3_MSK

GPI2_S3_MSK

GPI3_S3_MSK

GPI4_S3_MSK

GPI5_S3_MSK

GPI6_S3_MSK

If set, GPI0 errors are masked in S3 sleep state.

If set, GPI1 errors are masked in S3 sleep state.

If set, GPI2 errors are masked in S3 sleep state.

If set, GPI3 errors are masked in S3 sleep state.

If set, GPI4 errors are masked in S3 sleep state.

If set, GPI5 errors are masked in S3 sleep state.

If set, GPI6 errors are masked in S3 sleep state.

1

2

3

4

5

6

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Bit

Name

R/W

Description

If set, GPI7 errors are masked in S3 sleep state.

7

GPI7_S3_MSK

R/W

Register E8h S3 Tach Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TACH4_ TACH3_ TACH2_ TACH1_

S3 Tach

Mask

E8h

R/W

RES

S3

0Fh

_MSK

Bit

0

Name

R/W

Description

TACH1_S3_MSK

TACH2_S3_MSK

TACH3_S3_MSK

TACH4_S3_MSK

RES

R/W

R

If set, Tach1 errors are masked in S3 sleep state.

If set, Tach2 errors are masked in S3 sleep state.

If set, Tach3 errors are masked in S3 sleep state.

If set, Tach4 errors are masked in S3 sleep state.

Reserved

1

2

3

7:4

Register E9h S3 Temperature/Voltage Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S3

TEMP_

AIN14_S AIN13_S AIN12_S

E9h

R/W

Voltage

Mask

RES

S3_MSK

3

07h

_MSK

Bit

0

Name

R/W

Description

AIN12_S3_MSK

AIN13_S3_MSK

AIN14_S3_MSK

TEMP_S3_MSK

If set, AIN12 errors as masked in S3 sleep state.

If set, AIN13 errors as masked in S3 sleep state.

If set, AIN14 errors as masked in S3 sleep state.

1

2

3

If set, temperature errors and diode fault errors for zones 1 and 2 are masked in S3

sleep state.

7:3

RES

R

Reserved

Register EAh S4/5 GPI Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPI7

_S4/5

_MSK

GPI6

_S4/5

_MSK

GPI5

_S4/5

_MSK

GPI4

_S4/5

_MSK

GPI3

_S4/5

_MSK

GPI2

_S4/5

_MSK

GPI1

_S4/5

_MSK

GPI0

_S4/5

_MSK

S4/5 GPI

Mask

EAh

R/W

FFh

Bit

0

Name

R/W

Description

GPI0_S4/5_MSK

GPI1_S4/5_MSK

GPI2_S4/5_MSK

GPI3_S4/5_MSK

GPI4_S4/5_MSK

GPI5_S4/5_MSK

GPI6_S4/5_MSK

GPI7_S4/5_MSK

R/W

If set, GPI0 errors are masked in S4/5 sleep state.

If set, GPI1 errors are masked in S4/5 sleep state.

If set, GPI2 errors are masked in S4/5 sleep state.

If set, GPI3 errors are masked in S4/5 sleep state.

If set, GPI4 errors are masked in S4/5 sleep state.

If set, GPI5 errors are masked in S4/5 sleep state.

If set, GPI6 errors are masked in S4/5 sleep state.

If set, GPI7 errors are masked in S4/5 sleep state.

1

2

3

4

5

6

7

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Register EBh S4/5 Temperature/Voltage Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S4/5

Voltage

Mask

TEMP_

S4/5_MS

K

AIN14_S AIN13_S AIN12_S

EBh

R/W

RES

4/5

07h

_MSK

Bit

0

Name

R/W

Description

AIN12_S4/5_MSK

AIN13_S4/5_MSK

AIN14_S4/5_MSK

TEMP_S4/5_MSK

R/W

If set, AIN12 errors as masked in S4/5 sleep state.

If set, AIN13 errors as masked in S4/5 sleep state.

If set, AIN14 errors as masked in S4/5 sleep state.

1

2

3

If set, temperature errors and diode fault errors for zones 1 and 2 are masked in

S4/5 sleep state.

7:3

RES

R

Reserved

OTHER MASK REGISTERS

Register ECh GPI Error Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPI Error

Mask

GPI7

_MSK

GPI6

_MSK

GPI5

_MSK

GPI4

_MSK

GPI3

_MSK

GPI2

_MSK

GPI1

_MSK

GPI0

_MSK

ECh

R/W

FFh

Bit

0

Name

R/W

Description

GPI0_MSK

GPI1_MSK

GPI2_MSK

GPI3_MSK

GPI4_MSK

GPI5_MSK

GPI6_MSK

GPI7_MSK

When this bit is set, GPI0 error events are masked.

When this bit is set, GPI1 error events are masked.

When this bit is set, GPI2 error events are masked.

When this bit is set, GPI3 error events are masked.

When this bit is set, GPI4 error events are masked.

When this bit is set, GPI5 error events are masked.

When this bit is set, GPI6 error events are masked.

When this bit is set, GPI7 error events are masked.

1

2

3

4

5

6

7

These bits mask the corresponding bits in the B_ and H_GPI Error Status Registers. They do not effect the GPI

State register.

Register EDh Miscellaneous Error Mask

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Miscellan

eous

Error

DVccp2

_MSK

DVccp1

_MSK

SCSI2

_MSK

SCSI1

_MSK

VRD2

_MSK

VRD1

_MSK

EDh

R/W

RES

3Fh

Mask

Bit

0

Name

R/W

Description

VRD1_MSK

VRD2_MSK

SCSI1_MSK

SCSI2_MSK

DVccp1_MSK

DVccp2_MSK

RES

R/W

R

When this bit is set, VRD1_HOT error events are masked.

When this bit is set, VRD2_HOT error events are masked.

When this bit is set, GPI8 error events are masked.

When this bit is set, GPI9 error events are masked.

1

2

3

4

When this bit is set, dynamic Vccp limit error events for AD_IN7 (CPU1) are masked.

When this bit is set, dynamic Vccp limit error events for AD_IN8 (CPU2) are masked.

Reserved

5

7:6

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Register EE and EFh Zone 1a and Zone 2a Adjustment Register

Register

Address

Read/

Write

Register

Name

Default

Value

Bit 7

RES

Bit 6

RES

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Zone 1a

Adjust

EEh

EFh

R/W

Z1a_ADJUST[5:0]

Z2a_ADJUST[5:0]

00h

Zone 2a

Adjust

00h

Bit

Name

R/W

Description

5:0

Z1a_ADJUST[5:0] or

Z2a_ADJUST[5:0]

R/W

6-bit signed 2’s complement offset adjustment. This value is added to all zone

1a and 2a temperature measurements as they are made. All LM94 registers

and functions behave as if the resulting temperature was the true measured

temperature. This register allows offset adjustments from +31°C to −32°C in

1°C steps. The format is sign two's complement.

7:6

RES

R

Reserved

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1)(2)(3)

Absolute Maximum Ratings

Positive Supply Voltage (V_DD

)

6.0V

Voltage on Any Digital Input or

Output Pin

−0.3V to 6.0V

Voltage on +5V Input

−0.3V to +6.667V

Voltage at Positive Remote

Diode Inputs, AD_IN1, AD_IN2,

AD_IN3, and AD_IN15 Inputs

−0.3V to (V_DD+ 0.05V)

−0.3V to +6.0V

Voltage at Other Analog Voltage

Inputs

Input Current at Thermal Diode

Negative Inputs

±1 mA

±10mA

(4)

Input Current at any pin

(4)

Package Input Current

±100 mA

(5)

Maximum Junction Temperature

(T_JMAX

)

150 °C

3 kV

(6)

ESD Susceptibility

Human Body Model

Machine Model

300V

Charged Device Model

750V

Storage Temperature⁽⁷⁾

For soldering specifications, see product folder at www.ti.com/packaging and SNOA549⁽⁸⁾

−65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise noted.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4) When the input voltage (V_IN) at any pin exceeds the power supplies (V_IN< (GND or AGND) or V_IN> V_DD, except for analog voltage

inputs), the current at that pin should be limited to 10 mA. The 100 mA maximum package input current rating limits the number of pins

that can safely exceed the power supplies with an input current of 10 mA to ten. Parasitic components and/or ESD protection circuitry

are shown below for the LM94’s pins. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D− as

shown in circuits C and D. Doing so by more than 50 mV may corrupt temperature measurements. D1 and the ESD Clamp are

connected between V+ (V_DD, AD_IN16) and GND as shown in circuit B. SNP stands for snap-back device.

(5) Typical parameters are at T_J= T_A= 25 °C and represent most likely parametric norm.

(6) Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. Charged

device model (CDM) simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated

assembler) then rapidly being discharged.

(7) Reflow temperature profiles are different for lead-free and non lead-free packages.

(8) See the URL "www.ti.com/packaging" for other recommendations and methods of soldering surface mount devices.

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(1)(2)

Operating Ratings

T_MIN≤ T_A≤ T_MAX

Operating Temperature Range

Nominal Supply Voltage

0°C ≤ T_A≤ +85°C

3.3V

Supply Voltage Range (V_DD

)

+3.0V to +3.6V

−0.05V to +5.5V

−0.05V to (V_DD+ 0.05V)

79°C/W

VID0-VID5

Digital Input Voltage Range

Package Thermal Resistance

(3)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise noted.

(3) The maximum power dissipation must be de-rated at elevated temperatures and is dictated by T_JMAX, θ_JAand the ambient temperature,

T_A. The maximum allowable power dissipation at any temperature is P_{D MAX}= (T_JMAX− T_A) / θ_JA. The θ_JAfor the LM94 when mounted to

1 oz. copper foil PCB the θ_JAwith different air flow is listed in the following table.

Air Flow

0 m/s

Junction to Ambient Thermal Resistance, θ_JA

79 °C/W

62 °C/W

52 °C/W

1.14 m/s (225 LFPM)

2.54 m/s (500 LFPM)

DC Electrical Characteristics

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_Jover T_MINto

T_MAXof the operating range; all other limits T_A= T_J= 25°C unless otherwise noted. T_Ais the ambient temperature of the

LM94; T_Jis the junction temperature of the LM94; T_Dis the junction temperature of the thermal diode.

Typical

Limits

Units

(Limits)

Parameter

Test Conditions

(1)

(2)

POWER SUPPLY CHARACTERISTICS

Power Supply Current

Converting, Interface and

Fans Inactive, Peak Current

2

2.75

mA (max)

mA

Converting, Interface and

Fans Inactive, Average

Current

1.6

Power-On Reset Threshold Voltage

1.6

2.7

V (min)

V (max)

2

TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS

Local Temperature Accuracy Over Full Range

0°C ≤ T_A≤ 85°C

±2

±1

1

±3

°C (max)

°C

T_A= +55°C

±2.5

Local Temperature Resolution

Remote Thermal Diode Temperature Accuracy Over

Full Range; targeted for a typical Pentium processor

on 90 nm or 65 nm process⁽³⁾

0°C ≤ T_A≤ 85°C

and 0°C ≤ T_D≤ 100°C

±3

°C (max)

0°C ≤ T_A≤ 85°C

and T_D=70°C

±2.5

Remote Thermal Diode Temperature Accuracy;

targeted for a typical Pentium processor on 90nm or

65nm process

0°C ≤ T_A≤ 85°C

and 25°C ≤ T_D≤ 70°C

±1

°C

(3)

Remote Temperature Resolution

Thermal Diode Source Current

1

°C

µA (max)

µA

High Level

Low Level

172

230

10.75

(1) Typical parameters are at T_J= T_A= 25 °C and represent most likely parametric norm.

(2) Limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level).

(3) At the time of first pubication of this specification (Jan 2006), this specification applies to either Pentium or Xeon Processors on 90nm or

65nm process when TruTherm is selected. When TruTherm is deselected this specification applies to an MMBT3904. This specification

does include the error caused by the variability of the diode ideality and series resistance parameters.

100

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DC Electrical Characteristics (continued)

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_Jover T_MINto

T_MAXof the operating range; all other limits T_A= T_J= 25°C unless otherwise noted. T_Ais the ambient temperature of the

LM94; T_Jis the junction temperature of the LM94; T_Dis the junction temperature of the thermal diode.

Typical

Limits

Units

(Limits)

Parameter

Test Conditions

(1)

(2)

Thermal Diode Current Ratio

Total Monitoring Cycle Time

16

T_C

100

±2

ms (max)

ANALOG-TO-DIGITAL VOLTAGE MEASUREMENT CONVERTER CHARACTERISTICS

(4)(5)

TUE

Total Unadjusted Error

% of FS

(max)

DNL

PSS

Differential Non-Linearity

±1

LSB

Power Supply (V_DD) Sensitivity

%/V (of

FS)

T_C

Total Monitoring Cycle Time

100

140

ms (max)

Input Resistance for Inputs with Dividers

AD_IN1- AD_IN3 and AD_IN15 Analog Input Leakage

200

kΩ (min)

60

nA (max)

(6)

Current

REFERENCE OUTPUT (V_REF) CHARACTERISTICS

Tolerance

±1

% (max)

(7)

V_REF

Output Voltage

2.525

2.475

V (max)

V (min)

2.500

0.1

Load Regulation

I_SOURCE= −2 mA

I_SINK= 2 mA

%

DIGITAL OUTPUTS: PWM1, PWM2

I_OL

Maximum Current Sink

Output Low Voltage

8

mA (min)

V (max)

V_OL

I_OUT= 8.0 mA

0.4

DIGITAL OUTPUTS: ALL

V_OL

Output Low Voltage (Note excessive current flow

causes self-heating and degrades the internal

temperature accuracy.)

I_OUT= 4.0 mA

I_OUT= 6 mA

0.4

0.55

10

V (min)

I_OH

High Level Output Leakage Current

V_OUT= V_DD

0.1

20

µA (max)

I_OTMAX

Maximum Total Sink Current for all Digital Outputs

Combined

32

mA (max)

pF

C_O

Digital Output Capacitance

DIGITAL INPUTS: ALL

V_IH

V_IL

V_IH

V_IM

Input High Voltage Except Address Select⁽⁸⁾

2.1

0.8

V (min)

V (max)

V (min)

Input Low Voltage Except Address Select⁽⁸⁾

Input High Voltage for Address Select⁽⁸⁾

Input Mid Voltage for Address Select

90% V_DD

43% V_DD

57% V_DD

V (min)

V (max)

V_IL

Input Low Voltage for Address Select⁽⁸⁾

DC Hysteresis

10% V_DD

V (max)

V

V_HYST

I_IH

0.3

20

Input High Current

V_IN= V_DD

V_IN= 0V

−10

µA (min)

µA (max)

pF

I_IL

Input Low Current

10

C_IN

Digital Input Capacitance

DIGITAL INPUTS: P1_VIDx, P2_VIDx, GPI_9, GPI_8, GPIO_7, GPIO_6, GPIO_5, GPIO_4 (When respective bit set in Register BEh

GPI/VID Level Control)

V_IH

Alternate Input High Voltage (AGTL+ Compatible)

0.8

V (min)

(4) Total Monitoring Cycle Time includes all temperature and voltage conversions.

(5) TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.

(6) Leakage current approximately doubles every 20 °C.

(7) A total digital I/O current of 40 mA can cause 6 mV of offset in Vref.

(8) Timing specifications are tested at the TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge. TRI-STATE output

voltage is forced to 1.4V.

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DC Electrical Characteristics (continued)

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_Jover T_MINto

T_MAXof the operating range; all other limits T_A= T_J= 25°C unless otherwise noted. T_Ais the ambient temperature of the

LM94; T_Jis the junction temperature of the LM94; T_Dis the junction temperature of the thermal diode.

Typical

Limits

Units

(Limits)

Parameter

Test Conditions

(1)

(2)

V_IL

Alternate Input Low Voltage (AGTL+ Compatible)

0.4

V (max)

AC Electrical Characteristics

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_J= T_MINto T_MAX

of the operating range; all other limits T_A= T_J= 25°C unless otherwise noted.

Typical

Limits

Units

(Limits)

Parameter

Test Conditions

(1)

(2)

FAN RPM-TO-DIGITAL CHARACTERISTICS

Counter Resolution

14

2

bits

Number of fan tach pulses count is based

pulses

on

Counter Frequency

22.5

kHz

Accuracy

±6

% (max)

PWM OUTPUT CHARACTERISTICS

Frequency Tolerances

±6

% (max)

Duty-Cycle Tolerance

±2

RESET INPUT/OUTPUT CHARACTERISTICS

Output Pulse Width

Upon Power Up

250

330

ms (min)

ms (max)

Minimum Input Pulse Width

Reset Output Fall Time

10

1

µs (min)

µs (max)

1.6V to 0.4V Logic Levels

SMBus TIMING CHARACTERISTICS

f_SMBCLK

SMBCLK (Clock) Clock Frequency

10

100

kHz (min)

kHz (max)

t_BUF

SMBus Free Time between Stop and

Start Conditions

4.7

4.0

µs (min)

t_HD;STA

Hold time after (Repeated) Start

Condition. After this period, the first clock

is generated.

µs (min)

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;DAT

Repeated Start Condition Setup Time

Stop Condition Setup Time

4.7

4.0

250

µs (min)

ns (min)

Data Input Setup Time to SMBCLK High

Data Output Hold Time after SMBCLK

Low

300

1075

ns (min)

ns (max)

t_LOW

t_HIGH

SMBCLK Low Period

4.7

50

µs (min)

µs (max)

SMBCLK High Period

4.0

50

µs (min)

µs (max)

t_R

Rise Time

Fall Time

1

µs (max)

ns (max)

t_F

300

t_TIMEOUT

Timeout

31

ms

SMBDAT or SMBCLK low

time required to

25

35

ms (min)

ms (max)

reset the Serial Bus

Interface to the Idle State

t_POR

Time in which a device must be

operational after power-on reset

V_DD> +2.8V

500

ms (max)

(1) Typical parameters are at T_J= T_A= 25 °C and represent most likely parametric norm.

(2) Limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level).

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AC Electrical Characteristics (continued)

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_J= T_MINto T_MAX

of the operating range; all other limits T_A= T_J= 25°C unless otherwise noted.

Typical

Limits

Units

(Limits)

Parameter

Test Conditions

(1)

(2)

C_L

Capacitance Load on SMBCLK and

SMBDAT

400

pF (max)

t_LOW

t_R

t_F

V_IH

SMBCLK _V

IL

t_HD;STA

t_HD;DAT

t_SU;STA

t_HIGH

t_SU;STO

t_BUF

t_SU;DAT

V_IH

V_IL

SMBDAT

P

S

P

Symbol

Pin No.

Circuit

All Input Circuits

GPIO_0/TACH1

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

1

2

A

D1

SNP

3

4

GND

GPIO_4 / P1_THERMTRIP

GPIO_5 / P2_THERMTRIP

GPIO_6

5

Figure 13. Circuit A

6

7

GPIO_7

8

VRD1_HOT

9

VRD2_HOT

10

11

12

13

14

15

16

17

SCSI_TERM1

SCSI_TERM2

SMBDAT

V+

160 k

80 k

D2

D3

SMBCLK

ESD

Clamp

D1

6.5V

ALERT/XtestOut

RESET

GND

AGND

B (Internally

shorted to

GND pin.)

Figure 14. Circuit B

V_REF

18

19

20

21

22

A

C

D

C

D

REMOTE1–

REMOTE1+

REMOTE2–

REMOTE+

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Symbol

AD_IN1

Pin No.

23

Circuit

All Input Circuits

D

E

D

A

B

V+

AD_IN2

24

D2

AD_IN3

25

ESD

CLAMP

AD_IN4

26

D3

D1

6.5V

AD_IN5

27

GND

AD_IN6

28

Figure 15. Circuit C

AD_IN7

29

AD_IN8

30

AD_IN9

31

AD_IN10

32

AD_IN11

33

AD_IN12

34

50W

AD_IN13

35

AD_IN14

36

D1

SNP

AD_IN15

37

GND

ADDR_SEL

AD_IN16/V_DD(V+)

GND

38

Figure 16. Circuit D

39

40

B (Internally

shorted to

AGND)

PWM1

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

A

PWM2

P1_VID0

P1_VID1

P1_VID2

P1_VID3

P1_VID4

P1_VID5

P1_PROCHOT

P2_PROCHOT

P2_VID0

P2_VID1

P2_VID2

P2_VID3

P2_VID4

P2_VID5

R1

R2

SNP

D1

GND

Figure 17. Circuit E

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REVISION HISTORY

Changes from Revision B (March 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................ 105

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PACKAGE OUTLINE

DGG0056A

TSSOP - 1.2 mm max height

S

C

A

L

E

1

.

2

0

SMALL OUTLINE PACKAGE

C

8.3

7.9

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

54X 0.5

56

1

14.1

13.9

NOTE 3

2X

13.5

28

B

29

0.27

0.17

6.2

6.0

56X

1.2 MAX

0.08

C A

B

(0.15) TYP

0.25

GAGE PLANE

0 - 8

SEE DETAIL A

0.15

0.05

0.75

0.50

DETAIL A

TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05)

TYP

SYMM

28

29

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

METAL

SOLDER MASK

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05) TYP

SYMM

28

29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4222167/A 07/2015

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM94CIMTX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 β 补偿、风扇控制、硬件和电源监控器、采用 TSSOP 封装的 ±2°C 四路远程和本地温度传感器 \| DGG \| 56 \| 0 to 100 温度传感监控光电二极管风扇传感器温度传感器
文件：	总114页 (文件大小：1450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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