LM96000CIMTX/NOPB [TI]
硬件监控器，带风扇控制功能和 6 个电源电压监控器 | PW | 24 | 0 to 125;
| 型号： | LM96000CIMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 硬件监控器，带风扇控制功能和 6 个电源电压监控器 | PW | 24 | 0 to 125 监控 光电二极管 风扇 |
| 文件： | 总43页 (文件大小：1292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM96000
www.ti.com
SNAS234C –APRIL 2004–REVISED MARCH 2013
LM96000 Hardware Monitor with Integrated Fan Control
Check for Samples: LM96000
1
FEATURES
KEY SPECIFICATIONS
2
•
2-wire, SMBus 2.0 Compliant, Serial Digital
Interface
•
•
•
•
Voltage Measurement Accuracy ±2% FS (max)
Resolution 8-bits, 1°C
•
•
8-bit ΣΔ ADC
Temperature Sensor Accuracy ±3°C (max)
Temperature Range
Monitors VCCP, 2.5V, 3.3 VSBY, 5.0V, and 12V
Motherboard/processor Supplies
–
–
LM96000 Operational 0°C to +85°C
•
•
Monitors 2 Remote Thermal Diodes
Remote Temp Accuracy 0°C to +125°C
Programmable Autonomous Fan Control
Based on Temperature Readings
•
•
Power Supply Voltage +3.0V to +3.6V
Power Supply Current 0.53 mA
•
Noise Filtering of Temperature Reading for
Fan Control
DESCRIPTION
The LM96000, hardware monitor, has a two wire
digital interface compatible with SMBus 2.0. Using an
8-bit ΣΔ ADC, the LM96000 measures:
•
•
•
1.0°C Digital Temperature Sensor Resolution
3 PWM Fan Speed Control Outputs
Provides High and Low PWM Frequency
Ranges
•
the temperature of two remote diode connected
transistors as well as its own die
the VCCP, 2.5V, 3.3VSBY, 5.0V, and 12V
supplies (internal scaling resistors).
•
•
•
•
4 Fan Tachometer Inputs
Monitors 5 VID Control Lines
24-pin TSSOP Package
XOR-tree Test Mode
•
To set fan speed, the LM96000 has three PWM
outputs that are each controlled by one of three
temperature zones. High and low PWM frequency
ranges are supported. The LM96000 includes a
digital filter that can be invoked to smooth
temperature readings for better control of fan speed.
The LM96000 has four tachometer inputs to measure
fan speed. Limit and status registers for all measured
values are included.
APPLICATIONS
•
•
Desktop PC
Microprocessor based equipment
–
(e.g. Base-stations, Routers, ATMs, Point of
Sales)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM96000
SNAS234C –APRIL 2004–REVISED MARCH 2013
www.ti.com
Block Diagram
SMBDAT
SMBCLK
SERIAL BUS
INTERFACE
VID0
VID1
VID2
VID3
VID4
VID0-4
REGISTER
VOLTAGE, FAN SPEED,
TEMPERATURE, AND
LIMIT VALUE REGISTERS
TACH1
TACH2
FAN SPEED
COUNTER
LIMIT COMPARATORS
STATUS REGISTERS
TACH3
TACH4/
Address Select
VDD
STEPPING AND
DEVICE ID
REGISTERS
3.3SBY
5VIN
CONFIGURATION
REGISTERS
PWM1
PWM2
ADDRESS
POINTER
REGISTER
12VIN
SPIKE SMOOTHING
2.5VIN
VCCP_IN
INPUT
ATTENUATORS,
EXTERNAL DIODE
SIGNAL
CONDITIONING,
AND
FAN TMIN/TRANGE/
HYST REGISTERS
REMOTE1+
REMOTE1-
8-bit
SD ADC
FAN CHARACTERISTICS
REMOTE2-
REMOTE2+
PWM3/
Address
Enable
FAN SPEED CONFIG.
REGISTERS
ANALOG
MULTIPLEXER
BANDGAP
REFERENCE
FAN PWM CONTROL
& PWM VALUE
REGISTERS
INTERNAL
TEMP
SENSOR
Connection Diagram
Top View
SMBDAT
1
24
23
22
21
20
19
18
17
16
15
14
13
PWM1/xTESTOUT
SMBCLK
GND
2
VCCP_IN
2.5V
3
3.3V
4
12V
VID0
5
5V
LM96000
VID1
6
VID4
VID2
7
REMOTE1+
REMOTE1-
REMOTE2+
REMOTE2-
TACH4/AddSel
PWM3/AddEnable
VID3
8
TACH3
PWM2
TACH1
TACH2
9
10
11
12
Figure 1. 24-Pin TSSOP Package
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SNAS234C –APRIL 2004–REVISED MARCH 2013
Pin Descriptions
Name
Pin No.
Type
Name and Function/Connection
SMBDAT
1
Digital I/O
(Open-Drain)
System Management Bus Data. Open-drain output. 5V tolerant, SMBus
2.0 compliant.
SMBus
SMBCLK
VID0
2
5
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
POWER
System Management Bus Clock. Tied to Open-drain output. 5V tolerant,
SMBus 2.0 compliant.
Voltage identification signal from the processor. This value is read in the
VID0–VID4 Status Register.
VID1
6
Voltage identification signal from the processor. This value is read in the
VID0–VID4 Status Register.
Processor
VID Lines
VID2
7
Voltage identification signal from the processor. This value is read in the
VID0–VID4 Status Register.
VID3
8
Voltage identification signal from the processor. This value is read in the
VID0–VID4 Status Register.
VID4
19
4
Voltage identification signal from the processor. This value is read in the
VID0–VID4 Status Register.
3.3V
+3.3V pin. Can be powered by +3.3V Standby power if monitoring in low
power states is required. This pin also serves as the analog input to
monitor the 3.3V supply. This pin should be bypassed with a 0.1µf
capacitor in parallel with 100pf. A bulk capacitance of approximately 10µf
needs to be in the near vicinity of the LM96000.
Power
GND
5V
3
GROUND
Analog Input
Analog Input
Analog Input
Analog Input
Ground for all analog and digital circuitry.
Analog input for +5V monitoring.
20
21
22
23
18
12V
Analog input for +12V monitoring.
Voltage
Inputs
2.5V
Analog input for +2.5V monitoring.
VCCP_IN
Remote1+
Analog input for VCCP (processor voltage) monitoring.
Remote Thermal Positive input (current source) from the first remote thermal diode.
Diode Positive
Input
Serves as the positive input into the A/D. Connected to THERMDA pin of
Pentium processor or the base of a diode connected MMBT3904 NPN
transistor.
Remote1−
Remote2+
Remote2−
17
16
15
Remote Thermal Negative input (current sink) from the first remote thermal diode. Serves
Diode Negative
Input
as the negative input into the A/D. Connected to THERMDC pin of
Pentium processor or the emmiter of a diode connected MMBT3904
NPN transistor.
Remote
Diodes
Remote Thermal Positive input (current source) from the first remote thermal diode.
Diode Positive
Output
Serves as the positive input into the A/D. Connected to THERMDA pin of
Pentium processor or the base of a diode connected MMBT3904 NPN
transistor.
Remote Thermal Negative input (current sink) from the first remote thermal diode. Serves
Diode Negative
Input
as the negative input into the A/D. Connected to THERMDC pin of
Pentium processor or the emmiter of a diode connected MMBT3904
NPN transistor.
TACH1
TACH2
TACH3
11
12
9
Digital Input
Digital Input
Digital Input
Digital Input
Input for monitoring tachometer output of fan 1.
Input for monitoring tachometer output of fan 2.
Input for monitoring tachometer output of fan 3.
Fan
Tachometer
Inputs
TACH4/Address
Select
14
Input for monitoring tachometer output of fan 4. If in Address Select
Mode, determines the SMBus address of the LM96000.
PWM1/xTest Out
24
10
13
Digital Open-Drain Fan speed control 1. When in XOR tree test mode, functions as XOR
Output Tree output.
PWM2
Digital Open-Drain Fan speed control 2.
Output
Fan Control
PWM3/Address
Enable
Digital Open-Drain Fan speed control 3. Pull to ground at power on to enable Address
Output
Select Mode (Address Select pin controls SMBus address of the device).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)(3)
Supply Voltage, V+
−0.5V to 6.0V
−0.5V to 6.0V
Voltage on Any Digital Input or
Output Pin
Voltage on 12V Analog Input
Voltage on 5V Analog Input
−0.5V to 16V
−0.5V to 6.66V
−0.5V to (V+ + 0.05V)
±1 mA
Voltage on Remote1+, Remote2+,
Current on Remote1−, Remote2−
Voltage on Other Analog Inputs
−0.5V to 6.0V
±5 mA
(4)
Input Current on Any Pin
(4)
Package Input Current
±20 mA
(5)
Package Dissipation at TA = 25°C
See
(6)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
Storage Temperature
−65°C to +150°C
Soldering process must comply with reflow temperature profile specifications. See www.ti.com/packaging(7)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND, unless otherwise noted.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(4) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN >V+ ), the current at that pin should be limited to
5mA. The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 5mA to four. Parasitic components and/or ESD protection circuitry are shown below for the LM96000's pins. The nominal
breakdown voltage the zener is 6.5V. Care should be taken not to forward bias the parasitic diode D1 present on pins D+ and D−. Doing
so by more that 50 mV may corrupt temperature measurements. SNP stands for snap-back device.
(5) Thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1 oz. foil is 113 °C/W.
(6) Human body model, 100pF discharged through a 1.5kΩ resistor. Machine model, 200pF discharged directly into each pin.
(7) Reflow temperature profiles are different for packages containing lead (Pb) than for those that do not.
Operating Ratings(1)(2)
LM96000 Operating Temperature Range
Remote Diode Temperature Range
Supply Voltage (3.3V nominal)
VIN Voltage Range
0°C ≤ TA ≤ +85°C
0°C ≤ TD ≤ +125°C
+3.0V to +3.6V
+12V VIN
−0.05V to 16V
−0.05V to 6.66V
3.0V to 4.4V
+5V VIN
+3.3V VIN
VCCP_IN and All Other Inputs
VID0–VID4
−0.05V to (V+ + 0.05V)
−0.05V to 5.5V
0.53 mA
Typical Supply Current
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND, unless otherwise noted.
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DC Electrical Characteristics
The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance RS = 50Ω unless otherwise
specified in conditions. Boldface limits apply for TA = TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C. TA is
the ambient temperature of the LM96000; TJ is the junction temperature of the LM96000; TD is the thermal diode junction
temperature.
Typical
Limits
Units
(Limits)
Parameter
Test Conditions
(1)
(2)
POWER SUPPLY CHARACTERISTICS
(3)
Supply Current
Converting, Interface and
Fans Inactive, Peak Current
1.8
3.5
mA (max)
mA
Converting, Interface and
Fans Inactive, Average
Current
0.53
Power-On Reset Threshold Voltage
1.6
2.8
V (min)
V (max)
TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS
Resolution
1
8
°C
Bits
Temperature Accuracy (See (4) for Thermal Diode
Processor Type)
TD=25°C
±2.5
±3
°C (max)
°C (max)
°C (max)
°C (max)
TD=0°C to 100°C
TD=100°C to 125°C
±1
±1
±4
Temperature Accuracy using Internal Diode. (5) See(6)
for the thermal resistance to be used in the self-
heating calculation.
±3
IDS
External Diode Current Source
High Level
Low Level
188
11.75
16
280
µA (max)
µA
External Diode Current Ratio
ANALOG TO DIGITAL CONVERTER CHARACTERISTICS
TUE
Total Unadjusted Error(7)
±2
%FS
(max)
DNL
Differential Non-linearity
Power Supply Sensitivity
Total Monitoring Cycle Time
1
LSB
%/V
±1
(8)
All Voltage and Temperature
readings
182
200
ms (max)
Input Resistance, all analog inputs
210
140
400
kΩ (min)
kΩ (max)
DIGITAL OUTPUT: PWM1, PWM2, PWM3, XTESTOUT
IOL
Logic Low Sink Current
Logic Low Level
VOL=0.4V
8
mA (min)
V (max)
VOL
IOUT = +8 mA
0.4
(1) Typicals are at TA = 25°C and represent most likely parametric norm.
(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(3) The average current can be calculated from the peak current using the following equation:Quiescent current will not increase
substantially with an SMBus transaction.
(4) The accuracy of the LM96000CIMT is ensured when using the thermal diode of Intel Pentium 4 90nm processors or any thermal diode
with a non-ideality of 1.011 and series resistance of 3.33Ω. When using a 2N3904 type transistor as a thermal diode the error band will
be typically shifted by -?°C.
(5) Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the
internal power dissipation of the LM96000 and the thermal resistance.
(6) Thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1 oz. foil is 113 °C/W.
(7) TUE , total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the "actual Vin" to achieve a
given code transition minus the "theoretical Vin" for the same code. Therefore, a positive error indicates that the input voltage is greater
than the theoretical input voltage for a given code. If the theoretical input voltage was applied to an LM96000 that has positive error, the
LM96000's reading would be less than the theoretical.
(8) This specification is provided only to indicate how often temperature and voltage data is updated. The LM96000 can be read at any time
without regard to conversion state (and will yield last conversion result).
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DC Electrical Characteristics (continued)
The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance RS = 50Ω unless otherwise
specified in conditions. Boldface limits apply for TA = TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C. TA is
the ambient temperature of the LM96000; TJ is the junction temperature of the LM96000; TD is the thermal diode junction
temperature.
Typical
Limits
Units
(Limits)
Parameter
Test Conditions
(1)
(2)
SMBUS OPEN-DRAIN OUTPUT: SMBDAT
VOL
IOH
Logic Low Output Voltage
High Level Output Current
IOUT = +4 mA
0.4V
10
V (max)
VOUT = V+
0.1
µA (max)
SMBUS INPUTS: SMBCLK. SMBDAT
VIH
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Hysteresis Voltage
2.1
0.8
V (min)
V (max)
mV
VIL
VHYST
300
DIGITAL INPUTS: ALL
VIH
VIL
VTH
IIH
Logic Input High Voltage
2.1
0.8
V (min)
V (max)
V
Logic Input Low Voltage
Logic Input Threshold Voltage
Logic High Input Current
Logic Low Input Current
Digital Input Capacitance
1.5
0.005
−0.005
20
VIN = V+
10
µA (max)
µA (max)
pF
IIL
VIN = GND
−10
CIN
AC Electrical Characteristics
The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for
TA = TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C.
Typical
Limits
Units
(Limits)
Parameter
Test Conditions
(1)
(2)
TACHOMETER ACCURACY
Fan Count Accuracy
±10
% (max)
(max)
Fan Full-Scale Count
65536
Fan Counter Clock Frequency
Fan Count Conversion Time
90
kHz
0.7
1.4
sec (max)
FAN PWM OUTPUT
Frequency Setting Accuracy
Frequency Range
±10
% (max)
10
30
Hz
kHz
Duty-Cycle Range
Low frequency range
0 to 100
% (max)
%
Duty-Cycle Resolution (8-bits)
Spin-Up Time Interval Range
0.390625
100
4000
ms
ms
Spin-Up Time Interval Accuracy
±10
±10
% (max)
SPIKE SMOOTHING FILTER
Time Interval Deviation
Time Interval Range
% (max)
35
0.8
sec
sec
(1) Typicals are at TA = 25°C and represent most likely parametric norm.
(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
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AC Electrical Characteristics (continued)
The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for
TA = TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C.
Typical
Limits
Units
(Limits)
Parameter
Test Conditions
(1)
(2)
SMBUS TIMING CHARACTERISTICS
fSMB
SMBus Operating Frequency
10
100
kHz (min)
kHz (max)
fBUF
SMBus Free Time Between Stop And
Start Condition
4.7
µs (min)
tHD_STA
Hold Time After (Repeated) Start
Condition (after this period, the first clock
is generated)
4.0
µs (min)
tSU:STA
tSU:STO
tHD:DAT
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Output Hold Time
4.7
4.0
µs (min)
µs (min)
ns (min)
ns (max)
ns (min)
300
930
250
tSU:DAT
Data Input Setup Time
tTIMEOUT
Data And Clock Low Time To Reset Of
SMBus Interface Logic(3)
25
35
ms (min)
ms (max)
tLOW
tHIGH
Clock Low Period
Clock High Period
4.7
µs (min)
4.0
50
µs (min)
µs (max)
tF
Clock/Data Fall Time
Clock/Data Rise Time
300
1000
500
ns (max)
ns (max)
ms (max)
tR
tPOR
Time from Power-On-Reset to LM96000 V+ > 2.8V
Reset and Operational
(3) Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM96000's SMBus state machine,
therefore setting the SMBDAT pin to a high impedance state.
tLOW
tR
tF
VIH
SMBCLK V
IL
tHD;STA
tHD;DAT
tSU;STA
tHIGH
tSU;STO
tBUF
tSU;DAT
VIH
VIL
SMBDAT
P
S
S
P
Pin
No.
Pin Name
Circuit
All Input Circuits
1
2
3
4
SMBDAT
SMBCLK
GND
A
PIN
D1
SNP
B
3.3V
GND
Figure 2. Circuit A
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Pin
No.
Pin Name
Circuit
All Input Circuits
5
6
7
8
9
VID0
VID1
A
V+
160 k
80 k
D2
VID2
ESD
Clamp
D1
6.5V
VID3
D3
TACH3
GND
Figure 3. Circuit B
10
11
12
13
14
PWM2
TACH1
V+
D3
50W
TACH2
PIN
ESD
CLAMP
PWM3/AddEnable
TACH4/AddSel
D4
D2
D1
6.5V
GND
Figure 4. Circuit C
15
16
17
18
19
REMOTE2−
REMOTE2+
REMOTE1−
REMOTE1+
VID4
C
D
C
D
A
V+
D2
50W
PIN
ESD
CLAMP
D3
D1
SNP
6.5V
GND
Figure 5. Circuit D
20
21
22
23
24
5V
12V
E
A
V+
D2
6.5V
D3
2.5V
PIN
VCCP_IN
PWM1/xTEXTOUT
D1
R1
ESD
Clamp
SNP
R2
GND
Figure 6. Circuit E
FUNCTIONAL DESCRIPTION
1.0 SMBUS
The LM96000 is compatible with devices that are compliant to the SMBus 2.0 specification. More information on
this bus can be found at: http://www.smbus.org/. Compatibility of SMBus2.0 to other buses is discussed in the
SMBus 2.0 specification.
1.1 Addressing
LM96000 is designed to be used primarily in desktop systems that require only one monitoring device.
If only one LM96000 is used on the motherboard, the designer should be sure that the PWM3/Address Enable
pin is High during the first SMBus communication addressing the LM96000. PWM3/Address Enable is an open
drain I/O pin that at power-on defaults to the input state of Address Enable. A maximum of 10k pull-up resistance
on PWM3/Address Enable is required to assure that the SMBus address of the device will be locked at 010
1110b, which is the default address of the LM96000.
During the first SMBus communication TACH4 and PWM3 can be used to change the SMBus address of the
LM96000 to 0101101b or 0101100b. LM96000 address selection procedure:
•
A 10 kΩ pull-down resistor to ground on the PWM3/Address Enable pin is required. Upon power up, the
LM96000 will be placed into Address Enable mode and assign itself an SMBus address according to the state
of the Address Select input. The LM96000 will latch the address during the first valid SMBus transaction in
which the first five bits of the targeted address match those of the LM96000 address, 0 1011b. This feature
eliminates the possibility of a glitch on the SMBus interfering with address selection. When the
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PWM3/Address Enable pin is not used to change the SMBus address of the LM96000, it will remain in a high
state until the first communication with the LM96000. After the first SMBus transaction is completed PWM3
and TACH4 will return to normal operation.
Address Enable
Address Select
Board Implementation
SMBus Address
0
0
1
0
1
X
Pulled to ground through a 10 kΩ 010 1100b, 2Ch
resistor
Pulled to 3.3V or to GND through 010 1101b, 2Dh
a 10 kΩ resistor
Pulled to 3.3V through a 10 kΩ
010 1110b, 2Eh
resistor
In this way, up to three LM96000 devices can exists on an SMBus at any time. Multiple LM96000 devices can be
used to monitor additional processors and temperature zones. When using the non-default addresses the TACH4
and PWM3 will not function. As shown in the timing diagram the Address Enable pin must remain low in order for
the latched address to remain in effect. If the address enable pin is pulled high after the first SMBus
communication, then the LM96000 SMBus address will revert to the default value (2Eh) after the first five clocks
of next SMBus communication.
Latch state of AE and AS
if first 5 address bits are
correct for SMBus
address 2Ch and 2Dh
selection.
first 5 address bits
0
START
0
1
1
1
SMBCLK
SMBDAT
Address
Enable
Address
Select
Figure 7. Address Latch Enable low during and after first communication
Latch state of AE if
first 5 address bits
are correct for
SMBus address 2Eh
selection.
first 5 address bits
0
START
0
1
1
1
SMBCLK
SMBDAT
Address
Enable
Address
Select
Figure 8. Address Latch Enable high during first communication
2.0 FAN REGISTER DEVICE SET-UP
The BIOS will follow the following steps to configure the fan registers on the LM96000. The registers
corresponding to each function are listed. All steps may not be necessary if default values are acceptable.
Regardless of all changes made by the BIOS to the fan limit and parameter registers during configuration, the
LM96000 will continue to operate based on default values until the START bit (bit 0), in the
Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START
bit to 1, the LM96000 will operate using the values that were set by the BIOS in the fan control limit and
parameter registers (adress 5Ch through 6Eh).
1. Set limits and parameters (not necessarily in this order):
–
–
–
–
– [5F-61h] Set PWM frequencies and auto fan control range.
– [62-63h] Set spike smoothing and min/off.
– [5C-5Eh] Set the fan spin-up delays.
– [5C-5Eh] Match each fan with a corresponding thermal zone.
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–
–
–
–
– [67-69h] Set the fan temperature limits.
– [6A-6Ch] Set the temperature absolute limits.
– [64-66h] Set the PWM minimum duty cycle.
– [6D-6Eh] Set the temperature Hysteresis values.
2. [40h] Set bit 0 (START) to update fan control and limit register values and start fan control based on these
new values.
3. [40h] Set bit 1 (LOCK) to lock the fan limit and parameter registers (optional).
3.0 AUTO FAN CONTROL OPERATING MODE
The LM96000 includes the circuitry for automatic fan control. In Auto Fan Mode, the LM96000 will automatically
adjust the PWM duty cycle of the PWM outputs. PWM outputs are assigned to a thermal zone based on the fan
configuration registers. It is possible to have more than one PWM output assigned to a thermal zone. For
example, PWM outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. At
any time, the temperature of a zone exceeds its absolute limit, all PWM outputs will go to 100% duty cycle to
provide maximum cooling to the system.
4.0 REGISTER SET
Register Read/
Address Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
20h
21h
R
R
2.5V
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
N/A
N/A
VCCP_I
N
22h
23h
24h
25h
R
R
R
R
3.3V
5V
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
N/A
N/A
N/A
N/A
12V
Process
or
(Zone1)
Temp
26h
27h
R
R
Internal
(Zone2)
Temp
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
N/A
N/A
Remote
(Zone3)
Temp
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
R
Tach1
LSB
7
15
7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
LEVEL1 LEVEL0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
R
Tach1
MSB
9
8
R
Tach2
LSB
LEVEL1 LEVEL0
R
Tach2
MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
R
Tach3
LSB
LEVEL1 LEVEL0
R
Tach3
MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
R
Tach4
LSB
LEVEL1 LEVEL0
R
Tach4
MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
R/W
Fan1
Current
PWM
Duty
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Register Read/
Address Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
31h
R/W
Fan2
7
6
5
4
3
2
1
0
N/A
Current
PWM
Duty
32h
R/W
Fan3
7
6
5
4
3
2
1
0
N/A
Current
PWM
Duty
3Eh
3Fh
40h
R
Compan
y ID
7
6
5
4
3
2
1
0
01h
68h
00h
R
Version/
Stepping
VER3
RES
VER2
RES
VER1
RES
VER0
RES
STP3
OVRID
STP2
READY
STP1
LOCK
STP0
START
R/W
Ready/L
ock/Start
/Overrid
e
41h
42h
R
R
Interrupt
Status
Register
1
ERR
ZN3
ZN2
ZN1
5V
3.3V
VCCP
RES
2.5V
12V
00h
00h
Interrupt
Status
Register
2
ERR2
ERR1
FAN4
FAN3
FAN2
FAN1
43h
44h
R
VID0–4
RES
7
RES
6
RES
5
VID4
4
VID3
3
VID2
2
VID1
1
VID0
0
N/A
00h
R/W
2.5V
Low
Limit
45h
46h
47h
48h
49h
R/W
R/W
R/W
R/W
R/W
2.5V
High
Limit
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
FFh
00h
FFh
00h
FFh
VCCP
Low
Limit
VCCP
High
Limit
3.3V
Low
Limit
3.3V
High
Limit
4Ah
4Bh
4Ch
4Dh
R/W
R/W
R/W
R/W
5V Low
Limit
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
00h
FFh
00h
FFh
5V High
Limit
12V Low
Limit
12V
High
Limit
4Eh
R/W
Process
or
7
6
5
4
3
2
1
0
81h
(Zone1)
Low
Temp
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Lock?
Register Read/
Address Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
4Fh
R/W
Process
or
7
6
5
4
3
2
1
0
7Fh
(Zone1)
High
Temp
50h
51h
52h
53h
R/W
R/W
R/W
R/W
Internal
(Zone2)
Low
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
81h
7Fh
81h
7Fh
Temp
Internal
(Zone2)
High
Temp
Remote
(Zone3)
Low
Temp
Remote
(Zone3)
High
Temp
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Tach1
Minimum
LSB
7
15
6
14
5
13
4
12
3
11
2
10
1
0
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
62h
62h
62h
C4h
Tach1
Minimum
MSB
9
8
Tach2
Minimum
LSB
7
6
5
4
3
2
1
0
Tach2
Minimum
MSB
15
14
13
12
11
10
9
1
8
0
Tach3
Minimum
LSB
7
6
5
4
3
2
Tach3
Minimum
MSB
15
14
13
12
11
10
9
8
Tach4
Minimum
LSB
7
6
5
4
3
2
1
0
Tach4
Minimum
MSB
15
14
13
12
11
10
9
8
Fan1
Configur
ation
ZON2
ZON2
ZON2
RAN3
ZON1
ZON1
ZON1
RAN2
ZON0
ZON0
ZON0
RAN1
INV
INV
INV
RAN0
RES
RES
RES
HLFRQ
SPIN2
SPIN2
SPIN2
FRQ2
SPIN1
SPIN1
SPIN1
FRQ1
SPIN0
SPIN0
SPIN0
FRQ0
✓
✓
✓
✓
Fan2
Configur
ation
Fan3
Configur
ation
Fan1
Range/F
requenc
y
60h
R/W
Fan2
RAN3
RAN2
RAN1
RAN0
HLFRQ
FRQ2
FRQ1
FRQ0
C4h
✓
Range/F
requenc
y
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Register Read/
Address Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
61h
R/W
Fan3
RAN3
RAN2
RAN1
RAN0
HLFRQ
FRQ2
FRQ1
FRQ0
C4h
✓
Range/F
requenc
y
62h
R/W
Min/Off,
Zone1
Spike
Smoothi
ng
OFF3
OFF2
ZN2-2
OFF1
ZN2-1
RES
ZN1E
ZN3E
ZN1-2
ZN3-2
ZN1-1
ZN3-1
ZN1-0
00H
✓
✓
63h
R/W
Zone2,
Zone3
Spike
Smoothi
ng
ZN2E
ZN2-0
ZN3-0
00h
64h
65h
66h
67h
R/W
R/W
R/W
R/W
Fan1
PWM
Minimum
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
80h
80h
80h
5Ah
✓
✓
✓
✓
Fan2
PWM
Minimum
Fan3
PWM
Minimum
Zone1
Fan
Temp
Limit
68h
69h
6Ah
6Bh
6Ch
6Dh
R/W
R/W
R/W
R/W
R/W
R/W
Zone2
Fan
Temp
Limit
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
5Ah
5Ah
64h
64h
64h
44h
✓
✓
✓
✓
✓
✓
Zone3
Fan
Temp
Limit
Zone1
Temp
Absolute
Limit
7
6
5
4
3
2
1
0
Zone2
Temp
Absolute
Limit
7
6
5
4
3
2
1
0
Zone3
Temp
Absolute
Limit
7
6
5
4
3
2
1
0
Zone1,
Zone2
Hysteres
is
H1-3
H1-2
H1-1
H1-0
H2-3
H2-2
H2-1
H2-0
6Eh
6Fh
R/W
R/W
Zone3
Hysteres
is
H3-3
RES
H3-2
RES
H3-1
RES
H3-0
RES
RES
RES
RES
RES
RES
RES
RES
XEN
40h
00h
✓
✓
XOR
Test
Tree
Enable
74h
R/W
Tach
RES
RES
T3/4-1
T3/4-0
T2-1
T2-0
T1-1
T1-0
00h
Monitor
Mode
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Register Read/
Address Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
75h
R/W
Fan
Spin-up
Mode
RES
RES
RES
RES
RES
PWM3
SU
PWM2
SU
PWM1
SU
7h
✓
4.1 Register 20-24h: Voltage Reading
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
20h
21h
22h
23h
24h
R
R
R
R
R
2.5V
VCCP
3.3V
5V
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
2
1
1
1
1
1
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
3
3
3
3
2
2
2
2
12V
The Register Names difine the typical input voltage at which the reading is ¾ full scale or C0h.
The Voltage Reading registers are updated automatically by the LM96000 at a minimum frequency of 4 Hz.
These registers are read only — a write to these registers has no effect.
4.2 Register 25-27h: Temperature Reading
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
25h
26h
27h
R
R
R
Processo
r (Zone1)
Temp
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
Internal
(Zone2)
Temp
N/A
N/A
Remote
(Zone3)
Temp
The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Processor
(Zone1) Temp register reports the temperature measured by the thermal diode connected to the Remote1− and
Remote1+ pins, Remote (Zone3) Temp register reports the temperature measured by the thermal diode
connected to the the Remote2− and Remote2+ pins, and the Internal (Zone2) Temp register reports the
temperature measured by the internal (junction) temperature sensor. Temperatures are represented as 8 bit, 2’s
complement, signed numbers, in Celsius, as shown below in Table 1. The Temperature Reading register will
return a value of 80h if the remote diode pins are not used by the board designer or are not functioning properly.
This reading will cause the zone limit bit(s) (bits 6 and 4) in the Interrupt Status Register (41h) and the remote
diode fault status bit(s) (bit 6 or 7) in the Interrupt Status Register 2 (42h) to be set. The Temperature Reading
registers are updated automatically by the LM96000 at a minimum frequency of 4 Hz. These registers are read
only — a write to these registers has no effect.
Table 1. Temperature vs Register Reading
Temperature
Reading (Dec)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
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Table 1. Temperature vs Register Reading (continued)
Temperature
Reading (Dec)
Reading (Hex)
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
80h
(SENSOR ERROR)
4.3 Register 28-2Fh: Fan Tachometer Reading
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
28h
29h
R
R
Tach1
LSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
Tach1
MSB
2Ah
2Bh
R
R
Tach2
LSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
Tach2
MSB
2Ch
2Dh
R
R
Tach3
LSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
Tach3
MSB
2Eh
2Fh
R
R
Tach4
LSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
Tach4
MSB
The Fan Tachometer Reading registers contain the number of 11.111 µs periods (90 kHz) between full fan
revolutions. The results are based on the time interval of two tachometer pulses, since most fans produce two
tachometer pulses per full revolution. These registers will be updated at least once every second.
The value, for each fan, is represented by a 16-bit unsigned number.
The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when
a fan is disabled or non-functional.
The least two significant bits (LEVEL1 and LEVEL2) of the least significant byte are used to indicate the
accuracy level of the tachometer reading. The accuracy ranges from most to least accurate.
[LEVEL1:LEVEL2]=11indicates a most accurate value, [LEVEL1:LEVEL2]=01 indicates the least accurate value
and [LEVEL1:LEVEL2]=00 is reserved for future use.
FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal.
These registers are read only — a write to these registers has no effect.
When the LSByte of the LM96000 16-bit register is read, the other byte (MSByte) is latched at the current value
until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated.
During spin-up, the PWM duty cycle reported is 0%.
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4.4 Register 30-32h: Current PWM Duty
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
30h
31h
32h
R/W
Fan1
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
N/A
N/A
Current
PWM
Duty
R/W
R/W
Fan2
Current
PWM
Duty
Fan3
Current
PWM
Duty
The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM
duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register
Start bit is set, this register and the PWM signals will be updated based on the algorithm described in the Auto
Fan Control Operating Mode section.
When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read only
unless the fan is in manual (test) mode, in which case a write to these registers will directly control the PWM duty
cycle for each fan. The PWM duty cycle is represented as shown in the following table.
Current Duty
0%
Value (Decimal)
Value (Hex)
00h
0
1
0.3922%
01h
.
.
.
.
.
.
.
.
.
25.098%
64
40h
.
.
.
.
.
.
.
.
.
50.196%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FFh
4.5 Register 3Eh: Company ID
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
3Eh
R
Company
ID
7
6
5
4
3
2
1
0
01h
The company ID register contains the company identification number. For Texas Instruments this is 01h. This
number is assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read
only — a write to this register has no effect.
4.6 Register 3Fh: Version/Stepping
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
VER2
Bit 5
VER1
Bit 4
VER0
Bit 3
STP3
Bit 2
STP2
Bit 1
STP1
3Fh
R
Version/S VER3
tepping
STP0
68h
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The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM96000
silicon. The four most significant bits [7.4] reflect the LM96000 base device number when set to a value of
0110b. For the LM96000, this register will read 01101000b (68h). Bit 3 of the stepping field is set to indicate that
the LM96000 is a super-set of the LM85 family of products.
The register is used by application software to identify which device in the hardware monitor family of ASICs has
been implemented in the given system. Based on this information, software can determine which registers to
read from and write to. Further, application software may use the current stepping to implement work-arounds for
bugs found in a specific silicon stepping.
This register is read only — a write to this register has no effect.
4.7 Register 40h: Ready/Lock/Start/Override
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
RES
Bit 5
RES
Bit 4
RES
Bit 3
Bit 2
Bit 1
LOCK
40h
R/W
Ready/Lo RES
ck/Start/O
OVRID
READY
START
00h
verride
Bit
Name
START
R/W
R/W
Default
Description
0
0
When software writes a 1 to this bit, the LM96000 fan monitoring and PWM output control
functions will use the values set in the fan control limit and parameter registers (address
5Ch through 6Eh). Before this bit is set, the LM96000 will not update the used register
values, the default values will remain in effect. Whenever this bit is set to 0, the LM96000
fan monitoring and PWM output control functions use the default fan limits and
parameters, regardless of the current values in the limit and parameter registers (5C
through 6Eh). The LM96000 will preserve the values currently stored in the limit and
parameter registers when this bit is set or cleared. This bit is not effected by the state of
the Lock bit.
It is expected that all limit and parameter registers will be set by BIOS or application
software prior to setting this bit.
1
LOCK
R/W
0
0
Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit
and parameter registers become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is set.
2
3
READY
OVRID
R
The LM96000 sets this bit automatically after the part is fully powered up, has completed
the power-up-reset process, and after all A/D converters are properly functioning.
R/W
If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of whether or
not the lock bit is set. The OVRID bit has precedence over the disabled mode. Therefore,
when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode.
4–7
Reserved
R
0
Reserved
4.8 Register 41h: Interrupt Status Register 1
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
ZN3
Bit 5
ZN2
Bit 4
ZN1
Bit 3
5V
Bit 2
3.3V
Bit 1
VCCP
41h
R
Interrupt
Status 1
ERR
2.5V
00h
The Interrupt Status Register 1 bits will be automatically set, by the LM96000, whenever a fault condition is
detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers.
ZN3 and ZN1 bits will be set when a diode fault condition, such as a disconect or short, is detected. More than
one fault may be indicated in the interrupt register when read. This register will hold a set bit(s) until the event is
read by software. The contents of this register will be cleared (set to 0) automatically by the LM96000 after it is
read by software, if the fault condition is no longer exists. Once set, the Interrupt Status Register 1 bits will
remain set until a read event occurs, even if the fault condition no longer exists
This register is read only — a write to this register has no effect.
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Bit
Name
R/W
Default
Description
0
1
2
3
4
2.5V_Error
R
R
R
R
R
0
0
0
0
0
The LM96000 automatically sets this bit to 1 when the 2.5V input voltage is less than
or equal to the limit set in the 2.5V Low Limit register or greater than the limit set in
the 2.5V High Limit register.
VCCP_Error
3.3V_Error
5V_Error
The LM96000 automatically sets this bit to 1 when the VCCP input voltage is less
than or equal to the limit set in the VCCP Low Limit register or greater than the limit
set in the VCCP High Limit register.
The LM96000 automatically sets this bit to 1 when the 3.3V input voltage is less than
or equal to the limit set in the 3.3V Low Limit register or greater than the limit set in
the 3.3V High Limit register.
The LM96000 automatically sets this bit to 1 when the 5V input voltage is less than or
equal to the limit set in the 5V Low Limit register or greater than the limit set in the 5V
High Limit register.
Zone 1 Limit
Exceeded
The LM96000 automatically sets this bit to 1 when the temperature input measured by
the Remote1− and Remote1+ inputs is less than or equal to the limit set in the
Processor (Zone1) Low Temp register or more than the limit set in the Processor
(Zone1) High Temp register. This bit will be set when a diode fault is detected.
5
6
7
Zone 2 Limit
Exceeded
R
R
R
0
0
0
The LM96000 automatically sets this bit to 1 when the temperature input measured by
the internal temperature sensor is less than or equal to the limit set in the Internal
(Zone2) Low Temp register or greater than the limit set in the Internal (Zone2) High
Temp register.
Zone 3 Limit
Exceeded
The LM96000 automatically sets this bit to 1 when the temperature input measured by
the Remote2− and Remote2+ inputs is less than or equal to the limit set in the
Internal (Zone2) Low Temp register or greater than the limit set in the Remote
(Zone3) High Temp register. This bit will be set when a diode fault is detected.
Error in Status
Register 2
If there is a set bit in Status Register 2, this bit will be set to 1.
4.9 Register 42h: Interrupt Status Register 2
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
ERR1
Bit 5
FAN4
Bit 4
FAN3
Bit 3
FAN2
Bit 2
FAN1
Bit 1
RES
42h
R
Interrupt
Status
Register
2
ERR2
12V
00h
The Interrupt Status Register 2 bits will be automatically set, by the LM96000, whenever a fault condition is
detected. Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed droping
below minimum set by the tachometer minimum register, the 12V input voltage going outside the window set by
its limit registers. Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of
this register will be cleared (set to 0) automatically by the LM96000 after it is ready by software, if fault condition
no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if
the fault no longer exists
This register is read only — a write to this register has no effect.
Bit
Name
R/W
Default
Description
0
+12V_Error
R
0
The LM96000 automatically sets this bit to 1 when the 12V input voltage either falls
below the limit set in the 12V Low Limit register or exceeds the limit set in the 12V
High Limit register.
1
2
Reserved
R
R
0
0
Reserved
Fan1 Stalled
The LM96000 automatically sets this bit to 1 when the TACH1 input reading is above
the value set in the Tach1 Minimum MSB and LSB registers.
3
4
5
Fan2 Stalled
Fan3 Stalled
Fan4 Stalled
R
R
R
0
0
0
The LM96000 automatically sets this bit to 1 when the TACH2 input reading is above
the value set in the Tach2 Minimum MSB and LSB registers.
The LM96000 automatically sets this bit to 1 when the TACH3 input reading is above
the value set in the Tach3 Minimum MSB and LSB registers.
The LM96000 automatically sets this bit to 1 when the TACH4 input reading is above
the value set in the Tach4 Minimum MSB and LSB registers.
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Bit
Name
R/W
Default
Description
6
Remote Diode 1
Fault
R
R
0
0
The LM96000 automatically sets this bit to 1 when there is either a short or open
circuit fault on the Remote1+ or Remote1− thermal diode input pins. A diode fault will
also set bit 4, Diode 1 Zone Limit bit, of Interrupt Status Register 1.
7
Remote Diode 2
Fault
The LM96000 automatically sets this bit to 1 when there is either a short or open
circuit fault on the Remote2+ or Remote2− thermal diode input pins. A diode fault will
also set bit 6, Diode 2 Zone Limit bit, of Interrupt Status Register 1.
4.10 Register 43h: VID
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
RES
Bit 5
RES
Bit 4
VID4
Bit 3
VID3
Bit 2
VID2
Bit 1
VID1
43h
R
VID0–4
RES
VID0
The VID register contains the values of LM96000 VID0–VID4 input pins. This register indicates the status of the
VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information
in this register to determine the voltage that the processor is designed to operate at. With this information,
software can then dynamically determine the correct values to place in the VCCP Low Limit and VCCP High
Limit registers.
This register is read only — a write to this register has no effect.
4.11 Registers 44-4Dh: Voltage Limit Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
R/W
2.5V Low
Limit
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2.5V High
Limit
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
VCCP
Low Limit
VCCP
High Limit
3.3V Low
Limit
3.3V High
Limit
5V Low
Limit
5V High
Limit
12V Low
Limit
12V High
Limit
If a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the
voltage low limit register, the corresponding bit will be set automatically by the LM96000 in the interrupt status
registers (41-42h). Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at
nominal voltage, each input will be C0h, as shown in Table 2.
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
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Table 2. Voltage Limits vs Register Setting
Register Reading
at
Register Reading
at
Register Setting
at
Nominal Voltage
Nominal
Voltage
Maximum
Voltage
Minimum
Voltage
Input
Maximum
Voltage
Minimum
Voltage
2.5V
VCCP
3.3V
5V
2.5V
C0h
C0h
C0h
C0h
C0h
3.32V
FFh
FFh
FFh
FFh
FFh
0V
0V
00h
00h
AFh
00h
00h
2.25V
3.3V
3.00V
4.38V
6.64V
16.00V
3.0V
0V
5.0V
12V
12.0V
0V
4.12 Registers 4E-53h: Temperature Limit Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
4Eh
4Fh
50h
51h
52h
53h
R/W
Processo
r (Zone1)
Low
7
7
7
7
7
7
6
6
6
6
6
6
5
5
5
5
5
5
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
81h
Temp
R/W
R/W
R/W
R/W
R/W
Processo
r (Zone1)
High
7Fh
81h
7Fh
81h
7Fh
Temp
Processo
r (Zone2)
Low
Temp
Processo
r (Zone2)
High
Temp
Processo
r (Zone3)
Low
Temp
Processo
r (Zone3)
High
Temp
If an external temperature input or the internal temperature sensor either exceeds the value set in the
corresponding high limit register or falls below the value set in the corresponding low limit register, the
corresponding bit will be set automatically by the LM96000 in the Interrupt Status Register 1 (41h). For example,
if the temperature read from the Remote1− and Remote1+ inputs exceeds the Processor (Zone1) High Temp
register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are
represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 3.
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
Table 3. Temperature Limits vs Register Settings
Temperature
Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
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Table 3. Temperature Limits vs Register Settings (continued)
Temperature
Reading (Decimal)
Reading (Hex)
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
4.13 Registers 54-5Bh: Fan Tachometer Low Limit
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
54h
55h
R/W
R/W
Tach1
Minimum 15
LSB
7
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
Tach1
Minimum
MSB
56h
57h
R/W
R/W
Tach2
Minimum 15
LSB
7
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
Tach2
Minimum
MSB
58h
59h
R/W
R/W
Tach3
Minimum 15
LSB
7
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
Tach3
Minimum
MSB
5Ah
5Bh
R/W
R/W
Tach4
Minimum 15
LSB
7
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
Tach4
Minimum
MSB
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will
be set in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so
care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. The fan
tachometer will not cause a bit to be set in Interrupt Status Register 2 if the current value in Current PWM Duty
registers is 00h or if the fan 1 disabled via the Fan Configuration Register. Interrupts will never be generated for
a fan if its minimum is set to FF FFh.
Given the insignificance of Bit 0 and Bit 1, these bits could be programmed to remember which fan is which, as
follows.
Fan
Bit 1
Bit 0
CPU
0
0
1
1
0
1
0
1
Memory
Chassis Front
Chassis Rear
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Setting the Ready/Lock/Start/Override register Lock bit has no effect these registers.
4.14 Registers 5C-5Eh: Fan Configuration
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
INV
Bit 3
RES
Bit 2
Bit 1
Lock?
Address
Write
Name
5Ch
R/W
Fan1
ZON2
ZON2
ZON2
ZON1
ZON0
SPIN2
SPIN1
SPIN0
SPIN0
SPIN0
62h
62h
62h
✓
Configur
ation
5Dh
5Eh
R/W
R/W
Fan2
Configur
ation
ZON1
ZON1
ZON0
ZON0
INV
INV
RES
RES
SPIN2
SPIN2
SPIN1
SPIN1
✓
✓
Fan3
Configur
ation
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this register shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Bits [7:5] Zone/Mode
Bits [7:5] of the Fan Configuration registers associate each fan with a temperature sensor. When in Auto Fan
Mode the fan will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of
that zone. If ‘Hottest’ option is selected (101 or 110), the fan will be controlled by the hottest of zones 2 and 3, or
of zones 1, 2, and 3. To determine the ‘Hottest’ zone the PWM level for each zone is calculated then the the
highest PWM value is selected. When in manual control mode, the Current PWM duty registers (30h-32h)
become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers.
When the fan is disabled (100) the corresponding PWM output should be driven low (or high, if inverted).
Zone 1: External Diode 1 (processor)
Zone 2: Internal Sensor
Zone 3: External Diode 2
Table 4. Fan Zone Setting
ZON[2:0]
Fan Configuration
000
001
010
011
100
101
110
111
Fan on zone 1 auto
Fan on zone 2 auto
Fan on zone 3 auto
Fan always on full
Fan disabled
Fan controlled by hottest of zones 2, 3
Fan controlled by hottest of zones 1, 2, 3
Fan manually controlled (Test Mode)
Bit [4] PWM Invert
Bit [4] inverts the PWM output. If set to 0, 100% duty cycle will yield an output that is always high. If set to 1,
100% duty cycle will yield an output that is always low.
Bit [3] Reserved
Bits [2:0] Spin Up
Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM
output is held at 100% duty cycle for the time specified in the Table 5 below before scaling to a lower speed.
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Table 5. Fan Spin-Up Register
SPIN[2:0]
Spin Up Time
000
001
010
011
100
101
110
111
0 sec
100 ms
250 ms
400 ms
700 ms
1000 ms
2000 ms
4000 ms
4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
Address
Write
Name
5Fh
R/W
Zone1
Range/F
an1
Frequen
cy
RAN3
RAN3
RAN3
RAN2
RAN1
RAN0
HLFRQ FRQ2
HLFRQ FRQ2
HLFRQ FRQ2
FRQ1
FRQ0
C4h
C4h
C4h
✓
60h
61h
R/W
R/W
Zone2
Range/F
an2
Frequen
cy
RAN2
RAN2
RAN1
RAN1
RAN0
RAN0
FRQ1
FRQ1
FRQ0
FRQ0
✓
✓
Zone3
Range/F
an3
Frequen
cy
In Auto Fan Mode, when the temperature for a zone is above the Temperature Limit (Registers 67-69h) and
below its Absolute Temperature Limit (Registers 6A-6Ch), the speed of a fan assigned to that zone is determined
as follows.
When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be
Fan PWM Minimum. Between Fan Temp Limit and (Fan Temp Limit + Range), the PWM duty cycle will increase
linearly according to the temperature as shown in Figure 9 below. The PWM duty cycle will be 100% at (Fan
Temp Limit + Range).
Hot
Cold
Temperature
Fan Temp Limit +
Range
Fan Temp Limit - Hysteresis Fan Temp Limit
Hysteresis is 0oC-15oC (6Dh-6Eh) (67h-69h)
Absolute Limit
(6Ah-6Ch)
Range is 2oC to 80oC (5Fh-61h)
PWM duty cycle
linearly increasing as
temperature increases
Min PWM
or
OFF
PWM duty cycle linearly
deacreasing as
decreasing as
temperature decreases
Zone n
Zone n PWM set to Zone n PWM set to
Min FanSpeed (64h- Min FanSpeed (64h-
66h) 66h)
Zone n
100% PWM
All Zones
100% PWM
Figure 9. Fan Activity above Fan Temp Limit
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Example for PWM1 assigned to Zone 1:
•
•
•
– Zone 1 Fan Temp Limit (Register 67h) is set to 50°C (32h).
– Range (Register 5Fh) is set to 8°C (6xh).
– Fan 1 PWM Minimum (Register 64h) is set to 50% (32h).
In this case, the PWM1 duty cycle will be 50% at 50°C.
Since (Zone 1 Fan Temp Limit) + (Zone 1 Range) = 50°C + 8°C = 58°C, the fan will run at 100% duty cycle when
the temperature of the Zone 1 sensor reaches 58°C.
Since the midpoint of the fan control range is 54°C, and the median duty cycle is 75% (Halfway between the
PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54°C.
Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%.
PWM frequency bits [3:0]
The PWM frequency bits [3:0] determine the PWM frequency for the fan.The LM96000 has high and low
frequency ranges for the PWM outputs, that are controlled by the HLFRQ bit.
PWM Frequency Selection (Default = 0011 = 30.04 Hz).
Table 6. Register Setting vs PWM Frequency
HLFRQ
Freq [2:0]
PWM Frequency
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
10.01 Hz
15.02 Hz
23.14 Hz
30.04 Hz
38.16 Hz
47.06 Hz
61.38 Hz
94.12 Hz
22.5 kHz
24 kHz
25.7 kHz
25.7 kHz
27.7 kHz
27.7 kHz
30 kHz
30 kHz
Range Selection RAN [3:0]
RAN [3:0]
Range (°C)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
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RAN [3:0]
Range (°C)
1100
1101
1110
1111
32
40
53.33
80
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this register shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
4.16 Registers 62, 63h: Min/Off, Spike Smoothing
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
OFF2
Bit 5
OFF1
Bit 4
RES
Bit 3
ZN1E
Bit 2
Bit 1
Lock?
Address
Write
Name
62h
R/W
Min/Off, OFF3
Zone1
ZN1-2
ZN1-1
ZN1-0
00h
✓
Spike
Smoothi
ng
63h
R/W
Zone2,
Zone3
Spike
Smoothi
ng
ZN2E
ZN2-2
ZN2-1
ZN2-0
ZN3E
ZN3-2
ZN3-1
ZN3-0
00h
✓
The Off/Min Bits [7:5] specify whether the duty cycle will be 0% or Minimum Fan Duty when the measured
temperature falls below the Temperature LIMIT register setting (see table below). OFF1 applies to fan 1, OFF2
applies to fan 2, and OFF3 applies to fan 3.
If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may
be sampled by the LM96000. If these spikes are not ignored, the CPU fan (if connected to LM96000) may turn
on prematurely and produce unpleasant noise. For this reason, any zone that is connected to a chipset or
processor should have spike smoothing enabled.
When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the
temperature — not the ‘smoothed out’ value.
ZN1E, ZN2E, and ZN3E enable temperature smoothing for zones 1, 2, and 3 respectively.
ZN1-2, ZN1-1, and ZN1-0 control smoothing time for Zone 1.
ZN2-2, ZN2-1, and ZN2-0 control smoothing time for Zone 2.
ZN3-2, ZN3-1, and ZN3-0 control smoothing time for Zone 3.
These registers become ready only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to these registers shall have no effect.
35 second Smoothing Filter
100
INPUT
80
60
40
OUTPUT
1.0
0.8
20
0.6
0.4
0.2
0
0
5
10 15 20 25 30 35 40
TIME (s)
Figure 10. What LM96000 Auto Fan Control Sees With and Without Spike Smoothing
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Table 7. Spike Smoothing
ZN-X[2:0]
Spike Smoothed Over
000
001
010
011
100
101
110
111
35 seconds
17.6 seconds
11.8 seconds
7.0 seconds
4.4 seconds
3.0 seconds
1.6 seconds
.8 seconds
Table 8. PWM Output Below Limit Depending on Value of Off/Min
Off/Min
PWM Action
At 0% duty below LIMIT
0
1
At Min PWM Duty below LIMIT
4.17 Registers 64-66h: Minimum PWM Duty Cycle
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
Address
Write
Name
64h
R/W
Fan1
PWM
Minimum
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
80h
80h
80h
✓
65h
66h
R/W
R/W
Fan2
PWM
Minimum
✓
✓
Fan3
PWM
Minimum
These registers specify the minimum duty cycle that the PWM will output when the measured temperature
reaches the Temperature LIMIT register setting.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this register shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Table 9. PWM Duty vs Register Setting for PWM Low Frequency Range
Current Duty
0%
Value (Decimal)
Value (Hex)
00h
0
1
0.3922%
01h
.
.
.
.
.
.
.
.
.
25.098%
64
40h
.
.
.
.
.
.
.
.
.
50.196%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FF
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PWM Duty Cycle vs Register Setting for PWM High Frequency Range
22.5KHz PWM Frequency
PWM Duty Cycle Level (%)
Value in Decimal
Value in Hex
0.00
6.25
0
0
1
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
01
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0F
1F
2F
3F
4F
5F
6F
7F
8F
9F
AF
BF
CF
DF
EF
FF
12.50
18.75
25.00
31.25
37.50
43.75
50.00
56.25
62.50
68.75
75.00
81.25
87.50
93.75
100.00
31
32
47
48
63
64
79
80
95
96
111
127
143
159
175
191
207
223
239
255
112
128
144
160
176
192
208
224
240
24KHz PWM Frequency
PWM Duty Cycle Level (%)
Value in Decimal
Value in Hex
0
0
0
6.67
1
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
01
11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
21
32
43
54
65
76
88
99
AA
BB
CC
DD
EE
FF
13.33
20.00
26.67
33.33
40.00
46.67
53.33
60.00
66.67
73.33
80.00
86.67
93.33
100.00
33
34
50
22
51
67
33
68
84
44
85
101
118
136
153
170
187
204
221
238
255
55
102
119
137
154
171
188
205
222
239
66
77
89
9A
AB
BC
CD
DE
EF
25.7KHz PWM Frequency
PWM Duty Cycle Level (%)
Value in Decimal
Value in Hex
0
0
0
7.14
1
18
37
55
73
91
-
-
-
-
-
-
17
36
54
72
90
109
01
12
25
37
49
5B
-
-
-
-
-
-
11
24
36
48
5A
6D
14.29
21.43
28.57
35.71
42.86
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25.7KHz PWM Frequency
Value in Decimal
PWM Duty Cycle Level (%)
Value in Hex
50.00
57.14
64.29
71.43
78.57
85.71
92.86
100.00
110
128
146
165
183
201
219
238
-
-
-
-
-
-
-
-
127
145
164
182
200
218
237
255
6E
80
-
-
-
-
-
-
-
-
7F
91
92
A4
B6
C8
DA
ED
FF
A5
B7
C9
DB
EE
27.7KHz PWM Frequency
PWM Duty Cycle Level (%)
Value in Decimal
Value in Hex
0
0
0
7.69
1
20
-
-
-
-
-
-
-
-
-
-
-
-
-
19
01
14
27
3B
4F
62
76
8A
9E
B1
C5
D9
EC
-
-
-
-
-
-
-
-
-
-
-
-
-
13
26
3A
4E
61
75
89
9D
B0
C4
D8
EB
FF
15.38
23.08
30.77
38.46
46.15
53.85
61.54
69.23
76.92
84.62
92.31
100.00
38
39
58
59
78
79
97
98
117
137
157
176
196
216
235
255
118
138
158
177
197
217
236
30KHz PWM Frequency
PWM Duty Cycle Level (%)
Value in Decimal
Value in Hex
0
0
0
8.33
1
21
-
-
-
-
-
-
-
-
-
-
-
-
20
01
15
2B
40
55
6B
80
95
AB
C0
D5
EB
-
-
-
-
-
-
-
-
-
-
-
-
14
2A
3F
54
6A
7F
94
AA
BF
D4
EA
FF
16.67
25.00
33.33
41.67
50.00
58.33
66.67
75.00
83.33
91.67
100.00
42
43
63
64
84
85
106
127
148
170
191
212
234
255
107
128
149
171
192
213
235
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4.18 Registers 67-69h: Temperature Limit
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
Address
Write
Name
67h
R/W
Zone1
Fan
Temp
Limit
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
5Ah
5Ah
5Ah
✓
68h
69h
R/W
R/W
Zone2
Fan
Temp
Limit
✓
✓
Zone3
Fan
Temp
Limit
These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan
will be turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased
according to the algorithm set forth in the Auto Fan Range, PWM Frequency register description.
Default = 90°C = 5Ah
(1)
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this register shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Table 10. Temperature Limit vs Register Setting
Temperature
Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
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4.19 Registers 6A-6Ch: Absolute Temperature Limit
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
Address
Write
Name
6Ah
R/W
Zone1
Absolute
Temp
7
7
7
6
5
4
3
2
1
0
0
0
64h
64h
64h
✓
Limit
6Bh
6Ch
R/W
R/W
Zone2
Absolute
Temp
6
6
5
5
4
4
3
3
2
2
1
1
✓
✓
Limit
Zone3
Absolute
Temp
Limit
In the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of
the PWM outputs will incresase its duty cycle to 100%. This is a safety feature that attempts to cool the system if
there is
a potentially catastrophic thermal event. If set to 80h (-128°C), the feature is disabled.
Default=100°C=64h
These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to these registers shall have no effect. After power up the default values are used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to these registers are possible.
Table 11. Absolute Limit vs Register Setting
Temperature
Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
4.20 Registers 6D-6Eh: Zone Hysteresis Registers
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
H1-2
Bit 5
H1-1
Bit 4
H1-0
Bit 3
H2-3
Bit 2
H2-2
Bit 1
H2-1
Lock?
Address
Write
Name
6Dh
R/W
Zone1
and
H1-3
H2-0
44h
✓
Zone2
Hysteres
is
6Eh
R/W
Zone3
Hysteres
is
H3-3
H3-2
H3-1
H3-0
RES
RES
RES
RES
40h
✓
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If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur:
•
– The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan
Temp Limit.
•
– The Hysteresis registers control this amount. See below table for details.
These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to thses registers shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Table 12. Hysteresis Settings
Setting
HYSTERESIS
0h
0°C
.
.
.
.
.
.
5h
5°C
.
.
.
.
.
.
Fh
15°C
4.21 Register 6Fh: Test Register
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
RES
Bit 5
RES
Bit 4
RES
Bit 3
RES
Bit 2
RES
Bit 1
RES
6Fh
R/W
Test
RES
XEN
00h
Register
If the XEN bit is set high, the part will be placed into XOR tree test mode. Clearing the bit (writing a 0 to the XEN
bit) brings the part out of XOR tree test mode.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this registers shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
4.22 Registers 70-7Fh: Vendor Specific Registers
These registers are for vendor specific features, including test registers. They will not default to a specific value
on power up.
4.22.1 Register 74h: Tachometer Monitor Mode
Register Read/ Register
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Bit 6
RES
Bit 5
Bit 4
Bit 3
T2-1
Bit 2
T2-0
Bit 1
T1-1
Lock?
Address
Write
Name
74h
R/W
Tach
RES
T3/4-1
T3/4-0
T1-0
00h
Monitor
Mode
Each fan TACH input has 4 possible modes of operation when using the low frequency range for the PWM
outputs. Mode 0 is the only mode that is available when using the high frequecy range for the PWM outputs. The
modes for TACH3 and TACH4 share control bits T3/4-[1:0]; TACH2 is controlled by T2-[1:0]; TACH1 is controlled
by T1-[1:0]. The result reported in all modes is based on 2 pulses per revolution. In order for modes 2 and 3 to
function properly it is required that the:
•
•
•
PWM1 output must control the fan that has it's tachometer output connected to the TACH1 LM96000 input.
PWM2 output must control the fan that has it's tachometer output connected to the TACH2 LM96000 input.
PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4
LM96000 inputs.
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Setting (Tn[1:0])
Mode
Function
00
0
Traditional tach input monitor, false readings
when under minimum detctable RPM
01
10
11
1
2
3
Traditional tach input monitor, FFFFh reading
when under minimum detectable RPM
Most accurate readings, FFFFh reading
when under minimum detectable RPM
Least effect on programmed PWM of Fan,
FFFFh reading when under minimum
detectable RPM
•
Mode 0:
This mode uses the conventional method for fan tachometer pulse detection and does not include any circuitry to
compensate for PWM Fan drive. This mode should be used when PWM drive is not used to power the fan. This mode may
report a false RPM reading when under minimum detectable RPM as shown in the following table.
•
•
•
Mode 1:
Mode 2:
Mode 3:
This mode uses the conventional method for fan tach detection. The reading will be FFFFh if it is below minimum detectable
RPM.
This mode is optimized for accurate RPM readings and activates circuitry that extends the lower side of the RPM reading as
shown in the following table.
This mode minimizes the effect on the RPM setting and activates circuitry that extends the lower side of the RPM reading as
shown in the following table.
PWM Frequency
10.01
Mode 0 and 1 Minimum RPM
Mode 2 and 3 Minimum RPM
841
210
315
420
420
420
420
420
420
15.02
1262
1944
2523
3205
3953
5156
7906
23.14
30.04
38.16
47.06
61.38
94.12
This register is not effected when the Ready/Lock/Start/Override register Lock bit is set. After power up the
default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though
modifications to this register are possible.
4.22.2 Register 75h: Fan Spin-up Mode
Register Read/ Register
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock?
Address
Write
Name
75h
R/W
Fan
Spin-up
Mode
RES
RES
RES
RES
RES
PWM3
SU
PWM2
SU
PWM1
SU
7h
✓
The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after
time programmed by the Fan Configuration register has elapsed. When set to a 1, the spin-up time will terminate
early if the TACH reading exceeds the Tach Minimum value or after the time programmed by the Fan
Configuration register has elapsed, whichever occurs first.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further
attempts to write to this register shall have no effect. After power up the default value is used whenever the
Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
4.23 Undefined Registers
Any reads to undefined registers will always return 00h. Writes to undefined registers will have no effect and will
not return an error.
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5.0 XOR TEST MODE
The LM96000 incorporates a XOR tree test mode. When the test mode is enabled by setting the “XEN” bit high
in the Test Register at address 6Fh via the SMBus, the part will enter XOR test mode.
Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK
are not to be included in the test tree.
VID0
VID1
VID2
VID3
VID4
TACH1
TACH2
TACH3
TACH4
xTEST OUT
PWM2
PWM3
APPLICATIONS INFORMATION
+3.3V
+12V
+12V
6.8k
6.8k
.01
470
6.2k
4.3k
100 pF
6.2k
4.3k
Pentium 4
PROCESSOR
TACH1
PWM1
REMOTE1+
REMOTE1-
.01
+3.3V
+12V
TACH2
PWM2
REMOTE2+
REMOTE2-
6.8k
.01
470
6.2k
4.3k
PWM3
TACH3
MMBT3904
100 pF
TACH4
PROCESSOR
CORE VOLTAGE
VCCP_IN
+3.3V
68
VID0
VID1
VID2
VID3
VID4
2.5V SUPPLY
2.5V
12V
5V
FROM
PROCESSOR
VRM
470
470
+12V
12V SUPPLY
5V SUPPLY
3.3V STBY
6.8k
.01
3.3V
GND
6.2k
4.3k
SMBDAT
SMBCLK
100 pF
0.1
SMBus
68
(ICH or SIO Host)
LM96000
Figure 11. Typical Applications Schematic
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 33
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM96000CIMT/NOPB
LM96000CIMTX/NOPB
ACTIVE
TSSOP
TSSOP
PW
24
24
61
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 125
0 to 125
LM96000
CIMT
ACTIVE
PW
2500 RoHS & Green
SN
LM96000
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM96000CIMTX/NOPB TSSOP
PW
24
2500
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM96000CIMTX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM96000CIMT/NOPB
24
61
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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