LM96550SQX [TI]
LM96550 Ultrasound Transmit Pulser; LM96550超声发射脉冲发生器
| 型号： | LM96550SQX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM96550 Ultrasound Transmit Pulser |
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LM96550
LM96550 Ultrasound Transmit Pulser
Literature Number: SNAS504E
November 30, 2011
LM96550
Ultrasound Transmit Pulser
General Description
Features
The LM96550 is an eight-channel monolithic high-voltage,
high-speed pulse generator for multi-channel medical ultra-
sound applications. It is well-suited for use with National’s
LM965XX series chipset which offers a complete medical ul-
trasound solution targeted towards low-power, portable sys-
tems.
8-channel high-voltage CMOS pulse generator
Output pulses with ±50V and 2A peak current
Active damper with built-in blocking diodes
Up to 15 MHz operating frequency
■
■
■
■
■
■
Matched delays for rising and falling edges
Low second harmonic distortion allows and improves
harmonic imaging
The LM96550 contains eight high-voltage pulsers with inte-
grated diodes generating ±50V bipolar pulses with peak cur-
rents of up to 2A and pulse rates of up to 15 MHz. Advanced
features include low-jitter and low-phase-noise output pulses
ideal for continuous-wave (CW) modes of operation. Active
clamp circuitry is integrated for ensuring low harmonic distor-
tion of the output signal waveform.
Continuous-wave (CW) operation down to ±3.3V
■
■
Low Phase noise enables Doppler measurements
-145 dBc/Hz Phase Noise at 10 MHz (1 kHz offset)
Output state over-temperature protection
Blocking diodes for direct interface to transducer
2.5V to 5.0V CMOS logic interface
■
■
■
■
■
The LM96550 also featuers a low-power operation mode and
over-temperature protection (OTP) which are enabled by on-
chip temperature sensing and power-down logic.
Low-power consumption per channel
Over Temperature Protection
Applications
Key Specifications
Ultrasound Imaging
■
Output voltage
±50
±2.0
V
A
Output peak current
Output pulse rate
Rise/fall delay
Up to 15
< 3
MHz
ns
matching (max)
Pulser HD2 (5 MHz)
Operating Temp.
-40
dB
°C
0 to +70
Block Diagram
30129602
© 2011 Texas Instruments Incorporated
301296
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Typical Application
8-Channel Transmit/Receive Chipset
30129607
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2
Pin Diagram
30129601
FIGURE 1. Pin Diagram of LM96550
Ordering Information
Order Number
LM96550SQ
Package Type
80 Lead LLP
NSC Package Drawing
SQA80A
Supplied As
1000
250
LM96550SQE
LM96550SQX
2000
3
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TABLE 1. Pin Descriptions
Pin No.
Name
Type
Function and Connection
Logic control positive output channel P
1 = ON
0 = OFF
21, 23, 25, 27, 33, 35, 37,
39
PIN
n=0...7
Input
Logic control negative output channel N
1 = ON
0 = OFF
22, 24, 26, 28, 34, 36, 38,
40
NIN
n=0...7
Input
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VOUT0
59, 60
62, 63
65, 66
68, 69
72, 73
75, 76
78, 79
1, 2
Output
High voltage output of channels 0 to 7
Chip power enable
1 = ON
0 = OFF
29
31
EN
Input
Input
Output current mode control
1 = Max Current
MODE
0 = Low Current
Over-temperature indicating IC temp > 125°C
0 = Over-temperature
1 = Normal temperature
30
OTP
Output
This pin is open-drain.
4, 5, 6, 7, 54, 55, 56, 57
VPP
VNN
Power
Power
Positive high voltage power supply (+3.3V to +50V)
11, 12, 13, 14, 47, 48, 49,
50
Negative high voltage power supply (-3.3V to -50V)
8, 53
VPF
VNF
VDD
VDN
VLL
Power
Power
Power
Power
Power
Positive floating power supply (VPP -10V)
10, 51
18, 43
16, 45
20, 41
Negative floating power supply (VNN +10V)
Positive level-shifter supply voltage (+10V)
Negative level-shifter supply voltage (-10V)
Logic supply voltage. Hi voltage reference input (+2.5 to +5V)
All VSUB pins must be connected to most negative potential of
the IC.
0, 15, 46
VSUB
Power
NOTE: The exposed thermal pad is connected to VSUB.
3, 9, 52, 58, 61, 64, 67, 70,
71, 74, 77, 80
HVGND
AGND
Ground
Ground
High voltage reference potential (0V)
17, 19, 32, 42, 44
Analog and Logic voltage reference input, logic ground (0V)
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4
Absolute Maximum Ratings (Note 1)
Operating Ratings
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Operation Junction Temperature
VPP, −VNN; High-voltage supply
VPF, −VNF; Floating supply
VDD, −VDN; Level-shift supply
VLL, Logic Supply
0°C to + 70°C
+3.3V to +50V
VPP −10V
+9V to 11V
+2.4V to +5.3V
Maximum Junction Temperature (TJMAX
Storage Temperature Range
Supply Voltage (VDD)
)
+150°C
−40°C to +125°C
–0.3V to +12V
+0.3V and −12V
–0.3V and +55V
VPP −14V
VSUB, Substrate bias supply
must be most
negative supply
Supply Voltage (VDN)
Supply Voltage (VPP)
Package Thermal Resistance (θJA
ESD Tolerance
)
19.7°C/W
Supply Voltage (VPF)
Supply Voltage (VNN)
Supply Voltage (VNF)
Supply Voltage (VSUB)
IO Supply Voltage (VLL)
Voltage at Logic Inputs
+0.3V and −55V
VNN +14V
−65V
−0.3V to +5.5V
Human Body Model
Machine Model
Charge Device Model
2kV
150V
750V
−0.3V to VLL
+0.3V
Analog Characteristics
Unless otherwise stated, the following conditions apply
VLL = +3.3V, VPP = −VNN = 50V, VPF = −VNF = VPP-10V, VDD = −VDN = 10V, VSUB = −55V, RL = 2 KΩ, TA = 25°C, Mode =
LO, EN = HI, Fin=5MHz
Symbol
FOUT
Parameter
Conditions
Min
1
Typ
Max
15
Units
MHz
V
Output Frequency Range RL = 100Ω
Output Voltage Range
-48.5
+48.5
Output Current
2% Duty Cycle
100% Duty Cycle,
Mode=HI
2
A
Output Current
0.6
Second harmonic
distortion
HD2
RON
RL = 100Ω || CL = 330pF See (Note 2)
-40
dBc
Output ON Resistance
Output clamp
100 mA
7
11
Ω
A
Positive or Negative pulse
2
VPP
VNN
VDD
0.7
0.5
8
3
4.5
13
7
mA
VDN
4
Pin = Nin = 0
VLL
25
1.2
0.1
0.1
0.7
0.5
0.4
0.1
25
1.2
0.1
0.1
50
6
µA
VSUB
VPF
1.5
1.5
3
mA
VNF
VPP
VNN
VDD
Power Supply Current
4.5
2.7
2.2
50
6
mA
VDN
En = 0
VLL
µA
VSUB
VPF
1.5
1.5
mA
VNF
OPT
Over Temperature
Protection
125
°C
OTP sigma
σOTP
3.0
5.5
°C
°C
HsysOTP
OTP hysteresis
5
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AC and Timing Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, VPF = −VNF = 40V, CL = 330pF, RL = 100 Ω, TA = 25°C,
Fin=5MHz, Mode=LO, EN=HI
Symbol
Parameter
Output rise time
Conditions
See (Note 2)
Min
Typ
18
18
1
Max
26
Unit
ns
tr
tf
Output fall time
26
tE
tdr
tdf
Enable time
µs
Delay time on inputs rise
Delay time on inputs fall
Delay time mismatch
Delay on mode change
32
32
39
39
3
See (Note 2)
ns
µs
| tdr - tdr
tdm
|
P-to-N See (Note 2) & 3
1
DC Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, VPF = −VNF = 40V, TA = 25°C,
Symbol
Parameter
Low Input “LO” threshold
High Input “HI” threshold
input current
Conditions
Min
Typ
Max
Unit
V
VIL
VIH
IIN
1
2.3
V
1
µA
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics.
Note 2: VNF = -42V, VPF = 38V
Note 3: The delay time mismatch can be adjust to be less than 0.8ns with the LM96570 duty cycle control function.
Note 4: 10.24 MHz Differential Input signal from LMK04800 Evaluation board with 122.88 MHz Crystek CVHD-950 VCXO clock source. The LMK04800 clock
output channel was configured with a divide value of 12 and LVCMOS outputs with opposite polarity.
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6
tion into multi-channel (128/256 channel) systems. Its flexible,
integrated ±50V pulser architecture enables low-power de-
signs targeting portable systems. A complete system can be
designed using National’s companion LM965XX chipset.
Overview
The LM96550 pulser provides an 8-channel transmit side so-
lution for medical ultrasound applications suitable for integra-
30129602
FIGURE 2. Block Diagram of High-Voltage
Pulser Channel
A functional block diagram of the LM96550 is shown in . It has
Continuous-wave (CW) applications are supported for low
power consumption down to VPP = -VNN = 3.3V with Mode
=HI.
an input buffer at its CMOS logic interface, which is powered
by VLL (2.5 to 5.0V). When EN=HI, driving a channel’s inputs
(PIN n or NIN n) HI will result in a positive or negative pulse
at the channel’s output pin (VOUT n), respectively. The output
pins VOUT are pulled to either the positive or negative sup-
plies, VPP or VNN by power MOSFETs.
Internally, the CMOS logic input signals are level shifted to
VDD = 10V and VDN = -10V for pulse transmission. The out-
puts of the level shifter drive the high-voltage P and N drivers
that control the output power MOSFETs, which are supplied
from the positive and negative rails VPP and VNN, respec-
tively. The high-voltage rails are designed for a maximum of
50V; however, they can be operated down to 3.3V. The nec-
essary gate-overdrive voltage levels for the output drivers are
internally generated from the high-voltage rails.
When PIN and NIN are both LO, Vout is actively clamped to
GNDHI at 0V. This clamping reduces harmonic distortions
compared to competing architectures that use bleeding re-
sistors for implementing the return to zero of the output. The
user must avoid the condition in which PIN and NIN are
both HI simultaneously, as this will damage the output
stage!
The impedance of the output stage can be controlled via the
Mode-pin. When the Mode = HI as shown, only one output
transistor pair drives the output resulting in a peak current of
600 mA at VPP = -VNN = 50V. When Mode=LO, a peak-cur-
rent of 2A is achievable resulting in faster transients at the
output. However, faster output transients can lead to signifi-
cant overshoot of the output signal. This can be avoided using
the lower drive current option.
Over-Temperature Protection (OTP) is implemented by con-
tinuously monitoring the on-chip temperature. The OTP out-
put (open drain) pin goes LO when the chip temperature
exceeds a critical level. Prior to this event, the user must en-
sure that the chip is powered down before fatal damage
occurs. In addition to a primary software controlled safety
shutdown, the OTP pin can be also be hard-wired to the EN
pin as a secondary safety measure.
7
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Timing Diagrams
RISE AND FALL TIME
The timing diagram shown in Figure 3 defines the rise and fall
times tr and tf.
30129604
FIGURE 3. Timing Diagram Defining Rise and Fall Times
tr and tf, respectively
INPUT TO OUTPUT DELAY
The timing diagram shown in Figure 4 defines the delays be-
tween the input and output signals.
30129605
FIGURE 4. Timing Diagram Defining Input-to-Output Delays Times
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8
Typical Performance Characteristics Unless otherwise stated, the following conditions apply.
VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, VPF = VPP-12V, VNF = VNN+8V, CL = 330pF, RL =
100Ω, TA = 25°C, Fin=5MHz, Mode=LO, EN=HI
Return-to-Zero Rise Time (RL = 2KΩ)
Return-to-Zero Fall Time (RL = 2KΩ)
30129609
30129614
Harmonic Distortion (8 pulses)
Differential Input vs. Pulser Output Phase Noise (Note 4)
30129610
30129611
Over Temperature Protection
Constant 5W Total Power (RL = 300Ω)
100% CW mode, Mode=HI, VSUB=-10V, VPF=-VNF=VPP-10V
120
15
100
80
60
40
20
0
12
C =150pF
L
9
6
3
0
C =330pF
L
C =470pF
L
114
134
OTP Trip Point (°C)
3
4
5
6
7
8
9
10
VPP=-VNN (V)
30129613
30129612
9
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Functional Description
Note that the case, PINn = NNn = HI is not allowed as it will damage the output transistors.
Logic inputs
Output
Voutn
EN
1
PINn
NINn
0
1
0
1
X
0
0
1
1
X
0V
1
VPP - 0.7V
VNN + 0.7V
not allowed
0V
1
1
0
Applications
POWER-UP AND POWER-DOWN SEQUENCES
VSUB must always be the most negative supply, i.e., it must be equal to or more negative than the most negative supply, VNN or
VDN. VPF ≥ VPP −14V AND VNF = ≤ VNN +14V at all times.
Power UP Sequence:
1. Turn ON VSUB, hold EN pin LO
2. Turn ON VLL
3. Turn ON VDD, VDN, VPP, VPF, VNN and VNF
Power DOWN Sequence:
1. Turn OFF VDD, VDN, VPP, VPF, VNN and VNF
2. Turn OFF VLL
3. Turn OFF VSUB
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10
Physical Dimensions inches (millimeters) unless otherwise noted
80-Lead LLP Package
NS Package Number SQA80A
11
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Notes
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