LM9822CCWM_技术文档

May 1999

N

LM9822 3 Channel 42-Bit Color Scanner Analog Front End

General Description

The LM9822 is a high performance Analog Front End (AFE) for

Key Specifications

image sensor processing systems. It performs all the analog and

mixed signal functions (correlated double sampling, color spe-

cific gain and offset correction, and analog to digital conversion)

necessary to digitize the output of a wide variety of CIS and

• Output Data Resolution

14 Bits

6MHz

5V±5%

• Pixel Conversion Rate

• Analog SupplyVoltage

• I/O Supply Voltage

3.3V±10% or 5V±5%

375mW

CCD sensors. The LM9822 has a 14 bit 6MHz ADC.

• Power Dissipation (typical)

Applications

Features

• Color Flatbed Document Scanners

• Color Sheetfed Scanners

• Multifunction Imaging Products

• Digital Copiers

• 6 million pixels/s conversion rate

• Digitally programmed gain and offset for red, green and blue

color balancing

• Correlated Double Sampling for lowest noise from CCD

sensors

• General Purpose Linear Array Imaging

• Compatible with CCD and CIS type image sensors

• InternalVoltage Reference Generation

• TTL/CMOS compatible input/output

Connection Diagram

D7

28

V

1

BANDGAP

D6

V

27

2

REFMID

D5

26

V

3

A

D4

AGND

4

25

D3

24

OS

5

R

LM9822

28 pin

SOIC

D2

D1

V

6

23

22

21

20

REF+

7

OS

G

V

D0

8

REF-

OS

B

V_D

9

V

A

19

18

17

16

DGND

CLMP

VSMP

MCLK

10

11

12

13

14

AGND

SEN

SDI

15

SDO

SCLK

Ordering Information

Temperature Range

0°C ≤ T_A≤ +70°C

NS Package

Number

Order Number

Device Marking

LM9822CCWM¹

LM9822CCWMX²

LM9822CCWM

M28B

1

2

Notes: - Rail transport media, 26 parts per rail, - Tape and reel transport media, 1000 parts per reel

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

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Absolute Maximum Ratings ^{(Notes 1& 2)}

Operating Ratings ^{(Notes 1& 2)}

Positive Supply Voltage (V⁺=V_A=V_D)

OperatingTemperature Range

V_ASupply Voltage

T

_MIN=0°C≤T_A≤T_MAX=+70°C

+4.75V to +5.25V

+3.0V to +5.25V

≤ 100mV

With Respect to GND=AGND=DGND

Voltage On Any Input or Output Pin

Input Current at any pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T_A= 25°C

ESD Susceptibility (Note 5)

Human Body Model

6.5V

-0.3V to V⁺+0.3V

±25mA

V

_DSupplyVoltage

V_D-V_A

±50mA

(Note 4)

OS_R, OS_G, OS_B

InputVoltage Range

-0.05V to _A+ 0.05V

SCLK, SDI, SEN, MCLK, VSMP, CLMP

InputVoltage Range

7000V

450V

-0.05V to V_D+ 0.05V

Machine Model

Soldering Information

Infrared, 10 seconds (Note 6)

Storage Temperature

235°C

-65°C to +150°C

Electrical Characteristics

The following specifications apply for AGND=DGND=0V, V_A=+5.0V_DC, V_D=+3.0 or +5.0V_DC, f_MCLK=12MHz. Boldface limits apply

for T_A=T_J=T_MINto T_MAX; all other limits T_A=T_J=25°C. (Notes 7, 8, 12 & 16)

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

CCD/CIS Source Requirements for Full Specified Accuracy and Dynamic Range

(Note 12)

Gain = 0.933

Gain = 3.0

Gain = 9.0

2.1

0.65

0.21

V

Sensor’s Maximum Peak Differential

Signal Range

V_{OS PEAK}

Full Channel Linearity (In units of 12 bit LSBs)

(Note 14)

+0.9

-0.4

+2

-0.9

DNL

INL

Differential Non-Linearity

LSB(max)

+5

-7

Integral Non-Linearity Error (Note 11)

±2.2

Analog Input Characteristics

OS , OS , OS_BInput Capacitance

5

pF

µA (max)

nA

R

G

Measured with OS = 3.5V_DC

CDS disabled

20

10

25

5

OS , OS , OS_BInput Leakage Current

R

G

CDS enabled

Coarse Color Balance PGA Characteristics

Monotonicity

bits (min)

.90

.96

V/V (min)

V/V (max)

G

₀(Minimum PGA Gain)

₃₁(Maximum PGA Gain)

PGA Setting = 0

PGA Setting = 31

0.93

3.0

2.95

3.07

V/V (min)

V/V (max)

x3 Boost Setting On

(Bit 5 of Gain Register is set)

2.86

3.08

V/V (min)

V/V (max)

x3 Boost Gain

3.0

Gain Error at any gain (Note 13)

±0.3

1.6

% (max)

Static OffsetDAC Characteristics (In units of 12 bit LSBs)

Monotonicity

6

bits (min)

13

24

LSB (min)

LSB (max)

OffsetDAC LSB size

PGA gain = 1

18.9

OffsetDAC Adjustment Range

PGA gain = 1

3

±585

±570

LSB (min)

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Electrical Characteristics ^(Continued)

The following specifications apply for AGND=DGND=0V, V_A=+5.0V_DC, V_D=+3.0 or +5.0V_DC, f_MCLK=12MHz. Boldface limits apply

for T_A=T_J=T_MINto T_MAX; all other limits T_A=T_J=25°C. (Notes 7, 8, 12 & 16)

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Internal Reference Characteristics

V

Mid Reference Output Voltage

Positive Reference Output Voltage

Negative Reference OutputVoltage

Differential Reference Voltage

2.5

3.5

1.5

V

REFMID

V

REF+ OUT

V_{REF- OUT}

∆V_REF

2.0

V

_{REF+ OUT}- V_{REF- OUT}

System Characteristics (In units of 12 bit LSBs) (see section 5.1, Internal Offsets)

Analog Channel Gain Constant

(ADC Codes/V)

Includes voltage reference

variation, gain setting = 1

1934

2281

LSB (min)

LSB (max)

C

2107

17.3

27

Pre-Boost Analog Channel Offset Error,

CCD Mode

-61

+94

LSB (min)

LSB (max)

V_OS1

V_OS2

V_OS3

Pre-Boost Analog Channel Offset Error,

CIS Mode

-49

+103

LSB (min)

LSB (max)

-124

+44

LSB (min)

LSB (max)

Pre-PGA Analog Channel Offset Error

Post-PGA Analog Channel Offset Error

-40

-130

+55

LSB (min)

LSB (max)

-38

DC and Logic Electrical Characteristics

The following specifications apply for AGND=DGND=0V, V_A=+5.0V_DC, V_D=+3.0 or +5.0V_DC, f_MCLK=12MHz. Boldface limits apply

for T_A=T_J=T_MINto T_MAX; all other limits _A=T_J=25°C. (Notes 7& 8)

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

SCLK, SDI, SEN, MCLK, VSMP,CLMP Digital Input Characteristics

V_IN(1)

V_IN(0)

Logical “1” Input Voltage

Logical “0” Input Voltage

V_A=5.25V

V_A=4.75V

2.0

0.8

V (max)

V (min)

V

_IN=V_A

0.1

-0.1

µA(max)

I_IN

Input Leakage Current

Input Capacitance

V_IN=DGND

C_IN

5

pF

D0-D7 Digital Output Characteristics

V_OUT(1)

V_OUT(0)

Logical “1” Output Voltage

Logical “0” Output Voltage

I_OUT=-360µA

I_OUT=1.6mA

0.8*V_D

0.2*V_D

V (min)

V (max)

Power Supply Characteristics

Operating

75

675

210

2

108

900

475

25

mA (max)

µA (max)

I_A

Analog Supply Current

Power Down

Operating

I_D

Digital Supply Current (Note 15)

Power Down

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AC Electrical Characteristics

The following specifications apply for AGND=DGND=0V, V_A=+5.0V_DC, V_D=+3.0 or +5.0V_DC, f_MCLK=12MHz, except where noted

otherwise. Boldface limits apply for _A=T_J=T_MINto T_MAX; all other limits T_A=T_J=25°C. (Notes 7& 8)

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

f_MCLK

Maximum MCLK frequency

MCLK period

12

MHz (min)

ns (min)

t_MCLK

83

40

60

%(min)

%(max)

MCLK duty cycle

t_SCLK

t_SEN

t_SSU

t_SH

Serial Clock Period

Serial Enable high time

SDI setup time

t_MCLK(min)

ns (min)

1

3

1

SDI hold time

3

ns (min)

V

_D= 5.0V

8.5

19

20

t_SDDO

SCLK edge to new valid data

ns (max)

V_D= 3.3V

t_VSU

t_VH

t_CSU

t_CH

VSMP setup time

VSMP hold time

CLMP setup time

CLMP hold time

1

3

ns (min)

1

3

V

_D= 5.0V

16

25

ns (max)

t_DDO

MCLK edge to new valid data

V_D= 3.3V

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,

but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characte ristics. The guaranteed specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the list ed test conditions.

Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.

Note 3: When the input voltage (V ) at any pin exceeds the power supplies (V <GND or V >V or V ), the current at that pin should be limited to 25mA. The 50m

IN

A

D

maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T max, Θ and the ambient temperature, T . The maximum allow-

JA

J

A

able power dissipation at any temperature is P = (T max - T ) / Θ . T max = 150°C for this device. The typical thermal resistance ( Θ ) of this part when board mounted

JA JA

D

J

A

J

is 69°C/W for the M28B SOIC package.

Note 5: Human body model, 100pF capacitor discharged through a 1.5k Ω resistor. Machine model, 200 pF capacitor discharged through a 0Ω resistor.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear

Data Book for other methods of soldering surface mount devices.

Note 7: Two diodes clamp the OS analog inputs to AGND and V as shown below. This input protection, in combination with the external clamp capacitor and the output

A

impedance of the sensor, prevents damage to the LM9822 from transients during power-up.

V

A

TO INTERNAL

CIRCUITRY

OS Input

AGND

Note 8: To guarantee accuracy, it is required that

V and V be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When

A D

both V and V are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin.

A

D

5

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Electrical Characteristics ^(Continued)

Note 9: Typicals are at T =T =25°C, f

= 12MHz, and represent most likely parametric norm.

MCLK

J

A

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer

function of the AFE.

Note 12: The sensor’s maximum peak differential signal range is defined as the peak sensor output voltage for a white (full scale) image, with respect to the dark reference

level.

CIS Output Signal

CCD Output Signal

V_WHIT

V_RFT

V_WHITE

Black Level

V_REF

Note 13: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated using:

V

---

PGA code

32

31

Gain

=

G

+ X---------------------------- where

X

=

(

G

–

)

G

0

----- .

PGA

0

31

V

32

Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, DOE = 0, and a single OS input with a gain register setting of 1 (000001b) and

an offset register setting of 0 (000000b).

Note 15: The digital supply current (ID) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D7 - D0).

The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*V /t

MCLK

where Nd is total number of data pins, Psw is the probability of

is the period of the MCLK input. For most applications, Nd

D

each data bit switching, CL is the capacitive loading on each data pin, V is the digital supply voltage and t

D

MCLK

is 8, Psw is ≈ 0.5, and V is 5V,and the switching current can be calculated from: Isw = 40*CL/tMCLK. (With

at 3.3V, the equation becomes: Isw = 26.4*CL/t

D

.) For

MCLK

D

example, if the capacitive load on each digital output pin (D7 - D0) is 20pF and the period of t

is 1/12MHz or 83ns, then the digital switching current would be 9.6mA.

MCLK

The calculated digital switching current will be drawn through the V pin and should be considered as part of the total power budget for the LM9822.

D

Note 16: All specifications quoted in LSBs are based on 12 bit resolution.

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Typical Performance Characteristics

Full Channel DNL and INL

(Divide by 2, Monochrome Mode, 6 MHz Pixel Rate)

Typical 14 Bit DNL

Typical 14 Bit INL

10

5

2

1.5

1

0

LSB

-5

-10

-15

LSB

0.5

0

-0.5

-1

0

4096

8192

12288 16384

0

4096

8192

12288

16384

OutputCode

Typical 12 Bit DNL

Typical 12 Bit INL

2

1.5

1

1.5

1

0.5

0

LSB

0.5

0

LSB -0.5

-1

-1.5

-2

-2.5

-0.5

-1

0

1024

2048

OutputCode

3072

4096

0

1024

2048

OutputCode

3072

4096

Note: The LM9822 provides 14-bit data for high resolution imaging applications. The typical full channel device performance is shown

in the above graphs. In many applications, particularly those where high speed is important, or where lower cost CCD and CIS sensors

are used, the signal source is only accurate to 12 bits. In these applications, only 12-bit of data may be used. 12-bit DNL and INL plots

have also been provided to illustrate the performance of the LM9822 in these applications.

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Pin Descriptions

Analog Power

Data Output

V

The two _Apins are the analog supply pins.

They should be connected to a voltage

source of +5V and bypassed to AGND with a

0.1µF monolithic capacitor in parallel with a

10µF tantalum capacitor.

A

-

Data Output pins. The 14 bit conversion

results of the ADC are multiplexed in 8 bit

bytes to D7-D0 synchronous with MCLK.

The MSB consists of data bits d13-d6 on

pins D7-D0 and the LSB consists of d5-d0

on pins D7-D3 with D1 and D0low.

D7 D0

AGND

These two pins are the ground returns for

the analog supplies.

Serial Input/Output

V

D

This is the positive supply pin for the digital

I/O pins. It should be connected to a voltage

source between +3.3V and +5.0V and be

bypassed to DGND with a 0.1µF monolithic

capacitor in parallel with a 10µF tantalum

capacitor.

SCLK

SDO

Serial Shift Clock. Input data on SDI is valid

on the rising edge of SCLK. The minimum

SCLK period is 1 t_MCLK

.

Serial Data Output. Data bits are shifted out

of SDO on falling edges of SCLK. The first

eight falling edges of SCLK after SEN goes

low will shift out eight data bits (MSB first)

from the configuration register addressed

during the previous SEN low time.

DGND

This is the ground return for the digital sup-

ply.

Analog Input/Output

SDI

Serial Data Input. A read/write bit, followed

by a four address bits and eight data bits is

shifted into SDI, MSB first. Data should be

valid on the rising edge of SCLK. If the

read/write bit is a “0” (a write), then the

shifted data bits will be stored. If the

read/write bit is a “1” (a read), then the data

bits will be ignored, and SDO will shift out

the addressed register’s contents during the

next SEN low time.

OS , OS , OS

Analog Inputs. These inputs (for Red,

Green, and Blue) should be tied to the sen-

sor’s OS (Output Signal) through DC block-

ing capacitors.

R

G

B

V

Voltage reference bypass pins. V_REF+

,

REF+

REFMID

,

V_REFMID, and V_REF-should each be

REF-

bypassed to AGND through a 0.1uF mono-

lithic capacitor.

Timing Control

SEN

Shift enable and load signal. When SEN is

low, data is shifted into SDI. When SEN

goes high, the last thirteen bits (one

read/write, four address and eight data)

shifted into SDI will be used to program the

addressed configuration register. SEN must

be high for at least 3 MCLK cycles between

SEN low times.

MCLK

VSMP

Master clock input. The ADC conversion

rate will be 1/2 of MCLK. 12MHz is the max-

imum frequency for MCLK.

Sample timing input signal. If VSMP is high

on the rising edge of MCLK, the input is

sampled on the rising edge of the next

MCLK. The reference signal for the next

pixel will be sampled one to four MCLKs

later, depending on the value in the

CDSREF configuration bits. If CDS is not

enabled, the internal reference will be sam-

pled during the reference sample time.

Connection Diagram

The number of MCLK cycles between

VSMP pulses determines the pixel rate.

Timing Diagrams 1 through 6 illustrate the

VSMP timings for all the valid pixel rates.

D7

D6

D5

V

28

1

BANDGAP

V

27

26

25

24

2

REFMID

V

3

A

D4

D3

D2

D1

AGND

4

OS

R

5

6

7

8

Note: See the applications section of the

datasheet for the proper timing relationships

between VSMP and MCLK.

LM9822

28 pin

SOIC

V

23

22

21

REF+

OS

G

V

D0

REF-

CLMP

Clamp timing input. If CLMP and VSMP are

high on the rising edge of MCLK, all three

OS inputs will be internally connected to

OS

B

V_D

20

19

18

17

16

15

9

V

A

DGND

CLMP

VSMP

MCLK

10

11

12

13

14

AGND

SEN

V

_CLAMPduring the nextpixel. V_CLAMPis either

VREF+ or VREF- depending on the state of

the Signal Polarity bit in the Sample Mode

register (Reg. 0, Bit 4).

SDI

SDO

SCLK

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Timing Diagrams

OS , OS

R

,

G

OS

B

MCLK

VSMP

ADC Clock

(internal)

N-1

N

Sample Signal

Level

Sample Reference

Level

N

N+1

BH

D7 -D0

GH

GL

BH

BL

RH

RL

GH

GL

BL

RH

N-5

N-4

H = d13-d6

L = d5-d0

DOE (Register 0, Bit 4) = 0

Divide by 6 Color Mode Sample and Data Output Timing

Diagram 1:

OS

G

MCLK

VSMP

ADC Clock

(internal)

N-1

N

Sample Signal

Level

Sample Reference

Level

N

XX

DOE (Register 0, Bit 4) = 0

N+1

XX

D7 -D0

XX

GH

GL

XX

GH

N-4

H = d13-d6

L = d5-d0

Divide by 6 Monochrome Mode Sample and Data Output Timing (Green Input shown)

Diagram 2:

OS , OS

,

G

R

OS

B

MCLK

VSMP

ADC Clock

(internal)

Sample Signal

Level

Sample Reference

Level

N-1

N

N+1

D7 -D0

XX

RH

RL

GH

GL

BH

BL

XX

RH

RL

GH

N-4

N-3

H = d13-d6

L = d5-d0

DOE (Register 0, Bit 4) = 0

Divide by 8 Color Mode Sample and Data Output Timing

Diagram 3:

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Timing Diagrams ^(Continued)

OS

G

MCLK

VSMP

ADC Clock

(internal)

N

Sample Signal

Level

Sample Reference

Level

N-1

N

N+1

XX

D7 -D0

XX

GH

GL

XX

GH

GL

N-4

N-3

H = d13-d6

L = d5-d0

DOE (Register 0, Bit 4) = 0

Divide by 8 Monochrome Mode Sample and Data Output Timing (Green Input Shown)

Diagram 4:

OS

G

MCLK

VSMP

ADC Clock

(internal)

N-1

N+1

N+2

N

Sample Signal

Level

Sample Reference

Level

N

N+1

N+2

GL

CDSREF = 00

D7 -D0

GH

GL

N-11

DOE (Register 0, Bit 4) = 0

GH

GL

N-10

GH

GL

N-9

H = d13-d6

L = d5-d0

Divide by 3 Monochrome Mode Sample and Data Output Timing (Green Input shown)

Diagram 5:

OS

G

MCLK

VSMP

ADC Clock

(internal)

N-1

N+2

N+3

N

N+1

Sample Signal

Level

Sample Reference N-1

N

N+1

N+2

GL

N+3

GL

N+4

GL

Level

CDSREF = 00

D7 -D0

GH

GL

GH

GL

N-10

GH

N-11

N-9

N-8

N-7

H = d13-d6

L = d5-d0

DOE (Register 0, Bit 4) = 0

Divide by 2 Monochrome Mode Sample and Data Output Timing (Green Input shown)

Diagram 6:

10

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Timing Diagrams ^(Continued)

OS , OS

R

,

G

OS

B

MCLK

VSMP

Sample Signal

Sample Reference

D3 -D0

CDSREF=00

CDSREF=01

CDSREF=10

CDSREF=11

Programmable Reference Sample Timing

Diagram 7:

OS

MCLK

VSMP

CLMP

N-1

N+1

N+2

N

Sample Signal

Sample Reference

N

N+1

N+2

CDSREF = 00

Clamp On

(internal signal)

Clamp Timing With SMPCL = 0

Diagram 8:

OS

MCLK

VSMP

CLMP

N-1

N+1

N+2

N

Sample Signal

Sample Reference

N

N+1

N+2

CDSREF = 00

Clamp On

(internal signal)

Clamp Timing With SMPCL = 1

Diagram 9:

SCLK

SEN

SDI

XX

0

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

XX

R/W bit

Configuration Register Serial Write Timing

Diagram 10:

SCLK

SEN

SDI

XX

1

A3 - A0

XX

1

A3 - A0

b7 - b0

SDO

XX

R/W bit

Configuration Register Serial Read Timing

Diagram 11:

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Timing Diagrams ^(Continued)

t

SCLK

1/2 t

SCLK

t

SEN

SDI

t

SH

SSU

SH

SSU

D2

D1

D0

XX

R/W

D7

A3

D6

A2

A1

D4

A0

D3

D7

D2

t

SDDO

SDO

XX

D5

Serial Input and Output Timing

Diagram 12:

t

MCLK

VSMP

t

VSU

VH

t

CSU

CH

CLMP

t

DDO

DOE = 1

DOE = 0

D7 - D0

t

DDO

D7 - D0

MCLK, VSMP and CLMP Input Timing and Data Output Timing

Diagram 13:

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Table 1: Configuration Register Address Table

Address

(Binary)

Register Name and Bit Definitions

B5 B4 B3 B2

Sample Mode (Power Up Default = 62h)

CDS Polarity SMPCL CDSREF1 CDSREF0

Red Offset Setting (Power Up Default = 00h)

Polarity MSB

Green Offset Setting (Power Up Default = 00h)

Polarity MSB

Blue Offset Setting (Power Up Default = 00h)

Polarity MSB

Red Gain Setting (Power Up Default = 00h)

x3 MSB

Green Gain Setting (Power Up Default = 00h)

x3 MSB

Blue Gain Setting (Power Up Default = 00h)

x3 MSB

Color Mode (Power Up Default = 00h)

N/A N/A N/A N/A

Test Register 0 (Power Up Default = 00h)

A3

0

A2

A1

0

A0

0

B7

I/O Mode

N/A

0

B6

DOE

N/A

0

B1

B0

PD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LSB

CM0

0

CM1

0

Test Register 1 (Power Up Default = 10h)

0

1

0

Test Register 2 (Power Up Default = 00h)

0

13

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Table 2: Configuration Register Parameters

Power-Up Default Register Settings are shown in Bold Italics

Parameter

Control Bits

(Address)

Result

Sample Mode (0)

B7

0

1

I/O Mode

Normal Output Driver Operation

Reduced Slew Rate Output Driver Operation

(0)

B6

0

DOE

(Data Output Edge)

(0)

D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting for

lowest noise and best overall performance.

1

D7-D0 are clocked out (change) on the rising edge of MCLK

B5

0

1

CDS (Enable)

(0)

CDS disabled (CIS)

CDS Enabled (CCD)

B4

0

1

Signal Polarity

(0)

Negative Polarity (CCD) Clamping to V_REF+

Positive Polarity (CIS) Clamping to V_REF-

B3

0

1

SMPCL

(0)

Clamp is on for 1 MCLK before reference sampled

Clamp is on between the reference and the signal sample points

B2

0

1

B1

0

1

0

1

Reference (for pixel N+1) sampled 1 MCLK cycle after signal (for pixel N) sampled

Reference (for pixel N+1) sampled 2 MCLK cycle after signal (for pixel N) sampled

Reference (for pixel N+1) sampled 3 MCLK cycle after signal (for pixel N) sampled

Reference (for pixel N+1) sampled 4 MCLK cycle after signal (for pixel N) sampled

CDSREF

(0)

PD

(Power Down)

(0)

B0

0

1

Operating

Low Power Standby

14

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Table 2: Configuration Register Parameters ^(Continued)

Power-Up Default Register Settings are shown in Bold Italics

Parameter

Control Bits

(Address)

Result

Red, Green and Blue Offset DAC Settings (1, 2 & 3)

B5

0

1

Offset Polarity

Offset Value

Positive Offset

Negative Offset

B4(M

SB)

B3

B2

B3

B1

B2

B0(LSB) Typical Offset = 20LSBs * Offset Value * PGA Gain

Typical Offset (with PGA Gain = 1)

B5

(SIGN

)

0

• • •

0

1

• • •

1

B4

(MSB)

0

• • •

1

0

B1

B0

(LSB)

0

1

0

• • •

0

1

0

1

12 bit LSBs

0.00

+20

0

• • •

1

0

• • •

1

0

• • •

1

0

• • •

1

0

1

• • •

1

0

1

• • •

1

+40

• • •

+600

+620

0

-20

-40

• • •

-600

-620

Typical Offset

Values

0

• • •

1

0

• • •

0

1

Red, Green and Blue Gain Settings (4, 5 & 6)

B5

0

1

Boost Gain Enable

Boost Gain = 1V/V

Boost Gain = 3V/V

B4(M

SB)

PGA Gain Value

Gain

B3

PGA Gain (V/V) =.933 + 0.0667 * (PGA Gain Value)

B2

B1

B0(LSB)

Gain = Boost Gain * PGA Gain

15

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Table 2: Configuration Register Parameters ^(Continued)

Power-Up Default Register Settings are shown in Bold Italics

Parameter

Control Bits

(Address)

Result

B5

B4

(MSB)

0

B3

B2

B1

B0

(LSB)

0

1

Typical Gain

(V/V)

0.93

x3)

0

(

0

1.00

0

1

0

1.07

• • •

0

• • •

1

• • •

1

• • •

1

• • •

0

• • •

1

• • •

2.87

0

1

0

2.93

Typical Gain Values

0

• • •

1

• • •

0

1

• • •

0

1

• • •

0

1

• • •

0

1

• • •

0

3.00

• • •

2.79

1

0

1

3.00

1

0

1

0

3.20

• • •

1

• • •

1

• • •

1

• • •

1

• • •

0

• • •

1

• • •

8.60

1

0

8.80

1

9.00

Color Mode (7)

B1

0

B0

0

Color

Color Mode

0

1

0

1

Monochrome - Red

Monochrome - Green

Monochrome - Blue

Reserved Register 0 (8)

Register 0

Register 1

Register 2

0 0 0 0 0 0 0 0

Reserved

Reserved, always set to 00h.

Reserved, always set to 10h.

Reserved, always set to 00h.

Reserved Register 1 (9)

0 0 0 1 0 0 0 0

Reserved Register 2 (A)

0 0 0 0 0 0 0 0

16

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of Q1, and other sources of error. When the shift register clock

(Ø1) makes a low to high transition (period 4), the electrons from

the next pixel flow into C1. The charge across C1 now contains

the voltage proportional to the number of electrons plus V_RESID-

_UAL, an error term. If OS is sampled at the end of period 3 and

that voltage is subtracted from the OS at the end of period 4, the

V_RESIDUALterm is canceled and the noise on the signal is

reduced ([V_SIGNAL+V_RESIDUAL]-V_RESIDUAL= V_SIGNAL). This is the

principal of Correlated Double Sampling.

Applications Information

1.0 Introduction

The LM9822 is a high performance scanner Analog Font End

(AFE) for image sensor processing systems. It is designed to

work with color CCD and CIS image sensors and provides a full 3

channel sampling, gain and offset correction system, coupled

with a 14 bit high speed analog to digital converter. A typical

application of the LM9822 is in a color flatbed document scanner.

The image sensing and processing portion of the system would

be configured similar to that shown in Figure 1.

3.0 CIS Mode (CDS Off, Selectable Signal Polarity)

The also LM9822 supports CIS (Contact Image Sensor) devices.

The output signal of a CIS sensor (Figure 3) differs from a CCD

signal in two primary ways: its output usually increases with

increasing signal strength, and it does not usually have a refer-

ence level as an integral part of the output waveform of every

pixel.

To Host

CCD Control

ASIC

OS_R

AFE Control

OS_G

OS_B

8

8 Output Data

OS (CIS)

RAM

Other scanner elements

omitted for simplicity.

Figure 1: LM9822 in Basic Color Scanner

OS (CCD)

2.0 CDS Correlated Double Sampler

1

2

3

4

5

The LM9822 uses a high-performance CDS (Correlated Double

Sampling) circuit to remove many sources of noise and error from

the image sensor output signal. It also supports CIS image sen-

sors with a single ended sampling mode.

CIS

Figure 3:

When the LM9822 is in CIS (CDS off) mode (Register 0, B5=1), it

uses either V or V as the reference (or black) voltage for

REF+

REF-

each pixel (depending on the signal polarity setting (Register 0,

Bit 4)). If the signal polarity is set to one, then V_REF-will be sam-

Figure 2 shows the output stage of a typical CCD and the result-

ing output waveform:

pled as the reference level. If it is set to zero, then V

sampled as the reference level.

will be

REF+

V_DD

Q1

C1

RS (RESET)

4.0 Programmable Gain

e-

Q2

The output of the Sampler drives the input of the x3 Boost gain

stage. The gain of each x3 Boost gain is 3V/V if bit B5 of that

color’s gain register (register 4,5, or 6) is set, or 1V/V if bit B5 is

cleared. The output of each x3 gain stage is the input an offset

DAC and the output of each offset DAC is the input to a PGA

(Programmable Gain Amplifier). Each PGA provides 5 bits of gain

correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The x3

Boost gain stage and the PGA can be combined for an overall

gain range of 0.93V/V to 9.0V/V (-.6 to 19dB). The gain setting for

each color (registers 4, 5 and 6) should be set during calibration

to bring the maximum amplitude of the strongest pixel to a level

just below the desired maximum output from the ADC. The PGA

gain is determined by the following equation:

OS

(from shift register)

V_SS

Ø1

RS

OS

1

2

3

4

5

Figure 2: CDS

V

---

PGA Gain

= 0.933 + .0667 (value in bits B4-B0)

Capacitor C1 converts the electrons coming from the CCD’s shift

register to an analog voltage. The source follower output stage

(Q2) buffers this voltage before it leaves the CCD. Q1 resets the

voltage across capacitor C1 between pixels at intervals 2 and 5.

When Q1 is on, the output signal (OS) is at its most positive volt-

age. After Q1 turns off (period 3), the OS level represents the

residual voltage across C1 (V_RESIDUAL). V_RESIDUALincludes

charge injection from Q1, thermal noise from the ON resistance

PGA Gain

Equation 1:

If the x3 Boost gain is enabled then the overall signal gain will be

three times the PGA gain.

17

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Applications Information (Continued)

5.0 Offset DAC

6.0 Clamping

The Offset DACs remove the DC offsets generated by the sensor

and the LM9822’s analog signal chain (see section 5.1, Internal

Offsets). The DAC value for each color (registers 1,2 and 3)

should be set during calibration to the lowest value that still

results in an ADC output code greater than zero for all the pixels

when scanning a black line. With a PGA gain of 1V/V, each LSB

of the offset DAC typically adds the equivalent of 20 ADC LSBs,

providing a total offset adjustment range of ±590 ADC LSBs. The

Offset DAC’s output voltage is given by:

To perform a DC restore across the AC coupling capacitors at the

beginning of every line, the LM9822 implements a clamping func-

tion. The clamping function is initiated by asserting the CLMP

input. If CLMP and VSMP are both high on a rising edge of

MCLK, all three OS inputs will be internally connected to V_REF+or

V

_REF-during the next pixel, depending on bit 4 of register 0. If bit 4

is set to one (positive signal polarity), then the OS input will be

connected to V_REF-. If bit 4 is set to zero (negative signal polarity),

then it will be connected to V

.

REF+

6.1 Clamp Capacitor Selection

V

= 9.75mV • (value in B4 - B0)

DAC

Equation 2:

Offset DAC OutputVoltage

The output signal of many sensors rides on a DC offset (greater

than 5V for many CCDs) which is incompatible with the LM9822’s

5V operation. To eliminate this offset without resorting to addi-

tional higher voltage components, the output of the sensor is AC

In terms of 12 bit output codes, the offset is given by:

Offse = t20L SB•s(value in B4 - B0) • PGA Gain

coupled to the LM9822 through a DC blocking capacitor, C_CLAMP

.

Offset in ADC Output Codes

Equation 3:

The sensor’s DOS output, if available, is not used. The value of

this capacitor is determined by the leakage current of the

LM9822’s OS input and the output impedance of the sensor. The

leakage through the OS input determines how quickly the capaci-

tor value will drift from the clamp value of V_REF+or V_REF-, which

then determines how many pixels can be processed before the

droop causes errors in the conversion (±0.1V is the recom-

mended limit for CDS operation). The output impedance of the

sensor determines how quickly the capacitor can be charged to

the clamp value during the black reference period at the begin-

ning of every line.

The offset is positive if bit B5 is cleared and negative if B5 is set.

Since the analog offset is added before the PGA gain, the value

of the PGA gain must be considered when selecting the offset

DAC values.

5.1 Internal Offsets

Figure 4 is a model of the LM9822’s internal offsets. Equation 4

shows how to calculate the expected output code given the input

voltage (VIN), the LM9822 internal offsets ( OS1, VOS2, VOS3),

the programmed offset DAC voltage (V DAC), the programmed

gains (GB, GPGA) and the analog channel gain constant C.

The minimum clamp capacitor value is determined by the maxi-

mum droop the LM9822 can tolerate while converting one sensor

line. The minimum clamp capacitor valueis much smaller for CDS

mode applications than it is for CIS mode applications.

C is a constant that combines the gain error through the AFE, ref-

erence voltage variance, and analog voltage to digital code con-

version into one constant. Ideally, C = 2048 codes/V (4096

codes/2V) in 12 bit LSBs. Manufacturing tolerances widen the

range of C (see Electrical Specifications).

Inside LM9822

C_I

C_S

OS

C_CLAMP

P2

P1

x3 Boost

1V/V or

3V/V

PGA

0.93V/V to

3V/V

V_IN

+

V_OS2

+

V_OS1

G_PGA

G_B

ADC

V_IN

D_OUT

Σ

+

V_OS3

CDS Mode Input Circuitry

V_DAC

Inside LM9822

C_I

Offset

DAC

C_S

P1

OS

P2

Internal Offset Model

Figure 4:

V_IN

C_CLAMP

D

= (((V + V )G + V

+ V

)G

OS2 PGA

+ V

)C

OS3

OUT

IN

OS1

B

DAC

+

Vref

Equation 4: Output code calculation with internal offsets

Equation 5 is a simplification of the output code calculation,

neglecting the LM9822’s internal offsets.

CIS Mode Input Circuitry

Input Circuitry

Figure 5:

The LM9822 input current is considerably less when the LM9822

is operating in CDS mode. In CDS mode, the LM9822 average

input current is no more than 25nA. With CDS disabled, which will

likely be the case when CIS sensors are used, the LM9822 input

impedance will be 1/(f _Sample*C_S). where f_Sampleis the sample

rate of the analog input and C_Sis 2pF.

D

= (V

G

+ V

)G C

PGA

OUT

IN

B

DAC

Equation 5: Simplified output code calculation

18

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Applications Information (Continued)

6.1.1 CDS mode Minimum Clamp Capacitor Calculation:

sample reference time, if SMPCL=1, the clamps are on immedi-

ately after the sample reference time. If the LM9822 is operated

in Divide By 2 mode, then the clamp is on 50% of the time when

CLMP is high. In this case the available charge time per line can

be calculated using:

The following equation takes the maximum leakage current into

the OS input, the maximum allowable droop, the number of pixels

on the sensor, and the pixel conversion rate, f_VSMP, and provides

the minimum clamp capacitor value:

Number of optical black pixels

t

= -------------------------------------------------------------------------------

CLAMP

2f

VSMP

i

C

= --------dt

CLAMP MIN

Clamp Time Per Line Calculation

dV

Equation 12:

leakage current (A)number of pixel

For example, if a sensor has 18 black reference pixels and f_VSMP

is 2MHz with a 50% duty cycle, then tCLAMP is 4.5µs. Other

“Divide By” modes will have lower or higher clamp duty cycles

= ---------------------------------------------------------------------------------------------

max droop(V)

f

VSMP

Calculation

CDS mode C

Equation 6:

CLAMP MIN

accordingly, depending on the SMPCL setting. See

Diagram 8,

For example, if the OS input leakage current is 25nA worst-case,

the sensor has 2700 active pixels, the conversion rate is 2MHz

(t_VSMP= 500ns), and the max droop desired is 0.1V, the minimum

clamp capacitor value is:

and

Clamp Timing With SMPCL = 0

Diagram 9, Clamp Timing

.

With SMPCL = 1

The following equation takes the number of optical black pixels,

the amount of time (per pixel) that the clamp is closed, the sen-

sor’s output impedance, and the desired accuracy of the final

clamp voltage and provides the maximum clamp capacitor value

that allows the clamp capacitor to settle to the desired accuracy

within a single line:

25n 270

C

= ----------------------------

0.1V 2MHz

CLAMP MIN

= 340p

CDS mode C_{CLAMP MIN}Example

Equation 7:

t

1

C

= -------------------------------------

Rln(accuracy)

6.1.2 CIS mode Minimum Clamp Capacitor Calculation:

CLAMP MAX

t

If CDS is disabled, then the maximum LM9822 OS input leakage

current can be calculated from:

CLAMP

1

= -------------------------- --------------------------------

R

ln(accuracy)

CLAMP

I

= V

f

C

leakage

SAT SampCLK SAMP

Equation 13: CCLAMP MAX for a single line of charge time

CIS mode Input Leakage Current Calculation

Equation 8:

Where t_CLAMPis the amount of time (per line) that the clamp is

on, R_CLAMPis the output impedance of the CCD plus 50Ω for the

LM9822 internal clamp switch, and accuracy is the ratio of the

worst-case initial capacitor voltage to the desired final capacitor

voltage. If tCLAMP is 4.5µs, the output impedance of the sensor is

1500Ω, the worst case voltage change required across the capac-

itor (before the first line) is 5V, and the desired accuracy after

clamping is to within 0.1V (accuracy = 5/0.1 = 50), then:

where VSAT is the peak pixel signal swing of the CIS OS output

and CSAMP is the capacitance of the LM9822 internal sampling

capacitor (2pF). Inserting this into Equation 6 results in:

i

C

= --------dt

dV

CLAMP MIN

V

t

SAT

SampCLK

-----------------------------------num pixel

= --------------------------- C

SAMP

t

max droop(V)

SampCLK

4.5µs

1

C

= -------------------------------

CLAMP MAX

CIS mode C_{CLAMP MIN}Calculation

Equation 9:

155 Ωln(50)

= 728p

with CSAMP equal to 2pF and V SAT equal to 2V (the LM9822

maximum input signal), then Equation 9 reduces to:

C

Example

Equation 14:

The final value for C

CLAMP MAX

should be less than or equal to

C_{CLAMP MAX}, but no less than C_{CLAMP MIN}.

CLAMP

4p(F)(V)

-----------------------------------

C

=

num pixels

CLAMP MIN

max droop(V)

CIS mode C_{CLAMP MIN}Calculation

Equation 10:

In some cases, depending primarily on the choice of sensor,

C_{CLAMP MAX}may actually be less than C_{CLAMP MIN}, meaning that

the capacitor can not be charged to its final voltage during the

black pixels at the beginning of a line and hold it’s voltage without

drooping for the duration of that line. This is usually not a problem

because in most applications the sensor is clocked continuously

as soon as power is applied. In this case, a larger capacitor can

be used (guaranteeing that the C_{CLAMP MIN}requirement is met),

and the final clamp voltage is forced across the capacitor over

multiple lines. This equation calculates how many lines are

required before the capacitor settles to the desired accuracy:

C

In CIS mode (CDS disabled), the max droop limit must be much

more carefully chosen, since any change in the clamp capacitor’s

DC value will affect the LM9822 conversion results. If a droop of

one 10 bit LSB across a line is considered acceptable, then the

allowed droop voltage is calculated as: 2V/1024, or approximately

2mV. If there are 2700 active pixels on a line then:

4p(F)(V)

2mV

---------------------

270

C

=

CLAMP MIN

= 5.4uF

CIS mode C

Calculation Example

Equation 11:

Initial Error Voltag

Final Error Voltag

CLAMP

CLAMP MIN

----------------------------------------------------

line = sR

------------------------ ln

CLAMP

t

CLAMP

Number of Lines Required for Clamping

Equation 15:

6.1.3 Maximum Clamp Capacitor Calculation:

Using the values shown before and a clamp capacitor value of

0.01µF, this works out to be:

The maximum size of the clamp capacitor is determined by the

amount of time available to charge it to the desired value during

the optical black portion of the sensor output. The internal clamp

occurs when CLMP and VSMP are both high on a rising edge of

MCLK. If SMPCL=0, the clamps are on immediately before the

5V

0.1V

0.01µF

lines = 155 ------------------- ln

4.5µs

-----------

= 13.5 lines

Clamping Lines Required Example

Equation 16:

19

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Applications Information (Continued)

In this example, a 0.01µF capacitor takes 14 lines after power-up

to charge to its final value. On subsequent lines, the only error will

be the droop across a single line which should be significantly

less than the initial error. If the LM9822 is operating in CDS

mode and multiple lines are used to charge up the clamping

capacitors after power-up, then a clamp capacitor value of

0.01µF should be significantly greater than the calculated

9.1 Output Driver Mode

The Output Driver Mode bit is normal set to 0. This bit can be set

to 1 to reduce the slew rate of the output drivers.

9.2 DOE (Data Output Edge) Setting

The Data Output Edge bit selects which edge of MCLK is used to

clock output data onto the output pins. For lowest noise perfor-

mance, this bit should be set to 0. With this setting, new data is

placed on the D7-D0 pins on every falling edge of MCLK. See

Diagrams 1 through 6 and Diagram 13 for more information on

data output timing for the different Divide By modes, and detailed

timing of the output data signals.

C

_{CLAMP MIN}value and can virtually always be used.

If the LM9822 is operating in CIS mode, then significantly larger

clamp capacitors must be used. Fortunately, the output imped-

ance of most CIS sensors is significantly smaller than the output

impedance of CCD sensors, and R _CLAMPwill be dominated by

the 50Ω from the LM9822 internal clamp switch. With a smaller

R

_CLAMPvalue, the clamp capacitors will chargefaster.

The bit can be set to 1 to adjust the data output timing for some

applications, but the noise performance of the LM9822 may be

somewhat degraded.

7.0 Power Supply Considerations

The LM9822 analog supplies ( _A) should be powered by a single

+5V source. The two analog supplies are brought out individually

to allow separate bypassing for each supply input. They should

not be powered by two or more different supplies.

9.3 CDS Enable

The CDS Enable bit determines whether the sampling section of

the LM9822 operates in Correlated Double Sampling mode or in

Single Ended Sampling mode. CDS mode is normally used with

Each supply input should be bypassed to its respective ground CCD type sensors, while Single Ended mode is normally used

with a 0.1µF capacitor located as close as possible to the supply

input pin. A single 10µF tantalum capacitor should be placed near

the V_Asupply pins to provide low frequency bypassing.

with CIS type sensors.

9.4 Signal Polarity

Whether the LM9822 is operating in Correlated Double Sampling

Mode, or Single Ended Sampling mode, the basic sampling oper-

ation is the same. First a reference level is sampled, then a signal

level is sampled. For CDS mode operation, if the signal level is

lower in voltage than the reference level, the Signal Polarity bit

should be set to 0. This is the normal setting for CCD type sen-

sors. If the signal level is more positive than the reference level,

the Signal Polarity bit would be set to 1 for Positive Polarity mode.

The V_Dinput can be powered at 3.3Vor 5.0V. Power should be

supplied by a clean, low noise linear power supply, with a 0.1 µF

ceramic capacitor and a 10 µF tantalum capacitor placed near the

V_Dand DGND pins. If possible, a separate power and ground

plane should be provided to isolate the noisy digital output signals

from the sensitive analog supply pins. If the V voltage is lower

D

than V_A, a separate linear regulator should be used. If V_Dand

A

are both at 5.0V, then they should be supplied by a common lin-

ear regulator, with separate analog and digital power and ground

planes.

When Single Ended Mode is selected, the Signal Polarity bit

determines which internal reference voltage is used to compare

with the input signal. Most CIS type sensors have a positive polar-

ity type output, and in this case the Signal Polarity Bit should be

set to 1. In this case, the internal V_REF-is used as the reference

level during the Reference Sampling period.

To minimize noise, keep the LM9822 and all analog components

as far as possible from noise generators, such as switchingpower

supplies and high frequency digital busses. If possible, isolate all

the analog components and signals (OS, reference inputs and

outputs, _A, AGND) on an analog ground plane, separate from

the digital ground plane. The two ground planes should be tied

together at a single point, preferably the point where the power

supply enters the PCB.

In addition, the Signal Polarity bit determines which internal refer-

ence voltage is used during the Clamping interval. If Signal Polar-

ity = 0, V_REF+is used for clamping, if Signal Polarity = 1, V _REF-is

used.

8.0 Serial Interface and Configuration Registers

9.5 SMPCL

The serial interface is used to program the configuration registers

which control the operation of the LM9822. The SEN, SCLK, SDI

and SDO signals are used to set and verify configuration register

settings. In addition, MCLK must be active during all serial inter-

face activity. MCLK is used to register the level of the SEN input

and drives the logic that process information input on the SDI line.

The SMPCL setting controls when the clamping action occurs

during the acquisition cycle. If SMPCL is set to 0, the Clamp will

be on for 1 MCLK before the reference sampling point. If SMPCL

is set to 1, clamping will occur in the interval after the reference

sampling point, and before the signal sampling point. In this case,

the clamping time is dependent on the present “Divide By” mode,

and the settings of the CDSREF bits.

9.0 Sample Mode Register Settings

A brief overview of the sample mode register and the bit locations

9.6 CDSREF

is give in

on page

Table 2: Configuration Register Parameters

The CDSREF setting is provided to allow adjustable sampling

points for the reference sample at the higher “Divide By” modes.

This may be useful to optimize the timing of the Reference Sam-

14. The function of each bit is summarized in the following sec-

tions.

20

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Applications Information (Continued)

pling point for particular CCD sensors. Diagram 7 shows how the

various settings of CDSREF can be used to delay the Reference

Sampling point. Care must be taken to avoid setting CDSREF to

an inappropriate value when operating in the lower “Divide By”

modes.

MCLK before the reference is sampled. If SMPCL = 1 then the

clamp is on between the reference and the signal sample points.

Please see Diagram 8 and Diagram 9 for a graphic example of

this timing.

Valid CDSREF settings are:

To clamp across multiple pixels in a row, CLMP can be set high

and remain there for the entire number of pixels to be clamped,

then returned to the low state for normal (signal) operation. This

may simplify the timing required to generate the CLMP signal.

“Divide By” Mode

Valid CDSREF

00,01,10,11

00,01

/8

/6

/3

/2

10.2 MCLK and VSMP Timing

The relationship between VSMP and MCLK is used to determine

the 'Divide By' mode that is presently being used with the part.

Valid 'Divide By' settings are:

00

Color - /8, /6

Monochrome - /8, /6, /3, /2

9.7 PD (Power Down) Mode

When entering a new mode, it is important to provide consistent

MCLK/VSMP timing signals that meet the following condition.

When switching to a new 'Divide By' mode, VSMP should be held

low for a minimum of 3 MCLK cycles, then valid timing according

to the datasheet diagrams for the particular mode should be

started. This ensures that all internal circuitry is properly synchro-

nized to the new conversion 'Divide By' mode being used. If the

timing relationship between VSMP and MCLK is disturbed for any

reason, the same procedure should be used before restarting

operation in the chosen 'Divide By' mode.

A Power Down bit is provided to configure the LM9822 in a lower

power “StandBy” mode. In this mode, typical power consumption

is reduced to less than 1% of normal operating power. The serial

interface is still active, but the majority of the analog and digital

circuitry is powered down.

10.0 LM9822 Basic Operation

The normal operational sequence when using the LM9822 is as

follows:

Immediately after applying power, all configuration registers are

reset to default settings. MCLK should be applied, and the appro-

priate values written to the registers using the procedure dis-

cussed in section 8.0 Serial Interface and Configuration Registers

on page 20 and detailed in Diagrams 10, 11 and 12. Once the

configuration registers are loaded, the timing control signals can

be applied at the proper rates for the mode of conversion desired.

MCLK is applied initially with VSMP and CLMPlow. After at least

3 MCLKS, VSMP and CLMP signals can begin. The Divide By

mode is determined by the ratio of MCLK to VSMP frequency as

described in section 10.2.

For example: To change from monochrome Divide By 3 mode to

monochrome Divide By 2 mode, VSMP should be held low for at

least 3 MCLK cycles, then VSMP can be brought high using

"Divide By 2" timing. If VSMP is not low for at least 3 MCLKs, the

LM9822 may enter an unknown mode.

MCLK

VSMP

Divide by 3

Transition

(≥ 3 MCLK)

Divide by 2

14-Bit conversion results are placed on the data output pins as

follows: The upper 8 bits are output first with bit 13 of the ADC on

D7 and the bit 6 of the ADC on D0. The lower 6 bits are then out-

put with bit 5 of the ADC on D7 and bit 0 of the ADC on D2. D0

and D1 are always 0 when the lower 6 bits of data are being out-

put. The exact timing and conversion latency of the output data is

affected by the settings of the DOE variable in the Sample Mode

register, and the Divide By mode of operation. If DOE = 0 (recom-

mended setting for best performance), output data will change on

the falling edge of MCLK. If DOE = 1, output data is updated on

the rising edge of MCLK. See Diagrams 1 through 6 and Diagram

13 for more information on data output timing.

Figure 6: Timing of Transitions between ‘Divide By’ Modes

10.1 CLMP Operation

The CLMP signal is used to engage the LM9822 internal clamp

circuits at the proper time during the CCD or CIS data output

cycle. If both CLMP and VSMP are high on a rising edge of

MCLK, then CLMP will be applied during the next pixel. The exact

timing of the internal Clamp signal is determined by the Divide By

mode of operation and the setting of the SMPCL variable in the

Sample Mode register. If SMPCL = 0, then the Clamp is on for 1

21

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inches (millimeters) unless otherwise noted

Physical Dimension

28-Lead (0.300" wide) Molded Small Outline Package (JEDEC)

Order Number LM9822CCWM

NS Package Number M28B

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型号：	LM9822CCWM
厂家：	TEXAS INSTRUMENTS
描述：	3 Channel 42-Bit Color Scanner Analog Front End 光电二极管
文件：	总24页 (文件大小：282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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