LMC6062-MIL [TI]
精密 CMOS 双路微功耗运算放大器;
| 型号： | LMC6062-MIL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精密 CMOS 双路微功耗运算放大器 放大器 运算放大器 |
| 文件： | 总24页 (文件大小：1425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6062
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SNOS631D –NOVEMBER 1994–REVISED MARCH 2013
LMC6062 Precision CMOS Dual Micropower Operational Amplifier
Check for Samples: LMC6062
1
FEATURES
DESCRIPTION
The LMC6062 is a precision dual low offset voltage,
micropower operational amplifier, capable of
precision single supply operation. Performance
characteristics include ultra low input bias current,
high voltage gain, rail-to-rail output swing, and an
input common mode voltage range that includes
ground. These features, plus its low power
consumption, make the LMC6062 ideally suited for
battery powered applications.
2
•
•
•
•
•
•
(Typical Unless Otherwise Noted)
Low Offset Voltage 100μV
Ultra Low Supply current 16μA/Amplifier
Operates from 4.5V to 15V Single Supply
Ultra Low Input Bias Current 10fA
Output Swing within 10mV of Supply Rail, 100k
Load
Input Common-Mode Range Includes V−
•
•
•
Other applications using the LMC6062 include
precision full-wave rectifiers, integrators, references,
sample-and-hold circuits, and true instrumentation
amplifiers.
High Voltage Gain 140dB
Improved Latchup Immunity
APPLICATIONS
This device is built with TI's advanced double-Poly
Silicon-Gate CMOS process.
•
•
•
•
•
•
•
Instrumentation Amplifier
For designs that require higher speed, see the
LMC6082 precision dual operational amplifier.
Photodiode and Infrared Detector Preamplifier
Transducer Amplifiers
PATENT PENDING
Hand-Held Analytic Instruments
Medical Instrumentation
D/A Converter
Charge Amplifier for Piezoelectric Transducers
Connection Diagram
Figure 1. 8-Pin PDIP/SOIC
Top View
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2013, Texas Instruments Incorporated
LMC6062
SNOS631D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
(1)(2)
Absolute Maximum Ratings
Differential Input Voltage
±Supply Voltage
(V+) +0.3V,
(V−) −0.3V
16V
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature (Soldering, 10 sec.)
Storage Temp. Range
(3)
See
(4)
See
260°C
−65°C to +150°C
150°C
Junction Temperature
(5)
ESD Tolerance
2 kV
Current at Input Pin
±10 mA
Current at Output Pin
Current at Power Supply Pin
Power Dissipation
±30 mA
40 mA
(6)
See
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications
(3) Do not connect output to V+, when V+ is greater than 13V or reliability witll be adversely affected.
(4) Applies to both single-supply and split-supply operation. Continuos short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(5) Human body model, 1.5 kΩ in series with 100 pF.
(6) The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(Max) − TA)/θJA
.
(1)
Operating Ratings
Temperature Range
LMC6062AM
−55°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +85°C
4.5V ≤ V+ ≤ 15.5V
115°C/W
LMC6062AI, LMC6082I
Supply Voltage
(2)
Thermal Resistance (θJA
)
8-Pin PDIP
8-Pin SOIC
193°C/W
(3)
Power Dissipation
See
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) All numbers apply for packages soldered directly into a PC board.
(3) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA
.
DC Electrical Characteristics(1)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC6062AM
Limit(3)
350
LMC6062AI LMC6062I
Symbol
Parameter
Conditions
Typ(2)
Units
Limit(3)
Limit(3)
VOS
Input Offset Voltage
100
350
800
μV
1200
900
1300
Max
(1) For ensured Military Temperature Range parameters, see RETSMC6062X.
(2) Typical values represent the most likely parametric norm.
(3) All limits are ensured by testing or statistical analysis.
2
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DC Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC6062AM
Limit(3)
LMC6062AI LMC6062I
Symbol
Parameter
Conditions
Typ(2)
Units
Limit(3)
Limit(3)
TCVOS
Input Offset Voltage
Average Drift
1.0
μV/°C
IB
Input Bias Current
0.010
0.005
pA
Max
pA
100
100
4
2
4
2
IOS
Input Offset Current
Max
Tera Ω
dB
RIN
Input Resistance
Common Mode
>10
85
CMRR
0V ≤ VCM ≤ 12.0V
V+ = 15V
5V ≤ V+ ≤ 15V
75
70
75
72
66
63
Rejection Ratio
Min
dB
+PSRR
−PSRR
VCM
Positive Power Supply
Rejection Ratio
85
100
75
75
66
VO = 2.5V
0V ≤ V− ≤ −10V
70
72
63
Min
dB
Negative Power Supply
Rejection Ratio
84
84
74
70
81
71
Min
V
Input Common-Mode
Voltage Range
V+ = 5V and 15V
−0.4
−0.1
−0.1
−0.1
for CMRR ≥ 60 dB
0
0
0
Max
V
V+ − 1.9
4000
V+ − 2.3
V+ − 2.6
400
V+ − 2.3
V+ − 2.5
400
V+ − 2.3
V+ − 2.5
300
Min
V/mV
Min
V/mV
Min
V/mV
Min
V/mV
Min
V
AV
Large Signal
Voltage Gain
RL = 100 kΩ(4)
Sourcing
200
300
200
Sinking
Sourcing
Sinking
3000
180
180
90
70
100
60
(4)
RL = 25 kΩ
3000
400
400
200
150
150
80
2000
100
100
70
35
50
35
VO
Output Swing
V+ = 5V
4.995
0.005
4.990
0.010
14.990
0.010
14.965
0.025
4.990
4.970
0.010
0.030
4.975
4.955
0.020
0.045
14.975
14.955
0.025
0.050
14.900
14.800
0.050
0.200
4.990
4.980
0.010
0.020
4.975
4.965
0.020
0.035
14.975
14.965
0.025
0.035
14.900
14.850
0.050
0.150
4.950
4.925
0.050
0.075
4.950
4.850
0.050
0.150
14.950
14.925
0.050
0.075
14.850
14.800
0.100
0.200
RL = 100 kΩ to 2.5V
Min
V
Max
V
V+ = 5V
RL = 25 kΩ to 2.5V
Min
V
Max
V
V+ = 15V
RL = 100 kΩ to 7.5V
Min
V
Max
V
V+ = 15V
RL = 25 kΩ to 7.5V
Min
V
Max
(4) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC6062AM
LMC6062AI LMC6062I
Symbol
IO
Parameter
Conditions
Typ(2)
Units
Limit(3)
16
8
Limit(3)
16
10
16
8
Limit(3)
13
8
Output Current
Sourcing, VO = 0V
22
mA
Min
mA
Min
mA
Min
mA
Min
μA
V+ = 5V
Sinking, VO = 5V
Sourcing, VO = 0V
21
25
35
32
40
16
7
16
8
IO
Output Current
V+ = 15V
15
9
15
10
20
8
15
10
20
8
(5)
Sinking, VO = 13V
20
7
IS
Supply Current
Both Amplifiers
V+ = +5V, VO = 1.5V
38
60
47
70
38
46
47
55
46
56
57
66
Max
μA
Both Amplifiers
V+ = +15V, VO = 7.5V
Max
(5) Do not connect output to V+, when V+ is greater than 13V or reliability will be adversely affected.
AC Electrical Characteristics(1)
Unless otherwise specified, all limits ensured for TJ = 25°C, Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC6062AM LMC6062AI LMC6062I
Symbol
Parameter
Conditions
Typ(2)
Units
Limit(3)
Limit(3)
Limit(3)
(4)
SR
Slew Rate
See
35
20
20
15
V/ms
Min
8
10
7
GBW
Gain-Bandwidth Product
Phase Margin
100
50
kHz
θm
Deg
(5)
Amp-to-Amp Isolation
See
155
dB
en
Input-Referred Voltage Noise
Input-Referred Current Noise
Total Harmonic Distortion
F = 1 kHz
83
nV/√Hz
pA/√Hz
in
F = 1 kHz
0.0002
T.H.D.
F = 1 kHz, AV = −5
RL = 100 kΩ, VO = 2 VPP
±5V Supply
0.01
%
(1) For ensured Military Temperature Range parameters, see RETSMC6062X.
(2) Typical values represent the most likely parametric norm.
(3) All limits are ensured by testing or statistical analysis.
(4) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(5) Input referred V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 100 Hz to produce VO = 12 VPP
.
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SNOS631D –NOVEMBER 1994–REVISED MARCH 2013
Typical Performance Characteristics
VS = ±7.5V, TA = 25°C, Unless otherwise specified
Distribution of LMC6062 Input Offset Voltage
(TA = +25°C)
Distribution of LMC6062 Input Offset Voltage
(TA = −55°C)
Figure 2.
Figure 3.
Input Bias Current
vs.
Distribution of LMC6062 Input Offset Voltage
(TA = +125°C)
Temperature
Figure 4.
Figure 5.
Supply Current
vs.
Supply Voltage
Input Voltage
vs.
Output Voltage
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C, Unless otherwise specified
Common Mode Rejection Ratio
Power Supply Rejection Ratio
vs.
vs.
Frequency
Frequency
Figure 8.
Figure 9.
Input Voltage Noise
vs.
Frequency
Output Characteristics Sourcing Current
Figure 10.
Figure 11.
Gain and Phase Response
vs.
Temperature
(−55°C to +125°C)
Output Characteristics Sinking Current
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C, Unless otherwise specified
Gain and Phase Response
Gain and Phase Response
vs.
vs.
Capacitive Load
with RL = 20 kΩ
Capacitive Load
with RL = 500 kΩ
Figure 14.
Figure 15.
Open Loop Frequency Response
Inverting Small Signal Pulse Response
Figure 16.
Figure 17.
Inverting Large Signal Pulse Response
Non-Inverting Small Signal Pulse Response
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C, Unless otherwise specified
Crosstalk Rejection
vs.
Non-Inverting Large Signal Pulse Response
Frequency
Figure 20.
Figure 21.
Stability
Stability
vs.
Capacitive Load RL = 1 MΩ
vs
Capacitive Load, RL = 20 kΩ
Figure 22.
Figure 23.
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SNOS631D –NOVEMBER 1994–REVISED MARCH 2013
APPLICATIONS HINTS
AMPLIFIER TOPOLOGY
The LMC6062 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op amps. These features make the LMC6062 both easier to
design with, and provide higher speed than products typically found in this ultra low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6062.
Although the LMC6062 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and
even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce
phase margins.
When high input impedances are demanded, guarding of the LMC6062 is suggested. Guarding input lines will
not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK).
The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the
feedback resistor (as in Figure 24 ) such that:
(1)
or
R1 CIN ≤ R2 Cf
(2)
Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on
compensating for input capacitance.
Figure 24. Canceling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor
is normally included in this integrator stage. The frequency location of the dominate pole is affected by the
resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate
resistive load in parallel with the capacitive load (see typical curves).
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 25.
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Figure 25. LMC6062 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 26). Typically a pull up
resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 26. Compensating for Large Capacitive Loads
with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6062, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6062's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's
inputs, as in Figure 27. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the
LMC6062's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 28 for typical connections of guard
rings for standard op-amp configurations.
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SNOS631D –NOVEMBER 1994–REVISED MARCH 2013
Figure 27. Example of Guard Ring in P.C. Board Layout
(a) Inverting Amplifier
(b) Non-Inverting Amplifier
(c) Follower
Figure 28. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 29.
Latchup
CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and
output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate
lead. The LMC6062 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some
resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In
addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply
pins will also inhibit latchup susceptibility.
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(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).
Figure 29. Air Wiring
Typical Single-Supply Applications
(V+ = 5.0 VDC
)
The extremely high input impedance, and low power consumption, of the LMC6062 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held
pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
Figure 30 shows an instrumentation amplifier that features high differential and common mode input resistance
(>1014Ω), 0.01% gain accuracy at AV = 100, excellent CMRR with 1 kΩ imbalance in bridge source resistance.
Input current is less than 100 fA and offset drift is less than 2.5 μV/°C. R2 provides a simple means of adjusting
gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using
super precision matched resistors. For good CMRR over temperature, low drift resistors should be used.
If R1 = R5, R3 = R6, and R4 = R7; then
∴AV ≈ 100 for circuit shown (R2 = 9.822k).
Figure 30. Instrumentation Amplifier
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Figure 31. Low-Leakage Sample and Hold
Figure 32. 1 Hz Square Wave Oscillator
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMC6062AIM/NOPB
LMC6062AIMX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMC60
62AIM
ACTIVE
2500 RoHS & Green
SN
LMC60
62AIM
LMC6062I MDC
LMC6062IM
ACTIVE
NRND
DIESALE
SOIC
Y
D
0
8
288
95
RoHS & Green
Call TI
Call TI
Level-1-NA-UNLIM
-40 to 85
-40 to 85
Non-RoHS
& Green
Level-1-235C-UNLIM
LMC60
62IM
LMC6062IM/NOPB
LMC6062IMX/NOPB
LMC6062IN/NOPB
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
D
D
P
8
8
8
95
RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-NA-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMC60
62IM
2500 RoHS & Green
40 RoHS & Green
LMC60
62IM
NIPDAU
LMC6062
IN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC6062AIMX/NOPB
LMC6062IMX/NOPB
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMC6062AIMX/NOPB
LMC6062IMX/NOPB
SOIC
SOIC
D
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMC6062AIM/NOPB
LMC6062IM
D
D
D
D
P
SOIC
SOIC
SOIC
SOIC
PDIP
8
8
8
8
8
95
95
95
95
40
495
495
495
495
502
8
8
4064
4064
4064
4064
11938
3.05
3.05
3.05
3.05
4.32
LMC6062IM
8
LMC6062IM/NOPB
LMC6062IN/NOPB
8
14
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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