LMC6482M MD8 [TI]
超低偏置电流、精密 CMOS 轨到轨输入和输出运算放大器 | Y | 0 | -55 to 125;
| 型号： | LMC6482M MD8 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低偏置电流、精密 CMOS 轨到轨输入和输出运算放大器 | Y | 0 | -55 to 125 放大器 运算放大器 放大器电路 |
| 文件： | 总28页 (文件大小：2832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6482QML
LMC6482QML CMOS Dual Rail-To-Rail Input and Output Operational Amplifier
Literature Number: SNOSAR9
December 8, 2010
LMC6482QML
CMOS Dual Rail-To-Rail Input and Output Operational
Amplifier
General Description
Features
The LMC6482 provides a common-mode range that extends
to both supply rails. This rail-to-rail performance combined
with excellent accuracy, due to a high CMRR, makes it unique
among rail-to-rail input amplifiers.
(Typical unless otherwise noted)
Rail-to-Rail Input Common-Mode Voltage Range
(Guaranteed Over Temperature)
■
Rail-to-Rail Output Swing (within 20mV of supply rail,
100KΩ load)
■
It is ideal for systems, such as data acquisition, that require a
large input signal range. The LMC6482 is also an excellent
upgrade for circuits using limited common-mode range am-
plifiers such as the TLC272 and TLC277.
Guaranteed 5V and 15V Performance
■
■
■
■
■
Excellent CMRR and PSRR: 82dB
Ultra Low Input Current: 20fA
Maximum dynamic signal range is assured in low voltage and
single supply systems by the LMC6482's rail-to-rail output
swing. The LMC6482's rail-to-rail output swing is guaranteed
for loads down to 600Ω.
High Voltage Gain (RL = 500KΩ): 130dB
Specified for 2KΩ and 600Ω loads
Guaranteed low voltage characteristics and low power dissi-
pation make the LMC6482 especially well-suited for battery-
operated systems.
Applications
Data Acquisition Systems
■
■
■
■
Transducer Amplifiers
See the LMC6484 data sheet for a Quad CMOS operational
amplifier with these same features.
Hand-held Analytic Instruments
Medical Instrumentation
Active Filter, Peak Detector, Sample and Hold, pH Meter,
■
Current Source
Improved Replacement for TLC272, TLC277
■
Ordering Information
NS Part Number
SMD Part Number
NS Package Number
Package Description
LMC6482AMJ/883
5962–9453401MPA
J08A
8LD Ceramic Dip
Connection Diagram
20160704
© 2010 National Semiconductor Corporation
201607
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3V Single Supply Buffer Circuit
Rail-To-Rail Input
Rail-To-Rail Output
20160702
20160703
20160701
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2
Absolute Maximum Ratings (Note 1)
Supply Voltage (V+ − V−)
16V
± Supply Voltage
(V+) + 0.3V, (V−) − 0.3V
±5 mA
Differential Input Voltage
Voltage at Input/Output Pin
Current at Input Pin (Note 9)
Current at Output Pin (Note 4), (Note 7)
Current at Power Supply Pin
±30 mA
40 mA
Maximum Junction Temperature (TJmax) (Note 2), (Note 4)
Power Dissipation (Note 2)
150°C
160mW
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
Thermal Resistance(Note 5)
ꢀθJA
8LD Ceramic DIP (Still Air)
8LD Ceramic DIP (500LF/Min Air Flow)
ꢀθJC
117°C/W
62.0°C/W
8LD Ceramic DIP
Lead Temp. (Soldering, 10 sec.)
ESD Tolerance (Note 3)
16.0°C/W
260°C
1.5KV
Recommended Operating Range
(Note 1)
3.0V ≤ V+ ≤ 15.5V
−55°C ≤ TA ≤ +125°C
Supply Voltage
Operating Temperature Range
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp (°C)
1
2
Static tests at
Static tests at
+25
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
3
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LMC6482 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M.
Sub-
groups
Symbol
VIO
IIB
IIO
Parameter
Input Offset Voltage
Input Bias Current
Input Offset Current
Conditions
Notes
Min
Max
Units
0.75
1.35
25
mV
mV
pA
pA
pA
pA
dB
dB
1
2, 3
1
100
25
2, 3
1
100
2, 3
1
65
62
0V ≤ VCM ≤ 15.0V
V+ = 15V
2, 3
CMRR
Common Mode Rejection Ratio
65
62
65
62
dB
dB
dB
dB
1
0V ≤ VCM ≤ 5.0V
2, 3
1
5V ≤ V+ ≤ 15V
VO = 2.5V
Positive Power Supply Rejection
Ratio
+PSRR
-PSRR
2, 3
-15V ≤ V- ≤ -5V
Negative Power Supply
Rejection Ratio
65
62
dB
dB
1
VO = -2.5V, V+ = 0V
2, 3
V+
+0.25
V+
-0.25
0.0
V
1
5V ≤ VCM ≤ 15V
For CMRR ≥ 50dB
Input Common Mode Voltage
Range
VCM
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
2, 3
1
Sourcing VO = 0V
Sinking VO = 5V
16
12
11
9.0
28
22
30
24
2, 3
1
2, 3
1
ISC
Output Short Circuit Current
V+ = 15V
Sourcing, VO = 0V
2, 3
1
V+ = 15V
(Note 7)
(Note 7)
Sinking, VO = 12V
2, 3
1
1.4
1.8
Both Amps
2, 3
1
ICC
Supply Current
Both Amps
V+ = +15V
1.6
2.0
2, 3
4
V+ = 5V
RL = 2KΩ to V+/2
V+ = 5V
RL = 600Ω to V+/2
V+ = 15V
RL = 2KΩ to V+/2
V+ = 15V
4.8
4.7
4.5
4.24
14.4
14.2
13.4
13.0
140
84
0.18
0.24
0.50
0.65
0.32
0.45
1.00
1.30
V
5, 6
4
V
V
5, 6
4
VO
Output Swing
V
V
5, 6
4
V
RL = 600Ω to V+/2
V
5, 6
4
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
RL = 2KΩ Sourcing
RL = 2KΩ Sinking
RL = 600Ω Sourcing
RL = 600Ω Sinking
5, 6
4
35
20
5, 6
4
AV
Large Signal Voltage Gain
80
48
5, 6
4
18
13
5, 6
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4
AC Parameters
The following conditions apply, unless otherwise specified. V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M.
Sub-
groups
Symbol
SR
GBW
Parameter
Conditions
Notes
Min Max
Units
(Note 8)
(Note 8)
0.9
0.6
V/µS
V/µS
MHz
MHz
4
Slew Rate
Gain Bandwidth
5, 6
4
V+ = 15V
Set up for non-inverting
1.25
1.15
5, 6
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Human body model, 1.5 KΩ in series with 100 pF.
Note 4: Applies to both single supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability.
Note 5: All numbers apply for packages soldered directly into a PC board.
Note 6: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
Note 7: Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input, 2.5V to 12.5V for +slew, and 12.5V to 2.5V for −slew.. Number specified is the slower of
either the positive or negative slew rates.
Note 9: Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
5
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Typical Performance Characteristics VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Supply Current vs. Supply Voltage
Input Current vs. Temperature
20160740
20160741
Sourcing Current vs. Output Voltage
Sourcing Current vs. Output Voltage
20160742
20160743
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
20160745
20160744
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Sinking Current vs. Output Voltage
Sinking Current vs. Output Voltage
20160746
20160747
Output Voltage Swing vs. Supply Voltage
Input Voltage Noise vs. Frequency
20160749
20160748
Input Voltage Noise vs. Input Voltage
Input Voltage Noise vs. Input Voltage
20160750
20160751
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Input Voltage Noise vs. Input Voltage
Crosstalk Rejection vs. Frequency
20160752
20160753
Crosstalk Rejection vs. Frequency
Positive PSRR vs. Frequency
20160754
20160755
Negative PSRR vs. Frequency
CMRR vs. Frequency
20160756
20160757
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CMRR vs. Input Voltage
CMRR vs. Input Voltage
20160758
20160759
CMRR vs. Input Voltage
ΔVOS vs. CMR
20160760
20160761
Input Voltage vs. Output Voltage
ΔVOS vs. CMR
20160763
20160762
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Input Voltage vs. Output Voltage
Open Loop Frequency Response
20160764
20160765
Open Loop Frequency Response
Open Loop Frequency Response vs. Temperature
20160766
20160767
Maximum Output Swing vs. Frequency
Gain and Phase vs. Capacitive Load
20160768
20160769
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Gain and Phase vs. Capacitive Load
Open Loop Output Impedance vs. Frequency
20160770
20160771
Open Loop Output Impedance vs. Frequency
Slew Rate vs. Supply Voltage
20160773
20160772
Non-Inverting Large Signal Pulse Response
Non-Inverting Large Signal Pulse Response
20160774
20160775
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Non-Inverting Large Signal Pulse Response
Non-Inverting Small Signal Pulse Response
20160776
20160777
Non-Inverting Small Signal Pulse Response
Non-Inverting Small Signal Pulse Response
20160778
20160779
Inverting Large Signal Pulse Response
Inverting Large Signal Pulse Response
20160780
20160781
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Inverting Large Signal Pulse Response
Inverting Small Signal Pulse Response
20160782
20160783
Inverting Small Signal Pulse Response
Inverting Small Signal Pulse Response
20160784
20160785
Stability vs. Capacitive Load
Stability vs. Capacitive Load
20160786
20160787
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Stability vs. Capacitive Load
Stability vs. Capacitive Load
20160788
20160789
Stability vs. Capacitive Load
Stability vs. Capacitive Load
20160790
20160791
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Applications that exceed this rating must externally limit the
maximum input current to ±5mA with an input resistor (RI) as
shown in Figure 3.
Application Information
1.0 AMPLIFIER TOPOLOGY
The LMC6482 incorporates specially designed wide-compli-
ance range current mirrors and the body effect to extend input
common mode range to each supply rail. Complementary
paralleled differential input stages, like the type used in other
CMOS and bipolar rail-to-rail input amplifiers, were not used
because of their inherent accuracy problems due to CMRR,
cross-over distortion, and open-loop gain variation.
20160711
The LMC6482's input stage design is complemented by an
output stage capable of rail-to-rail output swing even when
driving a large load. Rail-to-rail output swing is obtained by
taking the output directly from the internal integrator instead
of an output buffer stage.
FIGURE 3. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
3.0 RAIL-TO-RAIL OUTPUT
2.0 INPUT COMMON-MODE VOLTAGE RANGE
The approximated output resistance of the LMC6482 is
180Ω sourcing and 130Ω sinking at VS = 3V and 110Ω sourc-
ing and 80Ω sinking at Vs = 5V. Using the calculated output
resistance, maximum output voltage swing can be estimated
as a function of load.
Unlike Bi-FET amplifier designs, the LMC6482 does not ex-
hibit phase inversion when an input voltage exceeds the
negative supply voltage. Figure 1 shows an input voltage ex-
ceeding both supplies with no resulting phase inversion on
the output.
4.0 CAPACITIVE LOAD TOLERANCE
The LMC6482 can typically directly drive a 100pF load with
VS = 15V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration. Direct capacitive
loading reduces the phase margin of op-amps. The combi-
nation of the op-amp's output impedance and the capacitive
load induces phase lag. This results in either an under-
damped pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 4. This simple technique
is useful for isolating the capacitive inputs of multiplexers and
A/D converters.
20160710
FIGURE 1. An Input Voltage Signal Exceeds the
LMC6482 Power Supply Voltages with
No Output Phase Inversion
20160717
The absolute maximum input voltage is 300mV beyond either
supply rail at room temperature. Voltages greatly exceeding
this absolute maximum rating, as in Figure 2, can cause ex-
cessive current to flow in or out of the input pins possibly
affecting reliability.
FIGURE 4. Resistive Isolation
of a 330pF Capacitive Load
20160739
FIGURE 2. A ±7.5V Input Signal Greatly
Exceeds the 3V Supply in Figure 3 Causing
No Phase Inversion Due to RI
15
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20160718
20160716
FIGURE 5. Pulse Response of
the LMC6482 Circuit in Figure 4
FIGURE 7. Pulse Response of
LMC6482 Circuit in Figure 6
Improved frequency response is achieved by indirectly driving
capacitive loads, as shown in Figure 6.
5.0 COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance
with amplifiers that have ultra-low input current, like the
LMC6482. Large feedback resistors can react with small val-
ues of input capacitance due to transducers, photodiodes,
and circuits board parasitics to reduce phase margins.
20160715
FIGURE 6. LMC6482 Noninverting Amplifier,
Compensated to Handle a 330pF Capacitive Load
20160719
R1 and C1 serve to counteract the loss of phase margin by
feeding forward the high frequency component of the output
signal back to the amplifiers inverting input, thereby preserv-
ing phase margin in the overall feedback loop. The values of
R1 and C1 are experimentally determined for the desired
pulse response. The resulting pulse response can be seen in
Figure 7.
FIGURE 8. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 8), Cf, is first estimated by:
or
R1 CI ≤ R2 Cf
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or small-
er than that of a bread-board, so the actual optimum value for
Cf may be different. The values of Cf should be checked on
the actual circuit. (Refer to the LMC660 quad CMOS amplifier
data sheet for a more detailed discussion.)
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16
6.0 PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-
IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low input current of the LMC6482, typically less
than 20fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even through it may sometimes appear ac-
ceptably low, because under conditions of high humidity or
dust or contamination, the surface leakage will be apprecia-
ble.
20160721
Inverting Amplifier
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LM6482's inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp's inputs, as in Figure
9. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil must
then be connected to a voltage which is at the same voltage
as the amplifier inputs, since no leakage current can flow be-
tween two points at the same potential. For example, a PC
board trace-to-pad resistance of 1012Ω, which is normally
considered a very large resistance, could leak 5pA if the trace
were a 5V bus adjacent to the pad of the input. This would
cause a 250 times degradation from the LMC6482's actual
performance. However, if a guard ring is held within 5 mV of
the inputs, then even a resistance of 1011Ω would cause only
0.05pA of leakage current. See Figure 10 for typical connec-
tions of guard rings for standard op-amp configurations.
20160722
Non-Inverting Amplifier
20160723
Follower
FIGURE 10. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to
lay out a PC board for the sake of just a few circuits, there is
another technique which is even better than a guard ring on
a PC board: Don't insert the amplifier's input pin into the board
at all, but bend it up in the air and use only air as an insulator.
Air is an excellent insulator. In this case you may have to
forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using
point-to-point up-in-the-air wiring. See Figure 11.
20160720
FIGURE 9. Example of Guard Ring in P.C. Board Layout
20160724
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 11. Air Wiring
17
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7.0 OFFSET VOLTAGE ADJUSTMENT
8.0 UPGRADING APPLICATIONS
Offset voltage adjustment circuits are illustrated in Figure 12
Figure 13. Large value resistances and potentiometers are
used to reduce power consumption while providing typically
±2.5mV of adjustment range, referred to the input, for both
configurations with VS = ±5V.
The LMC6484 quads and LMC6482 duals have industry stan-
dard pin outs to retrofit existing applications. System perfor-
mance can be greatly increased by the LMC6482's features.
The key benefit of designing in the LMC6482 is increased lin-
ear signal range. Most op-amps have limited input common
mode ranges. Signals that exceed this range generate a non-
linear output response that persists long after the input signal
returns to the common mode range.
Linear signal range is vital in applications such as filters where
signal peaking can exceed input common mode ranges re-
sulting in output phase inversion or severe distortion.
9.0 DATA ACQUISITION SYSTEMS
Low power, single supply data acquisition system solutions
are provided by buffering the ADC12038 with the LMC6482
(Figure 14). Capable of using the full supply range, the
LMC6482 does not require input signals to be scaled down to
meet limited common mode voltage ranges. The LMC4282
CMRR of 82dB maintains integral linearity of a 12-bit data
acquisition system to ±0.325 LSB. Other rail-to-rail input am-
plifiers with only 50dB of CMRR will degrade the accuracy of
the data acquisition system to only 8 bits.
20160725
FIGURE 12. Inverting Configuration
Offset Voltage Adjustment
20160726
FIGURE 13. Non-Inverting Configuration
Offset Voltage Adjustment
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18
20160728
FIGURE 14. Operating from the same
Supply Voltage, the LMC6482 buffers the
ADC12038 maintaining excellent accuracy
19
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10.0 INSTRUMENTATION CIRCUITS
these features include analytic medical instruments, magnetic
field detectors, gas detectors, and silicon-based transducers.
The LMC6482 has the high input impedance, large common-
mode range and high CMRR needed for designing instru-
mentation circuits. Instrumentation circuits designed with the
LMC6482 can reject a larger range of common-mode signals
than most in-amps. This makes instrumentation circuits de-
signed with the LMC6482 an excellent choice of noisy or
industrial environments. Other applications that benefit from
A small valued potentiometer is used in series with Rg to set
the differential gain of the 3 op-amp instrumentation circuit in
Figure 15. This combination is used instead of one large val-
ued potentiometer to increase gain trim accuracy and reduce
error due to vibration.
20160729
FIGURE 15. Low Power 3 Op-Amp Instrumentation Amplifier
A 2 op-amp instrumentation amplifier designed for a gain of
100 is shown in Figure 16. Low sensitivity trimming is made
for offset voltage, CMRR and gain. Low cost and low power
consumption are the main advantages of this two op-amp cir-
cuit.
Higher frequency and larger common-mode range applica-
tions are best facilitated by a three op-amp instrumentation
amplifier.
20160730
FIGURE 16. Low-Power Two-Op-Amp Instrumentation Amplifier
11.0 SPICE MACROMODEL
•
•
Quiescent and dynamic supply current
Output swing dependence on loading conditions
A spice macromodel is available for the LMC6482. This model
includes accurate simulation of:
and many more characteristics as listed on the macromodel
disk.
•
•
•
Input common-mode voltage range
Frequency and transient response
GBW dependence on loading conditions
Contact your local National Semiconductor sales office to ob-
tain an operational amplifier spice model library disk.
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20
Typical Single-Supply Applications
20160731
FIGURE 17. Half-Wave Rectifier
with Input Current Protection (RI)
20160734
FIGURE 20. Full Wave Rectifier Waveform
20160735
20160732
FIGURE 21. Large Compliance Range Current Source
FIGURE 18. Half-Wave Rectifier Waveform
The circuit in Figure 17 uses a single supply to half wave rec-
tify a sinusoid centered about ground. RI limits current into the
amplifier caused by the input voltage exceeding the supply
voltage. Full wave rectification is provided by the circuit in
Figure 19.
20160736
FIGURE 22. Positive Supply Current Sense
20160733
FIGURE 19. Full Wave Rectifier
with Input Current Protection (RI)
21
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20160737
FIGURE 23. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range
In Figure 23 dielectric absorption and leakage is minimized
diode leakage current. The ultra-low input current of the
by using a polystyrene or polyethylene hold capacitor. The
droop rate is primarily determined by the value of CH and
LMC6482 has a negligible effect on droop.
20160738
FIGURE 24. Rail-to-Rail Sample and Hold
The LMC6482's high CMRR (82dB) allows excellent accuracy
throughout the circuit's rail-to-rail dynamic capture range.
20160727
FIGURE 25. Rail-to-Rail Single Supply Low Pass Filter
The low pass filter circuit in Figure 25 can be used as an anti-
aliasing filter with the same voltage supply as the A/D con-
verter.
offset error even when large value resistors are used. This in
turn allows the use of smaller valued capacitors which take
less board space and cost less.
Filter designs can also take advantage of the LMC6482 ultra-
low input current. The ultra-low input current yields negligible
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22
Revision History
Released
Revision
Section
Changes
12/08/2010
A
New Release, Corporate format
1 MDS data sheet converted into one Corp. data
sheet format. MNLMC6482AM-X Rev 0A0 will be
archived.
23
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Ceramic Dual-In-Line Package
NS Package Number J08A
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24
Notes
25
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