概述
数据手册
替代型号LMG5200MOFR 概述
80V GaN 半桥功率级 | MOF | 9 | -40 to 125
LMG5200MOFR 数据手册
通过下载LMG5200MOFR数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
LMG5200 80V、10A GaN 半桥功率级
1 特性
3 说明
1
•
•
•
集成 15mΩ GaN FET 和驱动器
LMG5200 器件集成了 80V、10A 驱动器和 GaN 半桥
功率级，采用增强模式氮化镓 (GaN) FET 提供了一套
集成功率级解决方案。该器件包含两个 80V GaN
FET，它们由采用半桥配置的同一高频 GaN FET 驱动
器提供驱动。
80V 连续电压，100V 脉冲电压额定值
封装经过优化，可实现简单的 PCB 布局，无需考
虑底层填料、爬电和余隙要求
•
超低共源电感可确保实现高压摆率开关，同时在硬
开关拓扑中不会造成过度振铃
GaN FET 在功率转换方面的优势显著，因为其反向恢
复电荷几乎为零，输入电容 CISS 也非常小。所有器件
均安装在一个完全无键合线的封装平台上，尽可能减少
了封装寄生元件数。LMG5200 器件采用 6mm × 8mm
× 2mm 无铅封装，可轻松安装在 PCB 上。
•
•
•
•
•
非常适合隔离式和非隔离式 应用
栅极驱动器支持高达 10MHz 的开关频率
内部自举电源电压钳位可防止 GaN FET 过驱
电源轨欠压锁定保护
优异的传播延迟（典型值为 29.5ns）和匹配（典型
值为 2ns）
该器件的输入与 TTL 逻辑兼容，无论 VCC 电压如
何，都能够承受高达 12V 的输入电压。专有的自举电
压钳位技术确保了增强模式 GaN FET 的栅极电压处于
安全的工作范围内。
•
低功耗
2 应用
•
•
•
宽 VIN 数兆赫兹同步降压转换器
该器件配有用户友好型接口且更为出色，进一步提升了
分立式 GaN FET 的优势。对于具有高频、高效操作及
小尺寸要求的 应用 而言，该器件堪称理想的解决方
案。与 TPS53632G 控制器搭配使用时，LMG5200 能
够直接将 48V 电压转换为负载点电压 (0.5-1.5V)。
D 类音频放大器
适用于电信、工业和企业计算的 48V 负载点 (POL)
转换器
•
高功率密度单相和三相电机驱动
器件信息(1)
器件型号
LMG5200
封装
封装尺寸（标称值）
6.00mm × 8.00mm
QFM (9)
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。已更正中的印刷错误
简化框图
HS
3
HB
2
LMG5200
1
8
9
VIN
HS
HB
HI
LI
4
5
HI
LI
HO
LO
SW
GaN Driver
VCC
AGND
PGND
6
7
VCC
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSCY4
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
7.1 Propagation Delay and Mismatch Measurement...... 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
9
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Examples................................................... 16
12 器件和文档支持 ..................................................... 20
12.1 器件支持 ............................................................... 20
12.2 文档支持 ............................................................... 20
12.3 接收文档更新通知 ................................................. 20
12.4 社区资源................................................................ 20
12.5 商标....................................................................... 20
12.6 静电放电警告......................................................... 20
12.7 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
13.1 封装信息................................................................ 20
7
8
4 修订历史记录
Changes from Revision C (December 2016) to Revision D
Page
•
•
通用编辑全局编写和 SDS 更新............................................................................................................................................... 1
Changed Thermal Information table....................................................................................................................................... 5
Changes from Revision B (January 2016) to Revision C
Page
•
•
•
•
•
已更改 “GaN 技术预览”至“量产数据” ...................................................................................................................................... 1
已添加 Device Functional Modes Section ........................................................................................................................... 12
已添加 Typical Application Section ...................................................................................................................................... 12
Updated Power Supply Recommendations Section ............................................................................................................ 15
已添加 链接至“开发支持”部分 ............................................................................................................................................... 20
Changes from Revision A (March 2015) to Revision B
Page
•
已更改 part number typographical error in 图 14.................................................................................................................. 16
Changes from Original (March 2015) to Revision A
Page
•
简化框图
...................................................................................................................................................................................... 1
•
•
•
Corrected typographical error in 图 5 ..................................................................................................................................... 8
Corrected typographical error in 图 10 ................................................................................................................................. 10
Corrected typographical error in 图 11 ................................................................................................................................. 12
2
Copyright © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
5 Pin Configuration and Functions
MOF Package
9-Pin QFM
Top View
1 VIN
2
3
4
5
HI
LI
9 PGND
LMG5200
7
6
SW
8
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
AGND
HB
NO.
7
G
P
I
Analog ground. Ground of driver device.
High-side gate driver bootstrap rail.
High-side gate driver control input
High-side GaN FET source connection
Low-side driver control input
2
HI
4
HS
3
P
I
LI
5
PGND
SW
9
G
P
P
P
Power ground. Low-side GaN FET source. Electrically shorted to AGND pin.
Switching node. Electrically shorted to HS pin. Ensure low capacitance at this node on PCB.
5-V positive gate drive supply
8
VCC
VIN
6
1
Input voltage pin. Electrically connected to high-side GaN FET drain.
(1) I = Input, O = Output, G = Ground, P = Power
Copyright © 2015–2017, Texas Instruments Incorporated
3
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
MAX
80
UNIT
V
VIN to PGND
0
VIN to PGND (pulsed, 100-ms maximum duration)(2)
HB to AGND
100
86
V
–0.3
–5
V
HS to AGND
80
V
HI to AGND
–0.3
–0.3
–0.3
–0.3
0
12
V
LI to AGND
12
V
VCC to AGND
6
V
HB to HS
6
V
HB to VCC
80
V
SW to PGND
–5
80
V
IOUT from SW pin
Junction temperature, TJ
Storage temperature, Tstg
10
A
–40
–40
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Device can withstand 1000 pulses up to 100 V of 100-ms duration and less than 1% duty cycle over its lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VCC
4.75
5
5.25
LI or HI Input
0
0
12
V
VIN
80
80
V
HS, SW
–5
V
HB
VHS + 4
VHS + 5.25
50
V
HS, SW slew rate(1)
V/ns
°C
Junction temperature, TJ
–40
125
(1) This parameter is ensured by design. Not tested in production.
4
Copyright © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
6.4 Thermal Information
LMG5200
(1) (2)
THERMAL METRIC
MOF (QFM)
UNIT
9 PINS
35
R θJA
R θJC(top)
R θJB
ψ JT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
18
16
1.8
16
ψ JB
Junction-to-board characterization parameter
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator .
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC
VCC quiescent current
Total VCC operating current
HB quiescent current
HB operating current
LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V
f = 500 kHz
0.08
3
0.125
5
mA
mA
mA
mA
ICCO
IHB
LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V
f = 500 kHz, 50% Duty cycle, VDD = 5 V
0.09
1.5
0.15
2.5
IHBO
INPUT PINS
VIH
High-level input voltage
threshold
Rising edge
Falling edge
1.87
1.48
2.06
1.66
2.22
1.76
V
V
VIL
Low-level input voltage
threshold
VHYS
RI
Hysteresis between rising and
falling threshold
400
200
mV
Input pulldown resistance
100
3.2
2.5
300
4.5
3.9
kΩ
UNDERVOLTAGE PROTECTION
VCCR VCC Rising edge threshold
VCC(hyst) VCC UVLO threshold hysteresis
Rising
Rising
3.8
200
3.2
V
mV
V
VHBR
HB Rising edge threshold
VHB(hyst)
HB UVLO threshold hysteresis
200
mV
BOOTSTRAP DIODE
VDL
VDH
RD
Low-current forward voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
Regulation Voltage
0.45
0.9
1.85
5
0.65
1.0
V
V
Ω
V
High current forward voltage
Dynamic resistance
HB-HS clamp
2.8
4.65
5.2
Bootstrap diode reverse
recovery time
tBS
IF = 100 mA, IR = 100 mA
VVIN = 50 V
40
2
ns
Bootstrap diode reverse
recovery charge
QRR
nC
(1) Parameters that show only a typical value are ensured by design and may not be tested in production.
Copyright © 2015–2017, Texas Instruments Incorporated
5
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
POWER STAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RDS(ON)H High-side GaN FET on-
LI = 0 V, HI = VCC=5 V, HB-HS = 5 V,
VIN-SW = 10 A, TJ = 25℃
15
15
2
20
20
mΩ
mΩ
V
resistance
S
Low-side GaN FET on-
RDS(ON)LS
LI = VCC = 5V, HI = 0 V, HB-HS = 5 V,
SW-PGND = 10 A, TJ = 25℃
resistance
VSD
GaN 3rd quadrant conduction
drop
ISD = 500 mA, VIN floating, VVCC = 5 V, HI
= LI = 0 V
Leakage from VIN to SW when
IL-VIN-SW the high-side GaN FET and low-
side GaN FET are off
VIN = 80 V, HI = LI = 0 V, VVCC = 5 V, TJ=
25℃
25
25
150
150
µA
µA
pF
Leakage from SW to GND when
IL-SW-GND the high-side GaN FET and low-
side GaN FET are off
SW = 80 V, HI = LI = 0 V, VVCC = 5V, TJ =
25℃
Output capacitance of high-side
COSS
GaN FET and low-side GaN
FET
VDS=40 V, VGS= 0V (HI = LI = 0 V)
266
QG
Total gate charge
Output charge
VDS=40 V, ID= 10A, VGS= 5 V
VDS=40 V, ID= 10 A
3.8
21
nC
nC
QOSS
Source-to-drain reverse
recovery charge
Not including internal driver bootstrap
diode
QRR
0
29.5
29.5
29.5
29.5
2
nC
ns
ns
ns
ns
ns
ns
ns
LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN =
30 V
tHIPLH
tHIPHL
tLPLH
tLPHL
tMON
tMOFF
tPW
Propagation delay: HI rising(2)
Propagation delay: HI falling(2)
Propagation delay: LI rising(2)
Propagation delay: LI falling(2)
50
50
50
50
8
LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN =
30 V
HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN =
30 V
HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN =
30 V
Delay matching: LI high and HI
low(2)
Delay matching: LI low and HI
high(2)
2
8
Minimum input pulse width that
changes the output
10
(2) See Propagation Delay and Mismatch Measurement.
6
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
6.6 Typical Characteristics
All the curves are based on measurements made on a PCB design with dimensions of 3.2 inches (W) × 2.7 inches (L) ×
0.062 inch (T) and 4 layers of 2 oz copper.
The safe operating area (SOA) curves displays the temperature boundaries within an operating system by incorporating the
thermal resistance and system power loss. A buck converter is used for measuring the SOA. 图 2 outlines the temperature
and airflow conditions required for a given load current. The area under the curve dictates the SOA for different airflow
conditions.
90
80
70
60
50
40
30
20
100
10
1
400 LFM
200 LFM
100 LFM
Natural convection
No Load
10k
0.1
0
1
2
3
4
5
6
1
10
100
1k
Output Current (A)
Frequency (kHz)
D001
D001
VIN = 48 V
VOUT = 5 V
图 2. Safe Operating Area
fSW = 1 MHz
VDD = 5 V
图 1. VDD Supply Current vs Switching Frequency
12
10
8
25
23
21
19
17
15
13
11
9
6
4
2
7
5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125 140
Junction Temperature (°C)
0
0.5
1
1.5
2
2.5
3
Source-to-Drain Voltage (V)
D001
D001
.
GaN third quadrant conduction.
图 3. Source-to-Drain Current vs Source-to-Drain Voltage
图 4. GaN FET On-Resistance vs Junction Temperature
版权 © 2015–2017, Texas Instruments Incorporated
7
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
7 Parameter Measurement Information
7.1 Propagation Delay and Mismatch Measurement
图 5 shows the typical test setup used to measure the propagation mismatch. As the gate drives are not
accessible, pullup and pulldown resistors in this test circuit are used to indicate when the low-side GaN FET
turns ON and the high-side GaN FET turns OFF and vice versa to measure the tMON and tMOFF parameters.
Resistance values used in this circuit for the pullup and pulldown resistors are in the order of 1 kΩ; the current
sources used are 2 A.
图 6 through 图 9 show propagation delay measurement waveforms. For turnon propagation delay
measurements, the current sources are not used. For turnoff time measurements, the current sources are set to
2 A, and a voltage clamp limit is also set, referred to as VIN(CLAMP). When measuring the high-side component
turnoff delay, the current source across the high-side FET is turned on, the current source across the low-side
FET is off, HI transitions from high-to-low, and output voltage transitions from VIN to VIN(CLAMP). Similarly, for low-
side component turnoff propagation delay measurements, the high-side component current source is turned off,
and the low-side component current source is turned on, LI transitions from high to low and the output transitions
from GND potential to VIN(CLAMP). The time between the transition of LI and the output change is the propagation
delay time.
3
2
HB
HS
VIN
1
8
4
5
HI
LI
Pattern
Generator
SW
LMG5200
VOUT
PGND
9
VCC
6
AGND
7
(A)
Delay Measurement
图 5. Propagation Delay and Propagation Mismatch Measurement
8
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
Propagation Delay and Mismatch Measurement (接下页)
50%
50%
HI
LI
V
2
IN
V
IN
SW
10%
V
2
IN
10%
SW
GND
Time
Time
图 6. High-Side Gate Driver Turnon
图 7. Low-Side Gate Driver Turnon
HI
LI
50%
50%
V
IN(clamp)
V
IN
SW
10%
V
SW
10%
IN(clamp)
GND
Time
图 9. Low-Side Gate Driver Turnoff
.
图 8. High-Side Gate Driver Turnoff
8 Detailed Description
8.1 Overview
图 10 shows the LMG5200, half-bridge, GaN power stage with highly integrated high-side and low-side gate
drivers, which includes built-in UVLO protection circuitry and an overvoltage clamp circuitry. The clamp circuitry
limits the bootstrap refresh operation to ensure that the high-side gate driver overdrive does not exceed 5.4 V.
The device integrates two, 15-mΩ GaN FETs in a half-bridge configuration. The device can be used in many
isolated and non-isolated topologies allowing very simple integration. The package is designed to minimize the
loop inductance while keeping the PCB design simple. The drive strengths for turnon and turnoff are optimized to
ensure high voltage slew rates without causing any excessive ringing on the gate or power loop.
版权 © 2015–2017, Texas Instruments Incorporated
9
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
8.2 Functional Block Diagram
图 10 shows the functional block diagram of the LMG5200 device with integrated high-side and low-side GaN
FETs.
LMG5200
2
1
HB
UVLO and
Clamp
VIN
Level
Shifter
VCC
HI
6
4
3
8
HS
UVLO
SW
LI
5
9
7
PGND
AGND
图 10. Functional Block Diagram
8.3 Feature Description
The LMG5200 device brings ease of designing high power density boards without the need for underfill while
maintaining creepage and clearance requirements. The propagation delays between the high-side gate driver
and low-side gate driver are matched to allow very tight control of dead time. Controlling the dead time is critical
in GaN-based applications to maintain high efficiency. HI and LI can be independently controlled to minimize the
third quadrant conduction of the low-side FET for hard switched buck converters. A very small propagation
mismatch between the HI and LI to the drivers for both the falling and rising thresholds ensures dead times of <
10 ns. Co-packaging the GaN FET half-bridge with the driver ensures minimized common source inductance.
This minimized inductance has a significant performance impact on hard-switched topologies.
The built-in bootstrap circuit with clamp prevents the high-side gate drive from exceeding the GaN FETs
maximum gate-to-source voltage (Vgs) without any additional external circuitry. The built-in driver has an
undervoltage lockout (UVLO) on the VDD and bootstrap (HB-HS) rails. When the voltage is below the UVLO
threshold voltage, the device ignores both the HI and LI signals to prevent the GaN FETs from being partially
turned on. Below UVLO, if there is sufficient voltage (VVCC > 2.5 V), the driver actively pulls the high-side and
low-side gate driver output low. The UVLO threshold hysteresis of 200 mV prevents chattering and unwanted
turnon due to voltage spikes. Use an external VCC bypass capacitor with a value of 0.1 µF or higher. TI
recommends a size of 0402 to minimize trace length to the pin. Place the bypass and bootstrap capacitors as
close as possible to the device to minimize parasitic inductance.
8.3.1 Control Inputs
The LMG5200's inputs pins are independently controlled with TTL input thresholds and can withstand voltages
up to 12V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs of an
analog PWM controller with up to 12V power supply, eliminating the need for a buffer stage.
In order to allow flexibility to optimize deadtime according to design needs, the LMG5200 does not implement an
overlap protection functionality. If both HI and LI are asserted, both the high-side and low-side GaN FETs are
turned on. Careful consideration must be applied to the control inputs in order to avoid a shoot-through condition.
10
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
Feature Description (接下页)
8.3.2 Start-up and UVLO
The LMG5200 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the
threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially
turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates
low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET
gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.
表 1. VCC UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)
VCC - VSS < VCCR during device start-up
HI
H
L
LI
L
SW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VCC - VSS < VCCR during device start-up
H
H
L
VCC - VSS < VCCR during device start-up
H
L
VCC - VSS < VCCR during device start-up
VCC - VSS < VCCR - VCC(hyst) after device start-up
VCC - VSS < VCCR - VCC(hyst) after device start-up
VCC - VSS < VCCR - VCC(hyst) after device start-up
VCC - VSS < VCCR - VCC(hyst) after device start-up
H
L
L
H
H
L
H
L
表 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VCC > VCCR for all cases below)
HI
H
L
LI
L
SW
Hi-Z
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
H
H
L
PGND
PGND
Hi-Z
VHB-HS < VHBR during device start-up
H
L
VHB-HS < VHBR during device start-up
VHB-HS < VHBR - VHB(hyst) after device start-up
VHB-HS < VHBR - VHB(hyst) after device start-up
VHB-HS < VHBR - VHB(hyst) after device start-up
VHB-HS < VHBR - VHB(hyst) after device start-up
H
L
L
Hi-Z
H
H
L
PGND
PGND
Hi-Z
H
L
8.3.3 Bootstrap Supply Voltage Clamping
The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V (typical).
This clamp prevents the gate voltage from exceeding the maximum gate-source voltage rating of the
enhancement-mode GaN FETs.
8.3.4 Level Shift
The level-shift circuit is the interface from the high-side input HI to the high-side driver stage, which is referenced
to the switch node (HS). The level shift allows control of the high-side GaN FET gate driver output, which is
referenced to the HS pin and provides excellent delay matching with the low-side driver.
版权 © 2015–2017, Texas Instruments Incorporated
11
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
8.4 Device Functional Modes
The LMG5200 operates in normal mode and UVLO mode. See Start-up and UVLO for information on UVLO
operation mode. In the normal mode, the output state is dependent on the states of the HI and LI pins. 表 3 lists
the output states for different input pin combinations. Note that when both HI and LI are asserted, both GaN
FETs in the power stage are turned on. Careful consideration must be applied to the control inputs in order to
avoid this state, as it will result in a shoot-through condition, which can permanently damage the device.
表 3. Truth Table
HI
L
LI
L
HIGH-SIDE GaN FET
LOW-SIDE GaN FET
SW
Hi-Z
PGND
VIN
OFF
OFF
ON
OFF
ON
L
H
L
H
H
OFF
ON
H
ON
- - -
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMG5200 GaN power stage is a versatile building block for various types of high-frequency, switch-mode
power applications. The high-performance gate driver IC integrated in the package helps minimize the parasitics
and results in extremely fast switching of the GaN FETs. The device design is highly optimized for synchronous
buck converters and other half-bridge configurations.
9.2 Typical Application
图 11 shows a synchronous buck converter application with VCC connected to a 5-V supply. It is critical to
optimize the power loop (loop impedance from VIN capacitor to PGND). Having a high power loop inductance
causes significant ringing in the SW node and also causes the associated power loss. Refer to the Layout
Guidelines section for information on how to minimize this power loop.
3
2
HB
HS
VIN
1
8
4
5
HI
LI
VOUT
PWM
Controller
SW
LMG5200
PGND
9
VCC
6
AGND
7
5-V VIN
图 11. Typical Connection Diagram For a Synchronous Buck Converter
12
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
Typical Application (接下页)
9.2.1 Design Requirements
When designing a synchronous buck converter application that incorporates the LMG5200 power stage, some
design considerations must be evaluated first to make the most appropriate selection. Among these
considerations are the input voltages, passive components, operating frequency, and controller selection.表 4
shows some sample values for a typical application. See Power Supply Recommendations, Layout, and Power
Dissipation for other key design considerations for the LMG5200.
表 4. Design Parameters
PARAMETER
Half-bridge input supply voltage, VIN
Output voltage, VOUT
Output current
SAMPLE VALUE
48 V
12 V
8 A
VHB-HS bootstrap capacitor
Switching frequency
Dead time
0.1 uF, X5R
1 MHz
8 ns
Inductor
4.7 µH
Controller
TPS40400
9.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LMG5200 in a synchronous buck converter. For additional
design help, see 相关文档 .
9.2.2.1 VCC Bypass Capacitor
The VCC bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with 公式 1.
CVCC = (QgH + QgL + Qrr) / ΔV
(1)
QgH and QgL are the gate charge of the high-side and low-side transistors, respectively. Qrr is the reverse
recovery charge of the bootstrap diode. ΔV is the maximum allowable voltage drop across the bypass capacitor.
A 0.1-µF or larger value, good-quality, ceramic capacitor is recommended. Place the bypass capacitor as close
as possible to the VCC and AGND pins of the device to minimize the parasitic inductance.
9.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side gate drive, dc bias power for HB UVLO circuit,
and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated
using 公式 2.
CBST = (QgH + Qrr + IHB * tON(max)) / ΔV
where
•
•
•
•
•
IHB is the quiescent current of the high-side gate driver (150 µA, maximum)
tON(maximum) is the maximum on-time period of the high-side gate driver
Qrr is the reverse recovery charge of the bootstrap diode
QgH is the gate charge of the high-side GaN FET
ΔV is the permissible ripple in the bootstrap capacitor (< 100 mV, typical)
(2)
A 0.1-µF, 16-V, 0402 ceramic capacitor is suitable for most applications. Place the bootstrap capacitor as close
as possible to the HB and HS pins.
版权 © 2015–2017, Texas Instruments Incorporated
13
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
9.2.2.3 Power Dissipation
Ensure that the power loss in the driver and the GaN FETs is maintained below the maximum power dissipation
limit of the package at the operating temperature. The smaller the power loss in the driver and the GaN FETs,
the higher the maximum operating frequency that can be achieved in the application. The total power dissipation
of the LMG5200 device is the sum of the gate driver losses, the bootstrap diode power loss and the switching
and conduction losses in the FETs.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated using
公式 3.
P = (2 ì Qg) ì VDD ì fSW
where
•
•
•
Qg is the gate charge
VDD is the bias supply
fSW is the switching frequency
(3)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the outputs.
图 1 shows the measured gate driver power dissipation versus frequency and load capacitance. Use this graph
to approximate the power losses due to the gate drivers.
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
The power losses due to the GaN FETs can be divided into conduction losses and switching losses. Conduction
losses are resistive losses and can be calculated using 公式 4.
2
2
»
ÿ
»
ÿ
ì RDS(on)LS
PCOND = (IRMS(HS)
)
ì RDS(on)HS + (IRMS(LS)
)
⁄
⁄
where
•
•
•
•
RDS(on)HS is the high-side GaN FET on-resistance
RDS(on)LS is the low-side GaN FET on-resistance
IRMS(HS) is the high-side GaN FET RMS current
IRMS(LS) and low-side GaN FET RMS current
(4)
(5)
The switching losses can be computed to a first order using 公式 5.
= V ´I ´ f ´ t
P
SW
IN OUT
SW
TR
where
•
tTR is the switch transition time from ON to OFF and from OFF to ON
Note that the low-side FET does not suffer from this loss. The third quadrant loss in the low-side device is
ignored in this first order loss calculation.
As described previously, switching frequency has a direct effect on device power dissipation. Although the gate
driver of the LMG5200 device is capable of driving the GaN FETs at frequencies up to 10 MHz, careful
consideration must be applied to ensure that the running conditions for the device meet the recommended
operating temperature specification. Specifically, hard-switched topologies tend to generate more losses and self-
heating than soft-switched applications.
The sum of the driver loss, the bootstrap diode loss, and the switching and conduction losses in the GaN FETs is
the total power loss of the device. Careful board layout with an adequate amount of thermal vias close to the
power pads (VIN and PGND) allows optimum power dissipation from the package. A top-side mounted heat sink
with airflow can also improve the package power dissipation.
14
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
9.2.3 Application Curves
图 13. Zoom-In Showing the Dead Time of 7.7 ns and the
图 12. SW Node Behavior Showing the Dead Time
Overshoot of the SW Node
10 Power Supply Recommendations
The recommended bias supply voltage range for LMG5200 is from 4.75 V to 5.25 V. The lower end of this range
is governed by the internal undervoltage lockout (UVLO) protection feature of the VCC supply circuit. The upper
end of this range is driven by the 6 V absolute maximum voltage rating of VCC. Note that the gate voltage of the
low-side GaN FET is not clamped internally. Hence, it is important to keep the VCC bias supply within the
recommended operating range to prevent exceeding the low-side GaN transistor gate breakdown voltage.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VCC voltage drops, the device continues to operate in normal mode as far as the voltage
drop does not exceeds the hysteresis specification, VCC(hyst). If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 4.5 V range, the voltage ripple on
the auxiliary power supply output must be smaller than the hysteresis specification of LMG5200 to avoid
triggering device-shutdown.
Place a local bypass capacitor between the VDD and VSS pins. This capacitor must be located as close as
possible to the device. A low ESR, ceramic surface-mount capacitor is recommended. TI recommends using 2
capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed
very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias
requirements.
版权 © 2015–2017, Texas Instruments Incorporated
15
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
To maximize the efficiency benefits of fast switching, it is extremely important to optimize the board layout such
that the power loop impedance is minimal. When using a multilayer board (more than 2 layers), power loop
parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND),
small and directly underneath the first layer as shown in 图 14 and 图 15. Loop inductance is reduced due to flux
cancellation as the return current is directly underneath and flowing in the opposite direction. It is also critical that
the VCC capacitors and the bootstrap capacitors are as close as possible to the device and in the first layer.
Carefully consider the AGND connection of LMG5200 device. It must NOT be directly connected to PGND so
that PGND noise does not directly shift AGND and cause spurious switching events due to noise injected in HI
and LI signals.
11.2 Layout Examples
Placements shown in 图 14 and in the cross section of 图 15 show the suggested placement of the device with
respect to sensitive passive components, such as VIN, bootstrap capacitors (HS and HB) and VSS capacitors.
Use appropriate spacing in the layout to reduce creepage and maintain clearance requirements in accordance
with the application pollution level. Inner layers if present can be more closely spaced due to negligible pollution.
The layout must be designed to minimize the capacitance at the SW node. Use as small an area of copper as
possible to connect the device SW pin to the inductor, or transformer, or other output load. Furthermore, ensure
that the ground plane or any other copper plane has a cutout so that there is no overlap with the SW node, as
this would effectively form a capacitor on the printed circuit board. Additional capacitance on this node reduces
the advantages of the advanced packaging approach of the LMG5200 and may result in reduced performance.
图 16, 图 17, 图 18, and 图 19 show an example of how to design for minimal SW node capacitance on a four-
layer board. In these figures, U1 is the LMG5200 device.
PGND
Metal underneath solder mask
VIN Capacitors
VIN
VIN
HS
HB
HI
LI
LMG5200
PGND
PGND
Legend
VCC AGND
Metal 1
SW
SW
Metal 2 (PGND)
Vias
图 14. External Component Placement (Single Layer)
16
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
Layout Examples (接下页)
Legend
VIN
SW
PGND
PGND
Metal 3
Small Return Path
Minimizes Power Loop
Impedance
VIN Capacitors
LMG5200
4 Layer PCB
图 15. Four-Layer Board Cross Section With Return Path Directly Underneath for Power Loop
图 16. Top Layer
图 17. Ground Plane
版权 © 2015–2017, Texas Instruments Incorporated
17
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
Layout Examples (接下页)
图 18. Middle Layer
图 19. Bottom Layer
VIN Capacitors
VIN
VIN
HS
HB
HI
LI
LMG5200
PGND
PGND
Legend
Metal 1
Bottom Layer
Metal 1 (SW)
Vias
VCC AGND
SW
SW
VIN Capacitors (Bottom Layer)
图 20. External Component Placement (Double Layer PCB)
18
版权 © 2015–2017, Texas Instruments Incorporated
LMG5200
www.ti.com.cn
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
Layout Examples (接下页)
Legend
VIN
SW (Top Layer)
PGND
PGND (Bottom Layer)
Small Return Path
Minimizes Power Loop
Impedance
LMG5200
2 Layer PCB
VIN Capacitors
图 21. Two-Layer Board Cross Section With Return Path
Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance.
However, if design considerations allow only two board layers, place the input decoupling capacitors immediately
behind the device on the back-side of the board to minimize loop inductance. 图 20 and 图 21 show a layout
example for two-layer boards.
版权 © 2015–2017, Texas Instruments Incorporated
19
LMG5200
ZHCSFT3D –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
《LMG5200 PSpice 瞬态模型》
《LMG5200 TINA-TI 瞬态参考设计》
《LMG5200 TINA-TI 瞬态 Spice 模型》
12.2 文档支持
12.2.1 相关文档
《LMG5200 GaN 功率级模块布局指南》
《使用 LMG5200：GaN 半桥功率模块评估模块》
12.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
13.1 封装信息
LMG5200 器件封装为 MSL3 封装（湿敏等级 3）。请参阅应用报告 《AN-2029 操作和处理建议》获取 MSL3 封
装的具体操作和处理建议。
20
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMG5200MOFR
LMG5200MOFT
ACTIVE
QFM
QFM
MOF
9
9
2000 RoHS & Green
250 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LMG5200
513B
ACTIVE
MOF
NIAU
LMG5200
513B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMG5200MOFR
QFM
MOF
9
2000
330.0
16.4
6.3
8.3
2.2
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
QFM MOF
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
LMG5200MOFR
9
2000
Pack Materials-Page 2
PACKAGE OUTLINE
MOF0009A
QFM - 2 mm max height
S
C
A
L
E
1
.
8
0
0
QUAD FLAT MODULE
6.1
5.9
A
B
PIN 1 INDEX AREA
8.1
7.9
C
2 MAX
SEATING PLANE
1.8
SYMM
0.75
0.65
6X
4
5
3
2
6
7
1.2
0.55
6X
0.45
0.1
0.08
3.55
C A
B
2.05
PKG
1.78
4.3
4.2
3X
0.05
C A
B
(0.1)
ALL AROUND
8
1
9
0.75
0.65
2X
2.55
0.05
C A
B
1.1
1.0
4221487/B 06/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
MOF0009A
QFM - 2 mm max height
QUAD FLAT MODULE
SYMM
PKG
(2.55)
(1.05)
(R0.05) TYP
9
8
1
3X (4.25)
3X
(1.78)
PKG
2X (0.7)
(2.05)
(3.55)
7
2
3
(1.2)
6
6X (0.5)
4
5
6X (0.7)
(1.8)
4X (2.55)
LAND PATTERN EXAMPLE
SCALE:12X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
ALL PADS
4221487/B 06/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
MOF0009A
QFM - 2 mm max height
QUAD FLAT MODULE
PKG
SYMM
(2.55)
10X (0.7)
5X(1.05)
1
9
8
15X (0.59)
SOLDER MASK EDGE
TYP
METAL
TYP
(0.89) TYP
PKG
(R0.05) TYP
(2.05)
(3.55)
7
6
2
3
6X (0.5)
(1.2)
4
5
6X (0.7)
(1.8)
(2.55)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PADS 1, 8 & 9
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4221487/B 06/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
LMG5200MOFR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| LMG5200MOFT | TI | 80V GaN 半桥功率级 | MOF | 9 | -40 to 125 | 完全替代 |
|
LMG5200MOFR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LMG5200MOFT | TI | 80V GaN 半桥功率级 | MOF | 9 | -40 to 125 | 获取价格 |
|
| LMG5278XUFC-00T | HITACHI | INTERFACE SPECIFICATION | 获取价格 |
|
| LMG6382QHFR | HITACHI | LCD MODULE REFLECTIVE FILM BLACK & WHITE MODE WITH BULT-IN CONTROLLER AND RAM | 获取价格 |
|
| LMG6402PLFR | HITACHI | Optoelectronic Device | 获取价格 |
|
| LMG7400PLFC | HITACHI | 240 128 DOTS | 获取价格 |
|
| LMG7402PLFF | HITACHI | 240 128 DOTS | 获取价格 |
|
| LMG7420PLFC-X | HITACHI | 240 128 DOTS | 获取价格 |
|
| LMG7520RPFC | HITACHI | LCD MODULE | 获取价格 |
|
| LMG80G06A | LEIDITECH | Package : DFN5X6-8; Vdss Min(V) Drain-Source voltage : 60; Drain Current ID(A)25℃ : 80; Vgs(V) : 20; Vth Typ : 1.7; Ron(10V) (mΩ)Typ : 3.5; Ron(10V) (mΩ) Max : 4.2; Ron(4.5V) (mΩ)Typ : 4.2; Ron(4.5V) (mΩ)Max : 5.2; | 获取价格 |
|
| LMGSF1N02LT1 | LRC | Power MOSFET 750 mAmps, 20 Volts | 获取价格 |
|
LMG5200MOFR 相关文章
HARTING(浩亭)圆形连接器产品选型手册
- 2024-10-31
- 6
HYCON(宏康科技)产品选型手册
- 2024-10-31
- 6
GREEGOO整流二极管和晶闸管产品选型手册
- 2024-10-31
- 7
西门子豪掷106亿美元，战略收购工程软件巨头Altair
- 2024-10-31
- 8
