LMH0044SQ/NOPB [TI]
SMPTE 292M/259M 自适应电缆均衡器 | RUM | 16 | 0 to 85;
| 型号： | LMH0044SQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SMPTE 292M/259M 自适应电缆均衡器 | RUM | 16 | 0 to 85 电信 电信集成电路 |
| 文件： | 总16页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH0044
www.ti.com
SNLS216E –APRIL 2006–REVISED APRIL 2013
LMH0044 SMPTE 292M / 259M Adaptive Cable Equalizer
Check for Samples: LMH0044
1
FEATURES
DESCRIPTION
The LMH0044 SMPTE 292M / 259M adaptive cable
2
•
SMPTE 292M, SMPTE 344M and SMPTE 259M
Compliant
equalizer is monolithic integrated circuit for
a
equalizing data transmitted over cable (or any media
with similar dispersive loss characteristics). The
equalizer operates over a wide range of data rates
from 125 Mbps to 1.485 Gbps and supports SMPTE
292M, SMPTE 344M and SMPTE 259M.
•
•
•
Supports DVB-ASI at 270 Mbps
Data rates: 125 Mbps to 1.485 Gbps
Equalizes up to 200 Meters of Belden 1694A at
1.485 Gbps or up to 400 meters of Belden
1694A at 270 Mbps
The LMH0044 implements DC restoration to correctly
handle pathological data conditions (DC restoration
may be bypassed for low data rate applications). The
equalizer may be driven in either a single ended or
differential configuration.
•
Manual Bypass and Output Mute with a
Programmable Threshold
•
•
•
•
Single-Ended or Differential Input
50Ω Differential Outputs
Additional features include separate carrier detect
and output mute pins which may be tied together to
mute the output when no signal is present. A
programmable mute reference is provided to mute the
output at a selectable level of signal degradation.
Single 3.3V Supply Operation
208 mW Typical Power Consumption with 3.3V
Supply
•
Replaces the GS1574 and GS1574A
APPLICATIONS
•
SMPTE 292M, SMPTE 344M, and SMPTE 259M
Serial Digital Interfaces
•
•
Serial Digital Data Equalization and Reception
Data Recovery Equalization
Typical Application
6.8 nH
LMH0044 Adaptive
Cable Equalizer
Coaxial Cable
1 mF
4.7 mF
SDO
SDO
SDI
SDI
75W
Outputs
75W
4.7 mF
1 mF
MUTE
MUTE
CD
AEC+
AEC-
REF
BYPASS
37.4W
1 mF
MUTE
CD
MUTE
REF
BYPASS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMH0044
SNLS216E –APRIL 2006–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.5V to 3.6V
−0.3V to VCC+0.3V
−65°C to +150°C
+150°C
Input Voltage (all inputs)
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering 4 Sec)
Package Thermal Resistance
+260°C
θJA 16-pin WQFN
θJC 16-pin WQFN
+43°C/W
+9°C/W
ESD Rating (HBM)
ESD Rating (MM)
8kV
250V
(1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of "Electrical Characteristics" specifies acceptable device operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Supply Voltage (VCC – VEE
)
3.3V ±5%
1.0 µF
Input Coupling Capacitance
AEC Capacitor (Connected between AEC+ and AEC-)
Operating Free Air Temperature (TA)
1.0 µF
0°C to +85°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2)
.
Parameter
Test Conditions
Reference
Min
Typ
1.9
Max
Units
V
VCMIN
VSDI
Input Common Mode Voltage
Input Voltage Swing
SDI, SDI
At LMH0044 input(3)(4)
720
800
950
mVP−P
VCMOUT Output Common Mode Voltage
SDO, SDO
VCC –
VSDO/2
V
VSDO
Output Voltage Swing
MUTEREF DC Voltage (floating)
MUTEREF Range
50Ω load, differential
750
1.3
0.7
mVP-P
MUTEREF
CD
V
V
CD Output Voltage
Carrier not present
Carrier present
2.6
3.0
V
0.4
V
MUTE Input Voltage
Supply Current
Min to mute outputs
Max to force outputs active
See(5)
MUTE
V
0.8
77
V
ICC
63
mA
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3V and TA = +25°C.
(3) Specification is ensured by characterization.
(4) The maximum input voltage swing assumes a nonstressing, DC-balance signal; specifically, the SMPTE-recommended color bar test
signal. Pathological or other stressing signals may not be used. This specification is for 0m cable only.
(5) Supply current depends on the amount of cable being equalized. The current is highest for short cable and decreases as the cable
length is increased. Refer to Figure 2 and Figure 3.
2
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Product Folder Links: LMH0044
LMH0044
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SNLS216E –APRIL 2006–REVISED APRIL 2013
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)
.
Parameter
Test Conditions
Reference
SDI, SDI
Min
Typ
Max
Units
Mbps
Mbps
BRMIN
BRMAX
Minimum Input Data Rate
Maximum Input Data Rate
125
1485
Jitter for various Cable Lengths 270 Mbps, Belden 1694A,
(with equalizer pathological)
0.2
0.2
UI
UI
UI
UI
UI
400 meters(2)
270 Mbps, Belden 8281,
280 meters(2)
1.485 Gbps, Belden 1694A,
140 meters(2)
0.25
0.25
0.3
1.485 Gbps, Belden 8281,
100 meters(2)
1.485 Gbps, Belden 1694A,
200 meters(2)
tr,tf
Output Rise Time, Fall Time
Mismatch in Rise/Fall Time
Output Overshoot
20% – 80%(2)
See(2)
See(2)
Single-Ended(3)
See(4)
SDO, SDO
SDI, SDI
100
2
220
15
5
ps
ps
%
tOS
1
ROUT
RLIN
RIN
Output Resistance
50
Ω
Input Return Loss
15
18-20
1.3
1
dB
kΩ
pF
Input Resistance
Single-Ended
Single-Ended(3)
CIN
Input Capacitance
(1) Typical values are stated for VCC = +3.3V and TA = +25°C.
(2) Specification is ensured by characterization.
(3) Specification is ensured by design.
(4) Input return loss is dependent on board design. The LMH0044 meets this specification on the SD044 evaluation board from 5 MHz to
1.5 GHz.
Connection Diagram
16
15
14
13
1
2
3
4
12
11
10
9
V
V
EE
EE
SDI
SDI
SDO
SDO
LMH0044
(top view)
V
EE
V
EE
5
6
7
8
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative
power supply voltage.
Figure 1. 16-Pin WQFN Package
See Package Number RUM0016A
Copyright © 2006–2013, Texas Instruments Incorporated
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SNLS216E –APRIL 2006–REVISED APRIL 2013
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Table 1. Pin Descriptions
Pin No.
Name
Description
1
2
3
4
5
6
7
8
VEE
Negative power supply (ground).
SDI
Serial data true input.
SDI
Serial data complement input.
Negative power supply (ground).
VEE
AEC+
AEC-
AEC loop filter external capacitor (1µF) positive connection.
AEC loop filter external capacitor (1µF) negative connection.
BYPASS
MUTEREF
Bypasses equalization and DC restoration when high. No equalization occurs in this mode.
Mute reference. Sets the threshold for CD and (with CD tied to MUTE) determines the maximum cable
to be equalized before muting. MUTEREF may be unconnected for maximum equalization.
9
VEE
Negative power supply (ground).
Serial data complement output.
Serial data true output.
10
11
12
13
14
SDO
SDO
VEE
Negative power supply (ground).
Positive power supply (+3.3V).
VCC
MUTE
Output mute. To disable the mute function and enable the output, MUTE must be tied to GND or a low
level signal. To force the outputs to a muted state, tie to VCC. CD may be tied to this pin to inhibit the
output when no input signal is present. MUTE has no function in BYPASS mode.
15
16
CD
Carrier detect. CD is high when no signal is present. CD has no function in BYPASS mode.
Positive power supply (+3.3V).
VCC
VEE
DAP
Connect exposed DAP to negative power supply.
Block Diagram
BYPASS
Output
Driver
DC
SDI
SDI
SDO
SDO
Equalizer
Filter
Restoration/
Level Control
Energy
Detect
Energy
Detect
S
Automatic
Equalization
Control
Carrier
Detect/
Mute
CD
MUTE
MUTE
REF
AEC+ AEC-
4
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Product Folder Links: LMH0044
LMH0044
www.ti.com
SNLS216E –APRIL 2006–REVISED APRIL 2013
Device Operation
BLOCK DESCRIPTION
The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This
block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this
function is disabled.
The signals before and after the DC Restoration / Level Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The
loop response in the AEC block is controlled by an external 1µF capacitor placed across the AEC+ and AEC-
pins.
The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output.
This block utilizes the CD and MUTE signals along with Mute Reference (MUTEREF).
The Output Driver produces SDO and SDO.
MUTE REFERENCE (MUTEREF
)
The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to
equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the
length of cable to equalize. As the applied MUTEREF voltage is increased, the amount of cable that can be
equalized before carrier detect is de-asserted and the outputs are muted is decreased. MUTEREF may be left
unconnected for maximum equalization before muting.
CARRIER DETECT (CD) AND MUTE
Carrier detect CD indicates if a valid signal is present at the LMH0044 input. If MUTEREF is used, the carrier
detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the
LMH0044 input. CD is low when a valid input signal is detected.
MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the
LMH0044 outputs. Applying a low input will force the outputs to be active.
CD and MUTE may be tied together to automatically mute the output when no input signal is present.
INPUT INTERFACING
The LMH0044 accepts either differential or single-ended input. The input must be AC coupled. Transformer
coupling is not supported.
The LMH0044 correctly handles equalizer pathological signals for standard definition and high definition serial
digital video, as described in SMPTE RP 178 and RP 198, respectively.
OUTPUT INTERFACING
The SDO and SDO outputs are internally loaded with 50Ω. They produce a 750 mVP-P differential output, or a
375 mVP-P single-ended output.
Copyright © 2006–2013, Texas Instruments Incorporated
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SNLS216E –APRIL 2006–REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
PCB LAYOUT RECOMMENDATIONS
Refer to the following Application Note on TI's website: AN-1372, “LMH0034 PCB Layout Techniques.” The PCB
layout techniques in the application note apply to the LMH0044 as well.
REPLACING THE GENNUM GS1574A
The LMH0044 is footprint compatible with the Gennum GS1574A.
SUPPLY CURRENT VS. CABLE LENGTH
The supply current (ICC) depends on the amount of cable being equalized. The current is highest for short cable
and decreases as the cable length is increased. Figure 2 shows supply current vs. Belden 1694A cable length for
1.485 Gbps data and Figure 3 shows supply current vs. Belden 1694A cable length for 270 Mbps data.
75
70
65
60
55
0
50
100
150
200
BELDEN 1694A CABLE LENGTH (m)
Figure 2. Supply Current vs. Belden 1694A Cable Length, 1.485 Gbps
6
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Product Folder Links: LMH0044
LMH0044
www.ti.com
SNLS216E –APRIL 2006–REVISED APRIL 2013
75
70
65
60
55
0
100
200
300
400
BELDEN 1694A CABLE LENGTH (m)
Figure 3. Supply Current vs. Belden 1694A Cable Length, 270 Mbps
Copyright © 2006–2013, Texas Instruments Incorporated
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LMH0044
SNLS216E –APRIL 2006–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH0044SQ/NOPB
LMH0044SQE/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RUM
RUM
16
16
1000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 85
0 to 85
L044
L044
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0044SQ/NOPB
LMH0044SQE/NOPB
WQFN
WQFN
RUM
RUM
16
16
1000
250
178.0
178.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0044SQ/NOPB
LMH0044SQE/NOPB
WQFN
WQFN
RUM
RUM
16
16
1000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RUM0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
DIM A
OPT 1
0.2
OPT 2
0.1
2X 1.95
SYMM
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.6 0.1
12X 0.65
1
12
0.35
0.25
16X
PIN 1 ID
(45 X 0.3)
13
16
0.1
C A B
0.5
0.3
0.05
16X
4214998/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUM0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1.05)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214998/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUM0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.675) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.15)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4214998/A 11/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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