LMH0302SQE/NOPB [TI]
3G HD/SD SDI 电缆驱动器 | RUM | 16 | -40 to 85;
| 型号： | LMH0302SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3G HD/SD SDI 电缆驱动器 | RUM | 16 | -40 to 85 驱动 驱动器 |
| 文件： | 总20页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
LMH0302 3Gbps HD/SD SDI 电缆驱动器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
支持 ST 424 (3G)、292 (HD) 和 259 (SD)
LMH0302 3Gbps HD/SD SDI 电缆驱动器设计用于 ST
424、ST 292、ST 344 和 ST 259 串行数字视频 应
用。LMH0302 以高达 2.97Gbps 的数据速率驱动
75Ω 传输线路（Belden 1694A、Belden 8281 或等效
电缆）。
数据速率高达 2.97Gbps
支持 DVB-ASI（270Mbps 时）
100Ω 差分输入
75Ω 单端输出
可选转换率
LMH0302 提供有两种可选转换率，以符合 ST 259 和
ST 424/292。输出驱动器可通过输出驱动器使能引脚
实现掉电。
输出驱动器掉电控制
3.3V 单电源运行
工业温度范围：-40°C 至 85°C
LMH0302 由 3.3V 单电源供电运行。SD 模式下的典型
功耗为 125mW；HD 模式下的典型功耗为 165mW。
LMH0302 采用 16 引脚 WQFN 封装。
典型功耗：125mW（SD 模式），165mW（HD 模
式）
•
•
•
16 引脚超薄型四方扁平无引线 (WQFN) 封装
封装与 LMH0002SQ 兼容
器件信息(1)
替代 Gennum GS2978
器件型号
LMH0302
封装
封装尺寸（标称值）
WQFN (16)
4.00mm x 4.00mm
2 应用
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
•
ST 424、ST 292、ST 344 和 ST 259 串行数字接
口
•
•
数字视频路由器和交换机
分布式放大器
典型应用
V
CC
0.1 mF
75W
75W
SD/HD
ENABLE
6.8 nH
1.0 mF
4.7 mF
ENABLE
SDI
49.9W
49.9W
SD/HD
75W
75W
SDO
SDO
LMH0302
4.7 mF
R
REF
SDI
1.0 mF
Differential
Input
V
CC
6.8 nH
0.1 mF
750W
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS247
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
目录
7.3 Feature Description .................................................. 6
7.4 Device Functional Modes.......................................... 7
Application and Implementation .......................... 8
8.1 Application Information ............................................ 8
8.2 Typical Application ................................................... 8
Power Supply Recommendations...................... 10
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics – DC ................................. 4
6.6 Electrical Characteristics – AC.................................. 5
6.7 Typical Characteristics ............................................. 5
Detailed Description .............................................. 6
7.1 Overview .................................................................. 6
7.2 Functional Block Diagram ........................................ 6
8
9
10 Layout................................................................... 10
10.1 Layout Guidelines ................................................ 10
10.2 Layout Example ................................................... 11
11 器件和文档支持 ..................................................... 12
11.1 社区资源................................................................ 12
11.2 商标....................................................................... 12
11.3 静电放电警告......................................................... 12
11.4 Glossary................................................................ 12
12 机械、封装和可订购信息....................................... 12
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision G (April 2013) to Revision H
Page
•
已添加 ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
Changes from Revision F (April 2013) to Revision G
Page
•
已更改 国家数据表的版面布局至 TI 格式................................................................................................................................ 1
2
Copyright © 2007–2016, Texas Instruments Incorporated
LMH0302
www.ti.com.cn
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
5 Pin Configuration and Functions
RUM Package
16-Pin WQFN
Top View
SDI
SDI
1
12
11
10
9
SDO
SDO
2
3
4
GND
VEE
SD/HD
VCC
RREF
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Output driver enable. When low, the SDO/SDO output driver is powered off. ENABLE has an
internal pullup. H = Normal operation. L = Output driver powered off.
ENABLE
6
I
EP is the exposed pad at the bottom of the WQFN package. The exposed pad must be
connected to the ground plane through a via array. See Figure 6 for details.
EP
—
G
5, 7, 8, 13,
14, 15, 16
NC
—
No connect. Not bonded internally.
RREF
SD/HD
4
I
I
Output driver level control. Connect a resistor to VCC to set output voltage swing.
Output slew rate control. Output rise/fall time complies with ST 424 or 292 when low and ST 259
when high.
10
SDI
1
2
I
Serial data true input.
SDI
I
Serial data complement input.
Serial data true output.
SDO
SDO
VCC
VEE
12
11
9
O
O
P
G
Serial data complement output.
Positive power supply (3.3 V).
Negative power supply (ground).
3
(1) G = Ground, I = Input, O = Output, and P = Power
Copyright © 2007–2016, Texas Instruments Incorporated
3
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.3
MAX
3.6
UNIT
V
Supply voltage
Input voltage (all inputs)
Output current
VCC + 0.3
28
V
mA
°C
°C
°C
Lead temperature, soldering (4 s)
Junction temperature, TJ
Storage temperature, Tstg
260
125
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4500
±2000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3.46
100
85
UNIT
Supply voltage (VCC – VEE
)
3.13
3.3
V
Operating junction temperature
Operating free air temperature, TA
°C
°C
–40
25
6.4 Thermal Information
LMH0302
THERMAL METRIC(1)
RUM (WQFN)
16 PINS
47.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47.2
25.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
ψJB
25.7
RθJC(bot)
14.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics – DC
Over supply voltage and operating free-air temperature range (unless otherwise noted)
(1)(2)
PARAMETER
TEST CONDITIONS
SDI, SDI
Differential, SDI, SDI
MIN
1.1 + VSDI/2
100
TYP
MAX
VCC – VSDI/2
2200
UNIT
V
VCMIN
VSDI
Input common mode voltage
Input voltage swing
mVP−P
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 V.
(2) Typical values are stated for VCC = 3.3 V and TA = 25°C.
4
Copyright © 2007–2016, Texas Instruments Incorporated
LMH0302
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ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
Electrical Characteristics – DC (continued)
(1)(2)
Over supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SDO, SDO
MIN
TYP
MAX
UNIT
VCMOUT Output common mode voltage
VCC – VSDO
V
Single-ended, 75-Ω load,
RREF = 750 Ω 1%
VSDO
Output voltage swing
720
2
800
880
mVP−P
VIH
VIL
Input voltage high level
Input voltage low level
SD/HD, ENABLE
V
V
SD/HD, ENABLE
0.8
59
33
48
22
SD/HD = 0, SDO/SDO enabled
SD/HD = 0, SDO/SDO disabled
SD/HD = 1, SDO/SDO enabled
SD/HD = 1, SDO/SDO disabled
50
26
38
15
ICC
Supply current
mA
6.6 Electrical Characteristics – AC
Over supply voltage and operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
Input data rate
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRSDI
SDI, SDI
2970
Mbps
2.97 Gbps, SDO, SDO
20
18
15
90
Tjit
Additive jitter
1.485 Gbps, SDO, SDO
psP-P
270 Mbps, SDO, SDO
SD/HD = 0, 20% – 80%, SDO, SDO
SD/HD = 1, 20% – 80%, SDO, SDO
SD/HD = 0, SDO, SDO
130
800
30
tr,tf
Output rise time, fall time
ps
ps
400
TMATCH Mismatch in rise time, fall time
SD/HD = 1, SDO, SDO
50
SD/HD = 0, 2.97 Gbps, SDO, SDO(2)
SD/HD = 0, 1.485 Gbps, SDO, SDO(2)
SD/HD = 1, SDO, SDO(2)
SD/HD = 0, SDO, SDO(2)
SD/HD = 1, SDO, SDO(2)
27
TDCD
Duty cycle distortion
30
ps
100
10%
8%
TOS
Output overshoot
Output return loss
5 MHz to 1.5 GHz, SDO, SDO(3)
1.5 GHz to 3.0 GHz, SDO, SDO(3)
15
10
RLSDO
dB
(1) Typical values are stated for VCC = 3.3 V and TA = 25°C.
(2) Specification is ensured by characterization.
(3) Output return loss is dependent on board design. The LMH0302 meets this specification on the SD302 evaluation board.
6.7 Typical Characteristics
Typical device characteristics at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
200 ps/DIV
100 ps/DIV
Figure 2. SDO PRBS10 at 1.485 Gbps
Figure 1. SDO PRBS10 at 2.97 Gbps
Copyright © 2007–2016, Texas Instruments Incorporated
5
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LMH0302 ST 424, ST292, ST259 serial digital cable driver is a monolithic, high-speed cable driver designed
for use in serial digital video data transmission applications. The LMH0302 drives 75-Ω transmission lines
(Belden 8281, 1694A, Canare L-5CFB, or equivalent) at data rates up to 2.97 Gbps.
The LMH0302 provides two selectable slew rates for ST 259 and ST 292/424 compliance. The output voltage
swing is adjustable through a single external resistor ( RREF).
The LMH0302 is powered from a single 3.3-V supply. Power consumption is typically 125 mW in SD mode and
165 mW in HD mode. The LMH0302 is available in a 16-pin WQFN package.
7.2 Functional Block Diagram
SDO
SDO
SDI
+
-
+
-
SDI
RREF
Bias Generator
Control
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The LMH0302 data path consists of several key blocks:
•
•
•
•
Input interfacing
Output interfacing
Output slew rate control
Output enable
7.3.1 Input Interfacing
The LMH0302 accepts either differential or single-ended input. The inputs are self-biased, allowing for simple AC
or DC coupling. DC-coupled inputs must be kept within the specified common-mode range.
7.3.2 Output Interfacing
The LMH0302 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75-Ω AC-coupled
coaxial cable with an RREF resistor of 750 Ω. The RREF resistor is connected between the RREF pin and VCC
.
6
Copyright © 2007–2016, Texas Instruments Incorporated
LMH0302
www.ti.com.cn
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
Feature Description (continued)
The RREF resistor must be placed as close as possible to the RREF pin. In addition, the copper in the plane layers
below the RREF network must be removed to minimize parasitic capacitance.
7.3.3 Output Slew Rate Control
The LMH0302 output rise and fall times are selectable for either ST 259, ST 424, or 292 compliance through the
SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise and fall times,
ST 424 and ST 292 compliance, SD/HD is set low.
7.3.4 Output Enable
The SDO/SDO output driver are enabled or disabled with the ENABLE pin. When set low, the output driver is
powered off. ENABLE has an internal pullup.
7.4 Device Functional Modes
The LMH0302 features are programmed using pin mode only.
Copyright © 2007–2016, Texas Instruments Incorporated
7
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0302 is a single-channel SDI cable driver that supports different application spaces. The following
sections describe the typical use cases and common implementation practices.
8.1.1 General Guidance for All Applications
The SMPTE specifications define the use of AC-coupling capacitors for transporting uncompressed serial data
streams with heavy low-frequency content. This specification requires the use of a 4.7-µF AC-coupling capacitor
to avoid low frequency DC wander. The 75-Ω signal is also required to meet certain rise and fall timing to
facilitate highest eye opening for the receiving device.
SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, 3 Gbps,
and higher data rates over coaxial cables. One of the requirements is meeting the required return loss. This
requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band.
Output return loss is dependent on board design. The LMH0302 supports these requirements.
8.2 Typical Application
V
CC
0.1 mF
75W
75W
SD/HD
ENABLE
6.8 nH
1.0 mF
4.7 mF
ENABLE
SDI
49.9W
49.9W
SD/HD
75W
75W
SDO
SDO
LMH0302
4.7 mF
R
REF
SDI
1.0 mF
Differential
Input
V
CC
6.8 nH
0.1 mF
750W
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Application Circuit
8
Copyright © 2007–2016, Texas Instruments Incorporated
LMH0302
www.ti.com.cn
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
Typical Application (continued)
8.2.1 Design Requirements
For the LMH0302 design example, Table 1 lists the design parameters.
Table 1. LMH0302 Design Parameters
PARAMETER
Input termination
REQUIREMENT
Required; 49.9 Ω are recommended (see Figure 3).
Required; both SDO and SDO require AC-coupling capacitors. SDO AC-coupling capacitors
are expected to be 4.7 µF to comply with SMPTE wander requirement.
Output AC-coupling capacitors
To minimize power supply noise, place 0.1-µF capacitor as close to the device VCC pin as
possible.
DC power supply coupling capacitors
Distance from device to BNC
Keep this distance as short as possible.
High speed SDI and SDI trace impedance
Design differential trace impedance of SDI and SDI with 100 Ω.
High speed SDO and SDO trace impedance Single-ended trace impedance for SDO and SDO with 75 Ω.
8.2.2 Detailed Design Procedure
The following design procedure is recommended:
1. Select a suitable power supply voltage for the LMH0302. It can be powered from a single 3.3-V supply.
2. Check that the power supply meets the DC requirements in Electrical Characteristics – DC.
3. Select the proper pull-high or pull-low for SD/HD to set the slew rate.
4. Select proper pull-high or pull-low for ENABLE to enable or disable the output driver.
5. Choose a high-quality 75-Ω BNC that is capable to support 2.97-Gbps applications. Consult a BNC supplier
regarding insertion loss, impedance specifications, and recommended BNC footprint for meeting SMPTE
return loss requirements.
6. Choose small 0402 surface-mount ceramic capacitors for the AC-coupling and bypass capacitors.
7. Use proper footprint for BNC and AC-coupling capacitors. Anti-pads are commonly used in power and
ground planes under these landing pads to achieve optimum return loss.
8.2.3 Application Curves
920
900
880
860
840
820
800
780
760
660
680
700
720
740
760
780
1 ns/DIV
RREF Resistance (Ω)
C001
Figure 5. SDO Amplitude vs RREF Resistance
Figure 4. SDO PRBS10 at 270 Mbps
Copyright © 2007–2016, Texas Instruments Incorporated
9
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply must be designed to provide the recommended operating conditions (see Recommended
Operating Conditions).
2. The maximum current draw for the LMH0302 is provided in Electrical Characteristics – DC. This figure can
be used to calculate the maximum current the supply must provide.
3. The LMH0302 does not require any special power supply filtering, provided the recommended operating
conditions are met. Only standard supply coupling is required.
10 Layout
10.1 Layout Guidelines
TI recommends the following layout guidelines for the LMH0302:
1. The RREF 1% tolerance resistor must be placed as close as possible to the RREF pin. In addition, the copper
in the plane layers below the RREF network must be removed to minimize parasitic capacitance.
2. Choose a suitable board stackup that supports 75-Ω single-ended trace and 100-Ω differential trace routing
on the top layer of the board. This is typically done with a Layer 2 ground plane reference for the 100-Ω
differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.
3. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to SDO and SDO. The
trace width is typically 8-10 mil reference to a ground plane at Layer 3.
4. Use coupled differential traces with 100-Ω impedance for signal routing to SDI and SDI. They are usually
5-mil to 8-mil trace width reference to a ground plane at Layer 2.
5. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-μF AC-coupling
capacitor, return loss network, and IC landing pads to minimize parasitic capacitance. The size of the anti-
pad depends on the board stackup and can be determined by a 3-dimension electromagnetic simulation tool.
6. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic
impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.
7. Keep trace length short between the BNC and SDO. The trace routing for SDO and SDO must be
symmetrical, approximately equal lengths, and equal loading.
8. The exposed pad EP of the package must be connected to the ground plane through an array of vias. These
vias are solder-masked to avoid solder flow into the plated-through holes during the board manufacturing
process.
9. Connect each supply pin (VCC and VEE) to the power or ground planes with a short via. The via is usually
placed tangent to the landing pads of the supply pins with the shortest trace possible.
10. Power-supply bypass capacitors must be placed close to the supply pins.
10
Copyright © 2007–2016, Texas Instruments Incorporated
LMH0302
www.ti.com.cn
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
10.2 Layout Example
Figure 6 shows an example of proper layout requirements for the LMH0302.
BNC foot print
Anti-pad
GND stitch
> 5W
VCC
4.7 µF
Anti-pad:
Zo = 75 ꢀ
100 ꢀ coupled trace
W = 8
S = 10
0.1 µF
0.1 µF
Solder
Paste
mask
75 ꢀ
W = 8
4.7 µF
W = 10
> 5W
VCC
750 ꢀ
VCC
EP
GND
GND
Figure 6. LMH0302 High-Speed Traces Layout Example
版权 © 2007–2016, Texas Instruments Incorporated
11
LMH0302
ZHCSAK2H –APRIL 2007–REVISED JUNE 2016
www.ti.com.cn
11 器件和文档支持
11.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12
版权 © 2007–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH0302SQ/NOPB
LMH0302SQE/NOPB
LMH0302SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RUM
RUM
RUM
16
16
16
1000 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
L0302
L0302
L0302
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0302SQ/NOPB
LMH0302SQE/NOPB
LMH0302SQX/NOPB
WQFN
WQFN
WQFN
RUM
RUM
RUM
16
16
16
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0302SQ/NOPB
LMH0302SQE/NOPB
LMH0302SQX/NOPB
WQFN
WQFN
WQFN
RUM
RUM
RUM
16
16
16
1000
250
208.0
208.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
PACKAGE OUTLINE
RUM0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
DIM A
OPT 1
0.2
OPT 2
0.1
2X 1.95
SYMM
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.6 0.1
12X 0.65
1
12
0.35
0.25
16X
PIN 1 ID
(45 X 0.3)
13
16
0.1
C A B
0.5
0.3
0.05
16X
4214998/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUM0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1.05)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214998/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUM0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.675) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.15)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4214998/A 11/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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