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LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

LMH0324 3G/HD/SD SDI 双路输出自适应电缆均衡器

1 特性

3 说明

1

•

支持 ST 424(3G)、ST 292(HD) 和 ST 259(SD)

LMH0324 是一款低功耗、双路输出、延长长度、自适

应电缆均衡器。该器件旨在均衡通过 75Ω 同轴电缆传

输的 SDI 数据。该均衡器具有 125Mbps 至 2.97Gbps

的较宽数据速率范围。该均衡器包含有源传感电路，保

证了出色的性能并增强了对输入信号启动幅值变化的抗

扰性。

兼容 DVB-ASI 和 AES10 (MADI)

自适应电缆均衡器

电缆长度 (Belden 1694A)：

–

2.97Gbps 时为 200m

1.485Gbps 时为 280m

270Mbps 时为 600m

LMH0324 提供扩展电缆长度的同时还拥有低功耗特

性。该器件具备功率管理功能，可在无输入信号时进一

步降低功耗。

•

低功耗：78mW（典型值）

节能模式：15mW

片上输入终端（75Ω 单端）

集成输入回波损耗网络

LMH0324 具有两个差分串行数据输出，可灵活进行扇

出缓冲。输出驱动器提供可编程的去加重功能，用于补

偿 LMH0324 输出端的电路板走线损失。LMH0324 的

工作状态可通过控制引脚进行设置。该器件的附加设置

可通过 SPI 或 SMBus 接口进行编程设定。

具有去加重功能的双路 100Ω 输出驱动器

独立输出断电控制

支持信号分离器模式（–6dB 启动幅值）

电缆长度指示

数字 MUTE_REF阈值

LMH0324 与 LMH1219（带有集成时钟恢复器的

12Gbps 自适应电缆均衡器）引脚兼容。这一引脚兼容

性使得从 3Gbps 均衡器到具有集成时钟恢复器的

12Gbps 均衡器的升级变得更加容易。

通过 2.5V 或 1.8V 电源供电

可通过控制引脚、SPI 或者 SMBus 接口进行配置

4mm × 4mm 24 引脚 QFN 封装

工作温度范围：-40°C 至 +85°C

器件信息⁽¹⁾

器件型号

LMH0324

封装

QFN (24)

封装尺寸（标称值）

2 应用

4.00mm × 4.00mm

•

兼容 SMPTE 的串行数字接口 (SDI)

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

广播视频路由器、交换机和监视器

DVB-ASI 和分布式放大器

数字视频处理和编辑

简化框图

Low Power

Adaptive Cable Equalizer

VOD_DE

EQ

Bypass

2

100 Ω

Driver

OUT0±

OUT1±

SE 75 Ω

Term and

RL Network

2

Cable

EQ

VOD_DE

IN0±

100 Ω

Driver

Carrier

Detector

OUT_MUX

CD_N

Power

Serial

Interface

LDO

Control Logic

Management

Single 2.5 V

Control Carrier

SPI

or

VDD_LDO

or

Pins

Detect

1.8 V

SMBus

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS531

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 16

7.5 LMH0324 Register Map .......................................... 21

Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Application ................................................. 26

Power Supply Recommendations...................... 30

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

8

9

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 31

11 器件和文档支持 ..................................................... 32

11.1 接收文档更新通知 ................................................. 32

11.2 社区资源................................................................ 32

11.3 商标....................................................................... 32

11.4 静电放电警告......................................................... 32

11.5 术语表 ................................................................... 32

12 机械、封装和可订购信息....................................... 32

6.6 Recommended SMBus Interface AC Timing

Specifications............................................................. 9

6.7 Serial Parallel Interface (SPI) AC Timing

Specifications............................................................. 9

6.8 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7

4 修订历史记录

Changes from Revision A (May 2016) to Revision B

Page

•

已添加参考设计顶部导航图标链接；首次公开发布的产品说明书 ......................................................................................... 1

Changes from Original (April 2016) to Revision A

Page

•

Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F ............................................................. 8

Changed typical VOD_DE amplitude specifications for Levels F, R, and L .......................................................................... 8

Changed DEM value and DEM register settings in Table 4 to match correct VOD_DE pin logic levels ............................. 14

已添加 new row for VOD = 5, DEM = 5 setting in 表 9 ....................................................................................................... 28

2

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

5 Pin Configuration and Functions

RTW Package

24-Pin QFN

Top View

IN0+

IN0-

1

2

3

4

5

6

18 OUT0+

17 OUT0-

16 VSS

VSS

LMH0324

RSV1

15 OUT1+

14 OUT1-

13 RSV_L

RSV2

EP = VSS

MODE_SEL

Pin Functions

(1)

I/O

DESCRIPTION

NAME

NO.

High Speed Differential I/Os

IN0+

IN0-

1

2

I, Analog

I Analog

Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to

internal common mode voltage and return loss compensation network. Requires

external 4.7-µF AC coupling capacitors for SMPTE video applications.

RSV1

RSV2

OUT0+

4

5

Reserved pins.

Do not connect.

18

O, Analog

Differential complementary outputs with 100-Ω internal termination. Requires external

4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user

control.

OUT0-

17

15

14

OUT1+

Differential complementary outputs with 100-Ω internal termination. Requires external

4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user

control.

OUT1-

Control Pins

CD_N is the carrier detect. CD_N is pulled LOW when signal is detected and

adaptation is completed. CD_N is an open drain output. It requires an external

resistor to logic supply.

CD_N

12

O, LVCMOS, OD

CD_N is tolerant to 3.3 V when VDDIO is powered from 2.5 V supply.

IN_OUT_SEL selects the signal flow at input port IN0 to output ports. See Table 2 for

details. This pin setting can be overridden by register control.

IN_OUT_SEL

OUT_CTRL

8

I, 4-LEVEL

OUT_CTRL selects the equalized or un-equalized signal from IN0 to OUT0± and

OUT1±. See Table 3 for details. This pin setting can be overridden by register control.

19

VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0±

and OUT1±. See Table 4 for details. This pin setting can be overridden by register

control.

VOD_DE

11

6

I, 4-LEVEL

MODE_SEL

MODE_SEL enables SPI or SMBus serial control interface. See Table 5 for details.

(1) Note: I = Input, O=Output, IO=Input or Output, OD=Open Drain, LVCMOS=2-State Logic, 4-LEVEL=4-State Logic

3

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Pin Functions (continued)

(1)

I/O

DESCRIPTION

NAME

NO.

Serial Control Interface (SPI Mode), MODE_SEL = F (Float)

SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the

LMH0324 slave device. SS_N is a LVCMOS input referenced to VDDIO.

SS_N

MISO

MOSI

SCK

7

I, LVCMOS

O, LVCMOS

I, LVCMOS

MISO is the SPI serial data output from the LMH0324 slave device. MISO is a

LVCMOS output referenced to VDDIO.

20

10

21

MOSI is used as the SPI serial data input to the LMH0324 slave device. MOSI is

LVCMOS input referenced to VDDIO.

SCK is the SPI serial input clock to the LMH0324 slave device. SCK is LVCMOS

referenced to VDDIO.

Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS)

ADDR0

ADDR1

7

Strap, 4-LEVEL

ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus

addresses. ADDR[1:0] are 4-level straps and are read into the device at power up.

20

SMBus bi-directional open drain data line to or from the LMH0324 slave device. SDA

is an open drain IO and requires an external 2 kΩ to 5 kΩ pull-up resistor to the

SMBus termination voltage. SDA is 3.3 V tolerant when VDDIO is powered from 2.5

V.

SDA

SCL

10

21

IO, LVCMOS, OD

I, LVCMOS, OD

SMBus input clock to the LMH0324 slave device. It is driven by a LVCMOS open

drain driver from the SMBus master. SCL requires an external 2 kΩ to 5 kΩ pull-up

resistor to the SMBus termination voltage. SCL is 3.3 V tolerant when VDDIO is

powered from 2.5 V.

Power

VSS

3, 9, 16

24

I, Ground

I, Power

Ground reference.

VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ±

5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO

regulator and requires a bypass capacitor to VSS.

VIN

When VIN is powered from 1.8 V, for lower power operation, both VIN and VDD_LDO

should be connected to 1.8 V supply.

VDDIO powers the LVCMOS IO and 4-level input logic. VDDIO should be connected

to 2.5 V ± 5% or 1.8 V ± 5%. VDDIO must always be greater than or equal to VIN.

For SMBus access, VDDIO must be 2.5 V ± 5%.

VDDIO

22

23

I, Power

VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to

2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass capacitors

to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an

input when VIN is powered from 1.8 V for lower power operation. When VIN is

connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to the 1.8

V supply.

VDD_LDO

IO, Power

For pin compatibility with the LMH1219 (11.88 Gbps Ultra-HD adaptive cable

equalizer with integrated reclocker), connect RSV_L to a 2.5 V supply with a 0.1-µF

bypass capacitor. For low power operation, tie RSV_L to VSS. See Power Supply

Recommendations for details.

RSV_L

EP

13

I

EP is the exposed pad at the bottom of the QFN package. The exposed pad must be

connected to the ground plane through a via array. See 图 26 for details.

I, Ground

4

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.75

2.0

UNIT

V

Supply Voltage for 2.5-V Mode (VIN, VDDIO)

Supply Voltage for 1.8-V Mode (VIN, VDD_LDO, VDDIO)

V

4-Level Input/Output Voltage for 2.5 V Supply (IN_OUT_SEL, OUT_CTRL, VOD_DE,

MODE_SEL, ADDR0, ADDR1)

–0.5

-0.5

2.75

2.0

V

4-Level Input/Output Voltage for 1.8 V Supply (IN_OUT_SEL, OUT_CTRL, VOD_DE,

MODE_SEL, ADDR0, ADDR1)

SMBus Input/Output Voltage (SDA, SCL)⁽²⁾

SPI Input/Output Voltage for 2.5 V Supply (SS_N, MISO, MOSI, and SCK)

SPI Input/Output Voltage for 1.8 V Supply (SS_N, MISO, MOSI, and SCK)

Input Voltage (IN0±)

–0.5

-0.5

–0.5

–30

4.0

2.75

2.0

V

2.75

30

V

Input Current (IN0±)

mA

°C

Junction Temperature

125

150

Storage temperature

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) SDA and SCL is 3.3 V tolerant when VDDIO is 2.5 V.

6.2 ESD Ratings

VALUE

±4500

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500 V HBM is possible with the necessary precautions. Pins listed as ±4500 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250 V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

1.71

NOM

2.5

MAX

2.625

1.89

3.6

UNIT

2.5 V Supplies

1.8 V Supplies

VDD_SMBUS

VIN, VDDIO to VSS

V

VIN, VDDIO , VDD_LDO to VSS

SMBus: SDA, SCL Open Drain Termination Voltage, VDDIO = 2.5 V

Source Launch Amplitude before Coax

Splitter Mode

1.8

2.375

0.72

0.8

0.4

0.88

0.44

100

V_LAUNCH

Vp-p

0.36

T_JUNCTION

T_AMBIENT

Operating Junction Temperature

Ambient Temperature

°C

–40

25

85

50 Hz to 1 MHz, Sinusoidal

<20

(1)

N_PS

Supply Noise

mVp-p

1.1 MHz to 6 GHz,

Sinusoidal

<10

(1) The sum of the DC supply voltage and AC supply noise should not exceed the recommended supply voltage range.

5

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

6.4 Thermal Information

LMH0324

RTW (QFN)

24 PINS

33.2

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

28.8

11.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

11.3

R_θJC(bot)

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient

temperature (<85°C) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

78

MAX

UNIT

mW

POWER

Measured with PRBS-10, VOD =

Default, only OUT0 enabled, 2.97

Gbps,

VIN=VDD_LDO=VDDIO=1.8 V

PD_1P8V

Power Consumption⁽¹⁾

Measured with PRBS-10, VOD =

Default, OUT0 and OUT1 enabled,

2.97 Gbps,

100

mW

VIN=VDD_LDO=VDDIO=1.8 V

Power Save Mode: No input

signal,

PD_Z1P8V

15

mW

VIN=VDD_LDO=VDDIO=1.8 V

Measured with PRBS-10, 2.97

Gbps, VOD = Default, only OUT0

enabled, VIN=VDDIO=2.5 V

128

PD_2P5V

PD_Z2P5V

IDD

Power Consumption⁽¹⁾

Current Consumption⁽¹⁾

Measured with PRBS-10, 2.97

Gbps, VOD = Default, OUT0 and

OUT1 enabled, VIN=VDDIO=2.5 V

147

28

mW

Power Save Mode: No input

signal, VIN=VDDIO=2.5 V

Measured at 1.8 V supply with

PRBS-10, 2.97 Gbps, VOD =

Default, only OUT0 enabled

43

55

71

mA

Measured at 2.5 V supply with

PRBS-10, 2.97 Gbps, VOD =

Default, only OUT0 enabled

51

Forced Power Save Mode:

MODE_SEL = LEVEL-H,

Measured at 1.8 V supply,

VIN=VDD_LDO=VDDIO=1.8 V

IDD_{Z_1P8V}

Current Consumption⁽¹⁾

4

10

mA

V

LDO 1.8 V Output

Voltage

V_LDO

VIN = VDDIO = 2.5 V

1.71

1.8

1.89

(1) Measured with RSV_L tied to VSS.

6

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVCMOS DC SPECIFICATIONS

2-Level Input (SS_N, SCK, MOSI),

VDDIO = 2.5 V or 1.8 V

0.7 x VDDIO

VDDIO + 0.3

3.6

V_IH

High Level Input Voltage

V

2-Level Input (SCL, SDA), VDDIO

= 2.5 V

0.7 x VDDIO

2-Level Input (SS_N, SCK, MOSI)

VDDIO = 2.5 V or 1.8 V

-0.3

0.3 x VDDIO

VDDIO

0.2 x VDDIO

0.4

V_IL

Low Level Input Voltage

V

2-Level Input (SCL, SDA), VDDIO

= 2.5 V

0

High Level Output

Voltage

I_OH= -2 mA, (MISO), VDDIO = 2.5

V or 1.8 V

V_OH

0.8 x VDDIO

I_OL= 2 mA, (MISO), VDDIO = 2.5

V or 1.8 V

0

Low Level Output

Voltage

V_OL

I_OL= 3 mA, (CD_N, SCL, SDA),

VDDIO = 2.5 V

SPI Mode: LVCMOS (SS_N, SCK,

MOSI), Vinput = VDDIO

15

Input High Leakage

Current

I_IH

µA

SMBus Mode: LVCMOS (CD_N,

SCL, SDA), Vinput = VDDIO

10

SPI Mode: LVCMOS (SS_N),

Vinput = VSS

-40

-15

-10

Input Low Leakage

Current

SPI Mode: LVCMOS (SCK,

MOSI), Vinput = VSS

I_IL

SMBus Mode: LVCMOS (CD_N,

SCL, SDA), Vinput = VSS

4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)

V_{4_LVL_H}

V_{4_LVL_F}

LEVEL-H Input Voltage

External pull-up 1 kΩ to VDDIO

VDDIO

V

LEVEL-F Default Voltage Float, VDDIO = 2.5 V or 1.8 V

2/3 x VDDIO

External pull-down 20 kΩ to VSS,

LEVEL-R Input Voltage

V_{4_LVL_R}

V_{4_LVL_L}

1/3 x VDDIO

0

V

VDDIO = 2.5 V or 1.8 V

LEVEL-L Input Voltage

External pull-down 1 kΩ to VSS

4-Levels (IN_OUT_SEL,

OUT_CTRL, VOD_DE,

MODE_SEL), Vinput = VDDIO

20

45

80

Input High Leakage

Current

I_{4_LVL_IH}

µA

SMBus Mode: 4-Levels (ADDR0,

ADDR1), Vinput = VDDIO

4-Levels (IN_OUT_SEL,

OUT_CTRL, VOD_DE,

MODE_SEL), Vinput = VSS

-160

–93

-40

Input Low Leakage

Current

I_{4_LVL_IL}

SMBus Mode: 4-Levels (ADDR0,

ADDR1), Vinput = VSS

RECEIVER SPECIFICATIONS (IN0+)

R_{IN0_TERM}

DC Input Termination

IN0+ and IN0- to VSS

63

75

–20

–18

87

Ω

S11, 5 MHz to 1.485 GHz

S11, 1.485 GHz to 3 GHz

Input Return Loss

RL_IN0

dB

Reference to 75 Ω⁽²⁾

IN0 DC Common Mode

Voltage

Input common mode voltage at

IN0+ to VSS

V_{IN0_CM}

1.4

100

50

V

SD signal at IN0+, Input launch

amplitude = 0.8 Vp-p

mVp-p

V_WANDER

Input DC Wander

HD, 3G signal at IN0+, Input

launch amplitude = 0.8 Vp-p

(2) This parameter was measured with an LMH0324-18EVM.

7

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT DRIVERS (OUT0± OR OUT1±)

8T pattern, see Figure 6, VOD_DE

= LEVEL-H

SD, HD, and 3G

410

560

635

810

410

500

480

8T pattern, see Figure 6,VOD_DE

= LEVEL-F

SD, HD, and 3G

485

620

Output Differential

VOD

mVp-p

Voltage⁽³⁾

8T pattern, see Figure 6, VOD_DE

= LEVEL-R

SD, HD, and 3G

8T pattern, see Figure 6, VOD_DE

= LEVEL-L

SD, HD, and 3G

8T pattern, see Figure 7, VOD_DE

= LEVEL-H

SD, HD, and 3G

8T pattern, see Figure 7, VOD_DE

= LEVEL-F Default

SD, HD, and 3G

De-emphasized Output

VOD_DE

Differential Voltage⁽³⁾

8T pattern, see Figure 7, VOD_DE

= LEVEL-R

SD, HD, and 3G

8T pattern, see Figure 7, VOD_DE

= LEVEL-L

SD, HD, and 3G

480

100

45

DC Output Differential

R_{OUT_TERM}

Measured across OUTn+ and

OUTn-

80

120

Ω

Termination

20% - 80% using 8T Pattern 270

Mbps, 1.485 Gbps, 2.97 Gbps,

measured after 1 inch trace

Output Rise or Fall Time

t_R/t_F

ps

(4)

125

Mbps

Gbps

D_R

Input Data Rate

2.97

0.4

2.97 Gbps B1694A: 0 – 150 m

2.97 Gbps B1694A: 150 m

0.25

0.55

0.2

2.97 Gbps B1694A: 150 - 200 m

1.485 Gbps B1694A: 0 – 200 m

1.485 Gbps B1694A: 200 m

1.485 Gbps B1694A: 200 – 300 m

270 Mbps B1694A: 0 – 400 m

270 Mbps B1694A: 400 m

Jitter for Various Cable

Length⁽⁴⁾

JIT_RATE

0.2

0.35

0.3

UI

0.55

0.2

0.15

0.35

270 Mbps B1694A: 400 – 600 m

Equalizer Adapt Time -

Signal detect to

Adaptation Completed

PRBS-10, Belden 1694A coax

cable, nominal launch amplitude of

0.8 Vpp, 2.97 Gbps

T_ADAPT

5

ms

(3) ATE production tested with DC method.

(4) This parameter was measured with an LMH0324-18EVM.

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6.6 Recommended SMBus Interface AC Timing Specifications

over recommended operating supply and temperature ranges (unless otherwise noted)

(1)(2) (3)

MIN

NOM

MAX

UNIT

F_SCL

T_BUF

SMBus SCL Frequency

10

400

kHz

Bus Free Time between Stop and

Start Condition

1.3

0.6

µs

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

T_HD:STA

Repeated Start Condition Setup

Time

T_SU:STA

T_SU:STO

T_HD:DAT

T_SU:DAT

T_LOW

T_HIGH

T_R

Stop Condition Setup Time

Data Hold Time

0.6

0

µs

ns

µs

ns

Data Setup Time

100

1.3

0.6

Clock Low Period

Clock High Period

Clock/Data Rise Time

Clock/Data Fall Time

300

T_F

(1) These parameters support SMBus 2.0 specifications.

(2) These parameters are not production tested.

(3) See Figure 1 for timing diagrams.

6.7 Serial Parallel Interface (SPI) AC Timing Specifications

over recommended operating supply and temperature ranges (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

20

UNIT

MHz

ns

F_SCK

T_SCK

T_PH

SPI SCK Frequency

SCK Period

10

50

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup Time

0.40 x T_SCK

ns

T_PL

0.40 x T_SCK

ns

T_SU

4

ns

T_H

MOSI Hold Time

ns

T_SSSU

T_SSH

T_SSOF

T_ODZ

T_OZD

T_OD

SS_N Setup Time

14

4

ns

SS_N Hold Time

ns

SS_N Off Time

1

µs

MISO Driven-to-Tristate Time

MISO Tristate-to-Driven Time

MISO Output Delay Time

20

10

15

ns

(1) See Figure 2 for timing diagrams.

tt_LOW

t

t_R

t_HIGH

SCL

tt_HD:STA

t

t_HD:DAT

t_SU:STA

t_F

t_SU:STO

tt_BUF

t

t_SU:DAT

SDA

SP

ST

SP

Figure 1. SMBus Timing Parameters

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t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 2. SPI Timing Parameters

6.8 Typical Characteristics

Typical device characteristics at T_A= 25°C and VIN = VDDIO = 2.5 V, unless otherwise noted.

112 ps/DIV

56 ps/DIV

Figure 3. 2.97 Gbps, Input: 150 m Belden 1694A

PRBS10

Figure 4. 1.485 Gbps, Input: 200 m Belden 1694A

PRBS10

1.0

DE = 0

0.9

0.8

0.7

0.6

0.5

0.4

0

1

2

3

4

5

6

7

617 ps/DIV

VOD Register Settings

C001

Figure 5. 270 Mbps, Input: 400 m Belden 1694A

PRBS10

Figure 6. VOD vs. VOD and DEM Register Settings

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Typical Characteristics (continued)

Typical device characteristics at T_A= 25°C and VIN = VDDIO = 2.5 V, unless otherwise noted.

0

DE = 1

œ2

œ4

DE = 2

DE = 3

DE = 4

DE = 5

DE = 6

DE = 7

œ6

œ8

œ10

œ12

0

1

2

3

4

5

6

7

VOD Register Settings

C002

Figure 7. De-emphasis vs. VOD and DEM Register Settings

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7 Detailed Description

7.1 Overview

The LMH0324 is an adaptive cable equalizer designed to equalize serial digital video data transmitted over long

distance of coaxial cable, such as Belden 1694A. It is designed with high gain equalization boost implemented

with low power and low noise circuitry, supporting 3G/HD/SD SDI video transport over high loss coaxial cable.

It is designed to support common video data rates from 125 Mbps to 2.97 Gbps, compatible to SMPTE video

standards ST-424, ST-344, ST-292, ST-259, and DVB-ASI.

The LMH0324 automatically selects the correct level of equalization boost based on the signal quality of the input

signal. It offers two output drivers that support fan-out buffering. Programmable de-emphasis is available to

reduce the inter-symbol interference jitter caused by the printed circuit board traces connecting the drivers to

their downstream receivers.

7.2 Functional Block Diagram

Low Power

Adaptive Cable Equalizer

VOD_DE

2

100 Ω

DRIVER

EQ Bypass

OUT0±

OUT1±

2

SE 75 Ω

Term and

RL network

VOD_DE

Adaptive

Cable EQ

IN0±

2

100 Ω

DRIVER

Carrier

OUT_MUX

Detector

Control

LOS

Power

Management

Serial

Interface

LDO

Control Logic

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7.3 Feature Description

The LMH0324 consists of several key blocks:

•

4-Level Input Configuration Pins

Carrier Detect

Adaptive Cable Equalizer

Launch Amplitude

Input-Output Mux Selection

Output Function Control

Output Driver Amplitude and De-Emphasis Control

7.3.1 4-Level Input Configuration Pins

The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is

an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the control pin that sets the default voltage at 2/3 x

VDDIO. These resistors, together with the external resistor, combine to achieve the desired voltage level. By

using the 1-kΩ pull-down, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage levels for each of the

four input states are achieved as shown in Table 1.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTING

RESULTING PIN VOLTAGE

H

F

R

L

Tie 1 kΩ to VDDIO

Float (leave pin open)

Tie 20 kΩ to VSS

Tie 1 kΩ to VSS

VDDIO

2/3 × VDDIO

1/3 × VDDIO

0

Typical 4-Level Input Thresholds:

•

Internal Threshold between L and R = 0.2 × VDDIO

Internal Threshold between R and F = 0.5 × VDDIO

Internal Threshold between F and H = 0.8 × VDDIO

7.3.2 Carrier Detect

An internal Carrier Detector circuit is used to monitor the presence or absence of the input signal. When the input

signal amplitude exceeds the carrier detector’s threshold, adaptation is activated, and CD_N is pulled low at the

end of adaptation. When the input signal amplitude is below the carrier detector’s threshold, input equalization

circuitry is powered down and the CD_N is pulled high to indicate absence of input signal. The LMH0324 high

gain adaptive cable equalizer supports long cable reach. As a result, the carrier detector threshold is sensitive,

and system designers need to pay close attention to the PCB layout to avoid excessive crosstalk from interfering

with the carrier detection.

In the absence of input signal, the LMH0324 automatically goes into Power Save Mode to conserve power

consumption. When valid signal is detected, the LMH0324 automatically exits the Power Save Mode and returns

to the normal operating mode. An LED can be connected to CD_N through a current limiting resistor to provide

visual indication of the carrier detection.

7.3.3 Adaptive Cable Equalizer

IN0+ is the input to the adaptive cable equalizer. It has an on-chip 75-Ω termination to the input common mode

voltage and includes a series return loss compensation network for meeting stringent SMPTE return loss

requirements. It is designed for AC coupling, requiring a 4.7-µF AC coupling capacitor for minimizing base-line

wander due to the rare-occurring pathological bit pattern. The cable equalizer is designed with high gain and low

noise circuitry to compensate for the insertion loss of a coaxial cable, such as Belden 1694A, which is widely

used in broadcast video infrastructures.

Internal control loops are used to monitor the input signal quality and automatically select the optimum

equalization boost and DC offset compensation. The LMH0324 is designed to handle the stringent pathological

pattern defined in the SMPTE RP 198 and SMPTE RP 178 standards.

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7.3.4 Launch Amplitude

The LMH0324 is designed to equalize data transmitted through a coaxial cable driven by a SMPTE compatible

cable driver with launch amplitude of 800 mVp-p ± 10%. In applications where a 1:2 passive splitter is used, the

signal amplitude is reduced by half due to the 6 dB insertion loss of the splitter. The LMH0324 is designed to

support -6 dB splitter mode, enabled by SPI or SMBus serial interface.

7.3.5 Input-Output Mux Selection

By default, the LMH0324 input-to-output signal flow and data rate selection are configured by the IN_OUT_SEL

pin logic settings shown in Table 2. These settings can be overridden via register control by applying the

appropriate override bit values.

Table 2. IN_OUT_SEL Pin Settings

LEVEL

DEFINITION

H

F

R

L

IN0 to OUT0 and OUT1

IN0 to OUT0 (with OUT1 disabled)

Reserved

7.3.6 Output Function Control

By default, the LMH0324 output function control for OUT0 and OUT1 is configured by the OUT_CTRL pin logic

settings shown in Table 3. These settings can be overridden via register control by applying the appropriate

override bit values.

Table 3. OUT_CTRL Pin Settings

LEVEL

DEFINITION

Equalizer Bypass

Raw data at IN0+ is routed to the output drivers

H

Normal Data

Equalized data is routed to the output drivers

F

R

L

Reserved

7.3.7 Output Driver Amplitude and De-Emphasis Control

The VOD_DE control pin selects the output amplitude and de-emphasis settings for both OUT0± and OUT1±. It

offers users the capability to select higher output amplitude and de-emphasis level for longer board trace that

connects the drivers to their downstream receivers. Driver de-emphasis provides transmitter equalization to

reduce the ISI caused by the board trace.

By default, the output driver VOD and de-emphasis settings are configured by the VOD_DE pin logic settings

shown in Table 4. These settings can be overridden via register control. Through register programming, the

output amplitude and de-emphasis level can be individually set for OUT0± and OUT1±. SPI and SMBus register

programming provide a wider range of output amplitude and de-emphasis levels.

Table 4. Recommended VOD_DE Pin and Register Settings for Different FR4 Trace Lengths⁽¹⁾

VOD REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

DEM REG SETTING

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

FR4 TRACE

LENGTH

(inches)

VOD_DE

LEVEL

VOD

VOD_DE

DEM (dB)

(mVpp)⁽²⁾

H

F

R

L

0

2

3

5

0

2

3

5

410

560

635

810

410

500

480

0

0 – 1

2 – 4

5 – 6

7 – 8

-0.9

-2.4

-6.1

(1) The output drivers are capable of providing higher VOD and DEM levels (max settings are 7). For more VOD and de-emphasis levels,

refer to 表 9.

(2) See Figure 8.

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VOD

VODDE

Figure 8. VOD and VOD_DELevels

7.3.8 Additional Programmability

The LMH0324 supports extended programmability through the use of an SPI or SMBus serial control interface.

Such added programmability includes:

•

Cable Length Indicator (CLI).

Digital MUTE_REF

7.3.8.1 Cable Length Indicator (CLI)

The Cable Length Indicator (CLI) indicates the length of the coaxial cable attached to IN0+. CLI is accessible

through CableEQ/Driver Page Reg 0x25[5:0]. The 6-bit setting ranges in decimal value from 0 to 55 (000000'b to

110111'b binary), corresponding to approximately 0 to 600 m of Belden 1694A cable.

7.3.8.2 Digital MUTE_REF

Digital MUTE_REFCableEQ/Driver Page Reg 0x03[5:0] sets the threshold for the maximum cable length to be

equalized before muting the outputs. The MUTE_REFregister value is directly proportional to the cable length

being equalized. MUTE_REFis data rate dependent. Follow the steps below to set MUTE_REFregister setting for

any desired SDI rate:

1. Connect the desired input cable length at which the driver output needs to be muted.

2. Send video pattern at IN0+ at the SD rate (270 Mbps). At SD, the Cable Length Indicator (CLI) has the

largest dynamic range.

3. Read back Cable EQ/Driver Page Reg 0x25[5:0] to record the CLI value.

4. Copy the CLI value, and write this value to Digital MUTE_REFCable EQ/Driver Page Reg 0x03[5:0].

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7.4 Device Functional Modes

The LMH0324 operates in one of two modes: System Management Bus (SMBus) or Serial Peripheral Interface

(SPI) mode. In order to determine the mode of operation, the proper setting must be applied to the MODE_SEL

pin at power-up, as detailed in Table 5.

Table 5. MODE_SEL Pin Settings

LEVEL

DEFINITION

Forced Power Save Mode, only SPI is enabled (all other circuitry powered down)

Select SPI Interface for register access

H

F

R

L

Reserved for factory testing – do not use

Select SMBus Interface for register access

NOTE

Changing logic states between LEVEL-L and LEVEL-H after power up is not allowed.

7.4.1 System Management Bus (SMBus) Mode

If MODE_SEL = L, the LMH0324 is in SMBus mode. In SMBus mode, Pins 10 and 21 are configured as SDA

and SCL. Pins 7 and 20 act as 4-level address straps for ADDR0 and ADDR1 at power up to determine the 7-bit

slave address of the LMH0324, as shown in Table 6.

Table 6. SMBus Device Slave Addresses⁽¹⁾

ADDR0

ADDR1

7-BIT SLAVE

8-BIT WRITE

(LEVEL)

ADDRESS [HEX]

COMMAND [HEX]

L

R

F

H

L

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

3A

3C

3E

40

42

44

46

48

4A

4C

4E

50

52

54

56

58

L

R

F

H

R

F

H

L

R

F

H

L

R

F

H

(1) The 8-bit write command consists of the 7-bit slave address (Bits 7:1) with 0 appended to the LSB to

indicate an SMBus write. For example, if the 7-bit slave address is 0x1D (001 1101'b), the 8-bit write

command is 0x3A (0011 1010'b).

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7.4.1.1 SMBus Read and Write Transactions

SMBus is a two-wire serial interface through which various system component chips can communicate with the

master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of

SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a

bidirectional data signal between the master and slave devices. The LMH0324 SMBus SCL and SDA signals are

open drain and require external pull-up resistors.

Start and Stop:

The master generates start and stop patterns at the beginning and end of each transaction.

•

Start: High to low transition (falling edge) of SDA while SCL is high.

Stop: Low to high transition (rising edge) of SDA while SCL is high.

SDA

SCL

S

P

Start

Stop

Condition

Figure 9. Start and Stop Conditions

The master generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle.

The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device

pulls SDA low, while a NACK is recorded if the line remains high.

ACK Signal

from Receiver

SDA

MSB

SCL

1

2

3 - 6

7

8

9

1

2

3 - 8

9

S

P

ACK

Start

Stop

Condition

Byte Complete

Interrupt Within

Receiver

Clock Line Held Low

by Receiver While

Interrupt Serviced

Figure 10. Acknowledge (ACK)

7.4.1.1.1 SMBus Write Operation Format

Writing data to a slave device consists of three parts, as illustrated in Figure 11:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the 8-bit data is written, followed by a stop condition.

Device

Address

Word Address

Data

SDA

Line

Figure 11. SMBus Write Operation

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7.4.1.1.2 SMBus Read Operation Format

Reading data from a slave device consists of four parts, as illustrated in Figure 12:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the master initiates a re-start condition, followed by the slave address

with the R/W bit set to 1'b.

4. After an ACK from the slave device, the 8-bit data is read back. The last ACK is high if there are no more

bytes to read, and the last read is followed by a stop condition.

Device

Address

Word Address (n)

Address

Data (n)

SDA

Line

Set word address in the device

that will be read following restart

and repeat of device address

Figure 12. SMBus Read Operation

7.4.2 Serial Peripheral Interface (SPI) Mode

If MODE_SEL = F or H, the LMH0324 is in SPI mode. In SPI mode, the following pins are used for SPI bus

communication:

•

MOSI (pin 10): Master Output Slave Input

MISO (pin 20): Master Input Slave Output

SS_N (pin 7): Slave Select (active low)

SCK (pin 21): Serial clock (input to the LMH0324 slave device)

7.4.2.1 SPI Read and Write Transactions

Each SPI transaction to a single device is 17 bits long and is framed by SS_N when asserted low. The MOSI

input is ignored, and the MISO output is floated whenever SS_N is de-asserted (high).

The bits are shifted in left-to-right. The first bit is R/W, which is 1'b for "read" and 0'b for "write." Bits A7-A0 are

the 8-bit register address, and bits D7-D0 are the 8-bit read or write data. The previous SPI command, address,

and data are shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI

transactions, the MISO output signal is enabled asynchronously when SS_N asserts low. The contents of a

single MOSI or MISO transaction frame are shown in Table 7.

Table 7. 17-Bit Single SPI Transaction Frame

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

7.4.2.1.1 SPI Write Transaction Format

For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.

The signal timing for a SPI Write transaction is shown in Figure 13. The "prime" values on MISO (for example,

A7') reflect the contents of the shift register from the previous SPI transaction and are don’t-care for the current

transaction.

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t_SSOF

t_SSH

SS_N

t_PL

t_SSSU

t_PH

SCK

t_H

t_SU

HiZ

MOSI

0

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

t_ODZ

HiZ

MISO

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 13. Signal Timing for a SPI Write Transaction

7.4.2.1.2 SPI Read Transaction Format

A SPI read transaction is 34 bits per device and consists of two 17-bit frames. The first 17-bit read transaction

frame shifts in the address to be read, followed by a dummy transaction second frame to shift out 17-bit read

data. The R/W bit is 1'b for the read transaction, as shown in Figure 14.

The first 17 bits from the read transaction specifies 1-bit of R/W and 8-bits of address A7-A0 in the first 8 bits.

The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on

address 0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data

D7-D0 in the last 8 bits of the MISO output. As with the SPI Write, the “prime” values on MISO during the first 16

clocks are don’t-care for this portion of the transaction. The values shifted out on MISO during the last 17 clocks

reflect the read address and 8-bit read data for the current transaction.

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 14. Signal Timing for a SPI Read Transaction

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7.4.2.2 SPI Daisy Chain

The LMH0324 supports SPI daisy-chaining among multiple devices, as shown in Figure 15.

MISO

Device 1

Device 2

Device 3

Device N

Host

LMH0324

. . .

MOSI

MISO

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

SS

Figure 15. Daisy-Chain Configuration

Each LMH0324 device is directly connected to the SCK and SS_N pins of the host. The first LMH0324 device in

the chain is connected to the host’s MOSI pin, and the last device in the chain is connected to the host’s MISO

pin. The MOSI pin of each intermediate LMH0324 device in the chain is connected to the MISO pin of the

previous LMH0324 device, thereby creating a serial shift register. In a daisy-chain configuration of N x LMH0324

devices, the host conceptually sees a shift register of length 17 x N for a basic SPI transaction, during which

SS_N is asserted low for 17 x N clock cycles.

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7.5 LMH0324 Register Map

The LMH0324 register set definition is divided into two register pages. These register pages are used to control

different aspects of the LMH0324 functionality. A brief summary of the pages is shown below:

1. Share Register Page: This page corresponds to global parameters, such as LMH0324 device ID. This is the

default page at start-up.

2. CableEQ/Drivers Register Page: This page corresponds to IN0 Cable EQ and both OUT0 and OUT1 driver

output settings. Access this page by setting Reg 0xFF[2:0] = 101’b.

Please note the following about the LMH0324 default register values in the register map:

•

Default register values were read after power-up with no active inputs applied to IN0.

Default register values for Reserved "Read-Only" bits may vary dynamically from part to part.

7.5.1 Share Register Page

Address Register Name

Bit

7:0

7:5

Field

Default Type

Description

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Reserved

0x00

0x40

0x02

0x00

0x01

0x00

0x04

0x11

0x00

R

Reserved

RW Reserved

R

Reserved

1 = Internal state machine register initialization done.

0 = Internal state machine register initialization not done.

Reset

Share/Channel

Regs

4

reset_done

R

0xE2

0x10

3:1

0

Reserved

reset_init

Version

RW Reserved

RW 1 = Initialize internal state machine register settings.

0xF0

0xF1

Device Revision

Device ID

7:0

7:6

5:4

3

0x02

0x81

R

Device Revision

Device_ID

Reserved

For LMH0324, Device ID = 0x81

RW Reserved

Register

Communication

Control

0 = The shared registers are enabled.

RW 1 = Enables communication access to the Register Page

specified in Reg 0xFF[1:0].

0xFF

0x00

2

page_select_enable

page_select

Enable communication access to a specific Register Page

RW 01 = CableEQ/Drivers Register Page

Other values are invalid

1:0

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7.5.2 CableEQ/Drivers Register Page

Address Register Name

Bit

7

Field

Default Type

Description

CD_N pin status

adapt_cd

Reserved

RW 0 = CD_N indicates when Coarse Adaptation is done

1 = CD_N indicates carrier detect

6

RW Reserved

IN0 Power Save Override Control for Cable EQ

0 = Disable Power Save mode override. Automatic power

RW save mode when no input signal detected.

1 = Enable Power Save mode override. Power Save mode

control set by value in Reg 0x00[4:3].

5

reg_power_save_ov

IN0 Auto Power Save mode control for Cable EQ if Reg

0x00[5] = 1

00 = Enable Power Save mode when no input signal is

RW detected

Reset

CableEQ/Drivers

Registers

0x00

0x08

4:3

reg_power_save

01 = Disable auto Power Save mode

10 = Reserved

11 = Force Power Save mode

Reset registers (self-clearing)

0 = Normal operation

rst_cableEQ/Drivers_

regs

1 = Reset CableEQ/Drivers Registers. Register re-

initialization procedure required after resetting the

2

RW

CableEQ/Drivers Registers. Refer to the LMH0324

Programming Guide for details.

1:0

7:1

Reserved

RW Reserved

R

Reserved

EQ Observation

Status

0x01

0x02

0x03

0x80

0x07

0x3F

0 = Adaptation not completed

1 = Adaptation completed

0

7

adaptation_status

Reserved

Carrier Detect Status of IN0

0 = No signal present at IN0

1 = Signal present at IN0

6

5:3

2

IN0 Carrier Detect

freq_rate_det

R

Readback of rate detected

001 = 125M-270M

010 = 1.5G-3G

Observation Bit

0 = Power Save Mode is Inactive

1 = Power Save Mode is Active

power_save_status

Rate and Driver

Observation

Status

Observation Bit

0 = OUT1 Driver is Active

1

0

mute_tx1

mute_tx0

R

1 = OUT1 Driver is in Mute

Note: When muted, driver output remains at common mode

voltage.

Observation Bit

0 = OUT0 Driver is Active

1 = OUT0 Driver is in Mute

Note: When muted, driver output remains at common mode

voltage.

7:6

5:0

Reserved

MUTERef

RW Reserved

MUTERef Control

Digital MUTEref: Sets the threshold at which output will be

muted. See Digital MUTE_REF

RW

.

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

Reserved

7:0

Reserved

0x00

0xA0

0x24

0x27

0x01

0x05

0x37

RW Reserved

22

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

Address Register Name

Bit

7:0

7:6

Field

Default Type

RW Reserved

Description

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

Reserved

0x01

0x25

0x37

0x02

0x0A

0x02

0x08

0x04

0x3C

0x00

0x08

0x01

0x08

0x01

0xA7

0x00

0xC0

0x00

RW Reserved

R

Reserved

Cable Length

Indicator

Readback of the Cable Length Indicator after adaptation is

completed.

See Cable Length Indicator (CLI).

0x25

0x26

0x00

0x05

5:0

CLI

Reserved

7:0

7:4

Reserved

RW Reserved

Override eq_bypass value to analog core

0 = Disable EQ Bypass override

1 = Enable EQ Bypass override. Value of EQ Bypass Control

determined by Reg 0x27[2].

3

eq_bypass_ov

RW

EQ Bypass

Override

0x27

0x00

Override value of eq_bypass

2

eq_bypass_val

RW 0 = Do not Bypass Cable EQ. Use Adaptive EQ

1 = Bypass Cable EQ

1:0

7:0

Reserved

RW Reserved

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

Reserved

0x00

0x20

0x40

0x89

0x0B

0x20

0x00

R

Reserved

RW Reserved

R

Reserved

RW Reserved

23

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Address Register Name

Bit

Field

Default Type

Description

OUT0 Mute Override Control

0 = Disable OUT0 Mute Override Control

1 = Enable OUT0 Mute Override Control by value in Reg

0x30[6].

7

tx0_mute_ov

RW

0 = Normal Operation

1 = Mute OUT0 if Reg 0x30[7] = 1

6

5

tx0_mute_val

tx0_vod_ov

RW

OUT0 Output

0x30

0x0A

RW

OUT0 VOD Override Control

Control

0 = VOD settings for OUT0 determined by VOD_DE pin

1 = Override VOD pin settings for OUT0. VOD settings for

OUT0 are controlled by Reg 0x30[2:0]

4:3

2:0

7

Reserved

tx0_vod

RW Reserved

VOD settings with DE = 0 for OUT0 if Reg 0x30[5] = 1. See

Figure 6.

RW

Reserved

RW Reserved

OUT0 De-Emphasis Override Control

0 = De-emphasis for OUT0 determined by VOD_DE pin

1 = Override De-emphasis settings for OUT0. De-emphasis

settings for OUT0 are controlled by Reg 0x31[2:0]

6

5

tx0_dem_ov

tx0_PD_ov

OUT0 Power Down Override Control

0 = Disable OUT0 Power Down Override Control

1 = Enable OUT0 Power Down Override Control by value in

Reg 0x31[4].

OUT0

RW

0x31

De-Emphasis

Control

0x01

0 = Normal Operation

1 = Power Down OUT0 if Reg 0x31[5] = 1

4

3

tx0_PD

Reserved

tx0_dem

RW Reserved

De-emphasis settings for OUT0 if Reg 0x31[6] = 1. See

2:0

RW

Figure 7.

OUT1 Mute Override Control

0 = Disable OUT1 Mute Override Control

1 = Enable OUT1 Mute Override Control by value in Reg

0x32[6].

7

6

5

tx1_mute_ov

tx1_mute_val

tx1_vod_ov

0 = Normal Operation

1 = Mute OUT1 if Reg 0x32[7] = 1

OUT1 Output

Control

0x32

0x0A

OUT1 VOD Override Control

0 = VOD settings for OUT1 determined by VOD_DE pin

1 = Override VOD pin settings for OUT1. VOD settings for

OUT1 are controlled by Reg 0x32[2:0]

4:3

2:0

7

Reserved

tx1_vod

RW Reserved

VOD settings with DE = 0 for OUT1 if Reg 0x32[5] = 1. See

Figure 6.

RW Reserved

OUT1 De-Emphasis Override Control

RW

Reserved

0 = De-emphasis for OUT1 determined by VOD_DE pin

1 = Override De-emphasis settings for OUT1. De-emphasis

settings for OUT1 are controlled by Reg 0x33[2:0]

6

5

tx1_dem_ov

tx1_PD_ov

RW

OUT1 Power Down Override Control

0 = Disable OUT1 Power Down Override Control

1 = Enable OUT1 Power Down Override Control by value in

Reg 0x33[4].

OUT1

De-emphasis

Control

RW

0x33

0x11

0 = Normal Operation

1 = Power Down OUT1 if Reg 0x33[5] = 1

4

3

tx1_PD

Reserved

tx1_dem

RW Reserved

De-emphasis settings for OUT1 if Reg 0x33[6] = 1. See

Figure 7.

2:0

RW

-6 dB Launch Amplitude Adaptation Mode

0 = Enable EQ adaptation to operate with nominal 800 mV

launch amplitude

1 = Enable EQ adaptation to operate with 400 mV launch

amplitude

7

hi_gain_mode

Reserved

0x34

Splitter_Reg

0x17

6:0

Reserved

24

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

Address Register Name

Bit

7:0

Field

Default Type

RW Reserved

Description

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

Reserved

0x61

0x02

0x00

0x7F

0x00

0x01

0x00

0x0F

RW Reserved

R

Reserved

RW Reserved

R

Reserved

25

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 General Guidance for SMPTE Applications

SMPTE specifies the requirements for the Serial Digital Interface to transport digital video over coaxial cables.

One of the requirements is meeting return loss, which specifies how closely the port resembles 75-Ω impedance

across a specified frequency band. The SMPTE specifications also defines the use of AC coupling capacitors for

transporting uncompressed serial data streams with heavy low frequency content. The use of 4.7-μF AC coupling

capacitors is recommended to avoid low frequency DC wander. Refer to 表 8 for design requirements.

8.2 Typical Application

The LMH0324 is a low-power SDI equalizer that supports SDI data rates from 125 Mbps to 2.97 Gbps. 图 16

shows a typical implementation of the LMH0324 as a SDI adaptive cable equalizer. Signal attenuated by a long

coax cable is applied to the LMH0324 at the BNC port. Equalized data is output at OUT0± and OUT1± to a

downstream video processor.

2.5 V

0.1 µF

1 µF

10 µF

75 ꢀ BNC

4.7 µF

RSV_L

VDDIO

VIN

OUT0+

75 Ω board trace

IN0+

IN0-

RX+

RX-

100 Ω coupled trace

4.7 µF

OUT0-

VDD_LDO

EP

VSS

75 Ω

1 µF

0.1 µF

FPGA/Video

Processor

LMH0324

RSV1

RSV2

OUT1+

OUT1-

RX+

RX-

100-Ω coupled trace

4.7 µF

MODE_SEL = Float Enables SPI Interface

1 kΩ

220 Ω

VDDIO

图 16. LMH0324 SPI Mode Connection Diagram

26

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

Typical Application (接下页)

8.2.1 Design Requirements

表 8. LMH0324 Design Requirements

DESIGN PARAMETER

REQUIREMENTS

AC coupling capacitor at IN0+ should be a 4.7-μF surface mount ceramic capacitor. IN0-

should be AC terminated with 4.7 μF and 75 Ω to VSS.

Input AC coupling capacitors

IN0+ and IN0- should be routed with uncoupled board traces with 75-Ω characteristic

impedance.

High speed board trace for IN0

BNC connector

High performance BNC capable to support 2.97 Gbps should be used. Footprint of the BNC

should be designed to achieve 75-Ω characteristic impedance. For achieving best return loss

performance, the BNC should be placed as close to the LMH0324 device as possible

Both OUT0± and OUT1± require AC coupling capacitors. 4.7-μF capacitors are

recommended.

Output AC coupling capacitors

High speed board trace for OUT0± and

OUT1±

OUT0± and OUT1± should be routed with coupled board traces with 100-Ω differential

impedance.

Set MODE_SEL to Level-F (pin unconnected) for SPI. Set MODE_SEL to Level-L (connect 1

kΩ to VSS) for SMBus. SMBus is 3.3 V tolerant if VDDIO is powered from 2.5 V.

Use of SPI or SMBus interface

8.2.2 Detailed Design Procedure

The following general design procedure is recommended:

1. Select a suitable power supply voltage for the LMH0324. It can be powered from a single 2.5 V or 1.8 V

supply. See Power Supply Recommendations for details.

2. Check that the power supply meets the DC and AC requirements in the Recommended Operating

Conditions.

3. Select the proper pull-high or pull-low resistors for IN_OUT_SEL and OUT_CTRL for setting the signal path.

4. If -6 dB launch amplitude or other expanded programmable features are needed, select the use of SPI or

SMBus by setting the proper pull-high or pull-low resistor for the MODE_SEL pin.

5. Choose a high quality 75-Ω BNC that is capable to support 2.97 Gbps applications. Consult a BNC supplier

regarding insertion loss, impedance specifications, and recommended BNC footprint for meeting SMPTE

return loss requirements.

6. Depending on the length and insertion loss of the output traces for OUT0± and OUT1±, select the proper

pull-high or pull-low resistors for VOD_DE to set the output amplitude and de-emphasis settings. Refer to

Table 4 for details.

7. Choose a small 0402 surface mount ceramic capacitors for the AC coupling and bypass capacitors.

8. Use proper footprint for BNC and AC coupling capacitors. Anti-pads are commonly used in power and VSS

planes under these landing pads to achieve optimum return loss.

8.2.3 Recommended VOD and DE Register Settings

表 9 shows recommended output amplitude and de-emphasis register settings for most applications.

表 9. VOD and DE Register Settings

VOD REG SETTING

DEM REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

VOD (mVpp)

DEM (dB)

0

1

2

3

4

0

1

2

1

2

3

1

410

486

560

635

716

0

-0.1

-0.9

-0.3

-1.3

-2.4

-0.5

27

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

DEM (dB)

表 9. VOD and DE Register Settings (接下页)

VOD REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

DEM REG SETTING

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

VOD (mVpp)

4

5

6

7

2

3

4

1

2

3

4

5

1

2

3

4

5

1

2

3

4

5

716

810

880

973

-1.8

-3.0

-4.0

-0.8

-2.4

-3.6

-4.6

-6.1

-1.0

-2.7

-4.0

-5.0

-6.5

-1.2

-3.1

-4.6

-5.7

-7.1

8.2.4 Application Performance Plots

The LMH0324 performance was measured with the test setups shown in 图 17.

CC

75 Q /}ꢀÆ /ꢀꢁoꢂ

Pattern

Generator

IN0+ LMH0324 OUT0±

Oscilloscope

V_O= 800 mVp-p,

PRBS10

图 17. Test Setup for LMH0324 Cable Equalizer (IN0+)

The eye diagrams in this subsection show how the LMH0324 improves overall signal integrity in the data path

when different cable lengths are used at IN0+.

56 ps/DIV

图 18. 2.97 Gbps, CC = 150 m Belden 1694A

图 19. 2.97 Gbps, CC = 200 m Belden 1694A

28

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

112 ps/DIV

图 20. 1.485 Gbps, CC = 200 m Belden 1694A

图 21. 1.485 Gbps, CC = 280 m Belden 1694A

617 ps/DIV

图 23. 270 Mbps, CC = 600 m Belden 1694A

图 22. 270 Mbps, CC = 400 m Belden 1694A

29

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

9 Power Supply Recommendations

The LMH0324 is designed to provide flexibility in supply rails. There are two ways to power the LMH0324:

•

Single 2.5 V Supply Mode: This mode offers ease of use and pin compatibility with the LMH1219 (11.88

Gbps Ultra-HD Adaptive Cable Equalizer with Integrated Reclocker). The internal circuitry receives power

from the on-chip 1.8 V regulator. In this mode, 2.5 V is applied to VIN, VDDIO, and RSV_L. This mode

supports SPI or SMBus serial interface. See 图 24 for more details.

•

Single 1.8 V Supply Mode: This mode provides the lowest power consumption. In this mode, 1.8 V is

connected to VIN, VDD_LDO and VDDIO. RSV_L is tied to VSS. In this mode, SPI is supported, but SMBus

serial interface is not. In Single 1.8 V Supply Mode, the LMH0324 is not drop-in compatible with the

LMH1219. See 图 25 for more details.

2.5 V

1 µF

10 µF

0.1 µF

RSV_L

VDDIO

VIN

Internal LDO

2.5 V to 1.8 V

EP

VSS

VDD_LDO (1.8 V)

1 µF

0.1 µF

图 24. Single 2.5 V Supply Mode - Compatible with LMH1219

1.8 V

0.1 µF

10 µF

1.8 V

1 µF

0.1 µF

RSV_L

VDDIO

VIN

VDD_LDO

EP

VSS

1 µF

0.1 µF

图 25. Single 1.8 V Supply Mode - Not Compatible with LMH1219

For power supply de-coupling, 0.1-μF surface-mount ceramic capacitors are recommended to be placed close to

each supply pin to VSS. Larger bulk capacitors (for example, 10 µF and 1 µF) are recommended to be placed

close to each LMH0324 device. Good supply bypassing requires low inductance capacitors. This can be

achieved through an array of multiple small body size surface-mount bypass capacitors in order to keep low

supply impedance. Better results can be achieved through the use of a buried capacitor formed by a VDD and

VSS plane separated by 2-4 mil dielectric in a printed circuit board.

30

LMH0324

www.ti.com.cn

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

10 Layout

10.1 Layout Guidelines

The following layout guidelines are recommended for the LMH0324:

1. Choose a suitable board stack-up that supports 75-Ω single-ended trace and 100-Ω differential trace routing

on the board's top layer. This is typically done with a Layer 2 ground plane reference for the 100-Ω

differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.

2. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to IN0+ and IN0-. The

trace width is typically 8-10 mil reference to a ground plane at Layer 3.

3. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-µF AC coupling

capacitor and IC landing pads to minimize parasitic capacitance. The size of the anti-pad depends on the

board stack-up and can be determined by a 3-dimension electromagnetic simulation tool.

4. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic

impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.

5. Keep trace length short between the BNC and IN0+. The trace routing for IN0+ and IN0- should be

symmetrical, approximately equal lengths and equal loading.

6. Use coupled differential traces with 100-Ω impedance for signal routing to OUT0± and OUT1±. They are

usually 5-8 mil trace width reference to a ground plane at Layer 2.

7. The exposed pad EP of the package should be connected to the ground plane through an array of vias.

These vias are solder-masked to avoid solder flow into the plated-through holes during the board

manufacturing process.

8. Connect each supply pin (VIN, VDDIO, VDD_LDO, VSS) to the power or ground planes with a short via. The

via is usually placed tangent to the supply pins’ landing pads with the shortest trace possible.

9. Power supply bypass capacitors should be placed close to the supply pins. They are commonly placed at the

bottom layer and share the ground of the EP.

10.2 Layout Example

The following example layout demonstrates the high speed signal trace routing to the LMH0324.

1. BNC footprint and anti-pad: Consult BNC manufacturer for proper size.

2. Anti-pad under passive components.

3. 75-Ω single-ended trace.

4. 100-Ω coupled trace.

5. Vias with solder mask.

2

1

4

3

5

2

图 26. LMH0324 PCB Layout Example

31

LMH0324

ZHCSIC8B –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

32

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

4.1

3.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

7

12

20X 0.5

6

13

2X

25

2.5

2.6 0.1

1

18

0.3

24X

0.2

24

19

PIN 1 ID

(OPTIONAL)

0.1

C A B

C

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(1.05)

SYMM

25

(3.8)

20X (0.5)

(R0.05)

TYP

6

13

(

0.2) TYP

VIA

7

12

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

19

(R0.05) TYP

24

24X (0.6)

1

18

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

25

(3.8)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	LMH0324RTWR
厂家：	TEXAS INSTRUMENTS
描述：	3G HD/SD 低功耗 SDI 自适应电缆均衡器 \| RTW \| 24 \| -40 to 85
文件：	总40页 (文件大小：1286K)
中文：	中文翻译
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