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LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

具有集成时钟恢复器的 LMH0397 3G-SDI 双向 I/O

1 特性

2 应用

1

•

带有集成时钟恢复器的用户可配置型自适应电缆均

衡器或电缆驱动器

•

SMPTE 兼容串行数字接口 (SDI)

广播视频路由器、交换机、分配放大器和监视器

IP 媒体网关

•

支持 ST-424 (3G)、ST-292 (HD) 和 ST-259 (SD)

兼容 DVB-ASI 和 AES10 (MADI)

数字视频处理和编辑

集成时钟恢复器锁定为 2.97Gbps、1.485Gbps 或

1.001 分频子速率和 270Mbps 的 SMPTE 速率

3 说明

•

片上 75Ω 终端和回损补偿网络

EQ（均衡器）模式：

LMH0397 是带有集成时钟恢复器的 3G SDI-SDI 75Ω

双向 I/O。此器件可以在输入模式下配置为自适应电缆

均衡器，也可以在输出模式下配置为双电缆驱动器，允

许系统设计人员灵活地将单个 BNC 用作输入或输出端

口，从而简化 HD-SDI 视频硬件设计。集成的时钟恢

复器在两种模式下均可锁定到所有支持的高达

2.97Gbps 的 SMPTE 数据速率。此双向 I/O 具有片上

75Ω 终端和回损补偿网络，满足严格的 SMPTE 回损

要求。

–

带有集成时钟恢复器的自适应电缆均衡器

具有去加重功能的 100Ω 输出驱动器

时钟恢复型 75Ω 环通输出

EQ 模式电缆传输距离

（Belden 1694A，禁用 SDI_OUT）：

–

2.97Gbps 时为 200m

1.485Gbps 时为 300m

270Mbps 时为 600m

额外的 75Ω 驱动器输出可让 LMH0397 支持各种系统

功能。在 EQ（均衡器）模式下，该第二个 75Ω 驱动

器可用作环通输出。在电缆驱动器 (CD) 模式下，该

75Ω 驱动器可用作第二个扇出电缆驱动器。主机侧

100Ω 驱动器也可在 CD 模式下用作环回输出，从而用

于监控。

•

CD（电缆驱动器）模式：

–

带有集成时钟恢复器的双路差分输出电缆驱动器

自适应 PCB 输入均衡器

时钟恢复型 100Ω 环回输出

•

75Ω 输出端的自动预加重和转换率控制

75Ω 和 100Ω 输出端的极性反转

器件信息⁽¹⁾

没有输入信号时自动进入省电工作模式

器件型号

LMH0397

封装

WQFN (32)

封装尺寸（标称值）

–

功率耗散：25mW（典型值）

5.00mm × 5.00mm

•

通过 ENABLE 引脚进行断电控制

2.5V 单电源

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

EQ 模式功耗：275mW（典型值）

CD 模式功耗：290mW（典型值）

简化方框图

•

可通过引脚、SPI 或 SMBus 接口进行编程

工作温度范围：-40°C 至 +85°C

Cable

EQ

100-Ω

Driver

M

U

X

SDI_IO

OUT0

M

U

X

CDR

TX_RX

5mm × 5mm 32 引脚 WQFN 封装

Cable

Driver

与 LMH1297 引脚兼容，便于轻松升级至 12G-SDI

PCB

EQ

IN0

Cable

Driver

SDI_OUT

Control

Power

Management

Serial

Interface

LDO

Control Logic

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS558

LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

www.ti.com.cn

8.4 Device Functional Modes........................................ 24

8.5 Register Maps ........................................................ 28

Application and Implementation ........................ 29

9.1 Application Information............................................ 29

9.2 Typical Applications ................................................ 30

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

9

10 Power Supply Recommendations ..................... 36

11 Layout................................................................... 36

11.1 Layout Guidelines ................................................. 36

11.2 Layout Example .................................................... 38

12 器件和文档支持 ..................................................... 39

12.1 器件支持................................................................ 39

12.2 文档支持 ............................................................... 39

12.3 接收文档更新通知 ................................................. 39

12.4 支持资源................................................................ 39

12.5 商标....................................................................... 39

12.6 静电放电警告......................................................... 39

12.7 出口管制提示......................................................... 39

12.8 Glossary................................................................ 39

13 机械、封装和可订购信息....................................... 40

13.1 Package Option Addendum .................................. 41

7.6 Recommended SMBus Interface Timing

Specifications........................................................... 13

7.7 Serial Parallel Interface (SPI) Timing

Specifications........................................................... 13

7.8 Typical Characteristics............................................ 15

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

8

4 修订历史记录

Changes from Revision A (June 2017) to Revision B

Page

•

首次公开发布 .......................................................................................................................................................................... 1

2

LMH0397

www.ti.com.cn

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

5 说明（续）

片上时钟恢复器可减弱高频抖动并使用纯净的低抖动时钟完全重新生成数据。此时钟恢复器具有内置环路滤波器，

且不需要任何输入参考时钟。LMH0397 还有内部眼图张开度监视器和可编程引脚，以便进行 CDR 锁定指示、输

入载波检测或硬件中断，从而支持系统诊断和电路板启动。

LMH0397 由 2.5V 单电源供电运行。该器件采用小尺寸 5mm × 5mm 32 引脚 WQFN 封装。LMH0397 还与

LMH1297 的引脚兼容。

3

LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

www.ti.com.cn

6 Pin Configuration and Functions

RTV Package

32-Pin WQFN

Top View

1

24

23

22

21

20

19

18

SDI_IO+

SDI_VOD

OUT0+

OUT0-

VDD_CDR

VSS

2

SDI_IO-

3

VSS

4

OUT0_SEL

LMH0397

5

EQ/CD_SEL

6

IN0+

VSS

7

8

IN0-

SDI_OUT-

SDI_OUT+

EP = VSS

17

OUT_CTRL

Pin Functions

NAME

HIGH-SPEED DIFFERENTIAL I/OS

I/O⁽¹⁾

DESCRIPTION

NO.

SDI_IO+

SDI_IO–

SDI_OUT+

1

2

8

I/O, Analog

Single-ended complementary inputs or outputs with on-chip 75-Ω termination at SDI_IO+ and

SDI_IO–. SDI_IO± include integrated return loss networks designed to meet the SMPTE input

and output return loss requirements. Connect SDI_IO+ to a BNC through a 4.7-µF,

AC-coupling capacitor. SDI_IO– should be similarly AC-coupled and terminated with an

external 4.7-µF capacitor and 75-Ω resistor to GND.

I/O, Analog

O, Analog

EQ Mode:

SDI_IO+ is the 75-Ω input port of the adaptive cable equalizer for SMPTE video applications.

CD Mode:

SDI_IO+ is the 75-Ω output port of the cable driver for SMPTE video applications.

Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT+ and

SDI_OUT–. SDI_OUT± include integrated return loss networks designed to meet the SMPTE

output return loss requirements. SDI_OUT± is used as a second cable driver. Connect

SDI_OUT+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_OUT– should be similarly

AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to GND.

EQ Mode:

SDI_OUT± can be enabled as a loop-through 75-Ω output port. It outputs the reclocked data

from the adaptive cable equalizer to form a loop-through output with adaptive cable equalizer,

reclocker, and cable driver.

SDI_OUT–

7

O, Analog

CD Mode:

SDI_OUT± is the second 75-Ω fan-out cable driver.

IN0–

18

19

22

23

I, Analog

O, Analog

Differential inputs from host video processor. On-chip 100-Ω differential termination. Requires

external 4.7-µF, AC-coupling capacitors for SMPTE applications.

IN0+

OUT0–

OUT0+

Differential outputs to host video processor. On-chip 100-Ω differential termination. Requires

external 4.7-µF, AC-coupling capacitors for SMPTE applications.

(1) I = Input, O = Output, I/O = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic

4

LMH0397

www.ti.com.cn

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

Pin Functions (continued)

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

4

CONTROL PINS

OUT0_SEL enables the use of the 100-Ω host-side output driver at OUT0±.

See Table 3 for details.

OUT0_SEL is internally pulled high by default (OUT0 disabled).

OUT0_SEL

EQ/CD_SEL

I, LVCMOS

EQ/CD_SEL selects the signal direction of the LMH0397 bidirectional I/O. It configures the

LMH0397 as an adaptive equalizer (EQ Mode) or as a cable driver (CD Mode).

See Table 2 for details.

5

EQ/CD_SEL is internally pulled low by default (EQ Mode).

HOST_EQ0 selects the driver output amplitude and de-emphasis level for OUT0± (in EQ

Mode) and equalizer setting for IN0± (in CD Mode).

See Table 5 and Table 10 for details.

HOST_EQ0

MODE_SEL

SDI_OUT_SEL

9

I, 4-LEVEL

I, LVCMOS

MODE_SEL enables the SPI or SMBus serial control interface.

See Table 11 for details.

12

14

SDI_OUT_SEL enables the use of the 75-Ω output driver at SDI_OUT±.

See Table 3 for details.

SDI_OUT_SEL is internally pulled high by default (SDI_OUT disabled).

OUT_CTRL selects the signal being routed to the output. It is used to enable or bypass the

reclocker and to enable or bypass the cable equalizer.

See Table 7 for details.

OUT_CTRL

SDI_VOD

17

24

I, 4-LEVEL

SDI_VOD selects one of four output amplitudes for the cable drivers at SDI_IO± and

SDI_OUT±.

See Table 8 for details.

LOCK_N is the reclocker lock indicator. LOCK_N is pulled low when the reclocker has

acquired lock condition. LOCK_N is a 3.3-V tolerant, open-drain output. It requires an external

resistor to a logic supply.

LOCK_N can be reconfigured to indicate Carrier Detector (CD_N) or Interrupt (INT_N)

through register programming. See Status Indicators and Interrupts.

O, LVCMOS,

OD

LOCK_N

ENABLE

27

32

A logic-high at ENABLE enables normal operation for the LMH0397. A logic-low at ENABLE

places the LMH0397 in Power-Down Mode.

I, LVCMOS

ENABLE is internally pulled high by default.

SPI SERIAL CONTROL INTERFACE, MODE_SEL = F (FLOAT)

SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH0397

slave device.

SS_N

11

I, LVCMOS

SS_N is a 2.5-V LVCMOS input and is internally pulled high by default.

MOSI is the SPI serial control data input to the LMH0397 slave device when the SPI bus is

enabled. MOSI is a 2.5-V LVCMOS input.

An external pullup resistor is recommended.

MOSI

MISO

SCK

13

28

29

I, LVCMOS

O, LVCMOS

I, LVCMOS

MISO is the SPI serial control data output from the LMH0397 slave device.

MISO is a 2.5-V LVCMOS output.

SCK is the SPI serial input clock to the LMH0397 slave device when the SPI interface is

enabled. SCK is a 2.5-V LVCMOS input.

An external pullup resistor is recommended.

SMBUS SERIAL CONTROL INTERFACE, MODE_SEL = L (1 KΩ TO VSS)

ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one

of the 16 supported SMBus addresses when SMBus is enabled. See Table 12 for details.

ADDR0

11

13

28

29

Strap, 4-LEVEL

SDA is the SMBus bidirectional data line to or from the LMH0397 slave device when SMBus

is enabled. SDA is an open-drain I/O and requires an external pullup resistor to the SMBus

termination voltage. SDA is 3.3-V tolerant.

I/O, LVCMOS,

OD

SDA

ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one

of the 16 supported SMBus addresses when SMBus is enabled. See Table 12 for details.

ADDR1

SCL

Strap, 4-LEVEL

SCL is the SMBus input clock to the LMH0397 slave device when SMBus is enabled. It is

driven by a LVCMOS open-drain driver from the SMBus master. SCL requires an external

pullup resistor to the SMBus termination voltage. SCL is 3.3-V tolerant.

I/O, LVCMOS,

OD

5

LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

RESERVED

RSV1

NO.

10

15

16

25

26

RSV2

RSV3

—

Reserved pins. Do not connect.

Ground reference.

RSV4

RSV5

POWER

VSS

3, 6, 20

21

I, Ground

I, Power

VDD_CDR powers the reclocker circuitry. It is connected to the same 2.5-V ± 5% supply as

VIN.

VDD_CDR

VIN

30

VIN is connected to an external 2.5-V ± 5% power supply.

VDD_LDO is the output of the internal 1.8-V LDO regulator. VDD_LDO output requires an

external 1-µF and 0.1-µF bypass capacitor to VSS. The internal LDO is designed to power

internal circuitry only.

VDD_LDO

EP

31

—

O, Power

I, Ground

EP is the exposed pad at the bottom of the RTV package. The exposed pad should be

connected to the VSS plane through a 3 × 3 via array.

6

LMH0397

www.ti.com.cn

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–30

MAX

2.75

4

UNIT

V

Supply voltage (VIN, VDD_CDR)

Input voltage for 4-level pins

V

Input or output voltage for 2-level control pins

SMBus input or output voltage (SDA, SCL)

SPI input or output voltage (SS_N, MISO, MOSI, and SCK)

High-speed input or output voltage (IN0±, SDI_IO±, OUT0±, SDI_OUT±)

Input current (IN0±, SDI_IO±)

V

2.75

30

V

mA

°C

Operating junction temperature

125

150

Storage temperature, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±6000

±5500

±1500

UNIT

All pins except 13 and 29

Pins 13 and 29

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

0.72

NOM

MAX

2.625

3.6

UNIT

V

Supply voltage

VIN, VDD_CDR to VSS

2.5

VDD_SMBUS

SMBus: SDA, SCL open-drain termination voltage

V

Normal mode

Splitter mode

0.8

0.4

0.88

0.44

Source launch amplitude before

coaxial cable to SDI_IO+

V_{SDI_IO_LAUNCH}

Vp-p

0.36

V_{IN0_LAUNCH}

T_JUNCTION

T_AMBIENT

Source differential launch amplitude

Operating junction temperature

Ambient temperature

300

500

1000 mVp-p

110

85

°C

–40

25

< 20

< 10

50 Hz to 1 MHz, sinusoidal

NTps_max

Maximum supply noise⁽¹⁾

mVp-p

1.1 MHz to 50 MHz, sinusoidal

(1) The sum of the DC supply voltage and AC supply noise must not exceed the recommended supply voltage range.

7

LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

www.ti.com.cn

7.4 Thermal Information

LMH0397

RTV (WQFN)

32 PINS

32.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

15.0

6.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.5

R_θJC(bot)

1.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

Power dissipation, EQ Mode,

Measured with PRBS10,

CDR Locked to 2.97 Gbps,

VOD = default,

SDI_OUT± disabled

OUT0± enabled

275

405

mW

PD_{EQ_MODE}

SDI_OUT± enabled

OUT0± enabled

HEO/VEO lock monitor disabled

SDI_IO± enabled

SDI_OUT± disabled

OUT0± disabled

290

335

415

460

mW

SDI_IO± enabled

SDI_OUT± disabled

OUT0± enabled

Power dissipation, CD Mode,

Measured with PRBS10,

CDR Locked to 2.97 Gbps,

VOD = default,

PD_{CD_MODE}

SDI_IO± enabled

SDI_OUT± enabled

OUT0± disabled

HEO/VEO lock monitor disabled

SDI_IO± enabled

SDI_OUT± enabled

OUT0± enabled

EQ Mode, Power Save Mode,

ENABLE = H, no signal applied at SDI_IO+

25

Power dissipation,

Power Save Mode

PD_Z

mW

CD Mode, Power Save Mode,

ENABLE = H, no signal applied at IN0±

Current consumption, EQ Mode, SDI_OUT± disabled

110

131

191

mA

OUT0± enabled

Measured with PRBS10,

CDR Locked to 2.97 Gbps,

VOD = default,

IDD_{EQ_MODE}

SDI_OUT± enabled

OUT0± enabled

162

116

HEO/VEO lock monitor disabled

SDI_IO± enabled

SDI_OUT± disabled

OUT0± disabled

137

157

196

217

mA

SDI_IO± enabled

SDI_OUT± disabled

OUT0± enabled

Current consumption, CD Mode,

Measured with PRBS10,

CDR Locked to 2.97 Gbps,

VOD = default,

HEO/VEO lock monitor disabled

CD Mode

134

166

184

IDD_{CD_MODE}

SDI_IO± enabled

SDI_OUT± enabled

OUT0± disabled

SDI_IO± enabled

SDI_OUT± enabled

OUT0± enabled

8

LMH0397

www.ti.com.cn

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EQ Mode, Power Save Mode,

ENABLE = H, no signal applied at SDI_IO+

10

Current consumption,

Power Save Mode

IDD_Z

mA

CD Mode, Power Save Mode,

ENABLE = H, no signal applied at IN0±

10

EQ Mode, Power-Down Mode,

ENABLE = L, no signal applied at SDI_IO+

30

Current consumption,

Power-Down Mode

IDD_{Z_PD}

mA

CD Mode, Power-Down Mode,

ENABLE = L, no signal applied at IN0±

Current consumption, EQ Mode SDI_OUT± disabled

189

mA

OUT0± enabled

CDR acquiring lock to 2.97

Gbps,

VOD = default,

IDD_{TRANS_EQ}

SDI_OUT± enabled

OUT0± enabled

257

200

HEO/VEO lock monitor enabled

SDI_IO± enabled

SDI_OUT± disabled

OUT0± disabled

mA

SDI_IO± enabled

SDI_OUT± disabled

OUT0± enabled

Current consumption, CD Mode

CDR acquiring lock to 2.97

Gbps,

VOD = default,

HEO/VEO lock monitor enabled

222

271

290

IDD_{TRANS_CD}

SDI_IO± enabled

SDI_OUT± enabled

OUT0± disabled

SDI_IO± enabled

SDI_OUT± enabled

OUT0± enabled

LVCMOS DC SPECIFICATIONS

2-level input (SS_N, SCK, MOSI,

EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL,

ENABLE)

0.72 ×

VIN

VIN +

0.3

V_IH

Logic high input voltage

V

0.7 ×

VIN

2-level input (SCL, SDA)

3.6

2-level input (SS_N, SCK, MOSI,

EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL,

ENABLE, SCL, SDA)

0.3 ×

VIN

V_IL

Logic low input voltage

Logic high output voltage

0

V

0.8 ×

VIN

V_OH

IOH = –2 mA, (MISO)

VIN

0.2 ×

VIN

IOL = 2 mA, (MISO)

0

V_OL

Logic low output voltage

V

IOL = 3 mA, (LOCK_N, SDA)

0.4

LVCMOS (EQ/CD_SEL, SDI_OUT_SEL,

ENABLE)

15

LVCMOS (OUT0_SEL)

65

10

15

10

Input high leakage current

(Vinput = VIN)

I_IH

µA

LVCMOS (LOCK_N)

SPI mode: LVCMOS (SS_N, SCK, MOSI)

SMBus mode: LVCMOS (SCL, SDA)

LVCMOS (EQ/CD_SEL, SDI_OUT_SEL,

ENABLE)

–50

LVCMOS (OUT0_SEL)

–15

–10

–15

–50

–10

Input low leakage current

(Vinput = GND)

LVCMOS (LOCK_N)

I_IL

µA

SPI mode: LVCMOS (SCK, MOSI)

SPI mode: LVCMOS (SS_N)

SMBus mode: LVCMOS (SCL, SDA)

9

LMH0397

ZHCSKF3B –APRIL 2017–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)

Measured voltage at 4-level pin with

V_{LVL_H}

V_{LVL_F}

V _{LVL_R}

V_{LVL_L}

LEVEL-H input voltage

LEVEL-F default voltage

LEVEL-R input voltage

LEVEL-L input voltage

VIN

V

external 1 kΩ to VIN

2/3 ×

VIN

Measured voltage 4-level pin at default

Measured voltage at 4-level pin with

external 20 kΩ to VSS

1/3 ×

VIN

Measured voltage at 4-level pin with

external 1 kΩ to VSS

0

4-levels (HOST_EQ0, MODE_SEL,

OUT_CTRL, SDI_VOD)

20

45

80

Input high leakage current

(Vinput = VIN)

I_IH

µA

SMBus mode: 4-levels (ADDR0, ADDR1)

4-levels (HOST_EQ0, MODE_SEL,

OUT_CTRL, SDI_VOD)

–160

–93

–40

Input low leakage current

(Vinput = GND)

I_IL

SMBus mode: 4-levels (ADDR0, ADDR1)

RECEIVER SPECIFICATIONS (SDI_IO+, EQ MODE)

DC input single-ended

R_{SDI_IO_TERM}

SDI_IO+ and SDI_IO– to internal common

mode bias

63

75

87

Ω

dB

V

termination

S11, 5 MHz to 1.485 GHz

S11, 1.485 GHz to 3 GHz

–30

–22

Input return loss at SDI_IO+

RL_{SDI_IO_S11}

reference to 75 Ω⁽¹⁾

SDI_IO+ DC common-mode

Input DC common-mode voltage at

SDI_IO+ or SDI_IO– to GND

V_{SDI_IO_CM}

voltage

1.4

100

50

SD, input signal at SDI_IO+,

Input launch amplitude = 800 mVp-p

V_{SDI_IO_WANDER}Input DC wander

mVp-p

HD, 3G input signal at SDI_IO+,

Input launch amplitude = 800 mVp-p

RECEIVER SPECIFICATIONS (IN0±, CD MODE)

R_{IN0_TERM}

DC input differential termination Measured across IN0+ to IN0–

80

100

–22

120

Ω

RL_{IN0_SDD11}

Input differential return loss⁽¹⁾

SDD11, 10 MHz to 2.8 GHz

dB

Differential to common-mode

input conversion⁽¹⁾

RL_{IN0_SCD11}

V_{IN0_CM}

SCD11, 10 MHz to 11.1 GHz

–21

dB

V

Input common-mode voltage at IN0+ or

IN0– to GND

DC common-mode voltage

2.06

Signal detect (default)

Assert ON threshold level for

IN0±

2.97 Gbps, EQ and PLL pathological

pattern

CD_{ON_IN0}

20

18

mVp-p

Signal detect (default)

Deassert OFF threshold level

for IN0±

2.97 Gbps, EQ and PLL pathological

pattern

CD_{OFF_IN0}

DRIVER OUTPUT (SDI_IO+ AND SDI_OUT+, CD MODE)

SDI_IO+ and SDI_IO–,

SDI_OUT+ and SDI_OUT– to VIN

DC output single-ended

termination

R_{OUT_TERM}

63

75

87

Ω

Measure AC signal at SDI_IO+ and

SDI_OUT+, with SDI_IO– and SDI_OUT–

AC terminated with 75 Ω

840

SDI_VOD = H

VOD_{CD_OUTP}

Output single-ended voltage

mVp-p

SDI_VOD = F

SDI_VOD = R

SDI_VOD = L

720

800

880

760

880

(1) This parameter is measured with the LMH1297EVM (Evaluation board for LMH0397).

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measure AC signal at SDI_IO– and

SDI_OUT-, with SDI_IO+ and SDI_OUT+

AC terminated with 75 Ω

840

SDI_VOD = H

VOD_{CD_OUTN}

Output single-ended voltage

mVp-p

SDI_VOD = F

SDI_VOD = R

SDI_VOD = L

720

800

880

760

880

Output pre-emphasis boost amplitude at

SDI_IO+ and SDI_OUT+, programmed to

maximum setting through register,

measured at SDI_VOD=F

PRE_{CD_OUTP}

Output pre-emphasis

2

dB

Output pre-emphasis boost amplitude at

SDI_IO– and SDI_OUT–, programmed to

maximum setting through register,

measured at SDI_VOD=F

PRE_{CD_OUTN}

Measured with PRBS10 pattern, default

VOD at 20% – 80% amplitude, default pre-

emphasis enabled

59

67

t_{R_F_SDI}

Output rise and fall time⁽¹⁾

ps

2.97 Gbps

1.485 Gbps

270 Mbps

60

73

400

550

700

Measured with PRBS10 pattern, default

VOD at 20% – 80% amplitude, default pre-

emphasis enabled

0.8

11

Output rise and fall time

mismatch⁽¹⁾

t_{R_F_DELTA}

2.97 Gbps

1.485 Gbps

270 Mbps

0.8

72

12

150

Measured with PRBS10 pattern, default

VOD, default pre-emphasis enabled⁽²⁾

3G/HD/SD

V_OVERSHOOT

Output overshoot or undershoot

5%

V_{DC_OFFSET}

V_{DC_WANDER}

DC offset

3G/HD/SD

±0.2

20

V

DC wander

3G/HD/SD with EQ pathological pattern

S22, 5 MHz to 1.485 GHz

mV

dB

Output return loss at SDI_IO+

and SDI_OUT+ reference to 75

Ω⁽¹⁾

–25

RL_{CD_S22}

S22, 1.485 GHz to 3 GHz

–22

dB

DRIVER OUTPUT (OUT0±, EQ AND CD MODE)

DC output differential

R_{OUT0_TERM}

Measured across OUT0+ and OUT0–

80

100

410

120

620

Ω

termination

Measured with 8T pattern

HOST_EQ0 = H

Output differential voltage at

HOST_EQ0 = F

HOST_EQ0 = R

HOST_EQ0 = L

485

560

635

810

VOD_OUT0

OUT0±

mVp-p

Measured with 8T pattern

HOST_EQ0 = H

410

De-emphasized output

VOD_{OUT0_DE}

HOST_EQ0 = F

HOST_EQ0 = R

HOST_EQ0 = L

550

545

532

mVp-p

ps

differential voltage at OUT0±

Measured with 8T Pattern, 20% to 80%

amplitude

t_R/t_F

Output rise and fall time

45

(2) V_OVERSHOOTovershoot or undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The

maximum value specified in Electrical Characteristics for V_OVERSHOOTis based on bench evaluation across temperature and supply

voltages with the LMH1297EVM.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured with the device powered up and

RL_OUT0-SDD22

Output differential return loss⁽¹⁾outputs a 10-MHz clock signal.

SDD22, 10 MHz to 2.8 GHz

–24

dB

Measured with the device powered up and

outputs a 10-MHz clock signal.

SCC22, 10 MHz to 4.75 GHz

Output common-mode return

loss⁽¹⁾

RL_OUT0-SCC22

–12

8

dB

AC common-mode voltage on

OUT0±⁽¹⁾

V_{OUT0_CM}

Default setting, PRBS31, 2.97 Gbps

mV (rms)

RECLOCKER OUTPUT JITTER (EQ MODE)

Measured at OUT0±, with SDI_OUT

disabled (BER ≤ 1E-12), PRBS10,

TX launch amplitude = 800 mVp-p before

cable to SDI_IO+

0.1

TJ_{EQ_MODE}

Total jitter, reclocked output⁽¹⁾

UIp-p

2.97 Gbps: 200-m Belden 1694A

1.485 Gbps: 300-m Belden 1694A

270 Mbps: 600-m Belden 1694A

0.1

0.11

Measured at OUT0±, with SDI_OUT

disabled (BER ≤ 1E-12), PRBS10,

Total jitter, with CDR bypassed TX launch amplitude = 800 mVp-p before

cable to SDI_IO+

TJ_RAW

0.2

125 Mbps: 600-m Belden 1694A

RECLOCKER OUTPUT JITTER (CD MODE)

Measured at SDI_IO+ and SDI_OUT+,

OUT0± disabled

PRBS10, 3G/HD/SD

AJ_{CD_MODE}

Alignment jitter⁽¹⁾

Timing jitter⁽¹⁾

0.1

0.14

UI

Measured at SDI_IO+ and SDI_OUT+,

OUT0± disabled

TMJ_{CD_MODE}

0.45

PRBS10, 3G/HD/SD

RECLOCKER SPECIFICATIONS (EQ MODE UNLESS OTHERWISE SPECIFIED)

SMPTE 3G, /1

2.97

2.967

1.485

1.4835

270

SMPTE 3G, /1.001

Gbps

LOCK_RATE

BYPASS_RATE

BW_PLL

Reclocker lock data rates

SMPTE HD, /1

SMPTE HD, /1.001

SMPTE SD, /1

Mbps

Reclocker automatically goes to

bypass

MADI

125

Applied 0.2 UI input sinusoidal jitter,

measure –3-dB bandwidth on input-to-

output jitter transfer

5

PLL Bandwidth

MHz

2.97 Gbps

1.485 Gbps

3

1

270 Mbps

J_PEAKING

PLL jitter peaking

2.97 Gbps, 1.485 Gbps, 270 Mbps

<0.3

dB

UI

Sinusoidal jitter tolerance,

tested at 3G,

SJ amplitude swept from 1 MHz to 80 MHz,

tested at BER ≤ 1E-12, cable equalizer at

SDI_IO+ bypassed

J_{TOL_IN}

SDI_IO+ input jitter tolerance

0.65

SMPTE supported data rates, disable

HEO/VEO monitor, cable equalizer at

SDI_IO+ bypassed

T_LOCK

Lock time

5

ms

°C

Adaptation time for cable equalizer at

SDI_IO+, reclocker bypassed

T_ADAPT

EQ adapt time at EQ Mode

VCO temperature lock range

Measured with temperature ramp of 5°C

per minute, ramp up and down, –40°C to

85°C operating range at 2.97 Gbps

TEMP_LOCK

125

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured from SDI_IO+ to OUT0, 2.97

Gbps, SDI_IO+,

75-m Belden 1694A at SDI_IO+

1.4 UI +

465

TLAT_{EQ_MODE}

Reclocker latency at EQ Mode

ps

Measured from SDI_IO+ to SDI_OUT+,

2.97 Gbps, SDI_IO+, 75-m Belden 1694A

at SDI_IO+

1.7 UI +

415

Measured from IN0± to SDI_IO+, 2.97

Gbps

1.5 UI +

175

TLAT_{CD_MODE}

Reclocker latency at CD Mode

ps

Measured from IN0± to SDI_OUT+, 2.97

Gbps

1.6 UI +

130

7.6 Recommended SMBus Interface Timing Specifications

over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

F_SCL

T_BUF

SMBUS SCL frequency

10

400

kHz

Bus free time between stop and start

condition

See Figure 1.

1.3

0.6

µs

After this period, the first clock is

generated.

T_HD:STA

Hold time after (repeated) start condition.

T_SU:STA

T_SU:STO

T_HD:DAT

T_SU:DAT

T_LOW

Repeated start condition setup time

Stop condition setup time

Data hold time

See Figure 1.

0.6

0

µs

ns

µs

ns

Data setup time

100

1.3

0.6

Clock low period

T_HIGH

T_R

Clock high period

Clock and data rise time

Clock and data fall time

300

T_F

Time from minimum VDDIO to SMBus

valid write or read access

T_POR

SMBus ready time after POR

50

ms

(1) These parameters support SMBus 2.0 specifications.

7.7 Serial Parallel Interface (SPI) Timing Specifications

over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

F_SCK

T_PH

SPI SCK frequency

20

MHz

% SCK

period

SCK pulse width high

SCK pulse width low

40

See Figure 2 and Figure 3.

% SCK

period

T_PL

T_SU

MOSI setup time

4

ns

µs

ns

See Figure 2 and Figure 3.

T_H

MOSI hold time

T_SSSU

T_SSH

T_SSOF

T_ODZ

T_OZD

T_OD

SS setup time

14

4

SS hold time

SS off time

1

MISO driven-to-tristate time

MISO tristate-to-driven time

MISO output delay time

20

10

15

See Figure 2 and Figure 3.

(1) Typical SPI load capacitance is 2 pF.

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tt_LOW

t

t_R

t_HIGH

SCL

SDA

tt_HD:STA

t

t_HD:DAT

t_SU:STA

t_F

t_SU:STO

tt_BUF

t

t_SU:DAT

SP

ST

SP

Figure 1. SMBus Timing Parameters

t_SSOF

t_SSH

SS_N

SCK

t_PL

t_SSSU

t_PH

t_H

t_SU

HiZ

MOSI

MISO

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

t_ODZ

HiZ

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 2. SPI Timing Parameters (Write Operation)

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 3. SPI Timing Parameters (Read Operation)

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7.8 Typical Characteristics

T_A= 25°C and VIN = VDD_CDR = 2.5 V (unless otherwise noted)

Figure 4. EQ Mode at 2.97 Gbps, Measured at OUT0±,

200-m Belden 1694A Before SDI_IO+

Figure 5. CD Mode at 2.97 Gbps, Measured at SDI_IO+,

20-in. FR4 Before IN0±

1.0

0

DE = 0

DE = 1

DE = 2

DE = 3

DE = 4

DE = 5

DE = 6

DE = 7

0.9

0.8

0.7

0.6

0.5

0.4

œ2

œ4

œ6

œ8

œ10

œ12

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

VOD Register Settings

C001

C002

Figure 6. OUT0 VOD vs. OUT0 VOD and DE

Register Settings

Figure 7. OUT0 De-Emphasis vs. OUT0 VOD and DE

Register Settings

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

SDI_IO+ (EQ Mode)

SDI_IO+ (CD Mode)

SDI_OUT+ (EQ or CD Mode)

SMPTE RL Specification Limit

0

0.5

1

1.5

Frequency (GHz)

2

2.5

3

C001

Measured with LMH1297EVM

Figure 8. Return Loss (RL) vs Frequency

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8 Detailed Description

8.1 Overview

The LMH0397 is a 3G-SDI 75-Ω bidirectional I/O with integrated reclocker. The LMH0397 allows system

designers the flexibility to use a single BNC either as an input or output port, simplifying HD video hardware

designs.

8.1.1 Equalizer Mode (EQ Mode)

SDI_IO+ is configured as a 75-Ω adaptive cable equalizer. The input signal then goes through a reclocker,

followed by a 100-Ω driver with de-emphasis at OUT0±. A second 75-Ω cable driver provides a reclocked loop-

through output of SDI_IO+ at SDI_OUT+. This second signal path from SDI_IO+ to SDI_OUT+ forms a SDI cable

loop-through.

8.1.2 Cable Driver Mode (CD Mode)

SDI_IO+ is configured as a 75-Ω cable driver with a reclocked signal sourced from IN0±. SDI_OUT+ serves as a

second 75-Ω cable driver to offer 1:2 fan-out buffering from IN0± to SDI_IO+ and SDI_OUT+. The 100-Ω driver

at OUT0± can be used as a host-side loopback output for monitoring purposes.

8.2 Functional Block Diagram

Cable

EQ

100-Ω

Driver

M

U

X

SDI_IO

OUT0

M

U

X

CDR

TX_RX

Cable

Driver

PCB

EQ

IN0

Cable

Driver

SDI_OUT

Control

Power

Management

Serial

Interface

LDO

Control Logic

Figure 9. LMH0397 Block Diagram Overview

NOTE

Only one I/O path can be active at a time. In EQ Mode, the cable equalizer at SDI_IO is

enabled, and the SDI_IO cable driver is powered down. In CD Mode, the cable driver at

SDI_IO is enabled, and the SDI_IO cable equalizer is powered down.

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8.3 Feature Description

The LMH0397 data path consists of several key blocks as shown in the functional block diagram. These key

blocks are:

•

4-Level Input Pins and Thresholds

Equalizer (EQ) and Cable Driver (CD) Mode Control

Input Carrier Detect

–6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)

Continuous Time Linear Equalizer (CTLE)

Clock and Data (CDR) Recovery

Internal Eye Opening Monitor (EOM)

Output Function Control

Output Driver Control

Status Indicators and Interrupts

8.3.1 4-Level Input Pins and Thresholds

The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is

an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the control pin that sets the default voltage at 2/3 ×

VIN. These resistors, together with the external resistor, combine to achieve the desired voltage level. By using

the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage levels for each of the four

input states are achieved as shown in Table 1.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTING

Tie 1 kΩ to VIN

NOMINAL PIN VOLTAGE

H

F

R

L

VIN

2/3 × VIN

1/3 × VIN

0

Float (leave pin open)

Tie 20 kΩ to VSS

Tie 1 kΩ to VSS

Typical 4-Level Input Thresholds:

•

Internal Threshold between L and R = 0.2 × VIN

Internal Threshold between R and F = 0.5 × VIN

Internal Threshold between F and H = 0.8 × VIN

8.3.2 Equalizer (EQ) and Cable Driver (CD) Mode Control

The input and output signal flow of the LMH0397 is determined by the EQ/CD_SEL, OUT0_SEL, and

SDI_OUT_SEL pins.

8.3.2.1 EQ/CD_SEL Control

The EQ/CD_SEL pin selects the I/O as either an input (EQ Mode) or an output (CD Mode). The logic level

applied to the EQ/CD_SEL pin automatically powers down the unused I/O direction. For example, if the

LMH0397 is in EQ Mode (EQ/CD_SEL = L), the SDI_IO cable driver is powered down as shown in Table 2.

Table 2. EQ/CD_SEL Pin Settings

EQ/CD_SEL

INPUT

MODE

NOTES

75-Ω video input to SDI_IO+.

L

SDI_IO+

EQ Mode OUT0± automatically enabled.

SDI_IO Cable Driver powered down.

100-Ω input to IN0±.

SDI_IO+ enabled as a cable driver output.

SDI_OUT programmable as a secondary cable driver output.

H

IN0±

CD Mode

SDI_IO Equalizer powered down.

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The EQ/CD_SEL pin should be strapped at power up for normal operation. After power up, the EQ/CD_SEL pin

state can be dynamically changed from EQ Mode to CD Mode and vice versa. When changing the EQ/CD_SEL

state after power up, the signal flow to the reclocker is momentarily disturbed, and the chip automatically initiates

a CDR reset to relock to the new input signal.

8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control

The OUT0_SEL and SDI_OUT_SEL pins work in conjunction with the EQ/CD_SEL pin to select the LMH0397

data-path routes. Table 3 shows all possible signal path combinations and typical use cases for each

configuration.

Table 3. LMH0397 Signal Path Combinations

LINE SIDE

HOST SIDE

EQ/CD_SEL

(MODE)

MAIN

OUTPUT

OUT0_SEL SDI_OUT_SEL

INPUT

LOOP-THRU LOOPBACK TYPICAL APPLICATION

OUTPUT

X

H

L

SDI_IO+

OUT0±

Adaptive cable equalizer

L

Adaptive cable equalizer with line-side loop-through

output

(EQ Mode)

SDI_OUT±

H

L

H

L

IN0±

SDI_IO±

Single cable driver

SDI_OUT±

Dual cable drivers

H

(CD Mode)

H

L

OUT0±

Single cable driver with host-side loopback enabled

Dual cable drivers with host-side loopback enabled

L

8.3.3 Input Carrier Detect

SDI_IO (in EQ Mode) and IN0 have a carrier detect circuit to monitor the presence or absence of an input signal.

When the input signal amplitude for the selected input exceeds the carrier detect assert threshold, the LMH0397

operates in normal operation mode.

In the absence of an input signal, the LMH0397 automatically goes into Power Save Mode to conserve power

dissipation. When a valid signal is detected, the LMH0397 automatically exits Power Save Mode and returns to

the normal operation mode. If the ENABLE pin is pulled low, the LMH0397 is forced into Power-Down Mode. In

Power Save Mode, both the carrier detect circuit and the serial interface remain active. In Power-Down Mode,

only the serial interface remains active.

Users can monitor the status of the carrier detect through register programming. This can be done either by

configuring the LOCK_N pin to output the CD_N status or by monitoring the carrier detect status register. See

Table 4 for more details.

Table 4. Input Carrier Detect Modes of Operation

ENABLE

EQ/CD_SEL

SIGNAL INPUT

OPERATING MODE

EQ Mode, normal operation

Carrier detector at SDI_IO+

Serial interface active

H

L

75-Ω video input at SDI_IO+

OUT0 automatically enabled, regardless of OUT0_SEL setting

Power Save Mode

H

L

H

X

No signal at SDI_IO+

100-Ω signal input at IN0±

No signal at IN0±

Carrier detector at SDI_IO+

Serial interface active

CD Mode, normal operation

Carrier detector at IN0±

Serial interface active

Power Save Mode

Carrier detector at IN0±

Serial interface active

Power-Down Mode

Forced device power down

Serial interface active

Input signal ignored

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8.3.4 –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)

When placed in EQ Mode, the LMH0397 equalizes data transmitted into SDI_IO through a coaxial cable driven

by a SMPTE compatible cable driver with launch amplitude of 800 mVp-p ± 10%. In applications where a 1:2

passive splitter is used, the signal amplitude is reduced by half due to the 6-dB insertion loss of the splitter. The

LMH0397 can support –6-dB splitter mode for the SDI_IO input through register control. For more information,

refer to the LMH0397 Programming Guide (SNLU225).

8.3.5 Continuous Time Linear Equalizer (CTLE)

The LMH0397 has two continuous time linear equalizer (CTLE) blocks, one for SDI_IO in EQ Mode and another

for IN0 in CD Mode. The CTLE compensates for frequency-dependent loss due to the transmission media before

the device input. The CTLE accomplishes this by applying variable gain to the input signal, thereby boosting

higher frequencies more than lower frequencies. The CTLE block extends the signal bandwidth, restores the

signal amplitude, and reduces ISI caused by the transmission medium.

8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ Mode)

If the LMH0397 is placed in EQ Mode (EQ/CD_SEL = L), adaptive cable equalization is enabled for SDI_IO.

While the LMH0397 is in EQ Mode, IN0 EQ is powered down.

SDI_IO has an on-chip 75-Ω termination to the input common-mode voltage and includes a series return loss

compensation network for meeting stringent SMPTE return loss requirements (see Figure 8). The adaptive cable

equalizer is designed for AC coupling, requiring a 4.7-μF, AC-coupling capacitor for minimizing base-line wander

due to the rare-occurring pathological bit pattern. The cable equalizer is designed with high gain and low noise

circuitry to compensate for the insertion loss of a coaxial cable, such as Belden 1694A, which is widely used in

broadcast video infrastructures.

Internal control loops are used to monitor the input signal quality and automatically select the optimal EQ boost

and DC offset compensation. The LMH0397 is designed to handle the stringent pathological patterns defined in

the SMPTE RP 198 and SMPTE RP 178 standards.

8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)

If the LMH0397 is placed in CD Mode (EQ/CD_SEL = H), PCB trace equalization is enabled for IN0. While the

LMH0397 is in CD Mode, SDI_IO EQ is powered down.

IN0 has an on-chip 100-Ω termination and is designed for AC coupling, requiring a 4.7-μF, AC-coupling capacitor

for minimizing base-line wander. The PCB equalizer can compensate board trace insertion losses of –17 dB at

data rates up to 2.97 Gbps. There are two adapt modes for IN0: AM0 manual mode and AM1 adaptive mode. In

AM0 manual mode, fixed EQ boost settings are applied through user-programmable control. In AM1 adaptive

mode, state machines automatically find the optimal EQ boost from a set of 16 predetermined settings defined in

Registers 0x40-0x4F.

In CD Mode, the HOST_EQ0 pin determines the IN0 adapt mode and EQ boost level. For normal operation,

HOST_EQ0 = F is recommended. HOST_EQ0 pin logic settings are shown in Table 5. These HOST_EQ0 pin

settings can be overridden by register control. For more information, refer to the LMH0397 Programming Guide

(SNLU225).

Table 5. HOST_EQ0 Pin EQ Settings in CD Mode (EQ/CD_SEL = H)

RECOMMENDED INSERTION

HOST_EQ0⁽¹⁾IN0± EQ BOOST⁽²⁾

LOSS

BEFORE IN0±⁽³⁾

H

F

All Rates: AM0 Manual Mode, EQ=0x00

< –4 dB

Normal Operation

3G Rate: AM1 Adaptive Mode

1.5G, 270M Rates: AM0 Manual Mode, EQ= 0x00

0 to –17 dB

R

L

All Rates: AM0 Manual Mode, EQ=0x80

All Rates: AM0 Manual Mode, EQ=0x90

–8 dB

–10 dB

(1) The HOST_EQ0 pin is also used to set OUT0 VOD and de-emphasis values. See Host-Side 100-Ω

Output Driver (OUT0± in EQ or CD Mode) for more information.

(2) When the LMH0397 is in EQ Mode, IN0 EQ settings are ignored, because IN0 EQ is powered down.

(3) Recommended insertion loss at 2.97 Gbps.

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8.3.6 Clock and Data (CDR) Recovery

After the input signal passes through the CTLE, the equalized data is fed into the clock and data recovery (CDR)

block. Using an internal PLL, the CDR locks to the incoming equalized data and recovers a clean internal clock

to re-sample the equalized data. The LMH0397 CDR is able to tolerate high input jitter, tracking low-frequency

input jitter below the PLL bandwidth while reducing high-frequency input jitter above the PLL bandwidth. The

supported data rates are listed in Table 6.

Table 6. Supported Data Rates

INPUT

DATA RATE

2.97 Gbps, 1.485 Gbps, 270 Mbps⁽¹⁾

125 Mbps

RECLOCKER

Enable

SDI_IO+ (EQ Mode),

IN0± (CD Mode)

Bypass

(1) The LMH0397 supports divide-by-1.001 lock rates for 2.97 Gbps, and 1.485 Gbps.

8.3.7 Internal Eye Opening Monitor (EOM)

The LMH0397 has an on-chip eye opening monitor (EOM) that can be used to analyze, monitor, and diagnose

the post-equalized waveform, just before the CDR reclocker. The EOM is operational for 2.97 Gbps and higher

data rates.

The EOM monitors the post-equalized waveform in a time window that spans one unit interval and a configurable

voltage range that spans up to ±400 mV. The time window and voltage range are divided into 64 steps, so the

result of the eye capture is a 64 × 64 matrix of hits, where each point represents a specific voltage and phase

offset relative to the main data sampler. The number of hits registered at each point must be taken in context

with the total number of bits observed at that voltage and phase offset to determine the corresponding probability

for that point.

The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of

ways. Two common ways to visualize this data are shown in Figure 10 and Figure 11. These diagrams depict

examples of eye monitor plots implemented by software. The first plot is an example using the EOM data to plot

a basic eye using ASCII characters, which can be useful for diagnostic software. The second plot shows the first

derivative of the EOM data, revealing the density of hits and the actual waveforms and crossings that comprise

the eye.

Figure 10. Internal Input Eye Monitor Plot

Figure 11. Internal Eye Monitor Hit Density Plot

A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye

opening (HEO) represents the width of the post-equalized eye at 0-V differential amplitude, measured in unit

intervals or picoseconds (ps). The vertical eye opening (VEO) represents the height of the post-equalized eye,

measured midway between the mean zero crossing of the eye. This position in time approximates the CDR

sampling phase. HEO and VEO measurements can be read back through register control.

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8.3.8 Output Function Control

The LMH0397 output function control for data routed to outputs SDI_IO (in CD Mode), SDI_OUT, and OUT0 is

configured by the OUT_CTRL pin. The OUT_CTRL pin determines whether to bypass the input equalizer,

reclocker, or both. In normal operation (OUT_CTRL = F), both input equalizer and reclocker are enabled.

OUT_CTRL pin logic settings are shown in Table 7. These settings can be overridden through register control by

applying the appropriate override bit values. For more information, refer to the LMH0397 Programming Guide

(SNLU225).

Table 7. OUT_CTRL Settings for Bypass Modes

EQ/CD_SEL

(MODE)

SDI_IO+ CABLE

EQUALIZER

IN0± PCB

EQUALIZER

OUT_CTRL

RECLOCKER SUMMARY

Input SDI_IO cable equalizer bypassed

Reclocker enabled

H

Bypass

N/A

Enable

Normal operation

Input SDI_IO cable equalizer enabled

Reclocker enabled

F

Enable

N/A

L

(EQ Mode)

Input SDI_IO cable equalizer bypassed

Reclocker bypassed

R

L

Bypass

Enable

N/A

Bypass

Input SDI_IO cable equalizer enabled

Reclocker bypassed

Normal operation

H, F

R, L

N/A

Enable

Bypass

Input IN0 equalizer enabled

Reclocker enabled

H

(CD Mode)

Input IN0 equalizer enabled in AM0 manual mode.

IN0 EQ settings configurable by HOST_EQ0 pin.

Reclocker bypassed

8.3.9 Output Driver Control

8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD Mode, SDI_OUT+ in EQ or CD Mode)

The LMH0397 has two output cable driver (CD) blocks, one for SDI_IO in CD Mode and another for SDI_OUT.

These SDI outputs are designed to drive 75-Ω single-ended coaxial cables at data rates up to 2.97 Gbps. Both

SDI_IO and SDI_OUT feature an integrated 75-Ω termination and return loss compensation network for meeting

stringent SMPTE return loss requirements (see Figure 8). The cable drivers are designed for AC coupling,

requiring a 4.7-μF, AC-coupling capacitor for minimizing base-line wander due to the rare-occurring pathological

bit pattern.

8.3.9.1.1 Output Amplitude (VOD)

In CD Mode (EQ/CD_SEL = H), SDI_IO is enabled as an SDI cable driver output. In either CD or EQ Mode,

SDI_OUT is an SDI cable driver output. In EQ Mode, SDI_OUT serves as a loop-through output, and in CD

Mode, SDI_OUT serves as a secondary cable driver output.

SDI_IO (in CD Mode) and SDI_OUT are designed for transmission across 75-Ω single-ended impedance. The

nominal SDI cable driver output amplitude (VOD) is 800 mVp-p single-ended. In the presence of long output

cable lengths or crosstalk, the SDI_VOD pin can be used to optimize the cable driver output with respect to the

nominal amplitude. Table 8 details VOD settings that can be applied to both SDI_IO and SDI_OUT. The

SDI_VOD pin can be overridden through register control. In addition, the nominal VOD amplitude can be

changed by register control. For more information, refer to the LMH0397 Programming Guide (SNLU225).

Table 8. SDI_VOD Settings for Line-Side Output Amplitude

SDI_VOD

DESCRIPTION

H

F

R

L

about +5% of nominal

800 mVp-p (nominal)

about +10% of nominal

about –5% of nominal

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8.3.9.1.2 Output Pre-Emphasis

In addition to SDI cable driver VOD control, the LMH0397 can add pre-emphasis on the cable driver output to

improve output signal integrity when the reclocker recovers an HD (3G, 1.5G) input data rate. By default, the

LMH0397 in CD Mode automatically disables pre-emphasis at SDI_IO for all data rates. When enabled, the

amount of pre-emphasis applied to the cable driver outputs is determined by register control. If the reclocker is

bypassed or if the user desires to disable automatic pre-emphasis, pre-emphasis can be enabled manually

through register control. For more information, refer to the LMH0397 Programming Guide (SNLU225).

8.3.9.1.3 Output Slew Rate

SMPTE specifications require different output driver rise and fall times depending on the operating data rate. To

meet these requirements, the output edge rate of SDI_IO and SDI_OUT is automatically programmed according

to the signal recovered by the reclocker. Typical edge rates at the cable driver output are shown in Table 9.

Table 9. SDI_IO and SDI_OUT Output Edge Rate

CABLE DRIVER OUTPUT

DETECTED DATA RATE

EDGE RATE (TYPICAL)

2.97 Gbps

1.485 Gbps

270 Mbps

59 ps

60 ps

550 ps

If the reclocker is bypassed, users must program the desired edge rate manually through register control. For

more information, refer to the LMH0397 Programming Guide (SNLU225).

8.3.9.1.4 Output Polarity Inversion

Polarity inversion is supported on both SDI_IO and SDI_OUT outputs through register control.

8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD Mode)

OUT0 is a 100-Ω driver output. In EQ Mode, OUT0 serves as a host-side output from the SDI_IO cable

equalizer. In CD Mode, OUT0 serves as a host-side loopback output. OUT0 also supports polarity inversion.

NOTE

In EQ Mode, OUT0 is enabled by default, regardless of the logic applied to the

OUT0_SEL pin.

The driver offers users the capability to select higher output amplitude and de-emphasis levels for longer board

trace that connects the drivers to their downstream receivers. Driver de-emphasis provides transmitter

equalization to reduce the ISI caused by the board trace.

In EQ Mode, the HOST_EQ0 pin determines the output amplitude (VOD) and de-emphasis levels applied to the

OUT0 PCB driver. In CD Mode, the VOD and de-emphasis levels for OUT0 are set by default to 570 mVp-p and

–0.4 dB. These settings can be changed through register control if desired.

Table 10 details the OUT0 VOD and de-emphasis settings that can be applied. The HOST_EQ0 pin settings can

be overridden by register control. When these parameters are controlled by registers, the VOD and de-emphasis

levels can be programmed independently. For more information, refer to the LMH0397 Programming Guide

(SNLU225).

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Table 10. HOST_EQ0 Pin VOD and DEM Settings

EQ/CD_SEL

(MODE)

OUT0± VOD

(mVp-p)

OUT0± DEM

(dB)

HOST_EQ⁽¹⁾

H

F

R

L

400

570

660

830

0

–0.4

–2.1

–4.4

L

(EQ Mode)

H

X

570

–0.4

(CD Mode)

(1) The HOST_EQ0 pin is also used to set the IN0 EQ values when the LMH0397 is in CD Mode. See

Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode) for more information.

8.3.10 Status Indicators and Interrupts

The LOCK_N pin is a 3.3-V tolerant, active-low, open-drain output. An external resistor to the logic supply is

required. The LOCK_N pin can be configured to indicate reclocker lock, input carrier detect, or an interrupt event.

8.3.10.1 LOCK_N (Lock Indicator)

By default, LOCK_N is the reclocker lock indicator, and this pin asserts low when the LMH0397 achieves lock to

a valid SMPTE data rate. The LOCK_N pin functionality can also be configured through register control to

indicate CD_N (carrier detect) or INT_N (interrupt) events. For more information about how to reconfigure the

LOCK_N pin functionality, refer to the LMH0397 Programming Guide (SNLU225).

8.3.10.2 CD_N (Carrier Detect)

The LOCK_N pin can be reconfigured through register control to indicate a CD_N (carrier detect) event. When

configured as a CD_N output, the pin asserts low at the end of adaptation after a valid signal is detected by the

carrier detect circuit of the selected input. Under register control, this pin can be reconfigured to indicate CD_N

for SDI_IO (in EQ Mode) or IN0 (in CD Mode). For more information about how to configure the LOCK_N pin for

CD_N functionality, refer to the LMH0397 Programming Guide (SNLU225).

8.3.10.3 INT_N (Interrupt)

The LOCK_N pin can be configured to indicate an INT_N (interrupt) event. When configured as an INT_N output,

the pin asserts low when an interrupt occurs, according to the programmed interrupt masks. Seven separate

masks can be programmed through register control as interrupt sources:

•

If there is a loss of signal (LOS) event on SDI_IO in EQ Mode (2 separate masks).

If there is a loss of signal (LOS) event on IN0 in CD Mode (2 separate masks).

If HEO or VEO falls below a certain threshold after CDR is locked (1 mask).

If a CDR Lock event has occurred (2 separate masks).

INT_N is a sticky bit, meaning that it will flag after an interrupt occurs and will not clear until read-back. Once the

Interrupt Status Register is read, the INT_N pin will assert high again. For more information about how to

configure the LOCK_N pin for INT_N functionality, refer to the LMH0397 Programming Guide (SNLU225).

8.3.11 Additional Programmability

The LMH0397 supports extended programmability through SPI or SMBus serial control interface. Such added

programmability includes:

•

Cable EQ Index (CEI)

Digital MUTE_REF

8.3.11.1 Cable EQ Index (CEI)

The Cable EQ Index (CEI) indicates the cable EQ boost index used at SDI_IO+ in EQ Mode. CEI is accessible

through ConfigIO Page Reg 0x25[5:0]. The 6-bit setting ranges in decimal value from 0 to 55 (000000'b to

110111'b in binary), with higher values corresponding to larger gain applied at the SDI_IO+ input.

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8.3.11.2 Digital MUTE_REF

Digital MUTE_REFConfigIO Page Reg 0x03[5:0] sets the threshold for the maximum cable length at SDI_IO+ to be

equalized before muting the outputs. The MUTE_REFregister value is directly proportional to the cable length

being equalized. MUTE_REFis data rate dependent. Perform the steps that follow to set the MUTE_REFregister

setting for any desired SDI rate:

1. Connect the desired input cable length at which the driver output must be muted.

2. Send video patterns to SDI_IO+ at the SD rate (270 Mbps). At SD, the Cable EQ Index (CEI) has the largest

dynamic range.

3. Read back ConfigIO Page Reg 0x25[5:0] to record the CEI value.

4. Copy the CEI value, and write this value to Digital MUTE_REFConfigIO Page Reg 0x03[5:0].

8.4 Device Functional Modes

The LMH0397 operates in one of two modes: System Management Bus (SMBus) or Serial Peripheral Interface

(SPI) mode. To determine the mode of operation, the proper setting must be applied to the MODE_SEL pin at

power up, as detailed in Table 11.

Table 11. MODE_SEL Pin Settings

LEVEL

DESCRIPTION

H

F

R

L

Reserved for factory testing – do not use

Selects SPI Interface for register access

Reserved for factory testing – do not use

Selects SMBus Interface for register access

8.4.1 System Management Bus (SMBus) Mode

The SMBus interface can also be used to control the device. If MODE_SEL = Low (1 kΩ to VSS), Pins 13 and 29

are configured as SDA and SCL. Pins 11 and 28 are address straps ADDR0 and ADDR1 during power up. The

maximum operating speed supported on the SMBUS pins is 400 kHz. See Table 12 for more information.

Table 12. SMBus Device Slave Addresses⁽¹⁾

ADDR0

ADDR1

7-BIT SLAVE

8-BIT WRITE

(LEVEL)

ADDRESS [HEX]

COMMAND [HEX]

L

R

F

H

L

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

5A

5C

5E

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

L

R

F

H

R

F

H

L

R

F

H

L

R

F

H

(1) The 8-bit write command consists of the 7-bit slave address (Bits 7:1) with 0 appended to the LSB to

indicate an SMBus write. For example, if the 7-bit slave address is 0x2D (010 1101'b), the 8-bit write

command is 0x5A (0101 1010'b).

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8.4.1.1 SMBus Read and Write Transaction

SMBus is a 2-wire serial interface through which various system component chips can communicate with the

master. Slave devices are identified by having a unique device address. The 2-wire serial interface consists of

SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a

bidirectional data signal between the master and slave devices. The LMH0397 SMBus SCL and SDA signals are

open-drain and require external pullup resistors.

Start and Stop:

The master generates Start and Stop patterns at the beginning and end of each transaction, as shown in

Figure 12.

•

Start: High-to-low transition (falling edge) of SDA while SCL is high.

SDA

SCL

S

P

Start

Condition

Stop

Condition

Figure 12. Start and Stop Conditions

The master generates nine clock pulses for each byte transfer as shown in Figure 13. The 9th clock pulse

constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is

recorded when the device pulls SDA low, while a NACK is recorded if the line remains high.

ACK Signal

from Receiver

SDA

MSB

SCL

1

2

3 - 6

7

8

9

1

2

3 - 8

9

S

P

ACK

Start

Condition

Stop

Condition

Byte Complete

Interrupt Within

Receiver

Clock Line Held Low

by Receiver While

Interrupt Serviced

Figure 13. Acknowledge (ACK)

8.4.1.1.1 SMBus Write Operation Format

Writing data to a slave device consists of three parts, as shown in Figure 14:

1. The master begins with a start condition followed by the slave device address with the R/W bit set to 0’b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the 8-bit data is written, followed by a stop condition.

Device

Address

Word Address

Data

SDA

Line

Figure 14. SMBus Write Operation

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8.4.1.1.2 SMBus Read Operation Format

SMBus read operation consists of four parts, as shown in Figure 15:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the master initiates a restart condition, followed by the slave address

with the R/W bit set to 1'b.

4. After an ACK from the slave device, the 8-bit data is read-back. The last ACK is high if there are no more

bytes to read, and the last read is followed by a stop condition.

Device

Address

Device

Address

Word Address (n)

Data (n)

SDA

Line

Set word address in the device

that will be read following restart

and repeat of device address

Figure 15. SMBus Read Operation

8.4.2 Serial Peripheral Interface (SPI) Mode

If MODE_SEL = F or H, the LMH0397 is in SPI mode. In SPI mode, the following pins are used for SPI bus

communication:

•

MOSI (pin 13): Master Output Slave Input

MISO (pin 28): Master Input Slave Output

SS_N (pin 11): Slave Select (Active Low)

SCK (pin 29): Serial Clock (Input to the LMH0397 Slave Device)

8.4.2.1 SPI Read and Write Transactions

Each SPI transaction to a single device is 17 bits long and is framed by SS_N when asserted low. The MOSI

input is ignored, and the MISO output is floated whenever SS_N is deasserted (high).

The bits are shifted in left-to-right. The first bit is R/W, which is 1'b for read and 0'b for write. Bits A7-A0 are the

8-bit register address, and bits D7-D0 are the 8-bit read or write data. The previous SPI command, address, and

data are shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI

transactions, the MISO output signal is enabled asynchronously when SS_N asserts low. The contents of a

single MOSI or MISO transaction frame are shown in Figure 16.

Figure 16. 17-Bit Single SPI Transaction Frame

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

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8.4.2.2 SPI Write Transaction Format

For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.

The signal timing for a SPI Write transaction is shown in Figure 2. The prime values on MISO (for example, A7')

reflect the contents of the shift register from the previous SPI transaction and are don’t-care for the current

transaction.

t_SSOF

t_SSH

SS_N

SCK

t_PL

t_SSSU

t_PH

t_H

t_SU

HiZ

MOSI

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

t_ODZ

HiZ

MISO

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 17. Signal Timing for a SPI Write Transaction

8.4.2.3 SPI Read Transaction Format

A SPI read transaction is 34 bits per device and consists of two 17-bit frames. The first 17-bit read transaction

frame shifts in the address to be read, followed by a dummy transaction second frame to shift out 17-bit read

data. The R/W bit is 1'b for the read transaction, as shown in Figure 3.

The first 17 bits from the read transaction specifies 1 bit of R/W and 8 bits of address A7-A0 in the first 8 bits.

The eight 1s following the address are ignored. The second dummy transaction acts like a read operation on

address 0xFF and must be ignored. However, the transaction is necessary to shift out the read data D7-D0 in the

last 8 bits of the MISO output. As with the SPI Write, the prime values on MISO during the first 16 clocks are

listed as don’t care for this portion of the transaction. The values shifted out on MISO during the last 17 clocks

reflect the read address and 8-bit read data for the current transaction.

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 18. Signal Timing for a SPI Read Transaction

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8.4.2.4 SPI Daisy Chain

The LMH0397 supports SPI daisy-chaining among multiple devices, as shown in Figure 19.

MISO

Device 1

Device 2

Device 3

Device N

LMH0397

MOSI MISO

Host

LMH0397

. . .

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

SS

Figure 19. Daisy-Chain Configuration

Each LMH0397 device is directly connected to the SCK and SS_N pins of the host. The first LMH0397 device in

the chain is connected to the MOSI pin of the host, and the last device in the chain is connected to the MISO pin

of the host. The MOSI pin of each intermediate LMH0397 device in the chain is connected to the MISO pin of the

previous LMH0397 device, thereby creating a serial shift register. In a daisy-chain configuration of N × LMH0397

devices, the host conceptually sees a shift register of length 17 × N for a basic SPI transaction, during which

SS_N is asserted low for 17 × N clock cycles.

8.5 Register Maps

The LMH0397 register map is divided into three register pages. These register pages are used to control

different aspects of the LMH0397 functionality. A brief summary of the pages follows:

1. Share Register Page: This page corresponds to global parameters, such as LMH0397 device ID, I/O

direction override, and LOCK_N status configuration. This is the default page at start-up. Access this page by

setting Reg 0xFF[2:0] = 000’b.

2. CTLE/CDR Register Page: This page corresponds to IN0 PCB CTLE, input and output mux settings, CDR

settings, and output interrupt overrides. Access this page by setting Reg 0xFF[2:0] = 100’b.

3. ConfigIO Register Page: This page corresponds to SDI_IO Cable Equalizer settings. This page also

controls the OUT0, SDI_IO, and SDI_OUT driver output settings. Access this page by setting Reg 0xFF[2:0]

= 101’b.

For the complete register map, typical device configurations, and proper register reset sequencing, refer to the

LMH0397 Programming Guide (SNLU225).

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 SMPTE Requirements and Specifications

SMPTE specifies several key requirements for the Serial Digital Interface to transport digital video over coaxial

cables. Such requirements include return loss, AC coupling, and data rate dependency with rise and fall times.

1. Return Loss: This specification details how closely the port resembles 75-Ω impedance across a specified

frequency band. The LMH0397 features a built-in 75-Ω return-loss network on SDI_IO and SDI_OUT to

minimize parasitics and improve overall signal integrity.

2. AC Coupling: AC-coupling capacitors are required for transporting uncompressed serial data streams with

heavy low-frequency content. The use of 4.7-μF, AC-coupling capacitors is recommended to avoid low-

frequency DC wander.

3. Rise/Fall Time: Output 75-Ω signals are required to meet certain rise and fall timing depending on the data

rate. This improves the eye opening observed for the receiving device. The LMH0397 SDI_IO (in CD Mode)

and SDI_OUT cable drivers feature automatic edge rate adjustment to meet SMPTE rise and fall time

requirements.

TI recommends placing the LMH0397 as close as possible to the 75-Ω BNC ports to meet SMPTE specifications.

9.1.2 Low-Power Optimization in CD Mode

In CD Mode, the LMH0397 IN0 CTLE operates in either AM1 Adaptive Mode or AM0 Manual Mode. When

operating in AM1, the LMH0397 uses HEO/VEO Lock Monitoring as a key parameter to achieve lock. HEO/VEO

Lock Monitoring determines the CTLE boost setting that produces the best horizontal and vertical eye opening

after the CTLE. When AM1 adaptation is complete and the LMH0397 asserts CDR lock at the optimal IN0 CTLE

setting, HEO/VEO Lock Monitoring is no longer required to maintain lock. Therefore, HEO/VEO Lock Monitoring

can be disabled by setting CTLE/CDR Reg 0x3E[7] = 0'b after lock is declared. Disabling HEO/VEO Lock

Monitoring optimizes power dissipation in CD Mode, reducing the overall power by approximately 25 mW.

When operating in AM0, the LMH0397 does not use HEO/VEO Lock Monitoring, because the user manually sets

the IN0 CTLE setting. In AM0, HEO/VEO Lock Monitoring can be disabled at any time.

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9.2 Typical Applications

The LMH0397 is a bidirectional I/O with integrated reclocker that supports SDI data rates up to 2.97 Gbps. This

device supports multiple configurations and can be programmed as a cable equalizer or cable driver. Figure 20

shows a typical application circuit for the LMH0397.

Specific examples of typical applications for the LMH0397 as a bidirectional I/O and cable equalizer with loop-

through are detailed in the following subsections.

2.5 V

Place 0.1-µF Capacitors

close to each supply pin

4.7 µF

100-ꢀ Coupled Trace

VDD_CDR

VIN

VDD_LDO

(1.8 V) OUT0+

Line-Side I/O

SDI_IO+

SDI_IO-

RX+

RX-

75-ꢀ BNC

OUT0-

4.7 µF

SS_N

75 Ω

RSV1

RSV2

RSV3

RSV4

RSV5

SCK

Host-Side FPGA/

Video Processor

MOSI

VIN

MISO

LMH0397

EP

VSS

200 Ω

MODE_SEL

LOCK_N

Level F (SPI Mode)

LED

100-ꢀ Coupled Trace

Line-Side Output

SDI_OUT+

SDI_OUT-

TX+

TX-

IN0+

IN0-

75-ꢀ BNC

4.7 µF

75 Ω

VIN

Optional pullup or pulldown

resistors for 4-Level Strap

Configuration Pins

Optional pullup or pulldown

resistors for 2-Level Strap

Configuration Pins

1 kꢀ

Level H = 1 kΩ to VIN

Level F = No Connect

Level R = 20 kΩ to VSS

Level L = 1 kΩ to VSS

Level H = 1 kΩ to VIN

Level L = 1 kΩ to VSS

1 kꢀ

or

1 kꢀ

or

1 kꢀ

or

1 kꢀ

20 kꢀ

*Internally pulled high

**Internally pulled low

20 kꢀ

Figure 20. LMH0397 Typical Application Circuit

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Typical Applications (continued)

9.2.1 Bidirectional I/O

The LMH0397 can be configured as a bidirectional I/O to improve BNC port function flexibility. In EQ Mode, the

LMH0397 equalizes 75-Ω SDI input data at SDI_IO and outputs from OUT0 to an FPGA Rx. SDI_OUT is used

as an optional loop-through SDI output. In CD Mode, the LMH0397 equalizes 100-Ω SDI input data at IN0 and

uses the dual cable drivers at SDI_IO and SDI_OUT to drive out the SDI signal. OUT0 can be used as a

loopback output for system monitoring.

Figure 21 shows a typical application where an LMH0397 is used alongside an SDI FPGA to enable bidirectional

I/O port functionality.

IN0

SDI_IO

75-Ω SDI Input or

Output

LMH0397

Rx: EQ

Mode

SerDes Tx

SDI FPGA

OUT0

SDI_OUT

Tx: CD

Mode

75-Ω SDI Output

SerDes Rx

Figure 21. LMH0397 Bidirectional I/O Application

9.2.1.1 Design Requirements

For general LMH0397 design requirements, see the guidelines in Table 13.

For bidirectional I/O application-specific requirements, see the guidelines in Table 14.

Table 13. LMH0397 General Design Requirements

DESIGN PARAMETER

SDI_IO+, SDI_OUT+ AC-coupling capacitors

SDI_IO–, SDI_OUT– AC-coupling capacitors

IN0± and OUT0± AC-coupling capacitors

Input and output terminations

REQUIREMENTS

4.7-μF capacitors recommended

4.7-μF capacitors recommended, AC terminated with 75 Ω to VSS.

4.7-μF capacitors recommended

Input and output terminations provided internally. Do not add external terminations.

10-μF and 1-μF bulk capacitors; place close to each device.

0.1-μF capacitor; place close to each supply pin.

DC power supply decoupling capacitors

VDD_LDO decoupling capacitors

MODE_SEL pin

1-μF and 0.1-μF capacitors; place as close as possible to the device VDD_LDO pin.

SPI: Leave MODE_SEL unconnected (Level F)

SMBus: Connect 1 kΩ to VSS (Level L)

Input reclocked data rate (SDI_IO in EQ Mode or

IN0 in CD Mode)

2.97 Gbps, 1.485 Gbps, or divide-by-1.001 subrates and 270 Mbps.

For all other input data rates, the reclocker is automatically bypassed.

Table 14. LMH0397 Bidirectional I/O Requirements

DESIGN PARAMETER

EQ/CD_SEL pin

REQUIREMENTS

1 kΩ to VSS (Level L) when SDI_IO is used as a cable EQ input

1 kΩ to VIN (Level H) when SDI_IO is used as a cable driver output

1 kΩ to VSS (Level L) to enable OUT0 for monitoring purposes

1 kΩ to VIN (Level H) to disable OUT0 (available only in CD Mode)

OUT0_SEL pin

1 kΩ to VSS (Level L) to enable cable loop-through (EQ Mode) or secondary cable

output (CD Mode)

1 kΩ to VIN (Level H) to disable cable loop-through (EQ Mode) or secondary cable

output (CD Mode)

SDI_OUT_SEL pin

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9.2.1.2 Detailed Design Procedure

Follow this design procedure for bidirectional I/O applications:

1. Select a power supply that meets the DC and AC requirements in Recommended Operating Conditions.

2. Choose a small 0402 surface-mount ceramic capacitor for AC-coupling capacitors to maintain characteristic

impedance.

3. Choose a high-quality, 75-Ω BNC connector that can support 2.97-Gbps applications. Consult a BNC

supplier regarding insertion loss, impedance specifications, and recommended footprint for meeting SMPTE

return loss.

4. Follow detailed high-speed layout recommendations provided in Layout Guidelines to ensure optimal signal

quality when interconnecting 75-Ω and 100-Ω signals to the LMH0397.

5. Determine whether SPI or SMBus communication is necessary. If the LMH0397 must be programmed with

settings other than what is offered by pin control, users must use SPI or SMBus Mode for additional

programming.

6. Configure EQ/CD_SEL, OUT0_SEL, and SDI_OUT_SEL pins according to the desired default use case. In a

bidirectional I/O application, the EQ/CD_SEL pin or register settings may be modified to switch between EQ

Mode and CD Mode.

7. Configure the LMH0397 in EQ Mode. Tune the HOST_EQ0 100-Ω driver control pin to equalize the PCB

output trace following OUT0±. Use register control for more tuning options if necessary.

8. Configure the LMH0397 in CD Mode. Tune the SDI_VOD output amplitude control pin for optimal signal

quality depending on the cable length attached at SDI_IO+ and SDI_OUT+. Use register control for more

tuning options if necessary.

9.2.1.3 Application Curves

Depending on operation in EQ or CD Mode, the LMH0397 performance was measured with the test setups

shown in Figure 22 and Figure 23.

CC

75-Q /}ꢀÆ /ꢀꢁoꢂ

LMH0397

Pattern

Generator

SDI_IO+

OUT0

Oscilloscope

V_O= 800 mVp-p,

PRBS10

Figure 22. Test Setup for LMH0397 in EQ Mode

LMH0397

SDI_IO+

Pattern

Generator

TL

Differential 100-Ω

FR4 Channel

IN0

Oscilloscope

V_OD= 800 mVp-p,

PRBS10

Figure 23. Test Setup for LMH0397 in CD Mode

The eye diagrams in this subsection show how the LMH0397 improves overall signal integrity in the data path for

75-Ω coax at SDI_IO+ when operating in EQ Mode and 100-Ω differential FR4 PCB trace at IN0± when operating

in CD Mode.

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EQ Mode, measured at OUT0±

CD Mode, measured at SDI_IO+

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 24. 2.97 Gbps, CC = 200-m Belden 1694A,

Reclocked

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 25. 2.97 Gbps, TL = 20" FR4, Reclocked

EQ Mode, measured at OUT0±

CD Mode, measured at SDI_IO+

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 26. 1.485 Gbps, CC = 300-m Belden 1694A,

Reclocked

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 27. 1.485 Gbps, TL = 20" FR4, Reclocked

EQ Mode, measured at OUT0±

CD Mode, measured at SDI_IO+

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 28. 270 Mbps, CC = 600-m Belden 1694A,

Reclocked

HOST_EQ0 = F, SDI_OUT_SEL = H, OUT_CTRL = F

Figure 29. 270 Mbps, TL = 20" FR4, Reclocked

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9.2.2 Cable Equalizer With Loop-Through

The LMH0397 can be configured as a cable equalizer with loop-through output. In EQ Mode, the LMH0397 takes

in SDI data at the SDI_IO adaptive cable equalizer input and outputs the reclocked SDI signal at OUT0.

Meanwhile, a redundant reclocked loop-through SDI signal is output on SDI_OUT for system monitoring

purposes.

Figure 30 shows a typical application of an LMH0397 as a cable loop-through device. In this example, the

LMH0397 provides an SDI input to the SDI FPGA. Concurrently, the equalized and reclocked SDI_IO signal is

sent to the loop-through SDI_OUT cable driver output. Meanwhile, the FPGA sends post-processed SDI data out

on an LMH1218 cable driver with integrated reclocker.

SDI_IO

75-Ω SDI

Input

OUT0

LMH0397

Config IO

EQ Mode

SerDes Rx

SDI FPGA

SDI_OUT

OUT0

75-Ω SDI

Loop-Thru

IN0

75-Ω SDI

Output

SerDes Tx

LMH0318

CD +

Reclocker

Figure 30. LMH0397 Cable Loop-Through Application

9.2.2.1 Design Requirements

See Table 13 in Bidirectional I/O Design Requirements for general LMH0397 design requirements.

For cable equalizer with loop-through application-specific requirements, see the guidelines in Table 15.

Table 15. LMH0397 Cable Loop-Through Requirements

DESIGN PARAMETER

EQ/CD_SEL pin

REQUIREMENTS

1 kΩ to VSS (Level L) to enable SDI_IO as a cable EQ input

1 kΩ to VSS (Level L) to enable OUT0 as PCB output to the FPGA

1 kΩ to VSS (Level L) to enable SDI_OUT as a loop-through output

OUT0_SEL pin

SDI_OUT_SEL pin

9.2.2.2 Detailed Design Procedure

See Bidirectional I/O Detailed Design Procedure and follow Steps 1 through 5. See the steps that follow for cable

equalizer with loop-through applications.

1. Configure EQ/CD_SEL and SDI_OUT_SEL pins according to the desired default use case. In a cable loop-

through application, the EQ/CD_SEL pin must be set to Level L so that the LMH0397 operates in EQ Mode.

Also, OUT0 in EQ Mode is always enabled regardless of the logic applied to OUT0_SEL.

2. Tune the HOST_EQ0 100-Ω driver control pin to equalize the PCB output trace following OUT0±. Use

register control for more tuning options if necessary.

9.2.2.3 Application Curves

In EQ Mode, the LMH0397 SDI_OUT performance was measured with the test setup shown in Figure 31.

CC

75-Ω Coax

Cable

LMH0397

SDI_OUT+

Pattern

Generator

SDI_IO+

Oscilloscope

V_O= 800 mVp-p,

PRBS10

Figure 31. Test Setup for LMH0397 Loop-Through in EQ Mode

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The eye diagrams in this subsection show the LMH0397 75-Ω loop-through output at SDI_OUT+.

EQ Mode, measured at SDI_OUT+

HOST_EQ0 = F, SDI_OUT_SEL = L, OUT_CTRL = F

Figure 32. 2.97 Gbps, CC = 200-m Belden 1694A,

Reclocked

EQ Mode, measured at SDI_OUT+

HOST_EQ0 = F, SDI_OUT_SEL = L, OUT_CTRL = F

Figure 33. 1.485 Gbps, CC = 280-m Belden 1694A,

Reclocked

EQ Mode, measured at SDI_OUT+

HOST_EQ0 = F, SDI_OUT_SEL = L, OUT_CTRL = F

Figure 34. 270 Mbps, CC = 600-m Belden 1694A, Reclocked

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10 Power Supply Recommendations

The LMH0397 requires decoupling capacitors to ensure a stable power supply. For power supply decoupling,

0.1-μF surface-mount ceramic capacitors must be placed close to each VDD_CDR, VDD_LDO, and VIN supply

pin to VSS. Larger bulk capacitors (for example, 10 μF and 1 μF) are recommended for VDD_CDR and VIN.

2.5 V

10 µF

1 µF

0.1 µF

VDD_CDR

VIN

EP

VDD_LDO

(1.8 V)

VSS

LMH0397

1 µF

0.1 µF

Figure 35. Recommended Power Supply Decoupling

Good supply bypassing requires low inductance capacitors. This can be achieved through an array of multiple

small body size surface-mount bypass capacitors to keep low supply impedance. Better results can be achieved

through the use of a buried capacitor formed by a VDD and VSS plane separated by 2-mil to 4-mil dielectric in a

printed-circuit board.

11 Layout

11.1 Layout Guidelines

The following guidelines are recommended to optimize the board layout for the LMH0397.

11.1.1 Board Stack-Up and Ground References

•

Choose a suitable board stack-up that supports 75-Ω single-ended trace and 100-Ω differential trace routing

on the top layer of the board. This is typically done with a Layer-2 ground plane reference for the 100-Ω

differential traces and a Layer-3 ground plane reference for the 75-Ω single-end traces.

•

Maintain a distance of at least five times the trace width between signal trace and ground reference if they are

on the same layer. This prevents unwanted changes in the characteristic impedance.

Maintain a consistent ground plane reference for each high-speed trace from source to endpoint. Ground

reference discontinuities lead to characteristic impedance mismatch.

11.1.2 High-Speed PCB Trace Routing and Coupling

Observe the following general high-speed recommendations for high-speed trace routing:

•

For differential pairs, maintain a uniform width and gap for each differential pair where possible. When traces

must diverge (for example, due to AC-coupling capacitors), ensure that the traces branch out or merge

uniformly.

•

To prevent reflections due to trace routing, ensure that trace bends are at most 45°. Right-angle bends must

be implemented with at least two 45° corners. Radial bends are ideal.

Avoid using signal vias. If signal vias must be used, a return path (GND) via must be placed near the signal

via to provide a consistent ground reference and minimize impedance discontinuities.

Avoid via stubs by back-drilling as necessary.

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Layout Guidelines (continued)

11.1.2.1 SDI_IO± and SDI_OUT±

•

Use an uncoupled trace with 75-Ω single-ended impedance for signal routing to SDI_IO± and SDI_OUT±.

The trace width is typically 8 to 10 mils with reference to a Layer-3 ground plane.

11.1.2.2 IN0± and OUT0±

•

Use coupled traces with 100-Ω differential impedance for signal routing to IN0± and OUT0±.

The trace width is typically 5 to 8 mils with reference to a Layer-2 ground plane.

11.1.3 Anti-Pads

•

Place anti-pads (ground relief) on the power and ground planes directly under the 4.7-μF, AC-coupling

capacitor and IC landing pads to minimize parasitic capacitance. The size of the anti-pad and the number of

layers to use the anti-pad depend on the board stack-up and can be determined by a 3-dimension

electromagnetic simulation tool.

11.1.4 BNC Connector Layout and Routing

•

Use a well-designed BNC footprint to ensure the signal landing pad achieves 75-Ω characteristic impedance.

BNC suppliers usually provide recommendations on BNC footprint for best results.

•

Keep trace length short between the BNC and SDI_IO±. The trace routing for SDI_IO+ and SDI_IO– must be

as symmetrical as possible, with approximately equal lengths and equal loading. The same is true for

SDI_OUT+ and SDI_OUT–.

11.1.5 Power Supply and Ground Connections

•

Connect each supply pin (VDD_CDR, VIN, VDD_LDO) directly to the power or ground planes with a short via.

The via is usually placed tangent to the landing pads of the supply pins with the shortest trace possible.

•

Power supply decoupling capacitors must be a small physical size (0402 or smaller) and placed close to the

supply pins to minimize inductance. The capacitors are commonly placed on the bottom layer and share the

ground of the EP (Exposed Pad).

11.1.6 Footprint Recommendations

•

Stencil parameters for the EP (Exposed Pad) such as aperture area ratio and the fabrication process have a

significant impact on paste deposition. TI highly recommends inspecting the stencil before setting the

placement of the WQFN package to improve board assembly yields. If the via and aperture openings are not

carefully monitored, the solder may flow unevenly through the EP. Stencil parameters for aperture opening

and via locations are shown in the RTV package drawing in 机械、封装和可订购信息.

•

The EP of the package must be connected to the ground plane through a 3 × 3 via array. These vias are

solder-masked to avoid solder flowing into the plated-through holes during the board manufacturing process.

Details about via dimensions are also shown in the RTV package drawing in 机械、封装和可订购信息.

More information on the WQFN style package is provided in QFN/SON PCB Attachment Application Report

(SLUA271).

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11.2 Layout Example

The example shown in Figure 36 demonstrates the LMH0397 layout guidelines highlighted in Layout Guidelines.

Larger bulk capacitors (10 µF, 1 µF)

for VIN and VDD_CDR can be

placed farther from IC.

BNC Footprint

Anti-pad

Zo = 75 ꢀ

W = 10 mils

Via to

VDD_LDO

Pour

4.7 µF

Place 0.1-µF decoupling caps on

Bottom Layer close to pins. Connect

to Pour and EP with vias.

Via to VIN

Pour

4.7 µF

100-ꢀ coupled

trace

4.7 µF

75 ꢀ

W = 8 mils

S = 10 mils

W = 8 mils

Solder

Paste

Mask

(Stencil)

4.7 µF

VSS Via to

GND

Via to

VDD_CDR

Pour

W = 8 mils

S = 10 mils

W = 8 mils

4.7 µF

75 ꢀ

EP

(Exposed Pad)

Via Array on Bottom

Layer shared with VSS

pins and decoupling caps

where applicable

100-ꢀ coupled

trace

4.7 µF

W = 10 mils

> 5 W

Zo = 75 ꢀ

Layer 3 GND Reference for

75-Ω Single-Ended Traces

Layer 2 GND Reference for

100-Ω Differential Traces

Note: All high speed signal traces are assumed to be on Layer 1 (Top Layer).

Figure 36. LMH0397 High-Speed Trace Layout Example

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12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

如需开发支持，请参阅以下文档：

LMH1297。

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

《焊接的绝对最大额定值》(SNOA549)

《LMH0397 编程指南》 (SNLU225)

《QFN/SON PCB 连接应用报告》(SLUA271)

12.3 接收文档更新通知

如需接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 出口管制提示

接收方同意：如果美国或其他适用法律限制或禁止将通过本协议的披露方获得的任何产品或技术数据（其中包括软

件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制产品或此项技术的任

何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政府机构授权的情况下，接收

方不得在知情的情况下，以直接或间接的方式将其出口。

12.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

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13.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

LMH0397RTVR

LMH0397RTVT

WQFN

RTV

32

1000

250

178.0

12.4

5.3

1.1

8.0

12.0

Q2

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

Package Drawing Pins

SPQ

1000

250

Length (mm) Width (mm)

Height (mm)

35.0

LMH0397RTVR

LMH0397RTVT

WQFN

RTV

32

210.0

185.0

35.0

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46

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMH0397RTVR

LMH0397RTVT

WQFN

RTV

32

1000

250

180.0

12.4

5.3

1.1

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMH0397RTVR

LMH0397RTVT

WQFN

RTV

32

1000

250

210.0

185.0

35.0

Pack Materials-Page 2

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型号：	LMH0397RTVT
厂家：	TEXAS INSTRUMENTS
描述：	具有集成时钟恢复器的 3G SDI 双向 I/O \| RTV \| 32 \| -40 to 85 时钟电视
文件：	总52页 (文件大小：2507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMH0397RTVT [TI]

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