LMH6503MA/NOPB [TI]
宽带、低功耗、线性可变增益放大器 | D | 14 | -40 to 85;
| 型号： | LMH6503MA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 宽带、低功耗、线性可变增益放大器 | D | 14 | -40 to 85 放大器 光电二极管 |
| 文件： | 总36页 (文件大小：1865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6503
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
Check for Samples: LMH6503
1
FEATURES
DESCRIPTION
The LMH™6503 is
a wideband, DC coupled,
23
•
VS = ±5V, TA = 25°C, RF = 1kΩ, RG = 174Ω, RL =
100Ω, AV = AV(MAX) = 10, Typical Values Unless
Specified.
differential input, voltage controlled gain stage
followed by a high-speed current feedback Op Amp
which can directly drive a low impedance load. Gain
adjustment range is more than 70dB for up to 10MHz.
•
-3dB BW 135MHz
•
•
•
•
•
•
•
•
•
•
•
Gain Control BW 100MHz
Maximum gain is set by external components and the
gain can be reduced all the way to cut-off. Power
consumption is 370mW with a speed of 135MHz .
Output referred DC offset voltage is less than 350mV
over the entire gain control voltage range. Device-to-
device Gain matching is within 0.7dB at maximum
gain. Furthermore, gain at any VG is tested and the
tolerance is ensured. The output current feedback Op
Amp allows high frequency large signals (Slew Rate
= 1800V/μs) and can also drive heavy load current
(75mA). Differential inputs allow common mode
rejection in low level amplification or in applications
where signals are carried over relatively long wires.
For single ended operation, the unused input can
easily be tied to ground (or to a virtual half-supply in
single supply application). Inverting or non-inverting
gains could be obtained by choosing one input
polarity or the other.
Adjustment Range (Typical Over Temp) 70dB
Gain Matching (Limit) ±0.7dB
Slew Rate 1800V/µs
Supply Current (No Load) 37mA
Linear Output Current ±75mA
Output Voltage (RL = 100Ω) ±3.2V
Input Voltage Noise 6.6nV/√Hz
Input Current Noise 2.4pA/√Hz
THD (20MHz, RL = 100Ω, VO = 2VPP) −57dBc
Replacement for CLC522
APPLICATIONS
•
•
•
•
Variable Attenuator
AGC
To further increase versatility when used in a single
supply application, gain control range is set to be
from −1V to +1V relative to pin 11 potential (ground
pin). In single supply operation, this ground pin is tied
to a "virtual" half supply. Gain control pin has high
input impedance to simplify its drive requirement.
Gain control is linear in V/V throughout the gain
adjustment range. Maximum gain can be set to be
anywhere between 1V/V to 100V/V or higher. For
linear in dB gain control applications, see LMH6502
datasheet.
Voltage Controller Filter
Multiplier
The LMH6503 is available in the SOIC-14 and
TSSOP-14 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6503
SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
30
20
10
0
11
10
9
dB
85°C
-40°C
-40°C
85°C
8
25°C
7
-10
-20
6
5
4
25°C
-30
-40
-50
3
V/V
-60
-70
-80
2
1
0
V
= ±0.1V
0.8
IN_DIFF
0.4
-0.8
-0.4
0
-1.2
1.2
V
(V)
G
Figure 1. Gain vs. VG for Various Temperature
Typical Application
+5V
R
F
1kW
NC
13
+V
-V
IN
1
3
4
14
12
R
50W
1
V
OUT
R
170W
G
LMH6503
10
5
R
2
L
IN
9
100W
7
8
6
11
R
2
50W
-5V
V
G
Figure 2. AVMAX = 10V/V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)
ESD Tolerance:(3)
Human Body
2KV
200V
Machine Model
Input Current
±10mA
VIN Differential
±(V+ −V−)
120mA(4)
12.6V
Output Current
Supply Voltages (V+ - V−)
Voltage at Input/ Output pins
Soldering Information:
V+ +0.8V,V− - 0.8V
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235°C
260°C
Storage Temperature Range
Junction Temperature
−65°C to +150°C
+150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.
(4) The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Operating Ratings(1)
Supply Voltages (V+ - V−)
Temperature Range
Thermal Resistance:
14-Pin SOIC
5V to 12V
−40°C to +85°C
θJA
θJC
138°C/W
160°C/W
45°C/W
51°C/W
14-Pin TSSOP
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
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Electrical Characteristics(1)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min(2)
Typ(2)
Max(2)
Units
Frequency Domain Response
BW
-3dB Bandwidth
VOUT < 0.5PP
VOUT < 0.5PP, AV(MAX) = 100
VOUT < 0.5VPP
135
50
MHz
MHz
GF
Gain Flatness
,
40
−1V < VG < 1V, ±0.2dB
±0.2dB Flatness, f < 30MHZ
±0.1dB, f < 30MHZ
VG = 0V(4)
Att Range Flat Band (Relative to Max Gain)
Attenuation Range(3)
20
6.6
100
MHz
MHz
BW
Gain Control Bandwidth
Control
PL
Linear Phase Deviation
Group Delay
DC to 60MHz
DC to 130MHz
1.6
2.6
deg
ns
G Delay
CT (dB)
Feed-through
VG = −1.2V, 30MHz (Output
−48
dB
Referred)
GR
Gain Adjustment Range
f < 10MHz
f < 30MHz
79
68
dB
Time Domain Response
tr , tf
Rise and Fall Time
0.5V Step
0.5V Step
4V Step(5)
2.2
10
ns
%
OS%
SR
Overshoot
Slew Rate
1800
4.6
V/µs
dB/ns
ΔG Rate
Gain Change Rate
VIN = 0.3V, 10%−90% of final
output
Distortion & Noise performance
HD2
HD3
THD
En tot
In
2nd Harmonic Distortion
3rdHarmonic Distortion
Total Harmonic Distortion
Total Equivalent Input Noise
Input Noise Current
2VPP, 20MHz
−60
−61
−57
6.6
dBc
dBc
2VPP, 20MHz
2VPP, 20MHz
dBc
1MHz to 150MHz
1MHz to 150MHz
nV/√Hz
pA/√Hz
%
2.4
DG
Differential Gain
f = 4.43MHz, RL = 150Ω, Neg.
0.15
Sync
DP
Differential Phase
f = 4.43MHz, RL = 150Ω, Neg.
0.22
deg
Sync
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.
(3) Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB), relative to AVMAX gain. For example, for f<30MHz, here are the Flat Band Attenuation
ranges:±0.2dB:
10V/V down to 1V/V=20dB range±0.1dB:
10V/V down to 4.7V/V=6.5dB range
(4) Gain Control Frequency Response Schematic:
R
F
910W
+0.2V
DC
R
+V
R
OUT
50W
IN
+
R
1
G
PORT 2
50W
LMH6503
820W
R
50W
L
-V
IN
-
2
G
V
R
2
50W
+5V
-5V
C
1
R
F
IN
0.01mF
R
P1
10kW
0V
DC
R
T
PORT 1
50W
(5) Slew Rate is the average of the rising and falling rates.
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min(2)
Typ(2)
Max(2)
Units
DC & Miscellaneous Performance
GACCU
G Match
Gain Accuracy (see Application
Information)
VG =1.0V
+0.25
±0.3
±0.4
–
+0.9/−0.4
+1.3/−1.5
+4.4/−4.3
±0.7
0V < VG < 1V
−0.7V < VG < 1V
VG = 1.0
dB
Gain Matching (see Application
Information)
0 < VG < 1V
–
+1.7/−1.1
+4.0/−4.7
dB
−0.7V < VG < 1V
–
K
Gain Multiplier (see Application
Information)
1.58
1.58
1.72
1.87
1.91
V/V
V
VCM
Input Voltage Range
Differential Input Voltage
RG Current
Pin 3 & 6 Common Mode,
|CMRR| > 50dB(6)
±2.0
±1.80
±2.2
±0.37
±2.30
11
VIN_ DIFF
IRG MAX
IBIAS
Across pins 3 & 6
±0.34
±0.28
V
Pins 4 & 5
±1.70
±1.60
mA
Bias Current
Pins 3 & 6(7)
18
20
µA
Pins 3 & 6(7)
VS= ±2.5V
,
3
10
13
TCBIAS
I OFF
Bias Current Drift
Offset Current
Pin 3 & 6(8)
100
nA/°C
µA
Pin 3 & 6
0.01
2.0
2.5
TC IOFF
RIN
Offset Current Drift
Input Resistance
Input Capacitance
VG Bias Current
See(8)
5
750
5
nA/°C
kΩ
Pin 3 & 6
Pin 3 & 6
Pin 2, VG = 1.4V(7)
Pin 2(8)
CIN
pF
IVG
45
µA
TC IVG
R VG
C VG
VOUT
VG Bias Drift
20
nA/°C
KΩ
VG Input Resistance
VG Input Capacitance
Output Voltage Range
Pin 2
70
Pin 2
1.3
±3.20
pF
RL = 100Ω
±3.00
±2.97
V
RL Open
±3.95
±4.05
±3.90
ROUT
IOUT
Output Impedance
Output Current
DC
0.1
Ω
VOUT ±4V from Rails
±75
±90
mA
±70
VO OFFSET Output Offset Voltage
−1V < VG < 1V
±80
−80
−67
−67
±350
±380
mV
dB
dB
dB
+PSRR
−PSRR
CMRR
+Power Supply Rejection Ratio
(See(9)
Input Referred, 1V change,
VG = 1.4V
−58
−56
)
−Power Supply Rejection Ratio
(See(9)
Input Referred, 1V change,
VG = 1.4V
−57
−51
)
Common Mode Rejection Ratio
(See(10)
Input Referred, VG = 1V
−1.8V < VCM < 1.8V
)
(6) CMRR definition: [|ΔVOUT/ΔVCM|/AV] with 0.1V differential input voltage. ΔVOUT is the change in output voltage with offset shift
subtracted out.
(7) Positive current correspondes to current flowing in the device.
(8) Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
(9) +PSRR definition: [|ΔVOUT/ΔV+| /AV], -PSRR definition: [|ΔVOUT/ΔV−| /AV] with 0.1V differential input voltage. ΔVOUT is the change in
output voltage with offset shift subtracted out.
(10) CMRR definition: [|ΔVOUT/ΔVCM|/AV] with 0.1V differential input voltage. ΔVOUT is the change in output voltage with offset shift
subtracted out.
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Parameter
Supply Current
Test Conditions
RL = Open
Min(2)
Typ(2)
Max(2)
Units
IS
37
50
53
mA
RL = Open, VS = ±2.5V
12
20
23
Connection Diagram
Top View
+
14
13
12
11
10
9
1
2
3
4
5
6
7
+
V
V
NC
V
G
-
I
+V
IN
+R
GND
G
V
-R
-V
OUT
G
V
REF
IN
8
-
-
V
V
Figure 3. 14-Pin SOIC AND TSSOP Packages
See Package Numbers D0014A and PW0014A
6
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
Typical Performance Charateristics
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Small Signal Frequency Response (AV = 2)
Large Signal Frequency Response (AV = 2)
5
90
5
GAIN
R
F
= 920W, R = 820W
G
3
45
0
-5
0
0
-3
PHASE
-10
-15
-20
-25
-30
-35
-45
-90
-135
-180
-225
-5
R
F
= 2.4kW, R = 2.1kW
G
-8
-10
-13
-15
-18
-20
V
A
= 5V
PP
OUT
= 2
VMAX
R
R
= 2.4kW
V
A
= 0.5V
= 2
F
OUT
PP
= 2.15kW
G
VMAX
-270
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4.
Figure 5.
Frequency Response over Temperature (AV = 10)
Frequency Response for Various VG (AVMAX = 10)
1
1
150
100
50
40
-1.0V
GAIN
GAIN
20
0
0
85°C
1.2V
-40°C
25°C
-1
-1
-0.4V
0
PHASE
-20
-40
-60
-80
-100
-120
-140
-160
-2
-3
-4
-5
-6
-7
-2
-3
-4
-5
-6
-7
0
PHASE
1.2V
-0.4V
-1.0V
-40°C
25°C
85°C
-50
-100
-150
-200
-250
-300
-350
A
= 10, V = V
GMAX
VMAX
G
A
= 10
VMAX
GAIN/PHASE DATA
GAIN NORMALIZED TO LOW
FREQUENCY VALUE AT
NORMALIZED TO LOW
-8
-9
-8
-9
EACH V
G
FREQUENCY VALUE AT 25°C
1M
100M
1M
100M
1k
100k
10M
1G
1k
100k
10M
1G
10k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6.
Figure 7.
Frequency Response for Various VG (AVMAX = 10) (±2.5V)
Small Signal Frequency Response
3
2
270
3
40
V
= 0.5V
RF(kW)
-0.48V
0.55V
A
VMAX
OUT
GAIN
PP
225
180
135
2
20
PHASE
GAIN
1
0
100
10
2
750
1k
2.4k
0
1
0
0V
-20
-40
-60
-80
-100
-120
-160
-7
-1
-2
90
-1
-2
-3
-4
-5
-6
-7
100
45
0
-3
-4
-5
-6
-7
-8
-9
0V
10
2
25°C
-45
-0.48V
V
= ±2.5V
PHASE
S
-90
A
= 10
VMAX
-135
-180
-225
-270
GAIN NORMALIZED TO
LOW FREQUENCY
VALUE AT EACH V
G
SEE NOTE 12
1k
10k 100k 1M
10M 100M 1G
f (25 MHz/DIV)
FREQUENCY (Hz)
Figure 8.
Figure 9.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Frequency Response for Various VG (AVMAX = 100)
Large Signal Frequency Response
(Small Signal)
3
2
270
1
0
60
40
20
V
= 5V
PP
R (kW)
OUT
A
VMAX
SEE NOTE 12
F
225
180
135
GAIN
1
0
100
10
2
750
1k
2.4k
A
P
= 100
VMAX
GAIN
-1
-2
-3
= -42dBm
IN
-1
-2
90
0
PHASE
45
0
-20
-40
-60
-80
100
2
-3
-4
-5
-6
-7
-8
-9
-4
-5
-6
-7
-8
10
-45
1.1V
PHASE
-90
0.5V
-135
-180
-225
-270
0V
-100
-120
-0.5V
50M
SEE NOTE 12
0
100M
f (25 MHz/DIV)
f (10 MHz/DIV)
Figure 10.
Figure 11.
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
Gain Control Frequency Response
1
60
40
20
5
SEE NOTE 12
GAIN
0
A
P
= 100
VMAX
0
-1
-2
-3
= -22dBm
IN
0
PHASE
-5
-20
-40
-60
-80
-4
-5
-6
-7
-8
V
P
A
= 0V AVERAGE
= 0dBm
G
-10
1.1V
IN
0.5V
= 2V/V
VMAX
-15
-20
S21 (dB) + 20 PLOTTED
0V
-100
-120
SEE NOTE 11
-0.5V
0
50M
f (10 MHz/DIV)
100M
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 12.
IS vs. VS
Figure 13.
IS vs. VS
60
60
50
40
30
20
85°C
50
40
30
20
85°C
25°C
25°C
-40°C
-40°C
R
= OPEN
R
= OPEN
L
L
10
0
10
0
V
G
= V
V
G
= V
G_MAX
G_MIN
6
6
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
±SUPPLY VOLTAGE (V)
±SUPPLY VOLTAGE (V)
Figure 14.
Figure 15.
8
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Input Bias Current vs. VS
AVMAX vs. VS
18
16
14
12
10
-40°C
85°C
85°C
12
10
8
6
4
25°C
25°C
-40°C
8
6
4
2
0
-40°C
2
0
V
V
= V
G_MAX
G
= 0.1V
IN_DIFF
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGES (V)
±Supply Voltage (V)
Figure 16.
Figure 17.
PSRR ±5V
PSRR ±2.5V
0
-10
-20
0
-10
-20
SEE NOTE 10
SEE NOTE 10
-30
-40
-50
-30
-40
-50
+PSRR
+PSRR
-60
-60
-PSRR
-70
-80
-70
-80
V
V
= ±2.5V
= V
-PSRR
V
= ±5V
= V
S
S
V
G
GMAX
G
GMAX
-90
-90
1M
1M
10M
100k
10M
1k
10k 100k
100M
1k
10k
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18.
Figure 19.
CMRR ±5V
CMRR ±2.5V
0
0
SEE NOTE 9
SEE NOTE 9
-20
-20
-40
-60
-40
-60
MAXGAIN
MAXGAIN
-80
-80
V
S
= ±5V
= 10
V
A
P
= ±2.5V
S
-100
-100
A
VMAX
= 10
VMAX
P
IN
= 0dBm
= 0dBm
MIDGAIN
IN
MIDGAIN
100k
-120
-120
1M
10M
100k
1M
1k
10k
100M
1k
10k
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20.
Figure 21.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
AVMAX vs. VCM
AVMAX vs. VCM
12
12
10
8
10
8
85°C
25°C
85°C
25°C
-40°C
6
6
4
-40°C
4
2
2
0
V
V
V
= ±2.5V
0
-2
-4
V
V
V
= ±5V
S
S
= 0.1V
= 0.1V
1
IN_DIFF
= V
IN_DIFF
= V
G
GMAX
G
GMAX
-2
-1 -0.8 -0.6 -0.4 -0.2
V
0
0.2 0.4 0.6 0.8
(V)
1
-3
-2
-1
0
2
3
V
CM
(V)
CM
Figure 22.
Figure 23.
Supply Current vs. VCM
Supply Current vs. VCM
60
28
26
24
22
85°C
85°C
85°C
25°C
50
40
30
20
25°C
-40°C
20
18
16
14
12
10
-40°C
V
V
= ±5V
10
0
S
V
V
= ±2.5V
S
= V
G
GMAX
= V
G
GMAX
-1.5
-1
-0.5
0
0.5
1
1.5
-3
-2
-1
0
1
2
3
V (V)
CM
V
(V)
CM
Figure 24.
Figure 25.
Output Offset Voltage vs.VCM (Typical Unit 1)
Output Offset Voltage vs.VCM (Typical Unit 2)
0
120
85°C
-5
-40°C
110
25°C
-10
100
-15
25°C
90
-20
-25
-30
80
85°C
70
60
-40°C
-35
V
V
= ±5V
V
V
= ±5V
S
S
50
40
-40
-45
= V
= V
G
GMAX
G
GMAX
-3
-2
-1
0
1
2
3
-3
-2
-1
2
3
0
1
V
CM
(V)
V
(V)
CM
Figure 26.
Figure 27.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Output Offset Voltage vs.VCM (Typical Unit 3)
Feed through Isolation
60
40
20
-100
-110
-120
-40°C
85°C
0
-20
-40
A
= 100
VMAX
A
= 10
VMAX
-130
A
= 2
VMAX
-140
-60
-80
25°C
-150
V
V
= ±5V
S
-160
-170
-100
-120
= V
GMAX
G
100k
1M
10M
100M
-3
-2
-1
1
2
3
0
FREQUENCY (Hz)
V
(V)
CM
Figure 28.
Figure 29.
(1)
Gain Flatness and Linear Phase Deviation
Gain Flatness Frequency vs. Gain
0.40
2.4
2
±0.2dB
-1.0V
100M
GAIN
0.30
0.20
-0.4V
1.6
1.2
0.10
10M
1.2V
0.00
0.8
0.4
0
PHASE
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
1.2V
R
R
= 1kW
F
1M
-0.4
-0.8
-1.2
-1.6
-0.4V
= 170W
±0.1dB
G
IN
G
-1.0V
P
V
= -10dBm
VARIED
GAIN DATA NORMALIZED TO LOW
FREQUENCY VALUE AT EACH V
f (3 MHz/DIV)
G
100k
4
5
6
7
0
1
2
3
8
9
10
A
(V/V)
V
Figure 30.
Figure 31.
K Factor vs. RG
Group Delay vs. Frequency
2.80
2.70
2.60
2.50
2.40
2.30
2.20
2.10
2.00
2.1
V
A
= V
GMAX
G
R
= 477W
F
2
1.9
1.8
1.7
= 10
VMAX
R
= 690W
F
R
F
= 6.18kW
1.6
1.5
1.4
1.3
1.2
R
= 1.3kW
F
2k
1k
10
100
f (5 MHz/DIV)
R
(W)
G
Figure 32.
Figure 33.
(1) Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB), relative to AVMAX gain. For example, for f<30MHz, here are the Flat Band Attenuation
ranges:±0.2dB:
10V/V down to 1V/V=20dB range±0.1dB:
10V/V down to 4.7V/V=6.5dB range
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Gain vs. VG Including Limits
BW vs. RF for Various RG
1000
12
10
8
R
= 100W
G
V
= ±0.1V
IN_DIFF
R
= 180W
G
R
= 466W
LIMIT HIGH
G
100
10
R
= 1190W
G
TYPICAL
R
= 47W
G
6
LIMIT LOW
4
2
0
R
G
= 27W
1
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
100
1k
10k
100k
V
G
(V)
R
F
(W)
Figure 34.
Figure 35.
Output Offset Voltage vs. VG
(Typical Unit 1)
Gain vs. VG (±5V)
30
11
10
9
120
100
80
60
40
20
0
dB
-40°C
20
10
0
85°C
-40°C
25°C
-40°C
85°C
8
25°C
7
-10
-20
85°C
6
5
4
25°C
-30
-40
-50
3
V/V
-60
-70
-80
2
1
0
V
= ±0.1V
0.8
IN_DIFF
0.4
-1.2 -0.8
-0.4
0
1.2
-1.5
-1
-0.5
0
0.5
1
1.5
V
(V)
G
V
G
(V)
Figure 36.
Figure 37.
Output Offset Voltage vs. VG
(Typical Unit 2)
Output Offset Voltage vs. VG
(Typical Unit 3)
15
10
5
0
-20
-40
0
-60
85°C
-5
-10
-15
-20
-25
-30
-40°C
25°C
-80
-100
-120
-140
-160
85°C
25°C
-40°C
-1.5
1
-0.5
0
0.5
1
1.5
-1.5
-1
-05
0
0.5
1
1.5
V
(V)
G
V
(V)
G
Figure 38.
Figure 39.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Output Offset Voltage vs. ±VS for Various VG
Output Offset Voltage vs. ±VS for Various VG
(Typical Unit 1)
(Typical Unit 2)
140
25
20
MAX
120
15
MIN
100
10
5
MID
80
60
0
MID
-5
MIN
-10
40
MAX
-15
20
0
-20
-25
6.5
2.5
3
3.5
4
4.5
±V (V)
5
5.5
6
2.5
3
3.5
4
4.5
±V (V)
5
5.5
6
6.5
S
S
Figure 40.
Figure 41.
Output Offset Voltage vs. ±VS for Various VG
(Typical Unit 3)
Gain vs. VG (±2.5V)
10
9
0
V
= ±2.5V
= 980W
= 180W
S
-20
MIN
-40
R
F
8
R
G
7
-60
6
5
4
3
2
1
0
-80
-100
-120
-140
-160
-180
-200
MID
MAX
0.0
(V)
-0.6 -0.4
-0.2
0.2
0.4
0.6
2.5
3
3.5
4
4.5
±V (V)
5
5.5
6
6.5
V
G
S
Figure 42.
Noise vs. Frequency (AVMAX = 2)
Figure 43.
Noise vs. Frequency (AVMAX = 10)
10000
1000
100
10000
1000
100
A
= 2
= 910W
= 820W
A
= 10
VMAX
VMAX
R
R
R
R
= 1kW
F
F
= 180W
MAX GAIN
G
G
MAX GAIN
MID GAIN
MID GAIN
MIN GAIN
MIN GAIN
10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 44.
Figure 45.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Noise vs. Frequency (AVMAX = 100)
−1dB Compression
24
23
22
100k
10k
1k
OUTPUT LIMITED , R = 1.5kW
F
MAX GAIN
MID GAIN
NO GAIN
21
20
INPUT LIMITED, R = 620W
F
19
18
A
= 100
VMAX
100
10
R
F
R
G
R
L
= 2kW
17
16
15
= 24W
V
= V
GMAX
G
= 100W
R
= 180W
G
10k
0
20 40 60 80 100 120 140 160
10
1k
100k
1M
10M
100
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 46.
Figure 47.
Output Voltage vs. Output Current
HD2 vs. POUT
90
85
80
75
70
65
60
55
50
4.5
4
A
V
= 10
1MHz
VMAX
= V
V
= ±0.5V
IN_DIFF
G
GMAX
SINK
3.5
3
2.5
SOURCE
2
1.5
1
10MHz
0.5
0
20MHz
-10
-5
0
10
(dBm)
15
20
5
0
20
40
60
100
80
P
OUT
I
(mA)
OUT
Figure 48.
Figure 49.
HD3 vs. POUT
THD vs. POUT
90
85
100
90
80
70
60
50
40
30
20
1MHz
1MHz
80
75
70
65
60
55
50
45
40
10MHz
10MHz
20MHz
20MHz
A
V
= 10
VMAX
A
V
= 10
VMAX
= V
G
GMAX
= V
G
GMAX
-10
-5
0
10
(dBm)
15
20
5
-10
-5
0
5
10
15
20
P
P
OUT
(dBm)
OUT
Figure 50.
Figure 51.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
HD2 & HD3 vs. VG
THD vs. VG
80
70
60
50
40
30
20
90
80
70
60
50
HD3, 0.25V
PP
0.25V
PP
1V
HD2, 0.25V
PP
PP
HD2, 1V
PP
2V
PP
HD2, 2V
PP
HD3, 2V
40
30
20
PP
10
0
HD3, 1V
PP
f = 20MHz
20MHZ
0.6
-1
-0.6
-0.2
0.2
(V)
0.6
1
-1
-0.6
-0.2
0.2
1
V
V
(V)
G
G
Figure 52.
VG Bias Current vs. VG
Figure 53.
Step Response Plot
50
45
0.5V SMALL SIGNAL
PP
40
35
SS REF
30
25
20
LS REF
15
10
5
5V LARGE SIGNAL
PP
0
-1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 1.4
4 ns/DIV
V
(V)
G
Figure 54.
Figure 55.
Step Response Plot
Gain vs. VG Step
1.5
1.2
0.9
0.6
0.3
0
10
9
8
7
6
5
4
3
2
1
0
0.5V SMALL SIGNAL
PP
V
A
= 0.3V
IN
= 10
VMAX
R = 100W
L
SS REF
LS REF
V
G
-0.3
-0.6
-0.9
-1.2
-1.5
GAIN
2.5V LARGE SIGNAL
V
= V
G_MID
PP
G
4 ns/DIV
t (10ns/DIV)
Figure 56.
Figure 57.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
VG Feedthrough
A
= 10
VMAX
R = 100W
L
0
V
OUT
V
G
0
t (10ns/DIV)
Figure 58.
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APPLICATION INFORMATION
THEORY OF OPERATION
The LMH6503 is a linear wideband variable-gain amplifier as illustrated in Figure 59. A voltage input signal may
be applied differentially between the two inputs (+VIN, −VIN), or single-endedly by grounding one of the two
unused inputs. The LMH6503 input buffers convert the input voltage to a current (IRG) that is a function of the
differential input voltage (VINPUT = (+VIN) - (−VIN)) and the value of the gain setting resistor (RG). This current (IRG
)
is then mirrored to a gain stage with a current gain of K (1.72 nominal). The voltage controlled two-quadrant
multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output
amplifier is a current feedback op amp configured as a Transimpedance amplifier. Its Transimpedance gain is the
feedback resistor (RF). The input signal, output, and gain control are all voltages. The output voltage can easily
be calculated as shown in Equation 1:
V
+ 1
G
FOR -1 < V < +1
V
= I
RG
x K x
x R
F
G
OUT
2
(1)
Where K = 1.72 (Nominal)
since:
V
INPUT
I
=
RG
R
G
(2)
The gain of the LMH6503 is therefore a function of three external variables: RG, RF, and VG as expressed in
Equation 3:
R
V + 1
G
F
A
=
x 1.72 x
V
R
2
G
(3)
The gain control voltage (VG) has an ideal input range of −1V < VG < +1V. At VG = +1V, the gain of the LMH6503
is at its maximum as expressed in Equation 4:
R
F
A
= 1.72
V
R
G
(4)
Notice also that Equation 4 holds for both differential and single-ended operation.
V
G
+V
IN
X1
-
I
I
RG
V
INPUT
R
F
R
G
I
K
X
-
RG
CFB
V
OUT
OP AMP
V
G
+ 1
+
V
REF
2
X1
-V
IN
Figure 59. LMH6503 Functional Block Diagram
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CHOOSING RF AND RG
RG is calculated using Equation 5. VINPUTMAX is the maximum peak input voltage (Vpk) determined by the
application. IRGMAX is the maximum allowable current through RG and is typically 2.3mA. Once AVMAX is
determined from the minimum input and desired output voltages, RF is then determined using Equation 6. These
values of RF and RG are the minimum possible values that meet the input voltage and maximum gain constraints.
Scaling the resistor values will decrease bandwidth and improve stability.
VINPUT
MAX
RG =
I
RGMAX
(5)
1
RF =
RG AVMAX
*
*
K
(6)
Figure 60 illustrates the resulting LMH6503 bandwidths as a function of the maximum ( y axis) and minimum
(related to x axis) input voltages when VOUT is held constant at 1VPP
.
10
5MHz
2.7MHz
10MHz
1
150MHz
100MHz
0.1
V
V
= 1V
PP
OUT
50MHz
= V
G
GMAX
20MHz
I
= 2.3mA
RGMAX
0.01
1
10
100
A
(V/V)
VMAX
Figure 60. Bandwidth vs. VINMAX and AVMAX
ADJUSTING OFFSETS
Treating the offsets introduced by the input and output stages of the LMH6503 is accomplished with a two step
process. The offset voltage of the output stage is treated by first applying −1.1V on VG, which effectively isolates
the input stage and multiplier core from the output stage. As illustrated in Figure 61, the trim pot located at R14
on the LMH6503 Evaluation Board (LMH730033) should then be adjusted in order to null the offset voltage seen
at the LMH6503's output (pin 10).
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Figure 61. Nulling the Output Offset Voltage
Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated.
The second step requires the absence of an input signal and matched source impedances on the two input pins
in order to cancel the bias current errors. This done, then +1.1V should be applied to VG and the trim pot located
at R10 adjusted in order to null the offset voltage seen at the LMH6503's output. If a more limited gain range is
anticipated, the above adjustments should be made at these operating points. These steps will minimize the
output offset voltage. However, since the offset term itself varies with the gain setting, the correction is not
perfect and some residual output offset will remain.
GAIN ACCURACY
Defined as the ratio of measured gain (V/V), at a certain VG, to the best fit line drawn through the typical gain
(V/V) distribution for −1V < VG < 1V (results expressed in dB) (See Figure 62). The best fit gain (AV) is given by:
AV (V/V) = 4.87VG + 4.61
(7)
(8)
For: −1V ≤ VG ≤ + 1V, RF = 1kΩ, RG = 174Ω
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the worst case ratio between the "Typical Gain" and the best fit line. The "Max" value
would be the worst case between the max/min gain limit and the best fit line.
GAIN MATCHING
Defined as the limit on gain variation at a certain VG (expressed in dB) (See Figure 62). Specified as "Max" only
(no "Typical"). For a VG range, the value specified represents the worst case matching over the entire range. The
"Max" value would be the worst case ratio between the max/min gain limit and the typical gain.
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MAX GAIN LIMIT
MIN GAIN LIMIT
D
C
TYPICAL GAIN
B
A
BEST FIT LINE
V
(V)
G
PARAMETER:
GAIN ACCURACY (TYPICAL) = B/C (dB)
GAIN ACCURACY (+ & - LIMIT) = D/C & A/C (dB)
GAIN MATCHING (+ & - LIMIT) = D/B & A/B (dB)
Figure 62. Gain Accuracy and Gain Matching Parameters Defined
NOISE
Figure 63 describes the LMH6503's output-referred spot noise density as a function of frequency with AVMAX
=
10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50Ω, the input
noise contribution is minimal. At AVMAX = 10V/V, the LMH6503 has a typical flat-band input-referred spot noise
density (ein) of 6.6nV/√Hz. For applications with −3dB BW extending well into the flat-band region, the input RMS
voltage noise can be determined from the following single-pole model:
VRMS = ein * 1.57 * (-3dB BANDWIDTH)
(9)
10000
A
VMAX
= 10
R
F
= 1kW
R
G
= 180W
MAX GAIN
1000
100
10
MID GAIN
MIN GAIN
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 63. Output Referred Voltage Noise vs. Frequency
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CIRCUIT LAYOUT CONSIDERATIONS
Good high-frequency operation requires all of the de-coupling capacitors shown in Figure 64 to be placed as
close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass.
Adequate ground plane and low inductive power returns are also required of the layout. Minimizing the parasitic
capacitances at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency performance. The parasitic
inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load
capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or
circuit oscillation. The LMH6503 is fully stable when driving a 100Ω load. With reduced load (e.g. 1kΩ) there is a
possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the
LMH6503 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g.
100Ω and 39pF in series tied between the LMH6503 output and ground). CL can also be isolated from the output
by placing a small resistor in series with the output (pin 10).
Figure 64. Required Power Supply Decoupling
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board Part Number
LMH6503MA
SOIC-14
LMH730033
SINGLE SUPPLY OPERATION
It is possible to operate the LMH6503 with a single supply. To do so, tie pin 11 (GND) to a potential about mid
point between V+ and V−. Two examples are shown in Figure 65 & Figure 66.
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R
2
C
1
510W
0.1µF
R
510W
1
V
3
S
V /2
S
R
F
14
1kW
+V
-V
IN
13
1
C
OUT
0.1µF
+
12
R
180W
G
LMH6503
9
10
R
OUT
50W
IN
2
V
OUT
-
11
8
6
7
R
R
4
3
2kW
2kW
V
G
RANGE: ±1V FROM PIN 11
VOLTAGE (FOR V = 10V)
S
Figure 65. AC Coupled Single Supply VGA
C
R
2
1
0.1µF
510W
R
510W
1
V
3
S
V /2
S
R
1kW
F
14
13
1
C
OUT
0.1µF
+
12
R
160W
G
LMH6503
10
R
OUT
50W
V
OUT
2
9
-
11
8
6
7
V
G
Figure 66. Transformer Coupled Single Supply VGA
OPERATING AT LOWER SUPPLY VOLTAGES
The LMH6503 is rated for operation down to 5V supplies (V+ - V−). There are some specifications shown for
operation at ±2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared
to ±5V operation, at lower supplies:
a)
VG range constricts. Referring to Figure 67, note that VG_MAX (VG voltage required to get maximum gain) is
0.5V (VS = ±2.5V) compared to 1.0V for VS = ±5V. At the same time, gain cut-off (VG_MIN) would shift to
−0.5V from - 1V with VS = ±5V.
Table 1 shows the approximate expressions for various VG voltages as a function of V-:
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
Table 1. VG Definition Based on V−
VG
Definition
Gain Cut-off
AVMAX/2
Expression (V)
0.2 x V−
0
VG_MIN
VG_MID
VG_MAX
AVMAX
−0.2 x V−
b)
c)
VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device
arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive).
Referring to Figure 67, note that with V+ = 2.5V, and V− = −4V, VG_LIMIT is approaching VG_MAX and already
"Max gain" is reduced by 1dB. This means that operating under these conditions has reduced the
maximum permissible voltage on VG to a level below what is needed to get Max gain. If supply voltages
are asymmetrical, reference Figure 67 and Figure 68 plots to make sure the region of operation is not
overly restricted by the "pinching" of VG_LIMIT, and VG_MAX curves.
"Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced
(see Figure 43). In addition, there is the more drastic mechanism described in "b" above and shown in
Figure 67.
Similar plots for V+ = 5V operation are shown in Figure 68 for comparison and reference.
1.6
1.4
20.5
20
MAX GAIN
1.2
1
19.5
19
V
LIMIT
G
0.8
0.6
0.4
18.5
18
V
G
MAX
+
17.5
V
R
R
= 2.5V
= 1kW
F
17
0.2
0
= 170W
G
16.5
-4.5
-4
-3.5
-3
-2.5
-2
-
V (V)
Figure 67. VG_MAX, VG_LIMIT, & Max-gain vs. V-
(V+ = 2.5V)
5
4.5
4
20.5
20.4
20.3
20.2
20.1
V
LIMIT
G
3.5
3
MAX GAIN
2.5
2
20
+
V
= 5V
19.9
19.8
19.7
R
R
= 1kW
F
1.5
1
= 170W
G
0.5
0
19.6
19.5
V
MAX
G
-6
-5.5
-5
-4.5
-4
-3.5
-3
-
V (V)
Figure 68. VG_MAX, VG_LIMIT, & Max-gain vs. V-
(V+ = 5V)
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Application Circuits
www.ti.com
FOUR-QUADRANT MULTIPLIER
Applications requiring multiplication, squaring or other non-linear functions can be implemented with four-
quadrant multipliers. The LMH6503 implements a four-quadrant multiplier as illustrated in Figure 69:
Figure 69. Four Quadrant Multiplier
FREQUENCY SHAPING
Frequency shaping and bandwidth extension of the LMH6503 can be accomplished using parallel networks
connected across the RG ports. The network shown in the Figure 70 schematic will effectively extend the
LMH6503's bandwidth.
Figure 70. Frequency Shaping
2nd ORDER TUNABLE BANDPASS FILTER
The LMH6503 Variable-Gain Amplifier placed into a feedback loop provides signal processing function such as in
a 2nd order tunable bandpass filter. The center frequency of the 2nd order bandpass shown in Figure 71 is
adjusted through the use of the LMH6503's gain control voltage, VG. The integrators implemented with two
sections of a LMH6682, provide the coefficients for the transfer function.
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SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
1
s
VO
CRB
1
n
-
=
p
VIN
1
s2 + s
+
CRB C2RY2
pRB
p
RF
RY
, wO
, Q =
=
p = 1.72
RY
CRY
Figure 71. Tunable Bandpass Filter
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6503MA/NOPB
LMH6503MAX/NOPB
LMH6503MT
ACTIVE
ACTIVE
NRND
SOIC
SOIC
D
D
14
14
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH6503MA
2500 RoHS & Green
SN
LMH6503MA
TSSOP
PW
94
94
Non-RoHS
& Green
Call TI
LMH65
03MT
LMH6503MT/NOPB
LMH6503MTX/NOPB
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMH65
03MT
2500 RoHS & Green
LMH65
03MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6503MAX/NOPB
LMH6503MTX/NOPB
SOIC
D
14
14
2500
2500
330.0
330.0
16.4
12.4
6.5
9.35
5.6
2.3
1.6
8.0
8.0
16.0
12.0
Q1
Q1
TSSOP
PW
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6503MAX/NOPB
LMH6503MTX/NOPB
SOIC
D
14
14
2500
2500
356.0
367.0
356.0
367.0
35.0
35.0
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6503MA/NOPB
LMH6503MT
D
SOIC
14
14
14
14
55
94
94
94
495
495
495
495
8
8
8
8
4064
3.05
4.06
4.06
4.06
PW
PW
PW
TSSOP
TSSOP
TSSOP
2514.6
2514.6
2514.6
LMH6503MT
LMH6503MT/NOPB
Pack Materials-Page 3
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