LMH6517 [TI]
具有数字控制增益的低功耗、低噪声 IF 和基带双路 16 位 ADC 驱动器;
| 型号： | LMH6517 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有数字控制增益的低功耗、低噪声 IF 和基带双路 16 位 ADC 驱动器 驱动 驱动器 |
| 文件： | 总37页 (文件大小：1089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6517
www.ti.com
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
Low Power, Low Noise, IF and Baseband, Dual 16 bit ADC Driver With Digitally Controlled
Gain
Check for Samples: LMH6517
1
FEATURES
DESCRIPTION
The LMH6517 contains two high performance,
digitally controlled variable gain amplifiers (DVGA). It
has been designed for use in narrowband and
broadband IF sampling applications. Typically the
LMH6517 drives a high performance ADC in a broad
range of mixed signal and digital communication
applications such as mobile radio and cellular base
stations where automatic gain control (AGC) is
required to increase system dynamic range.
2
•
Accurate, 0.5dB Gain Steps
•
•
•
•
•
•
•
•
200Ω Resistive, Differential Input
Low Impedance, Differential Output
Disable Function for Each Channel
Parallel Gain Control
SPI Compatible Serial Bus
Two Wire, Pulse Mode Control
On Chip Register Stores Gain Setting
Each channel of LMH6517 has an independent,
digitally controlled attenuator and a high linearity,
differential output amplifier. Each block has been
optimized for low distortion and maximum system
design flexibility. Each channel can be individually
disabled for power savings.
Low Sensitivity of Linearity and Phase to Gain
Setting
•
•
Single 5V Supply Voltage
Small Footprint WQFN Package
The LMH6517 digitally controlled attenuator provides
precise 0.5dB gain steps over a 31.5dB range. On
chip digital latches are provided for local storage of
the gain setting. Both serial and parallel programming
options are provided. A Pulse mode is also offered
where simple up or down commands can change the
gain one step at a time.
APPLICATIONS
•
•
•
•
•
Cellular Base Stations
IF Sampling Receivers
Instrumentation
Modems
Imaging
The output amplifier has a differential output allowing
large signal swings on a single 5V supply. The low
impedance output provides maximum flexibility when
driving filters or analog to digital converters.
KEY SPECIFICATIONS
•
•
•
•
•
•
OIP3: 43dBm @ 200MHz
Noise figure 5.5dB
The LMH6517 operates over the industrial
temperature range of −40°C to +85°C. The LMH6517
is available in a 32-Pin, thermally enhanced, WQFN
package.
Gain step size of 0.5dB
Gain step accuracy: 0.05dB
Frequency Range of 1200 MHz
Supply current 80mA per channel
Typical Application: IF Sampling Receiver
V
CC
½ LMH6517
RF
200
ADC
LO
6
GAIN 0-5
LATCH
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMH6517
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
2 kV
100V
Machine Model
Charged Device Model
750V
Positive Supply Voltage (Pin 3)
Differential Voltage between Any Two Grounds
Analog Input Voltage Range
Digital Input Voltage Range
−0.6V to 5.5V
<200 mV
−0.6V to V+
−0.6V to 3.6V
Output Short Circuit Duration
(one pin to ground)
Infinite
+150°C
Junction Temperature
Storage Temperature Range
Soldering Information
−65°C to +150°C
Infrared or Convection (30 sec)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(1)
Operating Ratings
Supply Voltage (Pin 3)
4.5V to 5.25V
<10 mV
Differential Voltage Between Any Two Grounds
Analog Input Voltage Range,
AC Coupled
0V to V+
(2)
Temperature Range
−40°C to +85°C
Package Thermal Resistance (θJA
)
32-Pin WQFN
42°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
2
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
(1)
5V Electrical Characteristics
The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz.
Boldface limits apply at temperature extremes.
(2)
(3)
(2)
Parameter
Dynamic Performance
Test Conditions
Min
Typ
Max
Units
SSBW
Frequency Range
1200
22
MHz
dB
Maximum Voltage Gain
Input Noise Voltage
f = 200 MHz
Maximum Gain, f > 1MHz, RIN= 0 Ω
Maximum Gain, f > 1MHz
1.1
22
nV/√Hz
nV/√Hz
dB
Output Noise Voltage
Noise Figure
Maximum Gain
5.5
43
OIP3
IMD3
Output Third Order Intercept Point
Output Third Order Intercept Point
f = 150 MHz, V OUT = 4dBm per tone
f = 200 MHz, V OUT = 4dBm per tone
f = 150 MHz, V OUT = 4dBm per tone
dBm
43
Third Order Intermodulation
Products
−78
dBc
Third Order Intermodulation
Products
f = 200 MHz, V OUT = 4dBm per tone
−78
P1dB
1dB Compression Point
1dB Compression Point
f = 150 MHz, RL= 100Ω
f= 150 MHz, RL= 200Ω
18.3
15.5
dBm
Analog I/O
Input Resistance
Differential
170
200
2
220
Ω
Input Capacitance
pF
Input Common Mode Voltage
Self Biased
2.42
2.24
2.55
2.71
2.79
V
V
Input Common Mode Voltage
Range
Externally Driven, CMRR > 40dB
1.5
3.5
Maximum Input Voltage Swing
Output Common Mode Voltage
Volts peak to peak, differential
Self Biased
5.5
2.55
5.9
V
V
2.4
2.7
Maximum DIfferential Output
Voltage Swing
Differential
VPP
Output Voltage Swing
Output Offset Voltage
Single ended (each output)
All Gain Settings
1.05
1V to 4V
4.00
V
VOS
−25
−2
25
mV
-30
30
CMRR
PSRR
XTLK
XTLK
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Channel to Channel Crosstalk
Channel to Channel Crosstalk
Maximum Gain, f=100MHz
Maximum Gain, f=100MHz
Maximum Gain, f=100MHz
Maximum Gain, f=300MHz
60
60
dB
dB
−85
−72
dBc
dBc
Gain Parameters
Maximum Gain
Gain Code 000000,
DC Voltage Gain
21.7
21.65
21.85
22
22.05
dB
dB
Minimum Gain
Gain Code 111111,
DC Voltage Gain
−9.25
−9.1
−9.5
−9.78
−9.8
Gain Adjust Range
Gain Step Size
31.5
0.5
dB
dB
dB
°
Channel Matching
Channel Matching
Gain Step Error
Gain Step Error
Gain Error between A and B channel.
Phase Shift between A and B channel.
Any two steps
±0.05
±0.1
±0.05
±0.1
−0.3
−0.5
0.3
0.5
dB
dB
Maximum Gain to Maximum Gain −12dB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance
is indicated in the electrical tables under conditions different than those tested
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Copyright © 2008–2013, Texas Instruments Incorporated
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5V Electrical Characteristics (1) (continued)
The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz.
Boldface limits apply at temperature extremes.
(2)
(3)
(2)
Parameter
Test Conditions
between any two steps
Min
Typ
0.5
Max
Units
Gain Step Phase Shift
Gain Step Switching Time
°
15
ns
Power Requirements
ICC
P
Supply Current
Power
Each channel (two channels per package)
Each Channel
80
400
7.5
91
mA
mW
mA
ICC
Disabled Supply Current
Each Channel
All Digital Inputs
Logic Compatibility
TTL, 2.5V CMOS, 3.3V CMOS
VIL
VIH
IIH
IIL
Logic Input Low Voltage
0
0.4
3.6
V
V
Logic Input High Voltage
2.0
Logic Input High Input Current
Logic Input Low Input Current
Digital Input Voltage = 3.3V
Digital Input Voltage = 0V
−110
−110
110
110
μA
μA
Parallel and Pulse Mode Timing
tGS
tGH
tLP
Setup Time
3
3
ns
ns
ns
ns
ns
ns
Hold Time
Latch Low Pulse Width
Pulse Gap between Pulses
Minimum Latch Pulse Width
Reset Width
7
tPG
tPW
tRW
20
20
10
Serial Mode Timing and AC Characteristics
SPI Compatible
fSCLK
tPH
Serial Clock Frequency
10.5
60
MHz
%
SCLK High State Duty Cycle
SCLK Low State Duty cycle
Serial Data In Setup Time
Serial Data In Hold Time
% of SCLK Period
% of SCLK Period
40
40
tPL
60
%
tSU
0.5
5
ns
tH
ns
tODZ
Serial Data Out Driven-to- Tri-State Referenced to Positive edge of CS
Time
40
50
20
20
ns
tOZD
Serial Data Out Tri-State-to-Driven
Time
Referenced to Negative edge of SCLK
15
ns
ns
tOD
Serial Data Out Output Delay TIme Referenced to Negative edge of SCLK
15
5
tCSS
tCSH
tIAG
Serial Chip Select Setup TIme
Serial Chip Select Hold TIme
Inter-Access Gap
Referenced to Positive edge of SCLK
Referenced to Positive edge of SCLK
10
10
5
Minimum time Serial Chip Select pin must
be asserted between accesses.
3
Cycles of
SCLK
4
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
CONNECTION DIAGRAM
Top View
24
OPA+
OPA-
ENA
1
2
A3/SDI/DNA
A4/CLK/UPA
A5
23
22
21
20
19
18
17
LMH6517
3
LATA
LATB
ENB
4
5
6
MOD0
MOD1
B5
OPB-
OPB+
7
8
GND
B4/UPB
B3/DNB
Figure 1. 32-Pin WQFN Package
See Package Number RTV0032A
PIN DESCRIPTIONS
Pin Number
Pin Name
Description
Analog I/O
30, 11
IPA+, IPB+
Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed
V+ or go below GND by more than 0.5V.
29, 12
IPA−, IPB−
Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or
go below GND by more than 0.5V.
24, 17
23, 18
Power
OPA+, OPB+
Amplifier non—inverting output. Internally biased to mid supply.
Amplifier inverting output. Internally biased to mid supply.
OPA−, OPB−
13, 15, 26, 28,
center pad
GND
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is internally bonded to the
ground pins.
14, 27
+5V
Power supply pins. Valid power supply range is 4.5V to 5.25V.
Common Control Pins
4, 5
MOD0, MOD1
Digital Mode control pins. These pins float to the logic hi state if left unconnected. See below
for Mode settings.
22, 19
ENA, ENB
Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)
25, 16
31, 10
32, 9
1, 8
A0, B0
A1, B1
A2, B2
A3, B3
A4, B4
A5, B5
Gain bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum Gain)
Gain bit one = 1dB step
Gain bit two = 2dB step
Gain bit three = 4dB step
Gain bit four = 8dB step
Gain bit five = 16dB step
2, 7
3, 6
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PIN DESCRIPTIONS (continued)
Pin Number
21, 20
Pin Name
LATA, LATB
Description
Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high.
Connect to ground if the latch function is not desired.
6
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
Pin Number
Pin Name
Description
Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0)
2
CLK
SDI
CS
Serial Clock
1
Serial Data In (SPI Compatible) See Application Information for more details.
Serial Chip Select (SPI compatible)
32
31
SDO
Serial Data Out (SPI compatible)
3, 4, 6 — 10, 16, 20, GND
21, 25
Pins unused in Serial Mode, connect to DC ground.
Digital Inputs Pulse Mode (MOD1 = 0 , MOD0 = 1)
2, 7
UPA, UPB
DNA, DNB
Up pulse pin. A logic 0 pulse will increase gain one step.
1, 8
Down pulse pin. A logic 0 pulse will decrease gain one step.
1 & 2 or 7 & 8
31, 32
Pulsing both pins together will reset the gain to maximum gain.
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB
Pins unused in Pulse Mode, connect to DC ground.
S0A, S1A
S0B, S1B
GND
10, 9
3, 5, 6, 16, 25
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Typical Performance Characteristics
VCC = 5V
Frequency Response 2dB Gain Steps
Transformer Coupled
Frequency Response 2dB Gain Steps
30
R
= 120Ö
& 5 pF
L
20
25
20
15
10
5
15
10
5
0
0
-5
-5
-10
-10
1
10
100
1000
10
100
1000
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 2.
Figure 3.
Gain Flatness over Temperature
Group Delay
1.00
22.8
22.6
22.4
22.2
22.0
21.8
21.6
21.4
21.2
-40 °C
0 °C
20 °C
50 °C
80 °C
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
50 150 250 350 450 550 650 750 850
0
50
100 150 200 250 300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4.
Figure 5.
Third Order Intercept Point
Third Order Intermodulation Products
vs
vs
Frequency
Frequency
55
-40
POUT = 6 dBm
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
50
45
40
35
30
25
POUT = 6 dBm
100 200
100 200
0
300
400
500
0
300
400
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6.
Figure 7.
8
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Typical Performance Characteristics (continued)
VCC = 5V
Third Order Intercept Point at Various Attenuator Settings
Third Order Intercept Point at Various Attenuator Settings
f = 150 MHz
f = 200 MHz
46
44
42
46
44
42
40
40
38
36
38
36
R
= 100W
R = 100W
L
34
34
L
f = 200 MHz
f = 150 MHz
32
-2
32
-2
0
2
4
6
8
10
0
2
4
6
8
10
OUTPUT POWER (dBm/tone)
OUTPUT POWER (dBm/tone)
Figure 8.
Figure 9.
Third Order Intercept Point at Various Attenuator Settings
f = 250 MHz
Third Order Intermodulation at Various Attenuator Settings
f = 200 MHz
46
-30
R
L
= 100W
f = 200 MHz
44
-40
-50
42
40
38
36
34
32
-60
-70
-80
R
L
= 100W
-90
10
f = 250 MHz
-100
-2
0
2
4
6
8
10
-2
0
2
4
6
8
OUTPUT POWER (dBm/tone)
OUTPUT POWER (dBm/tone)
Figure 10.
Figure 11.
OIP3
vs
Temperature
Gain Shift
vs
Temperature
0.3
50
P
= 3 dBm / TONE
OUT
48
46
44
42
40
38
36
34
f = 200 MHz
MAXIMUM GAIN
0.2
0.1
0
ATT=0 dB
ATT=31 dB
ATT=16 dB
-0.1
-40
-40 -20
0
20 40 60 80 100 120
-10
20
50
80
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VCC = 5V
Cumulative Gain Error
vs
Attenuator Setting
Cumulative Gain Error over Temperature
0.4
0.3
0.4
0.3
0.2
0.1
0
f = 200 MHz
0.2
TEMP = -40
TEMP = 25
0.1
-0.1
-0.2
-0.3
-0.4
0.0
-0.1
-0.2
TEMP = 85
5
0
6
13
19
26
32
0
10
20
25
30
15
DVGA ATTENUATOR SETTING (dB)
ATTENUATION (0 = MAX GAIN)
Figure 14.
Figure 15.
Phase Shift
vs
Attenuator Setting
Noise Figure
vs
Attenuator Setting
3
2
30
25
20
f = 200 MHz
CH B
1
0
f = 150 MHz
-1
15
-2
-3
-4
-5
f = 70 MHz
10
5
0
6
13
19
26
32
0
5
10
15
20
25
30
ATTENUATION (0 = MAX GAIN)
ATTENUATOR SETTING (0 = MAX GAIN)
Figure 16.
Figure 17.
Noise Figure
vs.
Temperature
Noise Figure
vs
Frequency
9
10
8
7
6
5
8
6
4
2
0
40 80
120
4
-40
0
50 100 150 200 250 300 350 400
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 18.
Figure 19.
10
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Typical Performance Characteristics (continued)
VCC = 5V
Second Order Harmonic Distortion
at 10 MHz
Third Order Harmonic Distortion
at 10 MHz
-40
-50
-60
-70
-80
-90
-20
-38
R
L
= 100W
R = 100W
L
f = 10MHz
f = 10MHz
-56
-74
-92
-110
-4
0
5
9
14
18
-4
0
5
9
14
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 20.
Figure 21.
Second Order Harmonic Distortion
at 75 MHz
Third Order Harmonic Distortion
at 75 MHz
-40
-50
-60
-70
-80
-90
-20
-38
R
L
= 100W
R = 100W
L
f = 75 MHz
f = 75 MHz
-56
-74
-92
-110
-4
0
5
9
14
18
-4
0
5
9
14
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 22.
Figure 23.
Second Order Harmonic Distortion
at 150 MHz
Third Order Harmonic Distortion
at 150 MHz
-40
-50
-60
-70
-80
-90
-10
-28
R
= 100W
R = 100W
L
f = 150 MHz
L
f = 150 MHz
-46
-64
-82
14
14
-100
-4
0
5
9
18
-4
0
5
9
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VCC = 5V
Second Order Harmonic Distortion
at 200 MHz
Third Order Harmonic Distortion
at 200 MHz
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 100W
R = 100W
L
L
f = 200 MHz
f = 200 MHz
-4
0
5
9
14
18
-4
0
5
9
14
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 26.
Figure 27.
Second Order Harmonic Distortion
at 250 MHz
Third Order Harmonic Distortion
at 250 MHz
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 100W
R = 100W
L
f = 250 MHz
L
f = 250 MHz
-4
0
5
9
14
18
-4
0
5
9
14
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 28.
Figure 29.
Max Gain
vs.
Temperature
Supply Current
vs
Temperature
180
23.00
22.75
22.50
22.25
22.00
21.75
21.50
21.25
21.00
R
= 120W
L
and 4.7 pF
170
160
150
140
130
-40 -20
0
20 40 60 80 100 120
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
VCC = 5V
Output Offset Voltage
vs.
Temperature
Pulse Response
10
5
4
3
R
L
= 200W and 4.7 pF
ATT = 0 dB
2
1
0
0
-1
-2
-3
-4
-5
-40 -20
-10
0
20 40 60 80 100 120
0
5
10
15
20
25
TEMPERATURE (°C)
TIME (ns)
Figure 32.
Figure 33.
Gain Change Timing
Enable Timing Maximum Gain
0.4
0.4
0.3
0.2
0.1
0
3
3.0
2.5
2.0
1.5
1.0
0.5
0
0.3
0.2
0.1
0
2
1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
0
ATT = 0 dB
-1
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
TIME (ns)
Figure 34.
Figure 35.
Enable Timing Minimum Gain
Channel To Channel Crosstalk
3.5
0.4
0.3
0.2
0.1
0
-30
-40
-50
-60
-70
-80
-90
-100
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-0.1
-0.2
-0.3
-0.4
ATT = 32.5 dB
0
10 20 30 40 50 60 70 80 90 100
10
100
1000
TIME (ns)
FREQUENCY (MHz)
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
VCC = 5V
Input Impedance (S11)
Output Impedance (S22)
250
200
150
100
50
50
40
30
20
10
0
0
-50
10
-10
10
100
1000
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 38.
Figure 39.
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APPLICATION INFORMATION
The LMH6517 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6517
has a 200Ω input and a low impedance output. The gain is digitally controlled over a 31.5 dB range from +22dB
to −9.5dB. The LMH6517 is optimized for accurate gain steps and minimal phase shift combined with low
distortion products. This makes the LMH6517 ideal for voltage amplification and an ideal ADC driver where high
linearity is necessary. The LMH6517 was designed for differential signal inputs only. Single ended inputs require
a balun or transformer as shown on the evaluation board.
V
CC
½ LMH6517
RF
200
ADC
LO
6
GAIN 0-5
LATCH
Figure 40. LMH6517 Typical Application
5
4
3
1.25 V
P
COMMON MODE
= 2.5V
2
1
0
0
45 90 135 180 225 270 315 360
PHASE (°)
Figure 41. Output Voltage with Respect to the Output Common Mode
In order to help with system design TI offers the SP16160CH1RB High IF Receiver reference design board. This
board combines the LMH6517 DVGA with the ADC16DV160 ADC and provides a ready made solution for many
IF receiver applications. The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB
carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain
amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of
the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6
dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86 dBm. In this blocking condition, the
receiver sensitivity is determined by the ADC’s high spurious-free dynamic range (SFDR).
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Channel A
0 to -
Attenuator
31.5 dB
22 dB
22 dB
Attenuator
-
0 to 31.5 dB
Channel B
Figure 42. LMH6517 Block Diagram
INPUT CHARACTERISTICS
The LMH6517 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a
range of values as shown in the 5V Electrical Characteristics table. At higher frequencies parasitic reactances
will start to impact the impedance. This characteristic will also depend on board layout and should be verified on
the customer’s system board.
At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At
minimum gain the output is 9 dB or more smaller than the input. In this configuration the input signal will begin to
clip against the ESD protection diodes before the output reaches maximum swing limits. The input signal cannot
swing more than 0.5V below the negative supply voltage (normally 0V) nor should it exceed the positive supply
voltage. The input signal will clip and cause severe distortion if it is too large. Because the input stage self biases
to approximately mid rail the supply voltage will impose the limit for input voltage swing.
At the frequencies where the LMH6517 is the most useful the input impedance is not exactly 200 Ω and it may
not be purely resistive. For many AC coupled applications the impedance can be easily changed using LC
circuits to transform the actual impedance to the desired impedance.
SOURCE IMPEDANCE = 100W
f = 200 MHz
5V
C
1
LMH6517
V
IN
L
1
Z
IN
C
2
L = 160 nH
1
5
C = 16 pF
1
GAIN 1-5
LATCH
C = 16 pF
2
Z
= (200)W
AMP
Z
IN
= (100)W
Figure 43. Differential 200Ω LC Conversion Circuit
In Figure 43 a circuit is shown that matches the amplifier 200Ω input with a source of 100Ω. This would be the
case when connecting the LMH6517 directly to many common types of 50Ω test equipment. For an easy way to
calculate the L and C circuit values there are several options for online tools or down-loadable programs. The
following tool might be helpful.
http://www.circuitsage.com/matching/matcher2.html
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Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate
complex numbers.
OUTPUT CHARACTERISTICS
The LMH6517 has a low impedance output very similar to a traditional Op-amp output. This means that nearly
any load can be driven with minimal gain loss. Matching load impedance for proper termination of filters is as
easy as inserting the proper value of resistor between the filter and the amplifier. This flexibility makes system
design and gain calculations very easy. The LMH6517 was designed to run from a single 5V supply. In spite of
this low supply voltage the LMH6517 is still able to deliver very high power gains when driving low impedance
loads.
The ability of the LMH6517 to drive low impedance loads creates an opportunity to greatly increase power gain, if
required. One example of using power gain to offset filter loss is shown in Figure 59. A graph showing power
gain over various load conditions is shown below in Figure 44. This graph clearly shows the reduction in power
gain caused by back termination. While many RF amplifiers have internal resistance and deliver maximum power
into a matched load the LMH6517 has an output resistance very near to zero Ohms. The graph shows that
maximum power transfer does indeed occur with a load of nearly zero Ohms. Another useful feature of the graph
is the ability to determine how much gain can be recovered by dropping load resistance when it is necessary to
back terminate either a transmission line or a filter.
40
35
30
25
20
15
10
5
1
10
100
1000
LOAD RESISTANCE (W)
Figure 44. Power Gain vs Load
Note 6dB power loss when adding load matching resistors.
Here is an example of how to use the chart in Figure 44. In a system it is desired to have at least 20dB of
maximum gain from the amplifier input to output. The system noise and harmonic distortion requirements dictate
a 200 Ohm filter between the amplifier and the ADC. Using the chart we can see that a back terminated 200
Ohm filter will result in a net 16 dB of gain at the filter input. To recover this loss it is possible to use a 1:4 balun
to drop the load condition of the filter to 50 Ohms at the amplifier output. This gives an additional 6dB of power
gain. Since the transformer has a power loss of approximately 1dB we end up with 21dB of gain at the filter
output instead of 16dB. See Figure 59 for an example where the filter performs the impedance transformation
function.
The LMH6517, like most high frequency amplifiers, is sensitive to loading conditions on the output. Load
conditions that include small amounts of capacitance connected directly to the output can cause stability
problems. In order to ensure output stability resistors should be connected directly at the amplifier output
followed by a small capacitor. This circuit sets a dominant pole that will cancel out board parasitics in most
applications. An example of this is shown in figure Figure 45 . In this example the amplifier and ADC are less
than 0.1 wavelength apart and do not require a terminated transmission line. A more sophisticated filter may
require better impedance matching. Some example filters are shown later.
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f = 140 MHz
0.01m
10
10
+IN
ADC16DV160
V
RM
+
12p
12p
220n
100
100
4.7p
LMH6517
200W
.
-IN
-
0.01m
Figure 45. Output Configuration
DIGITAL CONTROL
The LMH6517 will support three modes of control, parallel mode, serial mode (SPI compatible) and pulse mode.
Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with
existing SPI compatible systems. The pulse mode is both fast and compact, but must step through intermediate
gain steps when making large gain changes.
The LMH6517 has gain settings covering a range of 31.5 dB. To avoid undesirable signal transients the
LMH6517 should not be powered on with large inputs signals present. Careful planning of system power on
sequencing is especially important to avoid damage to ADC inputs.
The LMH6517 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a
simple voltage divider at each logic pin will allow for this. To properly terminate 100Ω transmission lines a divider
with a 66.5Ω resistor to ground and a 33.2Ω series resistor will properly terminate the line as well as give the
3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic
pins.
Some pins on the LMH6517 have different functions depending on the digital control mode. These functions will
be described in the sections to follow.
Control Mode
MOD1 Pin Value
MOD0 Pin Value
Parallel
Serial
1
1
0
0
1
0
1
0
Pulse
Reserved
PARALLEL MODE (MOD1= 1, MOD0 = 1)
Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space
dedicated to control lines. When designing a system that requires very fast gain changes parallel mode is the
best selection.
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24
23
22
21
20
19
18
17
OPA+
OPA-
ENA
1
2
3
4
5
6
7
8
A3
A4
LMH6517
A5
LATA
LATB
ENB
+3.3/NC
+3.3/NC
B5
OPB-
OPB+
GND
B4
B3
Figure 46. Pin Functions for Parallel Mode
The LMH6517 has a 6-bit gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain
control pins is immediately sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin
transitions high the current gain state is held and subsequent changes to the gain set pins are ignored. To
minimize gain change glitches multiple gain control pins should not change while the latch pin is low. In order to
achieve the very fast gain step switching time of 5 ns the internal gain change circuit is very fast. Gain glitches
could result from timing skew between the gain set bits. This is especially the case when a small gain change
requires a change in state of three or more gain control pins. If continuous gain control is desired the Latch pin
can be tied to ground. This state is called transparent mode and the gain pins are always active. In this state the
timing of the gain pin logic transitions should be planned carefully to avoid undesirable transients
ENA and ENB pins are provided to reduce power consumption by disabling the highest power portions of the
LMH6517. The gain register will preserve the last active gain setting during the disabled state. These pins will
float high and can be left disconnected if they won't be used. If the pins are left disconnected a 0.01uF capacitor
to ground will help prevent external noise from coupling into these pins. See Typical Performance Characteristics
for disable and enable timing information.
DVGA
cmode
FPGA/DSP/mC/ASIC
V
SS
latcha
latcha
6
6
ga[5:0]
gb[5:0]
latchb
pd
ga[5:0]
gb[5:0]
latchb
pd
Pins: 15
MSPS: 125
Low Skew
Figure 47. Parallel Mode Connection for Fastest Response
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FPGA/DSP/mC/ASIC
DVGA
cmode
V
SS
V
SS
latcha
6
ga[5:0]
gb[5:0]
ga[5:0]
gb[5:0]
latchb
pd
6
Pins: 13
MSPS: 333
High Skew
V
SS
pd
Figure 48. Parallel Mode Connection Not Using Latch Pins (Latch pins tied to logic low state)
FPGA/DSP/mC/ASIC
DVGA
cmode
V
SS
latcha
latcha
6
ga/gb[5:0]
ga[5:0]
gb[5:0]
latchb
pd
Pins: 9
MSPS: 62.5
Low Skew
latchb
pd
Figure 49. Parallel Mode Connection Using Latch Pins to Mulitplex Digital Data
SPI COMPATIBLE SERIAL INTERFACE (MOD1= 1, MOD0 = 0)
Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4
wires for both channels allows for significant board space savings. The trade off for this reduced board
complexity is slower response time in gain state changes. For systems where gain is changed only infrequently
or where only slow gain changes are required serial mode is the best choice.
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24
23
22
21
20
19
18
17
OPA+
OPA-
ENA
1
2
3
4
5
6
7
8
SDI
CLK
LMH6517
GND
GND
GND
ENB
GND
+3.3/NC
GND
OPB-
OPB+
GND
GND
GND
Figure 50. Pin Functions for Serial Mode
The LMH6517 has a serial interface that allows access to the control registers. The serial interface is a generic
4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers
and DSP controllers.
The serial mode is active when the two mode pins are set as follows: MOD1=1, MOD0=0). In this configuration
the pins function as shown in the pin description table. The SPI interface uses the following signals: clock input
(CLK), serial data in (SDI), serial data out, and serial chip select (CS)
ENA and ENB pins are active in the serial mode. For fast disable capability these pins can be used and the serial
register will hold the last active gain state. These pins will float high and can be left disconnected for serial mode.
The serial control bus can also disable the DVGA channels, but at a much slower speed. The serial enable
function is an AND function. For a channel to be active both the Enable pin and the serial control register must
be in the enabled state. To disable a channel either method will suffice. See Typical Performance Characteristics
for disable and enable timing information.
LATA and LATB pins are not active during serial mode.
CLK: This pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the
rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it
in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled
or disabled.
CS: This pin is the chip select pin. Each assertion starts a new register access - i.e., the SDATA field protocol is
required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the
16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the
case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the
deasserted pulse - which is specified in Electrical Characteristics.
SDI: This pin is an input for the serial data. It must observe setup/hold requirements with respect to the SCLK.
Each cycle is 16-bits long
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SDO: This is the data output pin. Ths SDO pin is an open drain output and requires an external bias resistor.
See Figure 51 for resistor sizing guidance. This output is normally at TRI-STATE and is driven only when SCSb
is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the
second 8 SCLK falling edges. Upon power-up, the default register address is 00h.
Each serial interface access cycle is exactly 16 bits long as shown in Figure 52. Each signal's function is
described below. the read timing is shown in Figure 53, while the write timing is shown in figure Figure 54.
FPGA/DSP/uC/ASIC
LMH6517
Clock out
Chip Select out
Data Out
CLK
CS
SDI (MOSI)
SDO (MISO)
Data In
R
V+ (Logic High)
SDO
For SDO (MISO) pin only:
= V+,
V
OH
25W
V
= (V+) - (R/(R+25)) * V+
OL
Recommended:
R = 300 Ohms to 2000 Ohms
V+ (Logic) = 2.5V to 3.3V
Figure 51. SDO Pin External Bias Resistor Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
SCSb
COMMAND FIELD
DATA FIELD
D4 D3
C7
C6
0
C5
0
C4
0
C3
A3
C2
A2
C1
A1
C0
A0
D7
(MSB)
D6
D5
D2
D1
D0
(LSB)
R/Wb
Write DATA
SDI
Reserved (3-bits)
Address (4-bits)
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
Hi-Z
Read DATA
Data (8-bits)
SDO
Single Access Cycle
Figure 52. Serial Interface Protocol (SPI compatible)
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R/Wb
Read / Write bit. A value of 1 indicates a read operation, while a
value of 0 indicates a write operation.
Reserved
ADDR:
DATA
Not used. Must be set to 0.
Address of register to be read or written.
In a write operation the value of this field will be written to the
addressed register when the chip select pin is deasserted. In a read
operation this field is ignored.
st
th
th
1
clock
8
clock
16 clock
SCLK
t
t
CSS
CSH
t
t
CSH
CSS
CSb
t
t
OZD
ODZ
t
OD
SDO
D7
D1
D0
Figure 53. Read Timing
Table 1. Read Timing
Data Output on SDO Pin
Parameter
Description
tCSH
tCSS
tOZD
tODZ
tOD
Chip select hold time
Chip select setup time
Initial output data delay
High impedance delay
Output data delay
t
t
PL
PH
16th clock
SCLK
SDI
t
t
H
SU
Valid Data
Valid Data
Figure 54. Write Timing
Data Written to SDI Pin
Table 2. Write Timing
Data Input on SDI Pin
Parameter
Description
tPL
tPH
tSU
tH
Minimum clock low time (clock duty dycle)
Minimum clock high time (clock duty cycle)
Input data setup time
Input data hold time
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C0
Table 3. Serial Word Format for LMH6517
C7
1= read
0=write
C6
C5
C4
C3
C2
C1
0
0
0
0
0
0
0=Ch A
1=Ch B
Table 4. Serial Word Format for LMH6517 (cont)
Enable
Gb5
Gb4
1=+8dB
Gb3
1=+4dB
Gb2
1=+2dB
Gb1
1=+1dB
Gb0
RES
1=On
0=Off
1=+16dB
1=+0.5dB
0
PULSE MODE (MOD1= 0, MOD0 = 1)
Pulse mode is a simple yet fast way to adjust gain settings. Using only two control lines per device the LMH6517
gain can be changed by simple up and down signals. Gain steps are selectable either by hard wiring the board
or using two additional logic inputs. For a system where gain changes can be stepped from one gain to the next
and where board space is limited this mode may be the best choice. The ENA and ENB pins are fully active
during pulse mode, and the channel gain state is preserved during the disabled state. See Typical Performance
Characteristics for disable and enable timing information.
24
23
22
21
20
19
18
17
OPA+
OPA-
ENA
1
2
3
4
5
6
7
8
DNA
UPA
LMH6517
GND
GND
GND
ENB
GND
+3.3/NC
GND
OPB-
OPB+
GND
UPB
DNB
Figure 55. Pin Functions for Pulse Mode
The LMH6517 supports a simple pulse up or pulse down control mode. In this mode the gain step size can be
selected from a choice of 0.5, 1, 2 or 6dB steps. In operation the gain can be quickly adjusted either up of down
one step at a time by a negative pulse on the UP or DN pins. This mode of operation is most suitable for
applications where board space is at a premium and high speed gain changes are desired. As shown in
Figure 56 each gain step pulse must have a logic high state of at least tPW= 20 ns and a logic low state of at
least tPG 20 ns for the pulse to register as a gain change signal.
To provide a known gain state there is a reset feature in pulse mode. To reset the gain to maximum gain both
the UP and DN pins must be strobed low together as shown in Figure 56. There must be an overlap of at least
tRW= 20 ns for the reset to register.
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PULSE TIMING
t
t
PW
PG
UP/DN
RESET TIMING
UP
DN
t
RW
Figure 56. Pulse Mode Timing
EXPOSED PAD WQFN PACKAGE
The LMH6517 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It
is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any
case, the thermal dissipation of the device is largely dependent on the attachment of this pad. The exposed pad
should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is
also very important to maintain good high speed layout practices when designing a system board. Please refer to
the LMH6517 evaluation board for suggested layout techniques.
Package information is available on the Texas Instruments web site.
http://www.ti.com/packaging/
INTERFACING TO ADC
The LMH6517 was designed to be used with high speed ADCs such as the ADC16DV160. As shown in
Figure 40, AC coupling provides the best flexibility especially for IF sub-sampling applications. For DC coupled
applications the use of a level shifting amplifier or a resistive biasing network may be possible.
The inputs of the LMH6517 will self bias to the optimum voltage for normal operation. The internal bias voltage
for the inputs is approximately mid rail which is 2.5V with the typical 5V power supply condition. In most
applications the LMH6517 input will need to be AC coupled.
The output common mode voltage is also self biasing to mid supply. This means that for driving most ADCs AC
coupling is required. Since most often a band pass filter is desired between the amplifier and ADC the bandpass
filter can be configured to block the DC voltage of the amplifier output from the ADC input.
3 pF
100W
390 nH
27 nH
200W
41 pF
390 nH
200
100W
3 pF
Figure 57. Bandpass Filter
A. Center Frequency is 140 MHz with a 20 MHz Bandwidth. Designed for 200Ω Impedance
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ADC Noise Filter
Below are filter schematics and a table of values for some common IF frequencies. The filter shown in Figure 58
offers a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is
used on the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the
12 and 14 bit sub-sampling analog to digital converters shown in the Table 6 table.
Table 5. Filter Component Values
Filter Component Values
Fc
75 MHz
40 MHz
100Ω
140 MHz
20 MHz
200Ω
170 MHz
25 MHz
100Ω
250 MHz
Narrow Band
499Ω
BW
Components
R1, R2
L1, L2
C1, C2
C3
390 nH
10 pF
39 0nH
3 pF
560 nH
1.4 pF
32 pF
—
47 pF
22 pF
41 pF
11 pF
L5
220 nH
100Ω
27 nH
200Ω
30 nH
22 nH
R3, R4
100Ω
499Ω
C1
R1
L1
L5
AMP V
-
OUT
ADC V
+
IN
C2
L2
ADC V
-
IN
AMP V
OUT
+
R2
ADC V
CM
Figure 58. Sample Filter
While the filters shown above have excellent performance in most respects they have one very large drawback,
and that is voltage loss. There is a 6dB loss right up front from the matching resistors (R1 and R2 in Figure 58)
and there are additional losses in the filter, primarily due to the resistive losses of the inductors. One solution is
to use larger inductors with higher Q ratings. An even better solution is to use the filter as an impedance
transforming circuit. Designing a filter with a low impedance input and a high impedance output will result in a
voltage gain that can be used to offset the voltage losses. While this solution won't work with high impedance
amplifiers, the LMH6517's low impedance output stage is perfectly suited for it. In essence the additional power
gained from driving a given voltage into a lower value load impedance is used to offset the power lost in the filter
and matching resistors.
The filter shown in Figure 59 uses both an impedance transform as well as a slight input impedance mismatch to
reduce the voltage loss from the amplifier to the ADC input. This configuration makes use of the strengths of the
LMH6517 output stage to deliver the best linearity possible. Due to the low impedance output stage the
LMH6517 can drive a lot of current into a low impedance load and still deliver high linearity signals.
26
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LMH6517
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
AMP V
OUT
-
5
91n
240n
18n
ADC V
+
IN
100
100
27p
4.7p
5
5.2p
ADC V
-
IN
91n
240n
AMP V
OUT
+
ADC V
CM
Figure 59. Impedance Transforming Filter
25 Ω Input 200 Ω Output, 210 MHz Center Frequency
POWER SUPPLIES
The LMH6517 was designed primarily to be operated on 5V power supplies. The voltage range for VCC is 4.5V to
5.25V. A 5V supply provides the best performance while lower supplies will result in less power consumption.
Power supply regulation of 2.5% or better is advised. When operated on a board with high speed digital signals it
is important to provide isolation between digital signal noise and the LMH6517 inputs. The SP16160CH1RB
reference board provides an example of good board layout.
Of special note is that the digital circuits are powered from an internal supply voltage of 3.3V. The logic pins
should not be driven above the absolute maximum value of 3.6V. See DIGITAL CONTROL for details.
Table 6. Compatible High Speed Analog To Digital Converters
Product Number
ADC12L063
Max Sampling Rate (MSPS)
62
Resolution
Channels
12
12
12
12
12
12
12
12
12
12
12
14
14
14
14
14
16
16
8
SINGLE
DUAL
ADC12DL065
ADC12L066
ADC12DL066
CLC5957
65
66
SINGLE
DUAL
66
70
SINGLE
SINGLE
DUAL
ADC12L080
ADC12DL080
ADC12C080
ADC12C105
ADC12C170
ADC12V170
ADC14C080
ADC14C105
ADC14DS105
ADC14155
80
80
80
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
105
170
170
80
105
105
155
155
130
160
500
500
1000
1000
1500
1500
3000
SINGLE
SINGLE
SINGLE
DUAL
ADC14V155
ADC16V130
ADC16DV160
ADC08D500
ADC08500
DUAL
8
SINGLE
DUAL
ADC08D1000
ADC081000
ADC08D1500
ADC081500
ADC08(B)3000
8
8
SINGLE
DUAL
8
8
SINGLE
SINGLE
8
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
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Table 6. Compatible High Speed Analog To Digital Converters (continued)
Product Number
ADC08L060
Max Sampling Rate (MSPS)
60
Resolution
Channels
8
SINGLE
SINGLE
DUAL
ADC08060
ADC10DL065
ADC10065
ADC10080
ADC08100
ADCS9888
ADC08(B)200
ADC11C125
ADC11C170
60
8
65
10
10
10
8
65
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
80
100
170
200
125
170
8
8
11
11
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LMH6517
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SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision J (March 2013) to Revision K
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6517SQ/NOPB
LMH6517SQE/NOPB
LMH6517SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
L6517SQ
SN
SN
L6517SQ
L6517SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6517SQ/NOPB
LMH6517SQE/NOPB
LMH6517SQX/NOPB
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6517SQ/NOPB
LMH6517SQE/NOPB
LMH6517SQX/NOPB
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000
250
208.0
208.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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