LMH6551 [TI]
50 MHz 0.1 dB Bandwidth, 2400 V/μs Slew Rate, 18 ns Settling Time to 0.05%; 50 MHz的0.1分贝带宽， 2400 V / μs摆率， 18 ns的建立时间0.05 ％
| 型号： | LMH6551 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50 MHz 0.1 dB Bandwidth, 2400 V/μs Slew Rate, 18 ns Settling Time to 0.05% |
| 文件： | 总28页 (文件大小：1252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6551
www.ti.com
SNOSAK7C –FEBRUARY 2005–REVISED MARCH 2013
LMH6551 Differential, High Speed Op Amp
Check for Samples: LMH6551
1
FEATURES
DESCRIPTION
The LMH™6551 is a high performance voltage
feedback differential amplifier. The LMH6551 has the
high speed and low distortion necessary for driving
high performance ADCs as well as the current
handling capability to drive signals over balanced
transmission lines like CAT 5 data cables. The
LMH6551 can handle a wide range of video and data
formats.
23
•
370 MHz −3 dB Bandwidth (VOUT = 0.5 VPP
50 MHz 0.1 dB Bandwidth
)
•
•
•
•
2400 V/µs Slew Rate
18 ns Settling Time to 0.05%
−94/−96 dB HD2/HD3 @ 5 MHz
APPLICATIONS
With external gain set resistors, the LMH6551 can be
used at any desired gain. Gain flexibility coupled with
high speed makes the LMH6551 suitable for use as
an IF amplifier in high performance communications
equipment.
•
•
•
•
•
•
•
Differential AD Driver
Video Over Twisted Pair
Differential Line Driver
Single End to Differential Converter
High Speed Differential Signaling
IF/RF Amplifier
The LMH6551 is available in the space saving SOIC
and VSSOP packages.
SAW Filter Buffer/Driver
Typical Application
Figure 1. Single Ended to Differential ADC Driver
R
F
A , R
V
IN
+
V
R
S
R
O
R
G
V
I
+
IN-
-
V
+
V
S
V
CM
R
ADC
IN+
O
R
T
~
-
O
R
G
-
R
M
V
R
F
DesignTarget:
For RM << RG :
VO RF
1
1) Set RT =
Av =
@
1
1
V
RG
I
-
RS RIN
2RG(1+ Av )
2 + Av
RIN @
2) Set RM = RT ||RS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LMH6551
SNOSAK7C –FEBRUARY 2005–REVISED MARCH 2013
www.ti.com
Connection Diagram
1
2
3
4
8
-IN
+IN
-
+
7
6
V
NC
V-
CM
V+
5
-OUT
+OUT
Figure 2. 8-Pin SOIC & VSSOP - Top View
See Package Number D0008A and DGK0008A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
2000V
200V
13.2V
±Vs
Machine Model
Supply Voltage
Common Mode Input Voltage
Maximum Input Current (pins 1, 2, 7, 8)
Maximum Output Current (pins 4, 5)
Maximum Junction Temperature
Soldering Information
30mA
(4)
150°C
See Product Folder at www.ti.com and SNOA549
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200pF.
(4) The maximum output current (IOUT) is determined by device power dissipation limitations.
(1)
Operating Ratings
Operating Temperature Range
Storage Temperature Range
Total Supply Voltage
−40°C to +125°C
−65°C to +150°C
3V to 12V
(2)
Package Thermal Resistance (θJA
)
8-Pin VSSOP
235°C/W
150°C/W
8-Pin SOIC
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is P D= (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
2
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SNOSAK7C –FEBRUARY 2005–REVISED MARCH 2013
(1)
±5V Electrical Characteristics
Single ended in differential out, TA= 25°C, G = +1, VS = ±5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω; Unless specified
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC Performance (Differential)
SSBW
LSBW
Small Signal −3 dB Bandwidth
VOUT = 0.5 VPP
370
MHz
MHz
MHz
MHz
V/μs
ns
Large Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
Slew Rate
VOUT = 2 VPP
VOUT = 4 VPP
VOUT = 2 VPP
4V Step(4)
340
320
50
2400
1.8
Rise/Fall Time
2V Step
Settling Time
2V Step, 0.05%
18
ns
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
VCMbypass capacitor removed
200
MHz
Distortion and Noise Response
HD2
HD2
HD3
HD3
en
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20MHz, RL=800Ω
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
Freq ≥ 1 MHz
−94
−85
−96
−72
6.0
dBc
dBc
dBc
dBc
Input Referred Voltage Noise
Input Referred Noise Current
nV/√Hz
pA/√Hz
in
Freq ≥ 1 MHz
1.5
Input Characteristics (Differential)
VOSD
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
0.5
−0.8
-4
±4
±6
mV
µV/°C
µA
(5)
Input Offset Voltage Average
Temperature Drift
(6)
(5)
IBI
Input Bias Current
0
-10
Input Bias Current Average
Temperature Drift
−2.6
0.03
nA/°C
µA
Input Bias Difference
Difference in Bias currents between the
two inputs
CMRR
RIN
Common Mode Rejection Ratio
Input Resistance
DC, VCM = 0V, VID = 0V
Differential
72
80
5
dBc
MΩ
pF
CIN
Input Capacitance
Differential
1
CMVR
Input Common Mode Voltage Range
CMRR > 53dB
+3.1
−4.6
+3.2
−4.7
V
VCMPin Input Characteristics (Common Mode Feedback Amplifier)
VOSC
Input Offset Voltage
Common Mode, VID = 0
0.5
8.2
−2
±5
±8
mV
µV/°C
μA
(5)
Input Offset Voltage Average
Temperature Drift
(6)
Input Bias Current
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
Copyright © 2005–2013, Texas Instruments Incorporated
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±5V Electrical Characteristics (1) (continued)
Single ended in differential out, TA= 25°C, G = +1, VS = ±5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω; Unless specified
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
70
Typ
75
Max
Units
VCM CMRR
VID = 0V, 1V step on VCM pin, measure
VOD
dB
Input Resistance
25
kΩ
Common Mode Gain
ΔVO,CM/ΔVCM
0.995
0.999
1.005
V/V
Output Performance
Output Voltage Swing
Single Ended, Peak to Peak
±7.38
±7.8
V
±7.18
Output Common Mode Voltage Range VID = 0 V,
±3.69
±50
±3.8
±65
140
V
IOUT
ISC
Linear Output Current
Short Circuit Current
VOUT = 0V
mA
mA
Output Shorted to Ground
VIN = 3V Single Ended(7)
l
Output Balance Error
ΔVOUTCommon Mode
−70
dB
/ΔVOUTDIfferential , VOUT = 0.5 Vpp
Differential, f = 10 MHz
Miscellaneous Performance
AVOL
Open Loop Gain
Differential
DC, ΔVS = ±1V
RL = ∞
70
90
dB
dB
PSRR
Power Supply Rejection Ratio
Supply Current
74
11
12.5
14.5
mA
16.5
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.
(1)
5V Electrical Characteristics
Single ended in differential out, TA= 25°C, G = +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; Unless
specifiedBoldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
SSBW
Parameter
Small Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
Conditions
RL = 500Ω, VOUT = 0.5 VPP
RL = 500Ω, VOUT = 2 VPP
VOUT = 2 VPP
Min
Typ
350
Max
Units
MHz
MHz
MHz
V/μs
ns
LSBW
300
50
Slew Rate
4V Step(4)
1800
2
Rise/Fall Time, 10% to 90%
Settling Time
4V Step
4V Step, 0.05%
17
ns
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
170
MHz
Distortion and Noise Response
HD2
HD2
HD3
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
Freq ≥ 1 MHz
−84
−69
−93
−67
6.0
dBc
dBc
dBc
dBc
Input Referred Noise Voltage
Input Referred Noise Current
nV/√Hz
pA/√Hz
in
Freq ≥ 1 MHz
1.5
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
4
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SNOSAK7C –FEBRUARY 2005–REVISED MARCH 2013
5V Electrical Characteristics (1) (continued)
Single ended in differential out, TA= 25°C, G = +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; Unless
specifiedBoldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input Characteristics (Differential)
VOSD
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
0.5
±4
±6
mV
µV/°C
μA
(5)
Input Offset Voltage Average
Temperature Drift
−0.8
−4
(6)
(5)
IBIAS
Input Bias Current
0
-10
Input Bias Current Average
Temperature Drift
−3
nA/°C
µA
Input Bias Current Difference
Difference in Bias currents between the
two inputs
0.03
CMRR
VICM
Common-Mode Rejection Ratio
Input Resistance
DC, VID = 0V
Differential
70
78
5
dBc
MΩ
pF
Input Capacitance
Differential
1
Input Common Mode Range
CMRR > 53 dB
+3.1
+0.4
+3.2
+0.3
VCMPin Input Characteristics (Common Mode Feedback Amplifier)
Input Offset Voltage
Common Mode, VID = 0
0.5
5.8
±5
±8
mV
Input Offset Voltage Average
Temperature Drift
µV/°C
Input Bias Current
VCM CMRR
3
μA
VID = 0,
70
75
dB
1V step on VCM pin, measure VOD
Input Resistance
VCM pin to ground
25
kΩ
Common Mode Gain
ΔVO,CM/ΔVCM
0.995
0.991
1.005
V/V
Output Performance
VOUT
Output Voltage Swing
Single Ended, Peak to Peak, VS= ±2.5V,
VCM= 0V
±2.4
±45
±2.8
V
IOUT
ISC
Linear Output Current
VOUT = 0V Differential
±60
230
mA
mA
Output Short Circuit Current
Output Shorted to Ground
VIN = 3V Single Ended(7)
CMVR
Output Common Mode Voltage
Range
VID = 0, VCMpin = 1.2V and 3.8V
3.72
1.23
3.8
1.2
V
Output Balance Error
ΔVOUTCommon Mode /ΔVOUTDIfferential,
−65
dB
VOUT = 1Vpp Differential, f = 10 MHz
Miscellaneous Performance
Open Loop Gain
DC, Differential
DC, ΔVS = ±0.5V
RL = ∞
70
88
dB
dB
PSRR
IS
Power Supply Rejection Ratio
Supply Current
72
10
11.5
13.5
mA
15.5
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.
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(1)
3.3V Electrical Characteristics
Single ended in differential out, TA= 25°C, G = +1, VS = 3.3V, VCM = 1.65V, RF = RG = 365Ω, RL = 500Ω; Unless
specifiedBoldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
SSBW
Parameter
Small Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
Slew Rate
Conditions
RL = 500Ω, VOUT = 0.5 VPP
RL = 500Ω, VOUT = 1 VPP
1V Step(4)
Min
Typ
320
Max
Units
MHz
MHz
V/μs
ns
LSBW
300
700
2
Rise/Fall Time, 10% to 90%
1V Step
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
95
MHz
Distortion and Noise Response
HD2
HD2
HD3
HD3
2nd Harmonic Distortion
VO = 1 VPP, f = 5 MHz, RL=800Ω
VO = 1 VPP, f = 20 MHz, RL=800Ω
VO = 1VPP, f = 5 MHz, RL=800Ω
VO = 1VPP, f = 20 MHz, RL=800Ω
−93
−74
−85
−69
dBc
dBc
dBc
dBc
3rd Harmonic Distortion
Input Characteristics (Differential)
VOSD
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
1
mV
(5)
Input Offset Voltage Average
Temperature Drift
1.6
µV/°C
(6)
(5)
IBIAS
Input Bias Current
−8
μA
Input Bias Current Average
Temperature Drift
9.5
nA/°C
Input Bias Current Difference
Difference in Bias currents between the
two inputs
0.3
µA
CMRR
VICM
Common-Mode Rejection Ratio
Input Resistance
DC, VID = 0V
Differential
78
5
dBc
MΩ
pF
Input Capacitance
Differential
1
Input Common Mode Range
CMRR > 53 dB
+1.5
+0.3
VCMPin Input Characteristics (Common Mode Feedback Amplifier)
Input Offset Voltage
Common Mode, VID = 0
1
±5
mV
Input Offset Voltage Average
Temperature Drift
18.6
µV/°C
Input Bias Current
VCM CMRR
3
μA
VID = 0,
60
dB
1V step on VCM pin, measure VOD
Input Resistance
VCM pin to ground
25
kΩ
Common Mode Gain
ΔVO,CM/ΔVCM
0.999
V/V
Output Performance
VOUT
Output Voltage Swing
Single Ended, Peak to Peak, VS= 3.3V,
VCM= 1.65V
±0.75
±30
±0.9
V
IOUT
ISC
Linear Output Current
VOUT = 0V Differential
±40
200
mA
mA
Output Short Circuit Current
Output Shorted to Ground
VIN = 2V Single Ended(7)
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.
6
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SNOSAK7C –FEBRUARY 2005–REVISED MARCH 2013
3.3V Electrical Characteristics (1) (continued)
Single ended in differential out, TA= 25°C, G = +1, VS = 3.3V, VCM = 1.65V, RF = RG = 365Ω, RL = 500Ω; Unless
specifiedBoldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CMVR
Output Common Mode Voltage
Range
VID = 0, VCMpin = 1.2V and 2.1V
2.1
1.2
Output Balance Error
ΔVOUTCommon Mode /ΔVOUTDIfferential,
−65
dB
VOUT = 1Vpp Differential, f = 10 MHz
Miscellaneous Performance
Open Loop Gain
DC, Differential
DC, ΔVS = ±0.5V
RL = ∞
70
75
8
dB
dB
PSRR
IS
Power Supply Rejection Ratio
Supply Current
mA
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Typical Performance Characteristics
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
Frequency Response
vs.
Supply Voltage
Frequency Response
2
1
2
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
V
= 2 V
PP
V
= 2 V
OD PP
OD
V
= 0.5 V
PP
OD
V
= 0.5 V
PP
OD
SINGLE ENDED INPUT
= ±5V
SINGLE ENDED INPUT
V
S
V
S
= 5V
1
10
100
1000
1000
100
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Frequency Response
Frequency Response
vs.
Capacitive Load
vs.
VOUT
2
1
2
1
C
= 5.7 pF, R
= 60W
V
= ±5V
L
OUT
S
0
0
C
= 10 pF, R
= 27 pF, R
= 57 pF, R
= 34W
= 20W
= 15W
L
L
L
OUT
OUT
OUT
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
V
= 1 V
PP
OD
C
V
= 0.5 V
PP
OD
C
LOAD = (CL || 1 kW) IN
SERIES WITH 2 R
OUTS
SINGLE ENDED INPUT
= 3.3V
V
OUT
= 0.5 V
PP
DIFFERENTIAL
V
S
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
Suggested ROUT
vs.
Suggested ROUT
vs.
Cap Load
Cap Load
70
70
60
50
40
60
50
40
30
20
10
30
20
10
LOAD = 1 kW || CAP LOAD
= ±5V
LOAD = 1 kW || CAP LOAD
V
V = 5V
S
S
0
0
10
10
100
1
1
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 7.
Figure 8.
8
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
1 VPP Pulse Response Single Ended Input
2 VPP Pulse Response Single Ended Input
0.8
2.5
2
1.5
1
0.6
0.4
0.2
0
0.5
0
-0.5
-0.2
-1
-1.5
-2
V
= 5V
S
-0.4
-0.6
-0.8
V
= 3.3V
= 500W
= 360W
S
R
= 500W
= 360W
L
F
R
L
F
R
R
-2.5
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
TIME (ns)
Figure 9.
Figure 10.
Large Signal Pulse Response
Output Common Mode Pulse Response
3
2
0.12
V
= ±5V
S
0.1
0.08
0.06
0.04
0.02
0
R
= 500W
= 360W
L
R
F
V
= 4 V
PP
OUT
1
0
-1
-0.02
-0.04
-0.06
-0.08
V
= ±5V
S
R
= 500W
= 360W
L
F
-2
-3
R
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
TIME (ns)
Figure 11.
Figure 12.
Distortion
vs.
Frequency
Distortion
vs.
Frequency
-50
-60
-50
V
V
V
= 5V
V
V
V
= ±5V
HD3
HD3
S
S
= 2 V
PP
= 2 V
PP
OUT
OUT
-60
= 2.5V
= 0V
CM
CM
R
L
= 800W
R
= 800W
L
-70
-80
-90
-70
-80
HD2
HD2
-90
-100
-110
-100
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
Distortion
Distortion
vs.
Supply Voltage (Split Supplies)
vs.
Frequency
-30
-40
-50
V
= 2 V
PP
OUT
f = 5 MHz
= V /2
V
V
V
= 3.3V
S
HD3
= 1 V
PP
OUT
-60
V
CM
S
= 1.65V
CM
-50
-60
R
L
= 800W
-70
-80
-70
HD3
-80
HD2
-90
-90
HD2
-100
-100
3
4
5
6
0
5
10 15 20 25 30 35 40
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
Figure 15.
Figure 16.
Distortion
vs.
Supply Voltage (Single Supply)
Maximum VOUT
vs.
IOUT
-60
-65
-70
-75
-80
-85
-90
-95
-100
4
3.9
3.8
3.7
3.6
3.5
3.4
V
= 4 V
PP
OUT
f = 5 MHz
= 0V
V
CM
HD3
HD2
V
= 3.88V SINGLE ENDED
IN
3.3
3.2
3.1
3
V
A
= ±5V
= 2
S
V
R
= 730W
F
6
7
8
10
11
12
9
-50
-60 -70 -80 -90 -100
0
-10 -20 -30 -40
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 17.
Figure 18.
Minimum VOUT
vs.
IOUT
Closed Loop Output Impedance
100
-3
-3.1
-3.2
-3.3
-3.4
-3.5
-3.6
V
= 3.88V SINGLE ENDED
V
V
= ±5V
= 0V
IN
S
V
A
= ±5V
= 2
IN
S
V
10
1
R
= 730W
F
-3.7
-3.8
0.1
-3.9
-4
0.01
0
50
0.01
1
10
1000
10 20 30 40
60 70 80 90 100
100
0.1
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
Closed Loop Output Impedance
Closed Loop Output Impedance
100
100
V
V
= 5V
= 0V
V
V
= 3.3V
= 0V
S
S
IN
IN
10
1
10
1
0.1
0.1
0.01
0.01
0.01
0.01
1
10
100
1000
1
10
100
1000
0.1
0.1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21.
Figure 22.
PSRR
PSRR
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
PSRR +
PSRR -
V
= ±5V
= 200W
= 0V
V
= +5V
S
S
R
V
R
V
= 200W
L
L
= 2.5V
10
0
10
0
CM
CM
10
1
10
100
1
100
0.01
0.1
1000
0.01
0.1
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23.
Figure 24.
CMRR
Balance Error
80
75
70
65
60
55
50
45
40
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
V
= ±5V
S
R
= 360W
F
R
V
= 500W
L
= 0.5 V
IN
PP
V
V
, CM = 0.5 V
= ±5V
IN
PP
S
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25.
Figure 26.
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APPLICATION SECTION
The LMH6551 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6551, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common mode feedback circuit allows single ended to differential operation.
The LMH6551 is a voltage feedback amplifier with gain set by external resistors. Output common mode voltage
is set by the VCM pin. This pin should be driven by a low impedance reference and should be bypassed to ground
with a 0.1 µF ceramic capacitor. Any signal coupling into the VCM will be passed along to the output and will
reduce the dynamic range of the amplifier.
FULLY DIFFERENTIAL OPERATION
The LMH6551 will perform best when used with split supplies and in a fully differential configuration. See
Figure 27 and Figure 28 for recommend circuits.
R
F1
R
O
R
G1
+
-
C
L
R
L
V
O
V
CM
V
I
~
R
G2
R
O
R
F2
Figure 27. Typical Application
The circuit shown in Figure 27 is a typical fully differential application as might be used to drive an ADC. In this
circuit closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the applications in this data sheet VIN is presumed to be
the voltage presented to the circuit by the signal source. For differential signals this will be the difference of the
signals on each input (which will be double the magnitude of each individual signal), while in single ended inputs
it will just be the driven input signal.
The resistors RO help keep the amplifier stable when presented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the LMH6551 provides excellent distortion, balance and
common mode rejection provided the resistors RF, RG and RO are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80dB, the DC and low frequency CMRR of most circuits will be
dominated by the external resistors and board trace resistance. At higher frequencies board layout symmetry
becomes a factor as well. Precision resistors of at least 0.1% accuracy are recommended and careful board
layout will also be required.
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500
100W
TWISTED PAIR
50W
250
+
V
2 V
PP
CM
~
-
250
2 V
PP
50W
500
GAIN = 2
Figure 28. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6551 makes an
excellent cable driver as shown in Figure 28. The LMH6551 is also suitable for driving differential cables from a
single ended source.
The LMH6551 requires supply bypassing capacitors as shown in Figure 29 and Figure 30. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. The SMT capacitors should be connected directly to a ground plane. Thin traces or small vias will reduce
the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM pin to ground. The
VCM pin is a high impedance input to a buffer which sets the output common mode voltage. Any noise on this
input is transferred directly to the output. Output common mode noise will result in loss of dynamic range,
degraded CMRR, degraded Balance and higher distortion. The VCM pin should be bypassed even if the pin in not
used. There is an internal resistive divider on chip to set the output common mode voltage to the mid point of the
supply pins. The impedance looking into this pin is approximately 25 kΩ. If a different output common mode
voltage is desired drive this pin with a clean, accurate voltage reference.
+
+
V
V
0.01 mF
0.01 mF
10 mF
10 mF
0.01 mF
+
-
+
V
CM
0.1 mF
V
CM
0.1 mF
-
0.1 mF
0.01 mF
10 mF
-
V
Figure 29. Split Supply Bypassing Capacitors
Figure 30. Single Supply Bypassing Capacitors
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SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
The LMH6551 provides excellent performance as an active balun transformer. Figure 31 shows a typical
application where an LMH6551 is used to produce a differential signal from a single ended source.
In single ended input operation the output common mode voltage is set by the VCM pin as in fully differential
mode. Also, in this mode the common mode feedback circuit must recreate the signal that is not present on the
unused differential input pin. Figure 26 is the measurement of the effectiveness of this process. The common
mode feedback circuit is responsible for ensuring balanced output with a single ended input. Balance error is
defined as the amount of input signal that couples into the output common mode. It is measured as a the
undesired output common mode swing divided by the signal on the input. Balance error can be caused by either
a channel to channel gain error, or phase error. Either condition will produce a common mode shift. Figure 26
measures the balance error with a single ended input as that is the most demanding mode of operation for the
amplifier.
Supply and VCM pin bypassing are also critical in this mode of operation. See the above section on FULLY
DIFFERENTIAL OPERATION for bypassing recommendations and also see Figure 29 and Figure 30 for
recommended supply bypassing configurations.
R
F
A , R
V
IN
+
V
R
R
R
S
O
G
V
I
V
V
I1
O1
+
IN-
-
V
+
V
S
V
CM
R
ADC
IN+
O
R
T
~
-
V
O2
V
I2
O
R
G
-
R
M
V
+
-
R
F
Conditions :
RS = RT||RIN
RM = RT ||RS
Definitions :
RG
ꢀ1 =
RG + RF
RG + RM
RG + RM + RF
ꢀ2 =
VO 2(1-ꢀ1) RF
Av =
=
@
for RM << RG
V
ꢀ1 + ꢀ2
RG
I
ꢀ2
RG(1+
)
2RG + RM(1-ꢀ2)
1+ ꢀ2
ꢀ1
1+ ꢀ2
2RG(1+ Av )
RIN
=
=
@
for RM << RG
2 + Av
VO1 + VO2
VOCM = VCM
=
(by design)
2
V + V
VOCM
I1
I2
V
=
= VOCM.ꢀ2 @
for RM << RG
ICM
2
1+ Av
Figure 31. Single Ended In to Differential Out
SINGLE SUPPLY OPERATION
The input stage of the LMH6551 has a built in offset of 0.7V towards the lower supply to accommodate single
supply operation with single ended inputs. As shown in Figure 31, the input common mode voltage is less than
the output common voltage. It is set by current flowing through the feedback network from the device output. The
input common mode range of 0.4V to 3.2V places constraints on gain settings. Possible solutions to this
limitation include AC coupling the input signal, using split power supplies and limiting stage gain. AC coupling
with single supply is shown in Figure 32.
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In Figure 31 closed loop gain = VO / VI ≊ RF / RG, where VI =VS / 2, as long as RM << RG. Note that in single
ended to differential operation VI is measured single ended while VO is measured differentially. This means that
gain is really 1/2 or 6 dB less when measured on either of the output pins separately. Additionally, note that the
input signal at RT (labeled as VI) is 1/2 of VS when RT is chosen to match RS to RIN.
VICM = Input common mode voltage = (VI1+VI2) / 2.
R
F
R
O
V
O
1
V 1
I
R
R
G
S
+
C
L
R
L
V
O
V
CM
R
V
T
I
~
-
R
G
V 2
I
V
O
2
R
M
R
O
R
F
VICM = VOCM
VO1 + VO2
*VCM
=
VI1 + VI2
2
VICM
=
*BY DESIGN
2
Figure 32. AC Coupled for Single Supply Operation
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load conditions. They typically have high impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 33 shows a typical circuit for driving an ADC. The two
56Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In
addition, the resistors form part of a low pass filter which helps to provide anti alias and noise reduction
functions. The two 39 pF capacitors help to smooth the current spikes associated with the internal switching
circuits of the ADC and also are a key component in the low pass filtering of the ADC input. In the circuit of
Figure 33the cutoff frequency of the filter is 1/ (2*π*56Ω *(39 pF + 14pF)) = 53MHz (which is slightly less than
the sampling frequency). Note that the ADC input capacitance must be factored into the frequency response of
the input filter, and that being a differential input the effective input capacitance is double. Also as shown in
Figure 33 the input capacitance to many ADCs is variable based on the clock cycle. See the data sheet for your
particular ADC for details.
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R
F1
56
ADC12LO66
R
G1
39 pF
+
V
-
V
I
~
CM
7 - 8 pF
39 pF
56
R
G2
V
REF
R
F2
1V LOW IMPEDANCE
VOLTAGE REFERENCE
Figure 33. Driving an ADC
The amplifier and ADC should be located as closely together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 for more details on the subsampling process and the requirements this imposes on the filtering
necessary in your system.
USING TRANSFORMERS
Transformers are useful for impedance transformation as well as for single to differential, and differential to single
ended conversion. A transformer can be used to step up the output voltage of the amplifier to drive very high
impedance loads as shown in Figure 34. Figure 36 shows the opposite case where the output voltage is stepped
down to drive a low impedance load.
Transformers have limitations that must be considered before choosing to use one. Compared to a differential
amplifier, the most serious limitations of a transformer are the inability to pass DC and balance error (which
causes distortion and gain errors). For most applications the LMH6551 will have adequate output swing and drive
current and a transformer will not be desirable. Transformers are used primarily to interface differential circuits to
50Ω single ended test equipment to simplify diagnostic testing.
300W TWISTED PAIR
500
1:2 (TURNS)
37.5W
250
+
-
V
CM
4 V
PP
~
V
CM
250
8 V
PP
R
L
= 300W
37.5W
500
A
= 2
V
Figure 34. Transformer Out High Impedance Load
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VIN * AV * N
2 ROUT * N2
VL =
«
∆
∆
≈
≈
∆
∆
«
+ 1
RL
WHERE VIN = DIFFERENTIAL INPUT VOLTAGE
N = TRANSFORMER TURNS RATIO =
«
∆
∆
≈
≈
∆
∆
«
SECONDARY
PRIMARY
AV = CLOSED LOOP AMPLIFIER GAIN
ROUT = SERIES OUTPUT MATCHING RESISTOR
RL = LOAD RESISTOR
VL = VOLTAGE ACROSS LOAD RESISTOR
Figure 35. Calculating Transformer Circuit Net Gain
100W TWISTED PAIR
375
2:1 (TURNS)
200W
375
+
-
V
CM
4 V
PP
~
V
CM
375
1 V
PP
R
L
= 100W
200W
375
A
= 1
V
Figure 36. Transformer Out Low Impedance Load
50W COAX
375
2:1 (TURNS)
100W
375
+
-
V
CM
4 V
PP
~
C
1
375
1 V
PP
100W
375
GAIN = 1
IS NOT REQUIRED IF V
C
1
= GROUND
CM
Figure 37. Driving 50Ω Test Equipment
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CAPACITIVE DRIVE
As noted in DRIVING ANALOG TO DIGITAL CONVERTERS, capacitive loads should be isolated from the
amplifier output with small valued resistors. This is particularly the case when the load has a resistive component
that is 500Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component
could be 1000Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using
matching resistors will be sufficient to isolate any subsequent capacitance. For other applications see Figure 7
and Figure 8 in Typical Performance Characteristics.
POWER DISSIPATION
The LMH6551 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance,
thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAXof 150°C is
never exceeded due to the overall power dissipation.
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Follow these steps to determine the Maximum power dissipation for the LMH6551:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
•
VS = V+ - V−
(1)
Be sure to include any current through the feedback network if VOCM is not mid rail.
2. Calculate the RMS power dissipated in each of the output stages:
PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS − V−OUT) * I−
)
OUT
where
•
VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were
single ended amplifiers and VS is the total supply voltage
(2)
3. Calculate the total RMS power:
PT = PAMP + PD.
(3)
The maximum power that the LMH6551 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SOIC package θJA is 150°C/W.
(4)
NOTE
If VCM is not 0V then there will be quiescent current flowing in the feedback network. This
current should be included in the thermal calculations and added into the quiescent power
dissipation of the amplifier.
ESD PROTECTION
The LMH6551 is protected against electrostatic discharge (ESD) on all pins. The LMH6551 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6551 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins.
BOARD LAYOUT
The LMH6551 is a very high performance amplifier. In order to get maximum benefit from the differential circuit
architecture board layout and component selection is very critical. The circuit board should have a low
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as
should the supply bypass capacitors. The LMH730154 evaluation board is an example of good layout
techniques.
The LMH6551 is sensitive to parasitic capacitances on the amplifier inputs and to a lesser extent on the outputs
as well. Ground and power plane metal should be removed from beneath the amplifier and from beneath RF and
RG.
With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors.
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EVALUATION BOARD
Texas Instruments offers evaluation board(s) to aid in device testing and characterization and as a guide for
proper layout. Generally, a good high frequency layout will keep power supply and ground traces away from the
inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response
peaking and possible circuit oscillations (see Application Note OA-15 for more information).
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMH6551MA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
LMH65
51MA
LMH6551MA/NOPB
LMH6551MAX
ACTIVE
ACTIVE
ACTIVE
D
D
D
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
-40 to 85
LMH65
51MA
2500
2500
TBD
-40 to 85
LMH65
51MA
LMH6551MAX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
LMH65
51MA
LMH6551MM
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
AU1A
LMH6551MM/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
AU1A
LMH6551MMX
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
3500
3500
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
AU1A
AU1A
LMH6551MMX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6551MAX
LMH6551MAX/NOPB
LMH6551MM
SOIC
SOIC
D
8
8
8
8
8
8
2500
2500
1000
1000
3500
3500
330.0
330.0
178.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
6.5
6.5
5.3
5.3
5.3
5.3
5.4
5.4
3.4
3.4
3.4
3.4
2.0
2.0
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
D
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
LMH6551MM/NOPB
LMH6551MMX
LMH6551MMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6551MAX
LMH6551MAX/NOPB
LMH6551MM
SOIC
SOIC
D
8
8
8
8
8
8
2500
2500
1000
1000
3500
3500
367.0
367.0
210.0
210.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
D
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
LMH6551MM/NOPB
LMH6551MMX
LMH6551MMX/NOPB
Pack Materials-Page 2
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