LMH6572MQ/NOPB [TI]
具有三路 2:1 高速多路复用器的 350MHz 高速运算放大器 | DBQ | 16 | -40 to 85;
| 型号： | LMH6572MQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三路 2:1 高速多路复用器的 350MHz 高速运算放大器 | DBQ | 16 | -40 to 85 放大器 光电二极管 运算放大器 复用器 |
| 文件： | 总26页 (文件大小：1726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6572
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
LMH6572 三通道 2:1 高速视频多路复用器
1 特性
3 说明
1
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•
•
•
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350MHz、250mV、−3dB 带宽
LMH6572 是一款经过优化的高性能模拟多路复用器，
适用于专业级视频应用和其他高保真度、高带宽模拟
应用。LMH6572 可在 2VPP 输出信号电平提供
290MHz 带宽。140MHz 的 0.1dB 带宽和 1500V/µs
的压摆率使得该部件适用于高清电视 (HDTV) 和高分辨
率多媒体视频 应用。
290MHz、2VPP、−3dB 带宽
10ns 通道开关时间
90dB 通道到通道隔离（在 5MHz 条件下）
0.02% 差分增益，0.02° 差分相位
0.1dB 增益平坦度：140MHz
1400V/μs 压摆率
LMH6572 针对 NTSC 和 PAL 视频信号的差分增益误
差和差分相位误差分别为 0.02% 和 0.02°，支持复合
视频 应用 ，同时可驱动后部端接的单个 75Ω 负载。
LM6572 可提供 80mA 线性输出电流来驱动多个视频
负载 应用。
宽电源电压范围：
6V (±3V) 至 12V (±6V)
•
•
10MHz 时为 −78dB HD2
10MHz 时为 −75dB HD3
2 应用
LMH6572 具有 2V/V (+6dBv) 的内部增益，能够以
1V/V (0dBv) 的净增益驱动后部端接传输线。
•
•
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RGB 视频路由器
多输入视频监控器
容错数据开关
LMH6572 可提供 SSOP 封装。
器件信息(1)
器件型号
LMH6572
封装
SSOP (16)
封装尺寸（标称值）
4.90mm × 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNCS102
LMH6572
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
www.ti.com.cn
目录
7.1 Overview ................................................................. 11
7.2 Feature Description................................................. 11
Power Supply Recommendations...................... 15
8.1 Power Dissipation ................................................... 15
8.2 ESD Protection........................................................ 15
Layout ................................................................... 16
9.1 Layout Guidelines ................................................... 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 ±5V Electrical Characteristics ................................... 5
6.6 ±3.3V Electrical Characteristics ................................ 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
8
9
10 器件和文档支持 ..................................................... 17
10.1 接收文档更新通知 ................................................. 17
10.2 社区资源................................................................ 17
10.3 商标....................................................................... 17
10.4 静电放电警告......................................................... 17
10.5 术语表 ................................................................... 17
11 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (May 2013) to Revision G
Page
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已删除 预览水印...................................................................................................................................................................... 1
已添加 器件信息 表、引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、电源建议 部分、布局 部分、器件和
文档支持 部分以及机械、封装和可订购信息 部分 ................................................................................................................. 1
•
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Deleted bolding from Electrical Characteristics specifications, added temperature range to test conditions for clarification 5
Changed Overview title from General Information .............................................................................................................. 11
Changed Layout Considerations title to Layout Guidelines.................................................................................................. 16
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 16
2
Copyright © 2005–2018, Texas Instruments Incorporated
LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
Truth Table
SEL
0
EN
OUT
CH 1
0
0
1
1
CH 0
X
Disable
Copyright © 2005–2018, Texas Instruments Incorporated
3
LMH6572
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
see
MIN
MAX
13.2
130
UNIT
V
Supply Voltage (V+ − V−)
(3)
IOUT
mA
V
Input Voltage Range
Maximum Junction Temperature(4)
±(VS)
+150
+150
°C
Storage temperature, Tstg
–65
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section for
more details. A short circuit condition should be limited to 5 seconds or less.
(4) Human Body Model, 1.5 kΩ in series with 100 pF. Machine Model 0 Ω in series with 200 pF.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(1)
see
MIN
–40
6
NOM
MAX
85
UNIT
°C
Operating Temperature
Supply Voltage Range
12
V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
6.4 Thermal Information
LMH6572
THERMAL METRIC(1)
DBQ (SSOP)
16 PINS
125
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
36
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2005–2018, Texas Instruments Incorporated
LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
6.5 ±5V Electrical Characteristics
VS = ±5 V and RL = 100 Ω, (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
–3 dB Bandwidth
–3 dB Bandwidth(2)
VOUT = 0.25 VPP
350
290
MHz
MHz
MHz
VOUT = 2 VPP
250
.1 dBBW 0.1 dB Bandwidth
VOUT = 0.25 VPP
140
DG
DP
Differential Gain
RL = 150 Ω, f = 4.43 MHz
RL = 150 Ω, f = 4.43 MHz
0.02%
0.02
Differential Phase
deg
TIME DOMAIN RESPONSE
TRS
Channel to Channel Switching Time
Logic Transition to 90% Output
10
11
ns
ns
ns
ns
Enable and Disable Times
Rise and Fall Time
Settling Time to 0.05%
Overshoot
Logic Transition to 90% or 10% Output
TRL
TSS
OS
2-V Step
2-V Step
4-V Step
4-V Step
1.5
17
5%
1400
SR
Slew Rate(2)
1200
V/µs
DISTORTION
HD2
HD3
IMD
2nd Harmonic Distortion
3rd Harmonic Distortion
3rd Order Intermodulation Products
2 VPP , 10 MHz
−78
−75
−80
dBc
dBc
dBc
2 VPP , 10 MHz
10 MHz, Two tones 2 VPP at Output
EQUIVALENT INPUT NOISE
VN
Voltage
Current
>1 MHz, Input Referred
>1 MHz, Input Referred
5
5
nV√Hz
pA/√Hz
ICN
STATIC, DC PERFORMANCE
GAIN
Voltage Gain
2.0
V/V
No load, with respect to nominal gain of
2.00 V/V
±0.3%
±0.5%
±0.7%
Gain Error(3)
No load, with respect to nominal gain of
2.00 V/V, TA = –40°C to +85°C
±0.3%
0.3%
RL = 50 Ω, with respect to nominal gain
of 2.00 V/V
Gain Error
VIN = 0 V
1
1
±14
VIO
Output Offset Voltage(3)
Average Drift
mV
µV/°C
µA
VIN = 0 V, TA = –40°C to +85°C
±17.5
DVIO
IBN
27
VIN = 0 V
−1.4
−1.4
7
±5.0
±5.6
Input Bias Current(3)(4)
Average Drift
VIN = 0 V, TA = –40°C to +85°C
DIBN
PSRR
nA/°C
dB
DC, Input referred
50
48
20
20
54
Power Supply Rejection Ratio(3)
DC, Input referred, TA = –40°C to +85°C
No load
54
23
25
28.5
2.2
ICC
Supply Current(3)
mA
No load, TA = –40°C to +85°C
No load
23
2.0
2.0
Supply Current Disabled(3)
Logic High Threshold(3)
mA
V
No load, TA = –40°C to +85°C
Select and Enable Pins
2.3
VIH
2.0
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See the Power Dissipation section for information on temperature de-rating of this
device. Minimum and maximum ratings are based on product testing, characterization and simulation. Individual parameters are tested
as noted.
(2) Parameters ensured by design.
(3) Parameters ensured by electrical testing at 25° C.
(4) Positive Value is current into device.
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±5V Electrical Characteristics (continued)
VS = ±5 V and RL = 100 Ω, (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
VIL
IiL
Logic Low Threshold(3)
Select and Enable Pins
0.8
±5.0
±15
200
V
Logic Input = 0 V
−1
−1
Logic Pin Input Current Low(4)
µA
Logic Input = 0 V, TA = –40°C to +85°C
Logic Input = 2.0 V
112
100
150
IiH
Logic Pin Input Current High(4)
µA
Logic Input = 2.0 V, TA = –40°C to
+85°C
150
210
MISCELLANEOUS PERFORMANCE
650
620
800
800
940
Internal Feedback and Gain Set
Resistor Values
RF
Ω
TA = –40°C to +85°C
1010
Internal Feedback and Gain Set
Resistors in Series to Ground
RODIS
Disabled Output Resistance
1.3
1.6
1.88
kΩ
RIN+
CIN
Input Resistance
Input Capacitance
Output Resistance
100
0.9
kΩ
pF
Ω
ROUT
0.26
±3.9
±3.9
±3.53
±3.53
±2.5
±80
No Load
±3.83
±3.80
±3.52
±3.5
±2
VO
V
No Load, TA = –40°C to +85°C
RL = 100 Ω
Output Voltage Range
VOL
CMIR
IO
V
V
RL = 100 Ω, TA = –40°C to +85°C
Input Voltage Range
VIN = 0 V
+70
Linear Output Current(3)(4)
mA
VIN = 0 V, TA = –40°C to +85°C
VIN = ±2 V, Output Shorted to Ground
VIN = 2 VPP at 5 MHz
40
±80
ISC
Short Circuit Current(5)
±230
-90
mA
dBc
dBc
dBc
XTLK
XTLK
XTLK
Channel to Channel Crosstalk
Channel to Channel Crosstalk
All Hostile Crosstalk
VIN = 2 VPP at 100 MHz
-54
In A, C, Out B, VIN = 2 VPP at 5 MHz
-95
(5) The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section for
more details. A short circuit condition should be limited to 5 seconds or less.
6
Copyright © 2005–2018, Texas Instruments Incorporated
LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
6.6 ±3.3V Electrical Characteristics
VS = ±3.3 V, RL = 100 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
VOUT = 0.25 VPP
360
270
MHz
MHz
MHz
dB
VOUT = 2.0 VPP
0.1 dBBW 0.1 dB Bandwidth
VOUT = 0.5 VPP
80
GFP
DG
DP
Peaking
DC to 200 MHz
0.3
Differential Gain
Differential Phase
RL = 150 Ω, f = 4.43 MHz
RL = 150 Ω, f = 4.43 MHz
0.02%
0.03
deg
TIME DOMAIN RESPONSE
TRL
TSS
OS
Rise and Fall Time
Settling Time to 0.05%
Overshoot
2-V Step
2-V Step
2-V Step
2-V Step
2.0
15
ns
ns
5%
SR
Slew Rate
1000
V/µs
DISTORTION
HD2
HD3
IMD
2nd Harmonic Distortion
3rd Harmonic Distortion
3rd Order Intermodulation Products
2 VPP, 10 MHz
−70
−74
-79
dBc
dBc
dBc
2 VPP, 10 MHz
10 MHz, Two tones 2 VPP at Output
STATIC, DC PERFORMANCE
GAIN
VIO
Voltage Gain
2.0
1
V/V
mV
µV/°C
µA
Output Offset Voltage
Average Drift
Input Bias Current(2)
VIN = 0 V
VIN = 0 V
DVIO
IBN
36
2
DIBN
PSRR
ICC
Average Drift
24
54
20
nA/°C
dB
Power Supply Rejection Ratio
Supply Current
DC, Input Referred
RL = ∞
mA
V
VIH
Logic High Threshold
Logic Low Threshold
Select and Enable Pins
Select and Enable Pins
1.3
VIL
0.4
V
MISCELLANEOUS PERFORMANCE
RIN+
CIN
Input Resistance
Input Capacitance
Output Resistance
100
0.9
kΩ
pF
Ω
ROUT
VO
0.27
±2.5
±2.2
±1.2
±60
No Load
V
Output Voltage Range
VOL
CMIR
IO
RL = 100 Ω
V
Input Voltage Range
V
Linear Output Current
Short Circuit Current
VIN = 0V
mA
mA
dBc
ISC
VIN = ±1V, Output Shorted to Ground
5 MHz
±150
-90
XTLK
Channel to Channel Crosstalk
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See the Power Dissipation section for information on temperature de-rating of this
device. Minimum and maximum ratings are based on product testing, characterization and simulation. Individual parameters are tested
as noted.
(2) Positive Value is current into device.
Copyright © 2005–2018, Texas Instruments Incorporated
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LMH6572
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
www.ti.com.cn
6.7 Typical Characteristics
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 1. Frequency Response vs VOUT
Figure 2. Frequency Response vs VOUT
Load = 1 kΩ || CL
Figure 3. Frequency Response vs Capacitive Load
Figure 4. Suggested RS vs Capacitive Load
Figure 6. Harmonic Distortion vs Output Voltage
Figure 5. Harmonic Distortion vs Output Voltage
8
Copyright © 2005–2018, Texas Instruments Incorporated
LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
Typical Characteristics (continued)
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 8. Harmonic Distortion vs Frequency
Figure 7. Harmonic Distortion vs Frequency
Figure 9. Harmonic Distortion vs Supply Voltage
Figure 10. Channel Switching Time
Figure 11. Disable Time
Figure 12. Pulse Response
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Typical Characteristics (continued)
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 14. PSRR
Figure 13. Crosstalk
Figure 15. PSRR
Figure 16. Closed-Loop Output Impedance
Figure 17. Closed-Loop Output Impedance
10
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LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
7 Detailed Description
7.1 Overview
The LMH6572 is a high-speed triple 2:1 analog multiplexer, optimized for very high speed and low distortion.
With a fixed gain of 2 and excellent AC performance, the LMH6572 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6572 has no internal ground reference. Single or split supply
configurations are both possible. The LMH6572 features very high speed channel switching and disable times.
When disabled the LMH6572 output is high impedance, making multiplexer expansion possible by combining
multiple devices.
7.2 Feature Description
7.2.1 Single Supply Operation
The LMH6572 uses mid-supply referenced circuits for the select and disable pins. In order to use the LMH6572
in single supply configuration, it is necessary to use a circuit similar to Figure 19. In this configuration the logical
inputs are compatible with high breakdown open collector TTL, or open drain CMOS logic. In addition, the default
logic state is reversed since there is a pull-up resistor on those pins. Single supply operation also requires the
input to be biased to within the common mode input range of roughly ±2V from the mid-supply point.
7.2.2 Video Performance
The LMH6572 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-
terminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. Figure 18 shows a typical
configuration for driving a 75-Ω cable. The output buffer is configured for a gain of 2, so using back terminated
loads will give a net gain of 1.
Figure 18. Typical Application
Figure 19. Single Supply Application
7.2.3 Gain Accuracy
The gain accuracy of the LMH6572 is accurate to ±0.5% (0.3% typical) and stable over temperature. The internal
gain setting resistors, RF and RG, match very well; however, over process and temperature their absolute value
will change.
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Feature Description (continued)
7.2.4 Expanding the Multiplexer
It is possible to build higher density multiplexers by paralleling several LMH6572s. Figure 20 shows a 4:1 RGB
MUX using two LMH6572s:
Figure 20. RGB MUX Using Two LMH6572's
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added prior to the ENABLE(EN) pin of each device, as shown. Figure 21
shows one possible approach to this delay circuit. The delay circuit shown will delay ENABLE’s H to L transitions
(R1 and C1 decay) but will not delay its L to H transition.
Figure 21. Delay Circuit Implementation
R2 should be kept small compared to R1 in order to not reduce the ENABLE voltage and to produce little or no
delay to the ENABLE L to H transition.
With the ENABLE pin putting the output stage into a high impedance state, several LMH6572’s can be tied
together to form a larger input MUX. However, there is a slight loading effect on the active output caused by the
off-channel feedback and gain set resistors, as shown in Figure 21. Figure 22 is assuming there are four
LMH6572 devices tied together to form a triple 8:1 MUX. With the internal resistors valued at approximately
800Ω, the gain error is about -0.57 dB, or about −6%.
12
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Feature Description (continued)
Figure 22. Multiplexer Input Expansion by Combining Outputs
An alternate approach would be to tie the outputs directly together and let all devices share a common back
termination resistor in order to alleviate the gain error issue above.
The drawback in this case is the increased capacitive load presented to the output of each LMH6572 due to the
offstate capacitance of the LMH6572.
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Feature Description (continued)
7.2.5 Other Applications
The LMH6572 may be utilized in systems that involve a single RGB channel as well whenever there is a need to
switch between different “flavors” of a single RGB input.
Here are some examples:
1. RGB positive polarity, negative polarity switch
2. RGB full resolution, high-pass filter switch
In each of these applications, the same RGB input occupies one set of inputs to the LMH6572 and the other
“flavor” would be tied to the other input set.
7.2.5.1 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor. Figure 23 shows the
use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of
5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 24
gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values
suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good
compromise between settling time and bandwidth. For applications where maximum frequency response is
needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values.
Figure 23. Decoupling Capacitive Loads
Figure 25. Frequency Response vs Capacitive Load
Figure 24. Recommended ROUT vs Capacitive Load
14
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LMH6572
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ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
8 Power Supply Recommendations
8.1 Power Dissipation
The LMH6572 is optimized for maximum speed and performance in the small form factor of the standard SSOP
package. To achieve its high level of performance, the LMH6572 consumes 23 mA of quiescent current, which
cannot be neglected when considering the total package power dissipation limit. To ensure maximum output
drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make
sure that the TJMAX is never exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6572:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
•
VS = V+ - V−
(1)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms [(VS - VOUT) * IOUT
]
where
•
•
VOUT and IOUT are the voltage across and the current through the external load
VS is the total supply voltage
(2)
(3)
3. Calculate the total RMS power:
PT = PAMP + PD
The maximum power that the LMH6572 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150°C – TAMB)/ θJA
where
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SSOP package θJA is 125 °C/W
(4)
8.2 ESD Protection
The LMH6572 is protected against electrostatic discharge (ESD) on all pins. The LMH6572 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6572 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other
will prevent the chip from being powered up through the input.
Copyright © 2005–2018, Texas Instruments Incorporated
15
LMH6572
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
www.ti.com.cn
9 Layout
9.1 Layout Guidelines
Whenever questions about layout arise, use the LMH730151 evaluation board as a guide. To reduce parasitic
capacitances, ground and power planes should be removed near the input and output pins. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass
capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are
applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device; however, the
smaller ceramic capacitors should be placed as close to the device as possible. In Figure 18 and Figure 19, the
capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.
9.1.1 Evaluation Boards
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with these boards.
DEVICE
PACKAGE
EVALUATION BOARD PART NUMBER
LMH6572
SSOP
LMH730151
An evaluation board can be shipped when a device sample request is placed with Texas Instruments.
16
版权 © 2005–2018, Texas Instruments Incorporated
LMH6572
www.ti.com.cn
ZHCSIP3G –JUNE 2005–REVISED AUGUST 2018
10 器件和文档支持
10.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
10.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2005–2018, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6572MQ/NOPB
LMH6572MQX/NOPB
ACTIVE
SSOP
SSOP
DBQ
16
16
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LH65
72MQ
ACTIVE
DBQ
2500 RoHS & Green
SN
LH65
72MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6572MQX/NOPB
SSOP
DBQ
16
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH6572MQX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6572MQ/NOPB
16
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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