LMH6611MKX/NOPB [TI]
单电源 345 MHz 轨到轨输出放大器 | DDC | 6 | -40 to 125;
| 型号： | LMH6611MKX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单电源 345 MHz 轨到轨输出放大器 | DDC | 6 | -40 to 125 放大器 光电二极管 商用集成电路 |
| 文件： | 总46页 (文件大小：2974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6611, LMH6612
www.ti.com
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
LMH6611/LMH6612 Single Supply 345 MHz Rail-to-Rail Output Amplifiers
Check for Samples: LMH6611, LMH6612
1
FEATURES
DESCRIPTION
The LMH6611 (single, with shutdown) and LMH6612
23
•
VS = 5V, RL = 1 kΩ, TA = 25°C and AV = +1,
(dual) are 345 MHz rail-to-rail output amplifiers
consuming just 3.2 mA of quiescent current per
channel and designed to deliver high performance in
power conscious single supply systems. The
LMH6611 and LMH6612 have precision trimmed
input offset voltages with low noise and low distortion
performance as required for high accuracy video, test
and measurement, and communication applications.
The LMH6611 and LMH6612 are members of the
PowerWise family and have an exceptional power-to-
performance ratio.
Unless Otherwise Specified.
•
Operating Voltage Range 2.7V to 11V
Supply Current Per Channel 3.2 mA
Small Signal Bandwidth 345 MHz
Open Loop Gain 103 dB
•
•
•
•
•
•
•
•
•
Input Offset Voltage (Limit at 25°C) ±1.5 mV
Slew Rate 460 V/µs
0.1 dB Bandwidth 45 MHz
Settling Time to 0.1% 67 ns
With a trimmed input offset voltage of 0.022 mV and
a high open loop gain of 103 dB the LMH6611 and
LMH6612 meet the requirements of DC sensitive high
speed applications such as low pass filtering in
Settling Time to 0.01% 100 ns
SFDR (f = 100 kHz, AV = 2, VOUT = 2 VPP) 102
dBc
baseband
I
and
Q
radio channels. These
•
•
•
•
•
Low Voltage Noise 10 nV/√Hz
Output current ±100 mA
CMVR −0.2V to 3.8V
specifications combined with a 0.01% settling time of
100 ns, a low noise of 10 nV/√Hz and better than 102
dBc SFDR at 100 kHz make these amplifiers
particularly suited to driving 10, 12 and 14-bit high
speed ADCs. The 45 MHz 0.1 dB bandwidth (AV = 2)
driving 2 VPP into 150Ω allows the amplifiers to be
used as output drivers in 1080i and 720p HDTV
applications.
Rail-to-Rail Output
−40°C to +125°C Temperature Range
APPLICATIONS
•
•
•
•
•
•
•
•
ADC Driver
The input common mode range extends from 200 mV
below the negative supply rail up to 1.2V from the
positive rail. On a single 5V supply with a ground
terminated 150Ω load the output swings to within 49
mV of the ground, while a mid-rail terminated 1 kΩ
load will swing to 77 mV of either rail.
DAC Buffer
Active Filters
High Speed Sensor Amplifier
Current Sense Amplifier
1080i and 720p Analog Video Amplifier
STB, TV Video Amplifier
Video Switching and Muxing
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH6611, LMH6612
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
www.ti.com
DESCRIPTION (CONTINUED)
The amplifiers will operate on a 2.7V to 11V single supply or ±1.35V to ±5.5V split supply. The LMH6611 single
is available in 6-Pin SOT and has an independent active low disable pin which reduces the supply current to 120
µA. The LMH6612 is available in 8-Pin SOIC. Both the LMH6611 and LMH6612 are available in −40°C to
+125°C extended industrial temperature grade.
Typical Application
R
R
1
2
1 PF
549:
549:
IN
C
5
R
5
150 pF
1.24 k:
+
V
+
V
C
2
+
1 nF
V
0.1 PF
10 PF
5V
0.1 PF
10 PF
R
R6
14.3 k:
L
0.1 PF
1 PF
0.01 PF
-
22:
ADC121S101
LMH6611
GND
+
C
L
U1
0.1 PF
5.6 PF
390 pF
R
7
14.3 k:
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
For input pins only
For all other pins
2000V
2000V
200V
Human Body Model
ESD Tolerance(3)
Machine Model
Charge Device Model
1000V
12V
Supply Voltage (VS = V+ – V−)
Junction Temperature(4)
150°C max
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings(1)
Supply Voltage (VS = V+ – V−)
Ambient Temperature Range(2)
2.7V to 11V
−40°C to +125°C
231°C/W
6-Pin SOT
8-Pin SOIC
Package Thermal Resistance (θJA
)
160°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
2
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
www.ti.com
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
+3V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.(1)
Symbol
Parameter
Condition
Min(2)
Typ(3)
Max(2)
Units
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
305
115
135
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth
(LMH6611)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
MHz
Gain Bandwidth
(LMH6612)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
LSBW
Peak
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 1.5 VPP
AV = −1, RL = 150Ω, VOUT = 2 VPP
AV = 1
90
85
1.0
33
65
MHz
dB
Peaking
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 560Ω
MHz
AV = 2, VOUT = 1.5 VPP, RL = 150Ω,
RF = RG = 510Ω
47
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
0.03
0.06
%
RL = 150Ω to V+/2
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
deg
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
1.5V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
2.8
330
74
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
116
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
fC = 100 kHz, AV = −1, VOUT= 2 VPP
fC = 1 MHz, AV = −1, VOUT = 2 VPP
fC = 5 MHz, AV = −1, VOUT = 2 VPP
f = 100 kHz
109
97
80
10
2
dBc
en
in
Input Voltage Noise
Input Current Noise
Crosstalk (LMH6612)
nV/√Hz
pA/√Hz
dB
f = 100 kHz
CT
f = 5 MHz, VIN = 2 VPP
71
Input, DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = 0.5V
VCM = 0.5V
0.022
±1.5
±2
mV
Input Offset Voltage (LMH6612)
−0.015
±1.5
±2
TCVOS
IB
Input Offset Voltage Average Drift See(4)
4
μV/°C
μA
Input Bias Current
VCM = 0.5V
−5.9
−10.1
−11.1
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
MΩ
V
RIN
CMVR
Input Voltage Range
DC, CMRR ≥ 76 dB
−0.2
1.8
(1) Boldface limits apply to temperature range of −40°C to 125°C
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Voltage average drift is determined by dividing the change in VOS by temperature change.
Copyright © 2007–2013, Texas Instruments Incorporated
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3
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
www.ti.com
+3V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.(1)
Symbol
CMRR
AOL
Parameter
Common Mode Rejection Ratio
Open Loop Gain
Condition
VCM Stepped from −0.1V to 1.7V
RL = 1 kΩ, VOUT = 2.7V to 0.3V
RL = 150Ω, VOUT = 2.5V to 0.5V
Min(2)
Typ(3)
Max(2)
Units
79
98
dB
89
101
85
dB
78
Output DC Characteristics
VO
Output Swing High (LMH6611)
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 150Ω to V−
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 150Ω to V−
59
133
59
72
76
(Voltage from V+ Supply Rail)
169
182
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
74
80
133
42
171
188
52
56
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
58
68
73
131
61
157
172
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
71
79
139
43
168
187
51
56
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2(5)
f = 1 MHz
±70
mA
0.07
Ω
Enable Pin Operation
Enable High Voltage Threshold
Enabled(6)
2.0
V
µA
V
Enable Pin High Current
Enable Low Voltage Threshold
Enable Pin Low Current
Turn-On Time
VDISABLE = 3V
Disabled(6)
0.001
1.0
VDISABLE = 0V
0.8
18
50
µA
ns
ns
ton
toff
Turn-Off Time
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
81
96
dB
mA
μA
Supply Current (LMH6611)
RL = ∞
3.0
3.4
3.8
Supply Current (LMH6612)
(per channel)
RL = ∞
2.95
101
3.45
3.9
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
132
(5) Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
(6) This parameter is ensured by design and/or characterization and is not tested in production.
4
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
www.ti.com
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
+5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
345
112
135
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth (LMH6611)
Gain Bandwidth (LMH6612)
−3 dB Bandwidth Large Signal
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
LSBW
Peak
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1
77
85
0.3
45
68
MHz
dB
Peaking
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 680Ω
MHz
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 665Ω
45
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
0.05
0.06
%
RL = 150Ω to V+/2
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
deg
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
3.6
460
67
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
100
Distortion and Noise Performance
SFDR
Spurious Free Dynamic Range
fC = 100 kHz, AV = 2, VOUT = 2 VPP
fC = 1 MHz, AV = 2, VOUT = 2 VPP
fC = 5 MHz, AV = 2, VO = 2 VPP
f = 100 kHz
102
96
82
10
2
dBc
en
in
Input Voltage Noise
Input Current Noise
Crosstalk (LMH6612)
nV/√Hz
pA/√Hz
dB
f = 100 kHz
CT
f = 5 MHz, VIN = 2 VPP
71
Input, DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = 0.5V
VCM = 0.5V
0.013
0.022
±1.5
±2
mV
Input Offset Voltage (LMH6612)
±1.5
±2
TCVOS
IB
Input Offset Voltage Average Drift See(3)
4
µV/°C
Input Bias Current
VCM = 0.5V
−6.3
−10.1
−11.1
μA
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
MΩ
V
RIN
CMVR
Input Voltage Range
DC, CMRR ≥ 78 dB
−0.2
3.8
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Voltage average drift is determined by dividing the change in VOS by temperature change.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
www.ti.com
+5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
CMRR
AOL
Common Mode Rejection Ratio
Open Loop Gain
VCM Stepped from −0.1V to 3.7V
RL = 1 kΩ, VOUT = 4.6V to 0.4V
RL = 150Ω, VOUT = 4.4V to 0.6V
81
92
80
98
103
86
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
76
195
74
90
93
(Voltage from V+ Supply Rail)
239
256
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
92
98
193
48
243
265
60
64
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
75
86
91
195
77
223
241
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
88
98
202
49
234
261
58
64
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2(4)
f = 1 MHz
±100
0.07
mA
Ω
Enable Pin Operation
Enable High Voltage Threshold
Enabled(5)
3.0
V
µA
V
Enable Pin High Current
Enable Low Voltage Threshold
Enable Pin Low Current
Turn-On Time
VDISABLE = 5V
Disabled(5)
1.2
2.0
VDISABLE = 0V
2.8
20
60
µA
ns
ns
ton
toff
Turn-Off Time
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
81
96
dB
mA
μA
Supply Current (LMH6611)
RL = ∞
3.2
3.6
4.0
Supply Current (LMH6612)
(per channel)
RL = ∞
3.2
3.7
4.25
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
120
162
(4) Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
(5) This parameter is ensured by design and/or characterization and is not tested in production.
6
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
www.ti.com
SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO
= 0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
365
110
135
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth (LMH6611)
Gain Bandwidth (LMH6612)
−3 dB Bandwidth Large Signal
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
LSBW
Peak
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1
85
87
MHz
dB
Peaking
0.01
92
0.1
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
dBBW
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 750Ω
65
MHz
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 680Ω
45
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
0.05
0.05
%
RL = 150Ω to V+/2
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
deg
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
3.5
460
60
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
100
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
fC = 100 kHz, AV = 2, VOUT = 2 VPP
fC = 1 MHz, AV = 2, VOUT = 2 VPP
fC = 5 MHz, AV = 2, VOUT = 2 VPP
f = 100 kHz
102
100
81
10
2
dBc
en
in
Input Voltage Noise
Input Current Noise
Crosstalk (LMH6612)
nV/√Hz
pA/√Hz
dB
f = 100 kHz
CT
f = 5 MHz, VIN = 2 VPP
71
Input DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = −4.5V
VCM = −4.5V
0.074
0.095
±1.5
±2
mV
Input Offset Voltage (LMH6612)
±1.5
±2
TCVOS
IB
Input Offset Voltage Average Drift See(3)
4
µV/°C
Input Bias Current
VCM = −4.5V
−6.5
−10.1
−11.1
μA
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
MΩ
V
RIN
CMVR
Input Voltage Range
DC, CMRR ≥ 81 dB
−5.2
3.8
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Voltage average drift is determined by dividing the change in VOS by temperature change.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO
= 0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
CMRR
AOL
Common Mode Rejection Ratio
Open Loop Gain
VCM Stepped from −5.1V to 3.7V
RL = 1 kΩ, VOUT = +4.6V to −4.6V
RL = 150Ω, VOUT = +4.3V to −4.3V
81
96
80
98
103
87
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 150Ω to V−
107
339
103
332
54
125
130
(Voltage from V+ Supply Rail)
402
433
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
123
132
404
445
70
74
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 150Ω to V−
107
340
108
348
56
118
125
375
407
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
120
135
389
434
66
74
IOUT
RO
Linear Output Current
Output Resistance
VOUT = GND(4)
f = 1 MHz
±120
0.07
mA
Ω
Enable Pin Operation
Enable High Voltage Threshold
Enabled(5)
0.5
V
µA
V
Enable Pin High Current
Enable Low Voltage Threshold
Enable Pin Low Current
Turn-On Time
VDISABLE = +5V
Disabled(5)
17.0
−0.5
VDISABLE = −5V
18.6
19
µA
ns
ns
ton
toff
Turn-Off Time
60
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = −4.5V, VS = 2.7V to 11V
RL = ∞
81
96
dB
mA
μA
Supply Current (LMH6611)
3.3
3.8
4.4
Supply Current (LMH6612)
(per channel)
RL = ∞
3.45
160
4.05
4.85
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = −5V
212
(4) Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
(5) This parameter is ensured by design and/or characterization and is not tested in production.
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Connection Diagram
1
8
+
1
6
OUT A
+
V
V
V
OUT
A
-
+
2
3
4
7
6
5
-IN A
OUT B
-IN B
5
4
2
3
-
DISABLE
-IN
V
-
+
+IN A
B
+
-
+IN
-
+IN B
V
Figure 1. 6-Pin SOT
Top View
Figure 2. 8-Pin SOIC
Top View
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Typical Performance Characteristics
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
3
3
±1.5V
±1.5V
0
0
±2.5V
±2.5V
-3
±5V
-3
±5V
-6
-9
-6
-9
-12
-12
-15
-18
-21
A = +2
= 0.2V
A = +1
= 0.2V
V
OUT
= 1 k:
V
-15
-18
OUT
= 1 k:
R
L
R
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies (Gain = +2)
3
3
3V
5V
3V
5V
0
-3
0
10V
10V
-3
-6
-6
-9
-9
-12
-15
-18
-21
A = +2
= 0.2V
V
A = +1
= 0.2V
OUT
-12
-15
R
R
= 150:
= 560:
V
L
F
OUT
R
= 150:
L
10
1
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
Closed Loop Gain
vs.
Frequency for
Various Temperatures
Closed Loop Gain
vs.
Frequency for Various Temperatures
9
6
125°C
25°C
-40°C
125°C
25°C
6
3
3
0
-40°C
0
-3
-3
-6
+
-
+
-
V
= +2.5V
-6
V
= +2.5V
-9
V = -2.5V
V = -2.5V
-9
V
= 0.2V
V
= 0.2V
OUT
OUT
-12
-15
-18
-12
-15
-18
R
L
= 1 k:
R
= 150:
L
L
C
L
= 6 pF
C
= 6 pF
A = +1
A = +1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Closed Loop Gain
vs.
Frequency for
Various Gains
Large Signal Frequency Response
3
3
A = 1
±1.5V, V
OUT
= 1.5V
0
0
A = 2
A = 5
A = 10
-3
-3
-6
-9
-6
-9
±2.5V, V
OUT
= 2V
±5V, V
OUT
= 2V
+
-
V
= +2.5V
-12
-15
-18
-12
-15
-18
V = -2.5V
R
L
= 1 k:
A = +1
R = 1 k:
L
V
= 0.2V
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9.
Figure 10.
Large Signal Frequency Response
±0.1 dB Gain Flatness for Various Supplies
1.0
0.9
0.8
0.7
3
V
= 2V
OUT
R
= 150:
L
0
0.6
±1.5V
0.5
-3
±2.5V
0.4
0.3
0.2
-6
-9
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
±5V
±5V, A = +2
±1.5V, A = -1
-12
-15
-18
A = +1
= 0.5V
V
OUT
= 1 k:
±2.5V, = A = +2
R
L
10
100
1
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11.
Figure 12.
±0.1 dB Gain Flatness for Various Supplies
1.0
±0.1 dB Gain Flatness for Various Supplies
0.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
A = +2
= 0.5V
0.2
5V, R = 604:
F
V
OUT
= 1 k:
0.1
R
L
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
±2.5V, R = R = 680:
F
G
10V, R = 750:
F
3V, R = 560:
F
±1.5V, R = R = 560:
F
G
±5V, R = R = 750:
F
G
A = -1
V
= 2V
OUT
R
= 150:
L
1
10
100
10
100
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
±0.1 dB Gain Flatness for Various Supplies
±0.1 dB Gain Flatness for Various Supplies (Gain = +2)
0.3
0.3
3V, R = 510:,
3V
F
0.2
0.2
5V
V
= 1.5V
OUT
0.1
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
0
-0.1
10V, R = 680:,
F
10V
5V, R = 665:,
F
-0.2
-0.3
-0.4
-0.5
-0.6
V
= 2V
OUT
V
OUT
= 2V
-0.7
A = +1
-0.8
-0.9
A = +2
= 150:
-0.8
-0.9
V
= 2V
OUT
R
L
R
= 150:
L
-1.0
-1
1
10
100
1000
1
10
100
1000
FREQUENCY MHz
FREQUENCY (MHz)
Figure 15.
Figure 16.
Small Signal Frequency Response with
Small Signal Frequency Response with
Capacitive Load and Various RISO
Various Capacitive Load
9
9
C
= 10 pF
L
R
= 10
ISO
6
3
C
= 7 pF
6
3
L
R
= 20
= 25
ISO
C
= 5.5 pF
R
ISO
L
0
C
L
= 3.3 pF
-3
0
+
-
R
ISO
= 30
-6
V
= +2.5V
C
= 2 pF
L
-3
-9
+
-
V = -2.5V
V
= +2.5V
A
V
= +1
V
-12
-15
-18
-21
-6
-9
V = -2.5V
A = +1
= 0.1V
= 100 pF
= 1 k:
OUT
C
V
= 0.2V
L
L
OUT
R
R
= 1 k:
L
-12
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17.
Figure 18.
HD2 and HD3
vs.
HD2 and HD3
vs.
Frequency and Supply Voltage
Frequency and Load
0
0
V
= 2 V
PP
+
-
OUT
V
= +2.5V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 1 k:
L
V = -2.5V
A = +1
HD2
V
= 2 V
PP
OUT
A = +1
+
V
= +2.5V
-
HD2
V = -2.5V
+
R
= 150:
V
= +5V
L
HD3
+
-
V = -5V
= +2.5V
V
-
HD2
V = -2.5V
HD3
-100
-110
-120
+
-100
-110
-120
V
= +5V
R
L
= 1 k:
HD3
-
V = -5V
1
1
10
10
0.1
50
0.1
50
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
HD2 and HD3
HD2 and HD3
vs.
vs.
Common Mode Voltage
Common Mode Voltage
-50
-60
-50
-60
f = 1 MHz
f = 5 MHz
-70
-70
HD2
HD2
HD2
+
HD2
V
= +2.5V
+
+
+
V
= +5V
V
= +2.5V
-
V = +5V
-80
-90
-80
-90
V = -2.5V
-
-
-
V = -5V
V = -2.5V
V = -5V
HD3
HD3
HD3
+
HD3
-100
-110
-100
-110
+
+
+
V
= +2.5V
V
= +5V
V
= +5V
V
= +2.5V
-
-
-
-
V = -2.5V
V = -5V
V = -5V
V = -2.5V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
50
5
INPUT COMMON MODE VOLTAGE
INPUT COMMON MODE VOLTAGE
Figure 21.
Figure 22.
HD2
vs.
HD3
vs.
Frequency and Gain
Frequency and Gain
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
+
-
+
-
V
= +2.5V
V
= +2.5V
V = -2.5V
V = -2.5V
V
= 2 V
PP
V
= 2 V
OUT PP
OUT
R
= 1 k:
R
= 1 k:
L
F
L
F
R
= 560:
R
= 560:
G = +10, HD3
G = +1, HD3
G = +1, HD2
G = +2, HD2
G = +10, HD2
-100
-110
-120
-100
-110
-120
G = +2, HD3
10
1
1
10
0.1
50
0.1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23.
Figure 24.
HD2
vs.
Output Swing
Open Loop Gain and Phase
-10
-20
-30
120
100
80
120
+
-
PHASE
V
= +2.5V
90
V = -2.5V
A = -1
50 MHz
60
-40
-50
R
= 1 k:
L
GAIN
60
30
20 MHz
-60
40
0
10 MHz
-70
5 MHz
20
-30
-60
-90
-120
-80
2 MHz
-90
+
0
V
= +2.5V
-100
-110
-120
-
1 MHz
V = -2.5V
-20
-40
R
L
= 1 k:
0
1
2
3
4
1M
100M
1k
100k
10M
1G
10k
V (V )
OUT PP
FREQUENCY (Hz)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
HD3
HD2
vs.
Output Swing
vs.
Output Swing
-10
-20
-30
-40
-10
-20
-30
+
-
+
-
V
= +2.5V
V
= +2.5V
50 MHz
V = -2.5V
A = -1
50 MHz
20 MHz
V = -2.5V
A = +2
-40
-50
R
= 1 k:
L
R
= 1 k:
L
20 MHz
10 MHz
-50
-60
-60
10 MHz
-70
-70
5 MHz
-80
5 MHz
2 MHz
1 MHz
2 MHz
-80
-90
-90
-100
-110
-120
1 MHz
-100
-110
0
1
2
3
4
5
0
1
2
3
4
5
V (V )
OUT PP
V (V )
OUT PP
Figure 27.
Figure 28.
HD2
vs.
Output Swing
HD3
vs.
Output Swing
-10
-10
-20
-30
+
-
+
-
V
= +2.5V
V
= +2.5V
50 MHz
-20
-30
V = -2.5V
A = +2
V = -2.5V
A = +2
50 MHz
20 MHz
-40
-50
-40
-50
R
= 1 k:
R
= 150:
L
L
20 MHz
10 MHz
-60
-60
10 MHz
5 MHz
-70
-70
2 MHz
1 MHz
-80
-80
5 MHz
2 MHz
-90
-90
-100
-110
-120
-100
-110
-120
1 MHz
0
1
2
3
4
5
0
1
2
3
4
5
V
(V
)
V (V )
OUT PP
OUT PP
Figure 29.
Figure 30.
HD3
vs.
Output Swing
Settling Time
vs.
Input Step Amplitude
90
80
70
60
0
-10
-20
-30
-40
-50
-60
+
FALLING, 0.1%
V
= +2.5V
-
V = -2.5V
A = +2
50 MHz
R
L
= 150:
RISING, 0.1%
20 MHz
10 MHz
50
40
30
5 MHz
-70
-80
2 MHz
1 MHz
+
-90
V
= +2.5V
20
10
0
-
-100
-110
-120
V = -2.5V
= -1
A
V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
1
2
3
4
5
OUTPUT SWING (V
)
PP
V (V )
OUT PP
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Settling Time
Input Noise
vs.
vs.
Input Step Amplitude
Frequency
140
120
100
80
1000
100
10
1000
100
10
+
-
V
= +2.5V
V = -2.5V
FALLING, 0.01%
RISING, 0.01%
VOLTAGE NOISE
60
40
20
0
+
V
= +2.5V
-
V = -2.5V
= -1
A
V
CURRENT NOISE
1
10
1
10M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
10k
1M
100
1k
100k
OUTPUT SWING (V
)
PP
FREQUENCY (Hz)
Figure 33.
Figure 34.
VOS
vs.
VOUT
VOS
vs.
VOUT
6.0
4.0
6.0
+
+
V
= +2.5V
V = +2.5V
-
-
V = -2.5V
= 1 k:
V = -2.5V
R = 150:
L
4.0
2.0
R
L
2.0
-40°C
-40°C
25°C
25°C
0
0
125°C
125°C
-2.0
-2.0
-4.0
-6.0
-4.0
-6.0
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
(V)
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
(V)
V
V
OUT
OUT
Figure 35.
Figure 36.
VOS
vs.
VCM
VOS
vs.
VS
0.1
0.0
0.2
0.1
0
V
S
= 5V
-40°C
-40°C
-0.1
-0.2
-0.3
25°C
25°C
-0.1
-0.2
-0.3
125°C
-0.4
-0.5
-0.6
-
125°C
V = -0.5V
+
-
V
S
= V - V
-0.4
-0.5
V
CM
= 0V
10
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
2
4
8
12
6
V
CM
(V)
V (V)
S
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
VOS
vs.
IOUT
VOS Distribution
3.0
2.5
0.4
0.2
+
-
V
= +2.5V
-40°C
V = -2.5V
0
25°C
2.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
1.5
1.0
125°C
0.5
0
-1.0
-150 -100
-50
50
100
150
0
-0.6
-0.2
0.2
Vos (mv)
0.6
1.0
-0.8
-0.4
0.4
0.8
I
(mA)
OUT
Figure 39.
Figure 40.
IB
vs.
VS
IS
vs.
VS
-4.6
4.2
-
V = -0.5
+
4.0
-4.8
-5.0
-5.2
-5.4
-5.6
-5.8
-6.0
-6.2
-6.4
-6.6
-
V
V
= V - V
125°C
S
3.8
3.6
3.4
3.2
= 0V
CM
25°C
25°C
125°C
-40°C
3.0
2.8
2.6
2.4
-40°C
-
V = -0.5
2.2
2.0
1.8
1.6
+
-
V
V
= V - V
S
= 0.5V
CM
0
2
4
6
8
10
12
8
12
0
2
10
4
6
V
(V)
V
S
(V)
S
Figure 41.
Figure 42.
VOUT
vs.
VS
VOUT
vs.
VS
150
100
500
400
300
200
100
0
VOLTAGE V
+
IS
VOLTAGE V
+
IS
OUT
OUT
BELOW V SUPPLY
BELOW V SUPPLY
R
= 150:
L
50
to MID-RAIL
-40°C
25°C 125°C
0
25°C
125°C
-40°C
100
200
300
400
500
R
= 1 k: to
50
L
MID-RAIL
100
150
VOLTAGE V
-
IS
OUT
VOLTAGE V
-
IS
OUT
ABOVE V SUPPLY
ABOVE V SUPPLY
2
3
4
5
6
7
8
9
10 11 12
2
3
4
5
6
7
8
9
10 11 12
V
S
(V)
V
S
(V)
Figure 43.
Figure 44.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
VOUT
Closed Loop Output Impedance
vs.
vs.
VS
Frequency AV = +1
20
25
30
35
40
45
50
55
60
65
70
100
+
-
VOLTAGE V
OUT
IS
V
= +2.5V
-
ABOVE V SUPPLY
V = -2.5V
-
10
1
V = 0V
R
= 150: TO GND
L
-40°C
0.1
25°C
0.01
125°C
0.001
0.0001
2
3
4
5
6
7
(V)
8
9
10 11 12
0.1
10
0.001
0.01
1
100
FREQUENCY (MHz)
V
S
Figure 45.
Figure 46.
+PSRR
vs.
Circuit for Positive (+) PSRR Measurement
Frequency
50:
110
100
90
+
+
V
V
= +5V
+
-
0.1 PF
1000 PF
V = -5V
-
0.1 PF
80
+
-
70
+
-
R
F
V
= +2.5V
CABLE
560:
1000 PF
60
50
+
-
V = -2.5V
50:
R
V
= +1.5V
G
V
IN
a
560:
V = -1.5V
-
40
30
20
10
0
LMH6611
V
O
+
-
V
= 225 mV
IN
PP
V
R
F
= 560:
0.1 PF
1000 PF
10k 100k
10M
10 100 1k
1M
100M
FREQUENCY (Hz)
Figure 47.
Figure 48.
−PSRR
vs.
Circuit for Negative (−) PSRR Measurement
Frequency
+
120
110
100
90
80
70
60
50
40
30
20
10
0
V
R
+
F
+
0.1 PF
1000 PF
V
= +2.5V
560:
-
-
V = -2.5V
R
G
560:
6
4
-
1
+
-
V
O
LMH6611
V
= +5V
3
+
2
+
-
50:
V = -5V
V
= +1.5V
-
V
V = -1.5V
-
+
0.1 PF
1000 PF
0.1 PF
V
= 225 mV
PP
IN
-
+
CABLE
R
F
= 560:
1000 PF
50:
VIN
a
10M
10
1k 10k 100k 1M
100M
100
FREQUENCY (Hz)
Figure 49.
Figure 50.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
CMRR
Crosstalk
vs.
vs.
Frequency
Frequency
140
120
100
-40
+
-
+
-
V
= +2.5V
V
= +2.5V
-50
-60
V = -2.5V
V = -2.5V
A = +1
R
L
= 1 k:
V
= 2 V
PP
OUT
80
60
40
20
-70
-80
-90
-100
-110
0
0.1
10
0.0001
0.01
1
100
0.001
100k
1M
10M
100M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 51.
Figure 52.
Small Signal Step Response
Small Signal Step Response
+
+
V
= +2.5V
V
= +1.5V
-
-
V = -2.5V
A = +1
V = -1.5V
A = +1
V
= 0.2V
V
= 0.2V
OUT
OUT
R
L
= 1 k:
R
L
= 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 53.
Figure 54.
Small Signal Step Response
Small Signal Step Response
+
V
= +1.5V
-
+
V = -1.5V
A = -1
V
= +5V
-
V = -5V
A = +1
R
F
= 560:
V
= 0.2V
V
= 0.2V
OUT
OUT
R
L
= 1 k:
R
L
= 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 55.
Figure 56.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Small Signal Step Response
Small Signal Step Response
+
V
= +2.5V
V+ = +5V
V- = -5V
A = -1
-
V = -2.5V
A = -1
R
F
= 560:
R
F
= 560:
V
= 0.2V
V
= 0.2V
OUT
OUT
R
L
= 1 k:
R
L
= 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 57.
Figure 58.
Small Signal Step Response
Small Signal Step Response
+
+
V
= +1.5V
V
= +2.5V
-
-
V = -1.5V
A = +2
V = -2.5V
A = +2
R
F
= 560:
R = 560:
F
V
= 0.2V
V
= 0.2V
OUT
OUT
R = 150:
L
R
= 150:
L
12.5 ns/DIV
12.5 ns/DIV
Figure 59.
Figure 60.
Small Signal Step Response
Large Signal Step Response
+
V
= +5V
+
-
V
= +2.5V
V = -5V
A = +2
-
V = -2.5V
A = +1
R
F
= 560:
V
= 2V
V
= 0.2V
OUT
OUT
R
L
= 1 k:
R
L
= 150:
12.5 ns/DIV
12.5 ns/DIV
Figure 61.
Figure 62.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Large Signal Step Response
Overload Recovery Response
V
OUT
V
IN
+
V
= +2.5V
+
-
-
V
= +5V
V = -2.5V
A = +2
V = -5V
R
F
= 560:
A
= +5
V
V
= 2V
OUT
R
R
= 604:
= 1 k:
F
L
R
= 150:
L
12.5 ns/DIV
25 ns/DIV
Figure 63.
Figure 64.
IS
vs.
VDISABLE
4000
3500
3000
2500
2000
1500
1000
500
+
-
125°C
-40°C
V
= +2.5V
V = -2.5V
25°C
0
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
V
(V)
DISABLE
Figure 65.
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APPLICATION INFORMATION
The LMH6611 and LMH6612 are based on proprietary VIP10 dielectrically isolated bipolar process. This device
family architecture features the following:
•
•
•
•
Complimentary bipolar devices with exceptionally high ft (∼8 GHz) even under low supply voltage (2.7V) and
low bias current.
Common emitter push-push output stage. This architecture allows the output to reach within millivolts of either
supply rail.
Consistent performance with little variation from any supply voltage (2.7V - 11V) for the most important
specifications (BW, SR, IOUT, for example.)
Significant power saving compared to competitive devices on the market with similar performance.
With 3V supplies and a common mode input voltage range that extends beyond either supply rail, the LMH6611
is well suited to many low voltage/low power applications. Even with 3V supplies, the −3 dB BW (at AV = +1) is
typically 305 MHz.
The LMH6611 and LMH6612 are designed to avoid output phase reversal. With input overdrive, the output is
kept near the supply rail (or as close to it as mandated by the closed loop gain setting and the input voltage).
Figure 66 shows the input and output voltage when the input voltage significantly exceeds the supply voltages.
V
IN
V
OUT
+
-
V
= +2.5V
V = -2.5V
A
= +1
V
R
= 560:
= 1 k:
F
L
R
25 ns/DIV
Figure 66. Input and Output Shown with CMVR Exceeded
If the input voltage range is exceeded by more than a diode drop beyond either rail, the internal ESD protection
diodes will start to conduct. The current flow in these ESD diodes should be externally limited.
SHUTDOWN CAPABILITY AND TURN ON/OFF BEHAVIOR
The LMH6611 can be shutdown by connecting the DISABLE pin to a voltage 0.5V below the supply midpoint
which will reduce the supply current to typically 120 µA. The DISABLE pin is “active low” and can be connected
through a resistor to V+ or left floating for normal operation. Shutdown is specified when the DISABLE pin is 0.5V
below the supply midpoint at any operating supply voltage and temperature. Typical turn on time is 20 ns and the
turn off time is 60 ns.
In the shutdown mode, essentially all internal device biasing is turned off in order to minimize supply current flow
and the output goes into high impedance mode. During shutdown, the input stage has an equivalent circuit as
shown in Figure 67.
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R
S
50:
INVERTING
INPUT
D4
D3
D1
D2
NON-INVERTING
INPUT
Figure 67. Input Equivalent Circuit During Shutdown
When the LMH6611 is shutdown, there may be current flow through the internal diodes shown, caused by input
potential, if present. This current may flow through the external feedback resistor and result in an apparent output
signal. In most shutdown applications the presence of this output is inconsequential. However, if the output is
“forced” by another device, the other device will need to conduct the current described in order to maintain the
output potential.
To keep the output at or near ground during shutdown when there is no other device to hold the output low, a
switch using a transistor can be used to shunt the output to ground.
SELECTION OF RF AND EFFECT ON STABILITY AND PEAKING
The peaking of the LMH6611 depends on the value of the RF. From the graph shown in Figure 68, as the RF
value increases, the peaking increases.
For AV = 2, at RF = 1 kΩ, the −3 dB bandwidth is 113 MHz and peaking is about 0.6 dB whereas at RF = 665Ω,
the −3 dB bandwidth is about 110 MHz and peaking is 0 dB. RF and the input capacitance form a pole in the
amplifier’s response. If the time constant is too big, it will cause peaking and ringing.
Except for AV = 1 when RF should be 0Ω, across all other gain settings it is recommended that RF remain
between 500Ω and 1 kΩ to ensure optimum performance.
3
R
F
= R = 1000:
G
0
-3
-6
R
= R = 665:
G
F
+
-
V
= +2.5V
V = -2.5V
V
= 0.2V
OUT
R
= 1 k:
L
1
10
100
1000
FREQUENCY (MHz)
Figure 68. Closed Loop Gain vs. Frequency and RF = RG
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RF = RG
665
f −3 dB (MHz)
Peaking (dB)
110
113
0
1000
0.6
MINIMIZING NOISE
With a low input voltage noise of 10 nV/√Hz and an input current noise of 2 pA√Hz the LMH6611 and LMH6612
are suitable for high accuracy applications. Still being able to reduce the frequency band of operation of the
various noise sources (that is, op amp noise voltage, resistor thermal noise, input noise current) can further
improve the noise performance of a system. In a non-inverting amplifier configuration inserting a capacitor, CG, in
series with the gain setting resistor, RG, will reduce the gain of the circuit below frequency, f = 1/2πRGCG. This
can be set to reduce the contribution of noise from the 1/f region. Alternatively applying a feedback capacitor, CF,
in parallel with the feedback resistor, RF, will introduce a pole into your system at f = 1/2πRFCF and create a low
pass filter. This filter can be set to reduce high frequency noise and harmonics. Finally remember to keep resistor
values as small as possible for a given application in order to reduce resistor thermal noise.
POWER SUPPLY BYPASS
Since the LMH6611 and LMH6612 are wide bandwidth amplifiers, proper power supply bypassing is critical for
optimum performance. Improper power supply bypassing can result in large overshoot, ringing or oscillation. 0.1
μF capacitors should be connected from the supply pins, V+ and V−, to ground, as close to the device as is
practical. Additionally, a 10 μF electrolytic capacitor should be connected from both supply pins to ground
reasonably close to the device. Finally, near the device a 0.1 μF ceramic capacitor between the supplies will
provide the best harmonic distortion performance.
INTERFACING HIGH PERFORMANCE OP AMPS WITH ADCs
These amplifiers are designed for ease of use in a wide range of applications requiring high speed, low supply
current, low noise, and the ability to drive complex ADC and video loads.
The source that drives the modern high resolution analog-to-digital converters (ADCs) sees a high frequency AC
load and a DC load of a few hundred ohms or more. Thus, a high performance op amp with high input
impedance of a few mega ohms and low output impedance would be an ideal choice as an input ADC driver.
The LMH6611/LMH6612 have the low output impedance of 0.07Ω at f = 1 MHz. The ADC driver acts as a buffer
and a low pass filter to reduce the overall system noise. To utilize the full dynamic range of the ADC, the ADC
input has to be driven to full scale input voltage.
As signals travel through the traces of a printed circuit board (PCB) and long cables, system noise accumulates
in the signals and a differential ADC rejects any signals noise that appears as a common mode voltage. There
are a couple of advantages to using differential signals rather than single-ended signals. First, differential signals
double the dynamic range of the ADC and second, they offer better harmonic distortion performance. There are
several ways to produce differential signals from a dual op amp configuration. One method is to utilize the single-
ended to differential conversion technique and the other is the differential to differential conversion technique.
The first method requires a single input source and the second method requires differential input source.
A real world input source can have non-ideal impedance thus the buffer amplifier, with very low output
impedance, is required to drive the input of the ADC. To minimize the droop in the input voltage, external shunt
capacitance (CL) should be about ten times larger than the internal input capacitance of the ADC and external
series resistance (RL) should be large enough to maintain the phase delay at the output of the op amp and
hence maintain the stability (See Figure 69). Most applications benefit from the inclusion of a series isolation
resistor connected between the op amp output and ADC input. This series resistor helps to limit the output
current of the op amp. The value chosen for this series resistor is very important, as a higher value will increase
the load impedance seen by the op amp and improve the total harmonic distortion (THD) performance of the op
amp; however, the ADC prefers a low impedance source driving it. Thus, the optimum value for this series
resistor must be found so that it will offer the best performance in terms of THD, SNR and SFDR of the combined
op amp and ADC.
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Important Specifications of Op Amp and ADC
When interfacing an ADC with an op amp it is imperative to understand the specifications that are important to
get the expected performance results. Modern ADC AC specifications such as THD, SNR, settling time and
SFDR are critical for filtering, test and measurement, video and reconstruction applications. The high
performance op amp’s settling time, THD, and noise performance must be better than that of the ADC it is driving
to maintain the proper system accuracy with minimal or no error.
Some system applications require low THD, low SFDR and wide dynamic range (SNR), whereas some system
applications require high SNR and they may sacrifice THD and SFDR to focus on the noise performance.
Noise is a very important specification for both the op amp and the ADC. There are three main sources of noise
that contribute to the overall performance of the ADC: Quantization noise, noise generated by the ADC itself
(particularly at higher frequencies) and the noise generated by the application circuit. The impedance of the input
source affects the noise performance of the op amp. Theoretically, an ADC’s signal to noise ratio (SNR) can be
found from the equation:
SNR (in dB) = 6.02*N+1.72
(1)
where N is the resolution of the ADC. For example, according to this equation a 12-bit ADC has an SNR of 74
dB. However, the practical SNR number would be about 72 dB. In order to achieve better SNR, the ADC driver
noise should be as small as possible. The LMH6611/LMH6612 have the low voltage noise of only 10 nV/√Hz.
The combined settling time of the op amp and the ADC must be within 1 LSB. The 0.01% settling time of the
LMH6611/LMH6612 is 100 ns.
The ADC driver’s THD should be inherently lower than that of the ADC. The LMH6611/LMH6612 have an SFDR
of 96 dBc at 2 VPP output and 1 MHz input frequency.
Signal to Noise and Distortion (SINAD) is a parameter which is the combination of the SNR and THD
specifications. SINAD is defined as the RMS value of the output signal to the RMS value of all of the other
spectral components below half the clock frequency, including harmonics but excluding DC. It can be calculated
from SNR and THD according to the equation:
-SNR
THD
SINAD = 20 * LOG 1010 + 1010
(2)
Because SINAD compares all undesired frequency components with the input frequency, it is an overall measure
of an ADC’s dynamic performance. The following sections will discuss the three different ADC driver
architectures in detail.
SINGLE TO SINGLE ADC DRIVER
This architecture has a single-ended input source connected to the input of the op amp and the single-ended
output of the op amp is then fed to the single-ended input of the ADC. The low noise of only 10 nV/√Hz and a
wide bandwidth of 345 MHz make the LMH6611 an excellent choice for driving the 12-bit ADC121S101 500
KSPS to 1 MSPS ADC, which has a successive approximation architecture with internal sample and hold
circuits. Figure 67 shows the schematic of the LMH6611 in a 2nd order multiple-feedback with gain of −1
(inverting) configuration, driving an ADC121S101. The inverting configuration is preferred over the non-inverting
configuration, as it offers more linear output response. Table 1 shows the performance data of the LMH6611
combined with the ADC121S101. The ADC driver’s cutoff frequency of 500 kHz is found from the equation:
1
2S
1
´
x
¶ =
0
R2 x R5 x C2 x C5
(3)
(4)
The op amp’s gain is set by the equation:
R2
-
GAIN
=
R1
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R
R
1
2
1 PF
549:
549:
IN
C
5
R
5
150 pF
1.24 k:
+
V
+
V
C
2
+
1 nF
V
0.1 PF
10 PF
5V
0.1 PF
10 PF
R
R6
14.3 k:
L
0.1 PF
1 PF
0.01 PF
-
22:
ADC121S101
LMH6611
GND
+
C
L
U1
0.1 PF
5.6 PF
390 pF
R
7
14.3 k:
Figure 69. Single to Single ADC Driver
Table 1. Performance of the LMH6611 Combined with the ADC121S101
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
71.6
THD
(dB)
SFDR
(dBc)
77.6
ENOB
Notes
4
70.2
−75.7
11.4
ADC121S101 @ f = 200 kHz
When the op amp and the ADC are using the same supply, it is important that both devices are well bypassed. A
0.1 µF ceramic capacitor and a 10 µF tantalum capacitor should be located as close as possible to each supply
pin. A sample layout is shown in Figure 70. The 0.1 µF capacitors (C13 and C6) and the 10 µF capacitors (C11
and C5) are located very close to the supply pins of the LMH6611 and the ADC121S101.
The following are recommendations for the design of PCB layout in order to obtain the optimum high frequency
performance:
•
•
•
•
•
Place ADC and amplifier as close together as possible.
Put the supply bypassing capacitors as close as possible to the device (<1”).
Utilize surface mount instead of through-hole components and ground and power planes.
Keep the traces short where possible.
Use terminated transmission lines for long traces.
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Figure 70. LMH6611 and ADC121S101 Layout
SINGLE-ENDED TO DIFFERENTIAL ADC DRIVER
The single-ended to differential ADC driver in Figure 68 utilizes an LMH6612 dual op amp to buffer a single-
ended source to drive an ADC with differential inputs. One of the op amps is configured as a unity gain buffer
that drives the inverting (IN−) input of the op amp U2 and non-inverting (IN+) input of the ADC121S625. U2
inverts the input signal and drives the inverting input of the ADC121S625. The ADC driver is configured for a
gain of +2 to reduce the noise without sacrificing THD performance. The common mode voltage of 2.5V is set up
at the non-inverting inputs of both op amps U1 and U2. This configuration produces differential ±2.5 VPP output
signals, when the single-ended input signal of 0 to VREF is AC coupled into the non-inverting terminal of the op
amp and each non-inverting terminal of the op amp is biased at the mid-scale of 2.5V. The two output RC anti-
aliasing filters are used between both the outputs of U1 and U2 and the input of the ADC121S625 to minimize
the effect of undesired high frequency noise coming from the input source. Each RC filter has the cutoff
frequency of approximately 22 MHz.
+
V
+
V
0.1 PF
10 PF
33:
-
560:
560:
+
V
10 PF
LMH6612
INPUT
+
220 pF
U1
560:
0.1 PF
10 PF
560:
+
V
ADC121S625
+
V
0.1 PF
10 PF
33:
-
560:
LMH6612
+
U2
220 pF
560:
Figure 71. Single-Ended to Differential ADC Driver
26
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
The performance of the LMH6612 with the ADC121S625 is shown in Table 2.
Table 2. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
69
THD
(dB)
SFDR
(dBc)
75.1
ENOB
Notes
2.5
68.8
−81.5
11.2
ADC121S625 @ f = 20 kHz
DIFFERENTIAL TO DIFFERENTIAL ADC DRIVER
The LMH6612 dual op amp can be configured as a differential to differential ADC driver to buffer a differential
source to a differential input ADC as shown in Figure 72. The differential to differential ADC driver can be formed
using two single to single ADC drivers. Each output from these drivers goes to a separate input of the differential
ADC. Here, each single to single ADC driver uses the same components and is configured for a gain of -1
(inverting).
549:
1 PF 549:
+IN
150 pF
1.24 k:
+
V
1 nF
+
V
0.1 PF 10 PF
+
V
14.3 k:
-
22:
LMH6612
0.1 PF
10 PF
+
390 pF
5.6 PF
0.1 PF
14.3 k:
ADC121S705
549:
1 PF 549:
22:
-IN
390 pF
150 pF
1.24 k:
+
V
1 nF
+
V
0.1 PF
10 PF
14.3 k:
-
LMH6612
+
0.1 PF
5.6 PF
14.3 k:
Figure 72. Differential to Differential ADC Driver
The following table summarizes the performance of the LMH6612 combined with the ADC121S625 at two
different frequencies. In order to utilize the full dynamic range of the ADC, the maximum input of 2.5 VPP is
applied to the ADC input. Figure 73 shows the FFT plot of the LMH6612 and ADC121S625 combination tested at
f = 20 kHz input frequency.
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Table 3. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
72.3
72.2
THD
(dB)
SFDR
(dBc)
92.1
ENOB
Notes
2.5
2.5
72.2
−87.7
−87.8
11.7
11.7
ADC121S625 @ f = 20 kHz
ADC121S625 @ f = 200 kHz
72.2
90.8
Figure 73. The FFT Plot of Differential to Differential ADC Driver
28
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
DC LEVEL SHIFTING
Often a signal must be both amplified and level shifted while using a single supply for the op amp. The circuit in
Figure 74 can do both of these tasks. The procedure for specifying the resistor values is as follows.
1. Determine the input voltage.
2. Calculate the input voltage midpoint, VINMID = VINMIN + (VINMAX – VINMIN)/2.
3. Determine the output voltage needed.
4. Calculate the output voltage midpoint, VOUTMID = VOUTMIN + (VOUTMAX – VOUTMIN)/2.
5. Calculate the gain needed, gain = (VOUTMAX – VOUTMIN)/(VINMAX – VINMIN
)
6. Calculate the amount the voltage needs to be shifted from input to output, ΔVOUT = VOUTMID – gain x VINMID
7. Set the supply voltage to be used.
.
8. Calculate the noise gain, noise gain = gain + ΔVOUT/VS.
9. Set RF.
10. Calculate R1, R1 = RF/gain.
11. Calculate R2, R2 = RF/(noise gain-gain).
12. Calculate RG, RG= RF/(noise gain – 1).
Check that both the VIN and VOUT are within the voltage ranges of the LMH6611.
+
+
V
V
R
2
R
1
V
IN
+
V
OUT
LMH6611
-
R
R
F
G
Figure 74. DC Level Shifting
The following example is for a VIN of 0V to 1V with a VOUT of 2V to 4V.
1. VIN = 0V to 1V
2. VINMID = 0V + (1V – 0V)/2 = 0.5V
3. VOUT = 2V to 4V
4. VOUTMID = 2V + (4V – 2V)/2 = 3V
5. Gain = (4V – 2V)/(1V – 0V) = 2
6. ΔVOUT = 3V – 2 x 0.5V = 2
7. For the example the supply voltage will be +5V.
8. Noise gain = 2 + 2/5V = 2.4
9. RF = 2 kΩ
10. R1 = 2 kΩ/2 = 1 kΩ
11. R2 = 2 kΩ/(2.4-2) = 5 kΩ
12. RG = 2 kΩ/(2.4 – 1) = 1.43 kΩ
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4th ORDER MULTIPLE FEEDBACK LOW-PASS FILTER
Figure 75 shows the LMH6612 used as the amplifier in a multiple feedback low pass filter. This filter is set up to
have a gain of +1 and a −3 dB point of 1 MHz. Values can be determined by using the WEBENCH® Active Filter
Designer found at www.ti.com/amplifiers
1.05 k:
1.02 k:
150 pF
62 pF
+
V
+
V
0.1 PF
1 PF
523:
1.05 k:
1 PF
0.1 PF
INPUT
-
1.02 k:
510:
LMH6612
-
330 pF
LMH6612
+
OUTPUT
820 pF
+
1 PF
0.1 PF
0.1 PF
1 PF
-
V
-
V
Figure 75. 4th Order Multiple Feedback Low-Pass Filter
CURRENT SENSE AMPLIFIER AND OPTIMIZING ACCURACY IN PRECESION APPLICATIONS
With it’s rail-to-rail output capability, low VOS, and low IB the LMH6611 is an ideal choice for a current sense
amplifier application. Figure 76 shows the schematic of the LMH6611 set up in a low-side sense configuration
which provides a conversion gain of 2V/A. Voltage error due to VOS can be calculated to be VOS x (1 + RF/RG) or
1.5 mV x 21 = 31.5 mV. Voltage error due to IO is IO x RF or 0.5 µA x 1 kΩ = 0.5 mV. Hence worst case total
voltage error is 12.6 mV + 0.5 mV or 13.1 mV which translates into a current error of 13.1 mV/(2 V/A) = 6.55 mA.
This circuit employs DC source resistance matching at the two input terminals in order to minimize the output DC
error caused by input bias current. Another technique to reduce output offset in a non-inverting amplifier
configuration is to introduce a DC offset current into the inverting input of the amplifier. To ensure minimal impact
on frequency response be sure to inject the DC offset current through large resistors. Conversely if optimizing an
inverting amplifier configuration simply apply offset adjustment to the non-inverting input.
+5V
0A to 1A
51:
+
1 k:
LMH6611
0.1:
-
51:
1 k:
Figure 76. Current Sense Amplifier
30
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
TRANSIMPEDANCE AMPLIFIER
By definition, a photodiode produces either a current or voltage output from exposure to a light source. A
Transimpedance Amplifier (TIA) is utilized to convert this low-level current to a usable voltage signal. The TIA
often will need to be compensated to insure proper operation.
C
F
R
F
V
S
-
LMH6611
C
C
PD
IN
+
Figure 77. Photodiode Modeled with Capacitance Elements
Figure 77 shows the LMH6611 modeled with photodiode and the internal op amp capacitances. The LMH6611
allows circuit operation of a low intensity light due to its low input bias current by using larger values of gain (RF).
The total capacitance (CT) on the inverting terminal of the op amp includes the photodiode capacitance (CPD) and
the input capacitance of the op amp (CIN). This total capacitance (CT) plays an important role in the stability of
the circuit. The noise gain of this circuit determines the stability and is defined by:
1 + sRF (CT + CF)
NG =
1 + sCFRF
(5)
1
1
Where, fZ #
and fP =
2SRFCF
2SRFCT
(6)
OP AMP OPEN
LOOP GAIN
I-V GAIN (:)
NOISE GAIN (NG)
1 + sR (C + C )
F
T
F
1 + sR C
F
F
C
IN
1 +
C
F
0 dB
1
GBWP
1
FREQUENCY
f
#
f
=
z
P
2SR C
F F
2SR C
F
T
Figure 78. Bode Plot of Noise Gain Intersecting with Op Amp Open Loop Gain
Figure 78 shows the bode plot of the noise gain intersecting the op amp open loop gain. With larger values of
gain, CT and RF create a zero in the transfer function. At higher frequencies the circuit can become unstable due
to excess phase shift around the loop.
A pole at fP in the noise gain function is created by placing a feedback capacitor (CF) across RF. The noise gain
slope is flattened by choosing an appropriate value of CF for optimum performance.
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Theoretical expressions for calculating the optimum value of CF and the expected −3 dB bandwidth are:
CT
CF =
2SRF(GBWP)
(7)
(8)
GBWP
2SRFCT
f-3 dB
=
Equation 8 indicates that the −3 dB bandwidth of the TIA is inversely proportional to the feedback resistor.
Therefore, if the bandwidth is important then the best approach would be to have a moderate transimpedance
gain stage followed by a broadband voltage gain stage.
Table 4 shows the measurement results of the LMH6611 with different photodiodes having various capacitances
(CPD) and a feedback resistance (RF) of 1 kΩ.
Table 4. TIA (Figure 66) Compensation and Performance Results(1)
CPD
(pF)
22
CT
(pF)
24
CF CAL
(pF)
CF USED
(pF)
5.6
f −3 dB CAL
(MHz)
29.3
f −3 dB MEAS
(MHz)
27.1
Peaking
(dB)
0.5
5.42
47
49
7.75
8
20.5
21
0.5
100
222
330
102
224
332
11.15
20.39
20.2
12
14.2
15.2
0.5
18
9.6
10.7
0.5
22
7.9
9
0.8
(1) GBWP = 130 MHz, CT = CPD + CIN, CIN = 2 pF, VS = ±2.5V
Figure 79 shows the frequency response for the various photodiodes in Table 4.
3
C
C
= 22 pF,
PD
0
-3
= 5.6 pF
F
C
C
= 47 pF,
PD
-6
= 8 pF
F
-9
C
C
= 100 pF,
PD
-12
-15
-18
-21
-24
-27
= 12 pF
F
C
C
= 222 pF,
PD
= 18 pF
F
C
C
= 330 pF,
PD
= 22 pF
10M
F
1M
100M
FREQUENCY (Hz)
Figure 79. Frequency Response for Various Photodiode and Feedback Capacitors
When analyzing the noise at the output of the TIA, it is important to note that the various noise sources (that is,
op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do not all
operate over the same frequency band. Therefore, when the noise at the output is calculated, this should be
taken into account. The op amp noise voltage will be gained up in the region between the noise gain’s zero and
pole (fZ and fP in Figure 78). The higher the values of RF and CT, the sooner the noise gain peaking starts and
therefore its contribution to the total output noise will be larger. It is advantageous to minimize CIN by proper
choice of op amp or by applying a reverse bias across the diode but this will be at the expense of excess dark
current and noise.
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
EVALUATION BOARD
TI provides the following evaluation board as a guide for high frequency layout and as an aid in device testing
and characterization. Many of the datasheet plots were measured with this board:
Device
Package
SOT
Board Part #
LMH730216
LMH730036
LMH6611MK
LMH6612MA
SOIC
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SNOSB00K –NOVEMBER 2007–REVISED OCTOBER 2013
www.ti.com
REVISION HISTORY
Changes from Revision I (March 2013) to Revision J
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 33
Changes from Revision J (September 2013) to Revision K
Page
•
•
•
Changed from 0.1 uV/°C to 4 μV/°C ..................................................................................................................................... 3
Changed from 0.1 uV/°C to 4 μV/°C ..................................................................................................................................... 5
Changed from 0.4 uV/°C to 4 μV/°C ..................................................................................................................................... 7
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6611MK/NOPB
LMH6611MKE/NOPB
LMH6611MKX/NOPB
LMH6612MA/NOPB
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
D
6
6
6
8
1000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
95 RoHS & Green
2500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AX4A
AX4A
AX4A
SN
SN
SN
ACTIVE
ACTIVE
SOIC
SOIC
LMH66
12MA
LMH6612MAX/NOPB
D
8
SN
Level-1-260C-UNLIM
-40 to 125
LMH66
12MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6611MK/NOPB
LMH6611MKE/NOPB
LMH6611MKX/NOPB
LMH6612MAX/NOPB
SOT-
23-THIN
DDC
DDC
DDC
D
6
6
6
8
1000
250
178.0
178.0
178.0
330.0
8.4
3.2
3.2
3.2
6.5
3.2
3.2
3.2
5.4
1.4
1.4
1.4
2.0
4.0
4.0
4.0
8.0
8.0
Q3
Q3
Q3
Q1
SOT-
23-THIN
8.4
8.0
SOT-
23-THIN
3000
2500
8.4
8.0
SOIC
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6611MK/NOPB
LMH6611MKE/NOPB
LMH6611MKX/NOPB
LMH6612MAX/NOPB
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOIC
DDC
DDC
DDC
D
6
6
6
8
1000
250
208.0
208.0
208.0
367.0
191.0
191.0
191.0
367.0
35.0
35.0
35.0
35.0
3000
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6612MA/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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