LMH6644 MDC [TI]
低功耗、130MHz、75mA 轨到轨输出放大器 | Y | 0 | -40 to 85;
| 型号： | LMH6644 MDC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗、130MHz、75mA 轨到轨输出放大器 | Y | 0 | -40 to 85 放大器 |
| 文件： | 总23页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 9, 2012
LMH6642/LMH6643/LMH6644
Low Power, 130MHz, 75mA Rail-to-Rail Output Amplifiers
General Description
Features
The LMH664X family true single supply voltage feedback am-
plifiers offer high speed (130MHz), low distortion (−62dBc),
and exceptionally high output current (approximately 75mA)
at low cost and with reduced power consumption when com-
pared against existing devices with similar performance.
(VS = ±5V, TA = 25°C, RL = 2kΩ, AV = +1. Typical values un-
less specified).
−3dB BW (AV = +1)
Supply voltage range
130MHz
2.7V to 12.8V
130V/µs
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Slew rate (Note 8), (AV = −1)
Supply current (no load)
Output short circuit current
Linear output current
Input common mode volt.
Output voltage swing
Input voltage noise (100kHz)
Input current noise (100kHz)
THD (5MHz, RL = 2kΩ, VO = 2VPP, AV = +2)
Settling time
Input common mode voltage range extends to 0.5V below V
2.7mA/amp
+115mA/−145mA
−
and 1V from V+. Output voltage range extends to within
40mV of either supply rail, allowing wide dynamic range es-
pecially desirable in low voltage applications. The output
stage is capable of approximately 75mA in order to drive
heavy loads. Fast output Slew Rate (130V/µs) ensures large
peak-to-peak output swings can be maintained even at higher
speeds, resulting in exceptional full power bandwidth of
40MHz with a 3V supply. These characteristics, along with
low cost, are ideal features for a multitude of industrial and
commercial applications.
±75mA
0.5V beyond V−, 1V from V+
40mV from rails
17nV/
0.9pA/
−62dBc
68ns
Fully characterized for 3V, 5V, and ±5V
Overdrive recovery
Output short circuit protected (Note 11)
No output phase reversal with CMVR exceeded
Careful attention has been paid to ensure device stability un-
der all operating voltages and modes. The result is a very well
behaved frequency response characteristic (0.1dB gain flat-
ness up the 12MHz under 150Ω load and AV = +2) with
minimal peaking (typically 2dB maximum) for any gain setting
and under both heavy and light loads. This along with fast
settling time (68ns) and low distortion allows the device to
operate well in ADC buffer, and high frequency filter applica-
tions as well as other applications.
100ns
Applications
Active filters
■
■
■
■
CD/DVD ROM
ADC buffer amp
This device family offers professional quality video perfor-
mance with low DG (0.01%) and DP (0.01°) characteristics.
Differential Gain and Differential Phase characteristics are al-
so well maintained under heavy loads (150Ω) and throughout
the output voltage range. The LMH664X family is offered in
single (LMH6642), dual (LMH6643), and quad (LMH6644)
options. See ordering information for packages offered.
Portable video
Current sense buffer
■
Closed Loop Gain vs. Frequency for Various Gain
Large Signal Frequency Response
20018547
20018535
© 2012 Texas Instruments Incorporated
200185 SNOS966O
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Soldering Information
Infrared or Convection Reflow(20 sec)
Wave Soldering Lead Temp.(10 sec)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
235°C
260°C
Operating Ratings (Note 1)
ESD Tolerance
2KV (Note 2)
Supply Voltage (V+ – V−)
Junction Temperature Range (Note 4)
Package Thermal Resistance (Note 4) (θJA
5-Pin SOT-23
8-Pin SOIC
8-Pin MSOP
2.7V to 12.8V
−40°C to +85°C
200V (Note 9)
1000V (Note 13)
±2.5V
)
VIN Differential
265°C/W
190°C/W
235°C/W
145°C/W
155°C/W
Output Short Circuit Duration
Supply Voltage (V+ - V−)
Voltage at Input/Output pins
Input Current
Storage Temperature Range
Junction Temperature (Note 4)
(Note 3), (Note 11)
13.5V
V+ +0.8V, V− −0.8V
±10mA
−65°C to +150°C
+150°C
14-Pin SOIC
14- Pin TSSOP
3V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ = 25°C, V+ = 3V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage)
as noted (where applicable) and RL = 2kΩ to V+/2. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
BW
−3dB BW
AV = +1, VOUT = 200mVPP
80
115
46
MHz
MHz
AV = +2, −1, VOUT = 200mVPP
BW0.1dB
0.1dB Gain Flatness
19
AV = +2, RL = 150Ω to V+/2,
RL = 402Ω, VOUT = 200mVPP
AV = +1, −1dB, VOUT = 1VPP
f = 100kHz
PBW
en
Full Power Bandwidth
40
17
MHz
Input-Referred Voltage Noise
nV/
pA/
dBc
f = 1kHz
48
in
Input-Referred Current Noise
Total Harmonic Distortion
Differential Gain
f = 100kHz
0.90
3.3
−48
f = 1kHz
THD
DG
f = 5MHz, VO = 2VPP, AV = −1,
RL = 100Ω to V+/2
VCM = 1V, NTSC, AV = +2
RL =150Ω to V+/2
0.17
%
RL =1kΩ to V+/2
0.03
0.05
DP
Differential Phase
VCM = 1V, NTSC, AV = +2
RL =150Ω to V+/2
deg
RL =1kΩ to V+/2
0.03
47
CT Rej.
TS
Cross-Talk Rejection
Settling Time
f = 5MHz, Receiver:
dB
ns
Rf = Rg = 510Ω, AV = +2
VO = 2VPP, ±0.1%, 8pF Load,
VS = 5V
68
SR
Slew Rate (Note 8)
AV = −1, VI = 2VPP
90
120
±1
V/µs
VOS
Input Offset Voltage
For LMH6642 and LMH6644
±5
±7
mV
For LMH6643
±1
±3.4
±7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
(Note 12)
(Note 7)
±5
µV/°C
µA
−1.50
−2.60
−3.25
IOS
RIN
Input Offset Current
20
3
800
1000
nA
Common Mode Input Resistance
MΩ
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2
Symbol
CIN
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
Common Mode Input
Capacitance
2
pF
CMVR
Input Common-Mode Voltage
Range
−0.5
2.0
−0.2
−0.1
CMRR ≥ 50dB
V
1.8
1.6
CMRR
AVOL
Common Mode Rejection Ratio VCM Stepped from 0V to 1.5V
72
95
96
dB
Large Signal Voltage Gain
VO = 0.5V to 2.5V
RL = 2kΩ to V+/2
VO = 0.5V to 2.5V
RL = 150Ω to V+/2
80
75
dB
74
70
82
RL = 2kΩ to V+/2, VID = 200mV
RL = 150Ω to V+/2, VID = 200mV
RL = 2kΩ to V+/2, VID = −200mV
RL = 150Ω to V+/2, VID = −200mV
VO
Output Swing
High
2.90
2.80
2.98
2.93
25
V
Output Swing
Low
75
mV
75
150
ISC
Output Short Circuit Current
Sourcing to V+/2
50
95
35
VID = 200mV (Note 10)
mA
Sinking to V+/2
55
110
40
VID = −200mV (Note 10)
IOUT
Output Current
VOUT = 0.5V from either supply
±65
85
mA
dB
+PSRR
Positive Power Supply Rejection V+ = 3.0V to 3.5V, VCM = 1.5V
Ratio
75
IS
Supply Current (per channel)
No Load
2.70
4.00
4.50
mA
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage)
as noted (where applicable) and RL = 2kΩ to V+/2. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
BW
−3dB BW
AV = +1, VOUT = 200mVPP
90
120
46
MHz
MHz
AV = +2, −1, VOUT = 200mVPP
BW0.1dB
0.1dB Gain Flatness
15
AV = +2, RL = 150Ω to V+/2,
Rf = 402Ω, VOUT = 200mVPP
AV = +1, −1dB, VOUT = 2VPP
f = 100kHz
PBW
en
Full Power Bandwidth
22
17
MHz
Input-Referred Voltage Noise
nV/
pA/
dBc
f = 1kHz
48
in
Input-Referred Current Noise
f = 100kHz
0.90
3.3
f = 1kHz
THD
DG
Total Harmonic Distortion
Differential Gain
f = 5MHz, VO = 2VPP, AV = +2
−60
0.16
NTSC, AV = +2
RL =150Ω to V+/2
%
RL = 1kΩ to V+/2
NTSC, AV = +2
RL = 150Ω to V+/2
0.05
0.05
DP
Differential Phase
deg
dB
RL = 1kΩ to V+/2
0.01
47
CT Rej.
Cross-Talk Rejection
f = 5MHz, Receiver:
Rf = Rg = 510Ω, AV = +2
3
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
TS
Settling Time
VO = 2VPP, ±0.1%, 8pF Load
AV = −1, VI = 2VPP
68
125
±1
ns
SR
VOS
Slew Rate (Note 8)
Input Offset Voltage
95
V/µs
For LMH6642 and LMH6644
±5
±7
mV
For LMH6643
±1
±3.4
±7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
(Note 12)
(Note 7)
±5
µV/°C
µA
−1.70
−2.60
−3.25
IOS
Input Offset Current
20
800
1000
nA
RIN
CIN
Common Mode Input Resistance
3
2
MΩ
pF
Common Mode Input
Capacitance
CMVR
Input Common-Mode Voltage
Range
−0.5
4.0
−0.2
−0.1
CMRR ≥ 50dB
V
3.8
3.6
CMRR
AVOL
Common Mode Rejection Ratio VCM Stepped from 0V to 3.5V
72
95
98
dB
Large Signal Voltage Gain
VO = 0.5V to 4.50V
RL = 2kΩ to V+/2
VO = 0.5V to 4.25V
RL = 150Ω to V+/2
86
82
dB
76
72
82
RL = 2kΩ to V+/2, VID = 200mV
RL = 150Ω to V+/2, VID = 200mV
RL = 2kΩ to V+/2, VID = −200mV
RL = 150Ω to V+/2, VID = −200mV
VO
Output Swing
High
4.90
4.65
4.98
4.90
25
V
Output Swing
Low
100
150
mV
100
115
ISC
Output Short Circuit Current
Sourcing to V+/2
55
40
VID = 200mV (Note 10)
mA
Sinking to V+/2
70
140
55
VID = −200mV (Note 10)
IOUT
Output Current
VO = 0.5V from either supply
±70
90
mA
dB
+PSRR
Positive Power Supply Rejection V+ = 4.0V to 6V
Ratio
79
IS
Supply Current (per channel)
No Load
2.70
4.25
5.00
mA
±5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ = 25°C, V+ = 5V, V− = −5V, VCM = VO = 0V, VID (input differential voltage)
as noted (where applicable) and RL = 2kΩ to ground. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
BW
−3dB BW
AV = +1, VOUT = 200mVPP
95
130
46
MHz
MHz
AV = +2, −1, VOUT = 200mVPP
BW0.1dB
0.1dB Gain Flatness
12
AV = +2, RL = 150Ω to V+/2,
Rf = 806Ω, VOUT = 200mVPP
AV = +1, −1dB, VOUT = 2VPP
f = 100kHz
PBW
en
Full Power Bandwidth
24
17
48
MHz
Input-Referred Voltage Noise
nV/
f = 1kHz
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4
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
in
Input-Referred Current Noise
f = 100kHz
0.90
3.3
pA/
f = 1kHz
THD
DG
Total Harmonic Distortion
Differential Gain
f = 5MHz, VO = 2VPP, AV = +2
NTSC, AV = +2
RL = 150Ω to V+/2
−62
0.15
dBc
%
RL = 1kΩ to V+/2
NTSC, AV = +2
RL = 150Ω to V+/2
0.01
0.04
DP
Differential Phase
deg
RL = 1kΩ to V+/2
0.01
47
CT Rej.
TS
Cross-Talk Rejection
Settling Time
f = 5MHz, Receiver:
dB
ns
Rf = Rg = 510Ω, AV = +2
VO = 2VPP, ±0.1%, 8pF Load,
VS = 5V
68
SR
Slew Rate (Note 8)
AV = −1, VI = 2VPP
100
135
±1
V/µs
mV
VOS
Input Offset Voltage
For LMH6642 and LMH6644
±5
±7
For LMH6643
±1
±3.4
±7
TC VOS
IB
Input Offset Average Drift
Input Bias Current
(Note 12)
(Note 7)
±5
µV/°C
µA
−1.60
−2.60
−3.25
IOS
Input Offset Current
20
800
1000
nA
RIN
CIN
Common Mode Input Resistance
3
2
MΩ
pF
Common Mode Input
Capacitance
CMVR
Input Common-Mode Voltage
Range
−5.5
4.0
−5.2
−5.1
CMRR ≥ 50dB
V
3.8
3.6
CMRR
AVOL
Common Mode Rejection Ratio VCM Stepped from −5V to 3.5V
74
95
96
dB
Large Signal Voltage Gain
VO = −4.5V to 4.5V,
RL = 2kΩ
88
84
dB
VO = −4.0V to 4.0V,
RL = 150Ω
78
74
82
VO
Output Swing
High
4.90
4.65
4.96
4.80
RL = 2kΩ, VID = 200mV
RL = 150Ω, VID = 200mV
RL = 2kΩ, VID = −200mV
RL = 150Ω, VID = −200mV
V
V
Output Swing
Low
−4.96
−4.80
115
−4.90
−4.65
ISC
Output Short Circuit Current
Sourcing to Ground
60
VID = 200mV (Note 10)
35
mA
Sinking to Ground
85
145
VID = −200mV (Note 10)
65
IOUT
Output Current
VO = 0.5V from either supply
±75
78
mA
dB
PSRR
Power Supply Rejection Ratio
(V+, V−) = (4.5V, −4.5V) to (5.5V,
90
−5.5V)
IS
Supply Current (per channel)
No Load
2.70
4.50
5.50
mA
5
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5kΩ in series with 100pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: Positive current corresponds to current flowing into the device.
Note 8: Slew rate is the average of the rising and falling slew rates.
Note 9: Machine Model, 0Ω in series with 200pF.
Note 10: Short circuit test is a momentary test. See Note 11.
Note 11: Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
Note 12: Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
Note 13: CDM: Charge Device Model
Connection Diagrams
5-Pin SOT23 (LMH6642)
8-Pin SOIC (LMH6642)
20018561
20018562
Top View
Top View
8-Pin SOIC and 8-Pin MSOP
(LMH6643)
14-Pin SOIC and 14-Pin TSSOP
(LMH6644)
20018568
Top View
20018563
Top View
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6
Typical Performance Characteristics At TJ = 25°C, V+ = +5, V− = −5V, RF = RL = 2kΩ. Unless otherwise
specified.
Closed Loop Frequency Response for Various Supplies
Closed Loop Gain vs. Frequency for Various Gain
20018557
20018551
Closed Loop Gain vs. Frequency for Various Gain
Closed Loop Frequency Response for Various Temperature
20018550
20018535
Closed Loop Gain vs. Frequency for Various Supplies Closed Loop Frequency Response for Various Temperature
20018548
20018534
7
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Large Signal Frequency Response
Closed Loop Small Signal Frequency Response for Various
Supplies
20018547
20018546
Closed Loop Frequency Response for Various Supplies
±0.1dB Gain Flatness for Various Supplies
20018544
20018545
VOUT (VPP) for THD < 0.5%
VOUT (VPP) for THD < 0.5%
20018509
20018508
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8
VOUT (VPP) for THD < 0.5%
Open Loop Gain/Phase for Various Temperature
20018532
20018510
Open Loop Gain/Phase for Various Temperature
HD2 (dBc) vs. Output Swing
20018533
20018514
HD3 (dBc) vs. Output Swing
HD2 vs. Output Swing
20018504
20018515
9
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HD3 vs. Output Swing
THD (dBc) vs. Output Swing
20018505
20018506
Settling Time vs. Input Step Amplitude
(Output Slew and Settle Time)
Input Noise vs. Frequency
20018512
20018513
VOUT from V+ vs. ISOURCE
VOUT from V− vs. ISINK
20018518
20018519
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VOUT from V+ vs. ISOURCE
VOUT from V− vs. ISINK
20018516
20018517
Swing vs. VS
Short Circuit Current (to VS/2) vs. VS
20018529
20018531
Output Sinking Saturation Voltage vs. IOUT
Output Sourcing Saturation Voltage vs. IOUT
20018520
20018501
11
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Closed Loop Output Impedance vs. Frequency AV = +1
PSRR vs. Frequency
20018503
20018502
CMRR vs. Frequency
Crosstalk Rejection vs. Frequency
(Output to Output)
20018507
20018511
VOS vs. VOUT (Typical Unit)
VOS vs. VCM (Typical Unit)
20018527
20018530
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12
VOS vs. VS (for 3 Representative Units)
VOS vs. VS (for 3 Representative Units)
20018522
20018523
VOS vs. VS (for 3 Representative Units)
IB vs. VS
20018525
20018524
IOS vs. VS
IS vs. VCM
20018528
20018526
13
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IS vs. VS
Small Signal Step Response
20018553
20018521
Large Signal Step Response
Large Signal Step Response
20018541
20018539
Small Signal Step Response
Small Signal Step Response
20018556
20018536
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Small Signal Step Response
Small Signal Step Response
20018552
20018538
Large Signal Step Response
Large Signal Step Response
20018537
20018554
Large Signal Step Response
20018560
15
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Application Information
CIRCUIT DESCRIPTION
The LMH664X family is based on National Semiconductor’s
proprietary VIP10 dielectrically isolated bipolar process.
This device family architecture features the following:
•
•
•
Complimentary bipolar devices with exceptionally high ft
(∼8GHz) even under low supply voltage (2.7V) and low
bias current.
A class A-B “turn-around” stage with improved noise,
offset, and reduced power dissipation compared to similar
speed devices (patent pending).
Common Emitter push-push output stage capable of
75mA output current (at 0.5V from the supply rails) while
consuming only 2.7mA of total supply current per channel.
This architecture allows output to reach within milli-volts of
either supply rail.
20018542
FIGURE 1. Input and Output Shown with CMVR Exceeded
•
•
Consistent performance over the entire operating supply
voltage range with little variation for the most important
specifications (e.g. BW, SR, IOUT, etc.)
However, if the input voltage range of −0.5V to 1V from V+ is
exceeded by more than a diode drop, the internal ESD pro-
tection diodes will start to conduct. The current in the diodes
should be kept at or below 10mA.
Significant power saving (∼40%) compared to competitive
devices on the market with similar performance.
Output overdrive recovery time is less than 100ns as can be
seen from Figure 2 plot:
Application Hints
This Op Amp family is a drop-in replacement for the AD805X
family of high speed Op Amps in most applications. In addi-
tion, the LMH664X will typically save about 40% on power
dissipation, due to lower supply current, when compared to
competition. All AD805X family’s guaranteed parameters are
included in the list of LMH664X guaranteed specifications in
order to ensure equal or better level of performance. Howev-
er, as in most high performance parts, due to subtleties of
applications, it is strongly recommended that the performance
of the part to be evaluated is tested under actual operating
conditions to ensure full compliance to all specifications.
With 3V supplies and a common mode input voltage range
that extends 0.5V below V−, the LMH664X find applications
in low voltage/low power applications. Even with 3V supplies,
the −3dB BW (@ AV = +1) is typically 115MHz with a tested
limit of 80MHz. Production testing guarantees that process
variations with not compromise speed. High frequency re-
sponse is exceptionally stable confining the typical −3dB BW
over the industrial temperature range to ±2.5%.
20018543
FIGURE 2. Overload Recovery Waveform
As can be seen from the typical performance plots, the
LMH664X output current capability (∼75mA) is enhanced
compared to AD805X. This enhancement, increases the out-
put load range, adding to the LMH664X’s versatility.
INPUT AND OUTPUT TOPOLOGY
All input / output pins are protected against excessive volt-
ages by ESD diodes connected to V+ and V- rails (see Figure
3). These diodes start conducting when the input / output pin
voltage approaches 1Vbe beyond V+ or V- to protect against
over voltage. These diodes are normally reverse biased. Fur-
ther protection of the inputs is provided by the two resistors
(R in Figure 3), in conjunction with the string of anti-parallel
diodes connected between both bases of the input stage. The
combination of these resistors and diodes reduces excessive
differential input voltages approaching 2Vbe. The most com-
mon situation when this occurs is when the device is used as
a comparator (or with little or no feedback) and the device
inputs no longer follow each other. In such a case, the diodes
may conduct. As a consequence, input current increases and
the differential input voltage is clamped. It is important to
make sure that the subsequent current flow through the de-
vice input pins does not violate the Absolute Maximum Rat-
ings of the device. To limit the current through this protection
circuit, extra series resistors can be placed. Together with the
built-in series resistors of several hundred ohms, these ex-
Because of the LMH664X’s high output current capability at-
tention should be given to device junction temperature in
order not to exceed the Absolute Maximum Rating.
This device family was designed to avoid output phase re-
versal. With input overdrive, the output is kept near supply rail
(or as closed to it as mandated by the closed loop gain setting
and the input voltage). See Figure 1:
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16
ternal resistors can limit the input current to a safe number
(i.e. < 10mA). Be aware that these input series resistors may
impact the switching speed of the device and could slow down
the device.
C1 to ease biasing and allow single supply operation. With 5V
single supply, the device input/output is shifted to near half
supply using a voltage divider from VCC. Note that Q1 collector
does not have any voltage swing and the Miller effect is min-
imized. D1, tied to Q1 base, is for temperature compensation
of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and
not too large to shift the U1 output too far from mid-supply.
No matter how low an Rf is selected, there is a need for Cf in
order to stabilize the circuit. The reason for this is that the Op
Amp input capacitance and Q1 equivalent collector capaci-
tance together (CIN) will cause additional phase shift to the
signal fed back to the inverting node. Cf will function as a zero
in the feedback path counter-acting the effect of the CIN and
acting to stabilized the circuit. By proper selection of Cf such
that the Op Amp open loop gain is equal to the inverse of the
feedback factor at that frequency, the response is optimized
with a theoretical 45° phase margin.
20018569
FIGURE 3. Input Equivalent Circuit
(1)
SINGLE SUPPLY, LOW POWER PHOTODIODE
AMPLIFIER
where GBWP is the Gain Bandwidth Product of the Op Amp
The circuit shown in Figure 4 is used to amplify the current
from a photo-diode into a voltage output. In this circuit, the
emphasis is on achieving high bandwidth and the tran-
simpedance gain setting is kept relatively low. Because of its
high slew rate limit and high speed, the LMH664X family lends
itself well to such an application.
Optimized as such, the I-V converter will have a theoretical
pole, fp, at:
(2)
With Op Amp input capacitance of 3pF and an estimate for
Q1 output capacitance of about 3pF as well, CIN = 6pF. From
the typical performance plots, LMH6642/6643 family GBWP
is approximately 57MHz. Therefore, with Rf = 1k, from Equa-
tion 1 and 2 above.
This circuit achieves approximately 1V/mA of tran-
simpedance gain and capable of handling up to 1mApp from
the photodiode. Q1, in a common base configuration, isolates
the high capacitance of the photodiode (Cd) from the Op Amp
input in order to maximize speed. Input is AC coupled through
Cf = ∼4.1pF, and fp = 39MHz
20018564
FIGURE 4. Single Supply Photodiode I-V Converter
17
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For this example, optimum Cf was empirically determined to
be around 5pF. This time domain response is shown in Figure
5 below showing about 9ns rise/fall times, corresponding to
about 39MHz for fp. The overall supply current from the +5V
supply is around 5mA with no load.
PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT
VALUES SECTION
Generally, a good high frequency layout will keep power sup-
ply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to ground
will cause frequency response peaking and possible circuit
oscillations (see Application Note OA-15 for more informa-
tion). National Semiconductor suggests the following evalua-
tion boards as a guide for high frequency layout and as an aid
in device testing and characterization:
Device
Package
Evaluation Board
PN
LMH6642MF
LMH6642MA
LMH6643MA
LMH6643MM
LMH6644MA
LMH6644MT
5-Pin SOT-23
8-Pin SOIC
LMH730216
LMH730227
LMH730036
LMH730123
LMH730231
LMH730131
8-Pin SOIC
8-Pin MSOP
14-Pin SOIC
14-Pin TSSOP
Another important parameter in working with high speed/high
performance amplifiers, is the component values selection.
Choosing external resistors that are large in value will effect
the closed loop behavior of the stage because of the interac-
tion of these resistors with parasitic capacitances. These
capacitors could be inherent to the device or a by-product of
the board layout and component placement. Either way,
keeping the resistor values lower, will diminish this interaction
to a large extent. On the other hand, choosing very low value
resistors could load down nodes and will contribute to higher
overall power dissipation.
20018565
FIGURE 5. Converter Step Response (1VPP, 20 ns/DIV)
Ordering Information
Package
Part Number
LMH6642MF
LMH6642MFX
LMH6642MA
LMH6642MAX
LMH6643MA
LMH6643MAX
LMH6643MM
LMH6643MMX
LMH6644MA
LMH6644MAX
LMH6644MT
LMH6644MTX
Package Marking
Transport Media
1k Units Tape and Reel
3k Units Tape and Reel
95 Units/Rail
NSC Drawing
5-Pin SOT-23
A64A
MF05A
LMH6642MA
LMH6643MA
A65A
2.5k Units Tape and Reel
95 Units/Rail
8-Pin SOIC
M08A
2.5k Units Tape and Reel
1k Units Tape and Reel
3.5k Units Tape and Reel
55 units/Rail
8-Pin MSOP
14-Pin SOIC
14-Pin TSSO
MUA08A
M14A
LMH6644MA
LMH6644MT
2.5k Units Tape and Reel
94 Units/Rail
MTC14
2.5k Units Tape and Reel
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18
Physical Dimensions inches (millimeters) unless otherwise noted
5-Pin SOT23
NS Package Number MF05A
8-Pin SOIC
NS Package Number M08A
19
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8-Pin MSOP
NS Package Number MUA08A
14-Pin SOIC
NS Package Number M14A
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20
14-Pin TSSOP
NS Package Number MTC14
21
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Notes
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