LMH6655MAX/NOPB [TI]
双通道、低功耗、250MHz、低噪声放大器 | D | 8 | -40 to 85;
| 型号： | LMH6655MAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、低功耗、250MHz、低噪声放大器 | D | 8 | -40 to 85 放大器 光电二极管 |
| 文件： | 总35页 (文件大小：1660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6654, LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
LMH6654, LMH6655 Single and Dual Low Power, 250 MHz, Low Noise Amplifiers
1 Features
3 Description
The LMH6654 and LMH6655 single and dual high
speed voltage feedback amplifiers are designed to
have unity-gain stable operation with a bandwidth of
250 MHz. They operate from ±2.5 V to ±6 V and each
channel consumes only 4.5 mA. The amplifiers
feature very low voltage noise and wide output swing
to maximize signal-to-noise ratio, and possess a true
single supply capability with input common mode
voltage range extending 150 mV below negative rail
and within 1.3 V of the positive rail. The high speed
and low power combination of the LMH6654 and
LMH6655 make these products an ideal choice for
many portable, high speed applications where power
is at a premium.
1
•
(VS = ±5 V, TJ = 25 °C, Typical Values Unless
Specified)
•
•
•
•
•
•
•
•
•
•
Voltage Feedback Architecture
Unity Gain Bandwidth 250 MHz
Supply Voltage Range ±2.5V to ±6V
Slew Rate 200 V/µsec
Supply Current 4.5 mA/channel
Input Common Mode Voltage −5.15V to +3.7V
Output Voltage Swing (RL = 100 Ω) −3.6V to 3.4V
Input Voltage Noise 4.5 nV/√Hz
Input Current Noise 1.7 pA/√Hz
Settling Time to 0.01% 25 ns
The LMH6654 and LMH6655 are built on TI’s
Advance VIP10™ (Vertically Integrated PNP)
complementary bipolar process.
2 Applications
•
•
•
•
•
•
ADC Drivers
The LMH6654 is packaged in 5-Pin SOT-23 and 8-
Pin SOIC. The LMH6655 is packaged in 8-Pin
VSSOP (DGK) and 8-Pin SOIC.
Consumer Video
Active Filters
Device Information(1)
Pulse Delay Circuits
xDSL Receiver
Pre-amps
PART NUMBER
LMH6654
PACKAGE
BODY SIZE (NOM)
4.90 mm x 3.91 mm
2.90 mm x 1.60 mm
4.90 mm x 3.91 mm
3.00 mm x 3.00 mm
SOIC (8)
LMH6654
SOT-23 (5)
SOIC (8)
LMH6655
LMH6655
VSSOP (8)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Figure 1. Input Voltage and Curernt Noise vs.
Frequency (Vs= ±5V)
100
100
10
1
10
e
n
i
n
1
100k
FREQUENCY (Hz)
100
1k
10k
1M
10M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6654, LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 ±5V Electrical Characteristics ................................... 5
6.6 5V Electrical Characteristics ..................................... 7
6.7 Typical Characteristics.............................................. 9
7
Application and Implementation ........................ 16
7.1 Application Information............................................ 16
7.2 Typical Application .................................................. 16
Power Supply Recommendations...................... 20
8.1 Power Dissipation ................................................... 20
Layout ................................................................... 20
9.1 Layout Guidelines ................................................... 20
8
9
10 Device and Documentation Support ................. 21
10.1 Documentation Support ........................................ 21
10.2 Electrostatic Discharge Caution............................ 21
10.3 Glossary................................................................ 21
11 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
•
Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device
Information Table, Application and Implementation; Power Supply Recommendations; Device and Documentation
Support; Mechanical, Packaging, and Ordering Information. Deleted Switching Characteristics due to redundancy. ......... 1
Changed from Junction Temperature Range to "Operating Temperature Range" ................................................................ 4
Deleted TJ = 25°C................................................................................................................................................................... 5
Deleted TJ = 25°C .................................................................................................................................................................. 7
•
•
•
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
2
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Product Folder Links: LMH6654 LMH6655
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
5 Pin Configuration and Functions
5-Pin (LMH6654)
Package DBV
Top View
8-Pin (LMH6654)
Package D
8-Pin (LMH6655)
SOIC and VSSOP (DGK)
Top View
Top View
1
1
8
8
+
+
5
1
OUT A
V
V
N/C
N/C
OUTPUT
A
+
7
2
-
V
-
-IN
+
2
3
4
7
6
5
-IN A
+IN A
OUT B
-IN B
-
2
V
6
5
3
4
OUTPUT
N/C
+
+IN
-
+
B
4
3
-IN
-
+IN
+
-
V
-
+IN B
V
Pin Functions
PIN
LMH6654
LMH6655
DGK
I/O
DESCRIPTION
NAME
DBV
D
-IN
4
3
2
3
I
I
Inverting Input
+IN
Non-inverting Input
ChA Inverting Input
-IN A
+IN A
-IN B
+IN B
N/C
2
3
6
5
I
I
ChA Non-inverting Input
ChB Inverting Input
ChB Non-inverting Input
No Connection
ChA Output
I
I
1, 5, 8
––
O
O
O
I
OUT A
OUT B
OUTPUT
V-
1
7
ChB Output
1
2
5
6
4
7
Output
4
8
Negative Supply
Positive Supply
V+
I
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN Differential
±1.2
V
(2)
Output Short Circuit Duration
Supply Voltage (V+ − V−)
See
13.2
V
V
V+ +0.5
Voltage at Input pins
V- -0.5
Junction Temperature(3)
150
235
260
°C
°C
°C
Infrared or Convection (20 sec.)
Soldering Information
Wave Soldering (10 sec.)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
−65
150
°C
Human body model (HBM),
2000
200
per ANSI/ESDA/JEDEC JS-001, all pins(2)
V(ESD)
Electrostatic discharge(1)
V
Machine model (MM)(3)
(1) Human body model, 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 100 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted)
MIN
±2.5
−40
NOM
MAX
±6.0
85
UNIT
V
Supply Voltage (V+ - V−)
Operating Temperature Range
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Table.
6.4 Thermal Information
SOIC (D)
8 PINS
172
VSSOP (DGK)
8 PINS
SOT-23 (D)
5 PINS
265
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
235
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
6.5 ±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −5V, VCM = 0V, AV = +1, RF = 25Ω for gain = +1, RF = 402Ω
for gain ≥ +2, and RL = 100Ω. Boldface limits apply at the temperature extremes.
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
AV = +1
250
130
52
AV = +2
AV = +5
AV = +10
fCL
Close Loop Bandwidth
MHz
26
Gain Bandwidth Product
Bandwidth for 0.1 dB Flatness
Phase Margin
A
V ≥ +5
260
18
MHz
MHz
deg
GBWP
AV +1
φm
50
(3)
SR
Slew Rate
AV = +1, VIN = 2 VPP
AV = +1, 2V Step
200
V/µs
Settling Time
0.01%
25
ns
tS
0.1%
Rise Time
Fall Time
15
1.4
1.2
ns
ns
ns
tr
tf
AV = +1, 0.2V Step
AV = +1, 0.2V Step
DISTORTION and NOISE RESPONSE
en
in
Input Referred Voltage Noise
Input-Referred Current Noise
Second Harmonic Distortion
Third Harmonic Distortion
f ≥ 0.1 MHz
4.5
1.7
nV/√Hz
pA/√Hz
f ≥ 0.1 MHz
AV = +1, f = 5 MHz
VO = 2 VPP, RL = 100Ω
−80
−85
dBc
dB
Input Referred, 5 MHz,
Channel-to-Channel
Xt
Crosstalk (for LMH6655 only)
−80
DG
DP
Differential Gain
AV = +2, NTSC, RL = 150Ω
AV = +2, NTSC, RL = 150Ω
0.01%
0.025
Differential Phase
deg
INPUT CHARACTERISTICS
−3
−4
3
4
VOS
Input Offset Voltage
Input Offset Average Drift
Input Bias Current
VCM = 0V
±1
6
mV
µV/°C
µA
(4)
TC VOS
IB
VCM = 0V
12
18
VCM = 0V
VCM = 0V
5
−1
−2
1
2
IOS
RIN
Input Offset Current
Input Resistance
0.3
µA
Common Mode
Differential Mode
Common Mode
Differential Mode
4
20
1.8
1
MΩ
kΩ
CIN
Input Capacitance
pF
dB
V
Input Referred,
VCM = 0V to −5V
70
68
CMRR
CMVR
Common Mode Rejection Ration
Input Common- Mode Voltage Range
90
−5.15
−5.0
CMRR ≥ 50 dB
3.5
3.7
TRANSFER CHARACTERISTICS
AVOL Large Signal Voltage Gain
VO = 4 VPP, RL = 100Ω
60
58
67
dB
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −5V, VCM = 0V, AV = +1, RF = 25Ω for gain = +1, RF = 402Ω
for gain ≥ +2, and RL = 100Ω. Boldface limits apply at the temperature extremes.
PARAMETER
OUTPUT CHARACTERISTICS
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
3.4
3.2
Output Swing High
Output Swing Low
Output Swing High
Output Swing Low
No Load
3.6
−3.9
3.4
−3.7
−3.5
VO
No Load
V
3.2
3.0
RL = 100Ω
RL = 100Ω
−3.4
−3.2
−3.6
280
185
Sourcing, VO = 0V
ΔVIN = 200 mV
145
130
(5)
ISC
Short Circuit Current
mA
Sinking, VO = 0V
ΔVIN = 200 mV
100
80
Sourcing, VO = +3V
Sinking, VO = −3V
AV = +1, f <100 kHz
80
120
IOUT
RO
Output Current
mA
Output Resistance
0.08
Ω
POWER SUPPLY
Input Referred,
VS = ±5V to ±6V
dB
PSRR
IS
Power Supply Rejection Ratio
Supply Current (per channel)
60
76
6
7
4.5
mA
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
6
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −0V, VCM = 2.5V, AV = +1, RF = 25 Ω for gain = +1,
RF = 402Ω for gain ≥ +2, and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes.
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
AV = +1
230
120
50
AV = +2
AV = +5
AV = +10
fCL
Close Loop Bandwidth
MHz
25
GBWP
Gain Bandwidth Product
Bandwidth for 0.1 dB Flatness
Phase Margin
A
V ≥ +5
250
17
MHz
MHz
deg
V/µs
ns
AV = +1
φm
48
(3)
SR
Slew Rate
AV = +1, VIN = 2 VPP
AV = +1, 2V Step
190
Settling Time
0.01%
30
tS
0.1%
Rise Time
Fall Time
20
1.5
ns
ns
ns
tr
tf
AV = +1, 0.2V Step
AV = +1, 0.2V Step
1.35
DISTORTION and NOISE RESPONSE
en
in
Input Referred Voltage Noise
Input Referred Current Noise
Second Harmonic Distortion
Third Harmonic Distortion
f ≥ 0.1 MHz
4.5
1.7
nV/√Hz
pA/√Hz
f ≥ 0.1 MHz
AV = +1, f = 5 MHz
VO = 2 VPP, RL = 100Ω
Input Referred, 5 MHz
−65
−70
−78
dBc
dB
Xt
Crosstalk (for LMH6655 only)
INPUT CHARACTERISTICS
−5
−6.5
5
6.5
VOS
Input Offset Voltage
Input Offset Average Drift
Input Bias Current
VCM = 2.5V
±2
6
mV
µV/°C
µA
(4)
TC VOS
IB
VCM = 2.5V
12
18
VCM = 2.5V
VCM = 2.5V
6
−2
−3
2
3
IOS
RIN
Input Offset Current
Input Resistance
0.5
µA
Common Mode
Differential Mode
Common Mode
Differential Mode
4
20
1.8
1
MΩ
kΩ
CIN
Input Capacitance
pF
dB
V
Input Referred,
VCM = 0V to −2.5V
70
68
CMRR
CMVR
Common Mode Rejection Ration
Input Common Mode Voltage Range
90
CMRR ≥ 50 dB
−0.15
0
3.5
3.7
TRANSFER CHARACTERISTICS
AVOL Large Signal Voltage Gain
VO = 1.6 VPP, RL = 100Ω
58
55
64
dB
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −0V, VCM = 2.5V, AV = +1, RF = 25 Ω for gain = +1,
RF = 402Ω for gain ≥ +2, and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes.
PARAMETER
OUTPUT CHARACTERISTICS
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
3.6
3.4
Output Swing High
Output Swing Low
Output Swing High
Output Swing Low
No Load
3.75
0.9
1.1
1.3
VO
No Load
V
3.5
3.35
RL = 100Ω
RL = 100Ω
3.70
1
1.3
1.45
Sourcing , VO = 2.5V
ΔVIN = 200 mV
90
80
170
140
(5)
ISC
Short Circuit Current
mA
Sinking, VO = 2.5V
ΔVIN = 200 mV
70
60
Sourcing, VO = +3.5V
Sinking, VO = 1.5V
AV = +1, f <100 kHz
30
60
IOUT
RO
Output Current
mA
Output Resistance
.08
Ω
POWER SUPPLY
Input Referred ,
VS = ± 2.5V to ± 3V
dB
PSRR
IS
Power Supply Rejection Ratio
Supply Current (per channel)
60
75
6
7
4.5
mA
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
8
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
6.7 Typical Characteristics
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
4
2
9
6
0
3
-2
0
-4
-3
V
= ±2.5V
V
= ±2.5V
S
S
-6
-6
-8
-9
V
= ±5V
V = ±5V
S
S
-10
-12
-14
-16
-12
-15
-18
-21
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 2. Closed Loop Bandwidth (G = +1)
Figure 3. Closed Loop Bandwidth (G = +2)
24
19
25
20
V
S
= ±5V
V
S
= ±5V
14
9
15
10
5
4
-1
0
-6
-5
V
S
= ±2.5V
V
= ±2.5V
S
-11
-16
-21
-26
-10
-15
-20
-25
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (dB)
FREQUENCY (Hz)
Figure 4. Closed Loop Bandwidth (G = +5)
Figure 5. Closed Loop Bandwidth (G = +10)
5
5.0
4.9
4.8
4.7
4.9
85°C
4.8
4.7
V
= ±5V
4.6
4.5
S
4.6
4.5
4.4
4.3
4.2
4.4
25°C
4.3
-40°C
4.2
V
S
= 5V
4.1
4
5
6
7
8
9
10 11 12
-60 -40 -20
0
20 40 60 80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 6. Supply Current per Channel
vs. Supply Voltage
Figure 7. Supply Current per Channel
vs. Temperature
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
V
= ±5V
S
-40°C
-0.2
-40°C
-0.4
-0.6
-0.8
25°C
85°C
85°C
25°C
-1
-1.2
0
1
2
3
4
5
6
7
8
4
5
6
7
8
9
10 11 12
V
(V)
CM
V
(V)
SUPPLY
Figure 9. Offset Voltage
vs. Common Mode
Figure 8. Offset Voltage
vs. Supply Voltage (VCM = 0V)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
7
6
5
V
= ±2.5V
S
I
BIAS
4
3
2
-40°C
25°C
0.5
V
OS
85°C
3
1
0
0
1
1.5
2
2.5
3.5
-50
0
50
100
TEMPERATURE (°C)
V
(V)
CM
Figure 11. Bias Current and Offset Voltage
vs. Temperature
Figure 10. Offset Voltage
vs. Common Mode
7
-40°C
V
S
= 5V
6
5
25°C
4
85°C
3
2
1
0
-1
0
0.5
1
1.5
2
2.5
3
3.5
V
CM
(V)
Figure 13. Bias Current
vs. Common Mode Voltage
Figure 12. Bias Current
vs. Common Mode Voltage
10
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
120
110
100
CMRR
90
PSRR
80
70
AoL @ ±5V
AoL @ 5V
60
-50
0
50
100
TIME (12.5 ns/div)
TEMPERATURE (°C)
Figure 15. Inverting Large Signal Pulse Response
(VS = 5V)
Figure 14. AOL, PSRR and CMRR
vs. Temperature
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 16. Inverting Large Signal Pulse Response
(VS = ±5V)
Figure 17. Non-Inverting Large Signal Pulse Response
(VS = 5V)
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 18. Non-Inverting Large Signal Pulse Response
(VS = ±5V)
Figure 19. Non-Inverting Small Signal Pulse Response
(VS = 5V)
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 20. Non-Inverting Small Signal Pulse Response
(VS = ±5V)
Figure 21. Inverting Small Signal Pulse Response
(VS = 5V)
100
100
10
1
10
e
n
i
n
1
100k
10k
FREQUENCY (Hz)
100
1k
1M
10M
TIME (12.5 ns/div)
Figure 23. Input Voltage and Current Noise
vs. Frequency (VS = 5V)
Figure 22. Inverting Small Signal Pulse Response
(VS = ±5V)
100
100
10
1
-30
-40
-50
-60
3RD
10
-70
e
n
2ND
-80
-90
-100
-110
i
n
1
100k
FREQUENCY (Hz)
100
1k
10k
1M
10M
0.1
1
10
100
FREQUENCY (MHz)
Figure 24. Input Voltage and Current Noise
vs. Frequency (VS = ±5V)
Figure 25. Harmonic Distortion
vs. Frequency
G = +1, VO = 2 VPP, VS = 5V
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
-30
-60
-65
-70
-75
-80
-85
-90
-95
-100
2ND
-40
-50
-60
-70
3RD
-80
3RD
-90
2ND
-100
-110
-60 -40 -20
0
20 40 60 80 100
0.1
1
10
100
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 27. Harmonic Distortion
vs. Temperature
VS = 5V, f = 5 MHz, VO = 2 VPP
Figure 26. Harmonic Distortion
vs. Frequency
G = +1, VO = 2 VPP, VS = ±5V
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-60
-65
-70
-75
-80
-85
-90
-95
-100
2ND
3RD
3RD
2ND
1
2
3
4
5
6
7
8
9
10
-60 -40 -20
0
20 40 60 80 100
GAIN (V/V)
TEMPERATURE (°C)
Figure 29. Harmonic Distortion
vs. Gain
VS = 5V, f = 5 MHz, VO = 2 VPP
Figure 28. Harmonic Distortion
vs. Temperature
VS = ±5V, f = 5 MHz, VO = 2 VPP
-45
-50
-30
-40
-50
2ND
-55
-60
2ND
-65
-70
-75
-80
-85
-90
-95
-60
-70
-80
3RD
3RD
-90
-100
1
2
3
4
5
6
7
8
9
10
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT SWING (V
)
PP
GAIN (V/V)
Figure 30. Harmonic Distortion
vs. Gain
Figure 31. Harmonic Distortion
vs. Output Swing
VS = ±5V, f = 5 MHz, VO = 2 VPP
(G = +2, VS = 5V, f = 5 MHz)
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
100
-30
-40
-50
-60
-70
-80
-90
-100
NEGATIVE
90
80
70
2ND
60
50
POSITIVE
40
30
3RD
20
10
0
10k
1M
10
1k
100k
10M
100
0
1
2
3
4
5
6
7
8
FREQUENCY (Hz)
OUTPUT SWING (V
)
PP
Figure 33. PSRR vs. Frequency
Figure 32. Harmonic Distortion
vs. Output Swing
(G = +2, VS = ±5V, f = 5 MHz)
5
4
120
100
80
V
S
= ±5V
3
60
2
1
0
40
20
0
V
= 5V
S
V
= ±5V
S
100
1k
FREQUENCY
10
10k 100k
1M 10M
1
k
.01
0.1
1
10
100
OUTPUT SINKING CURRENT (mA)
Figure 34. CMRR vs. Frequency
Figure 35. Output Sinking Current
5
4
-20
-30
V
S
= 5V
-40
-50
3
-60
-70
V
= ±5V
S
2
1
0
-80
-90
-100
-110
-120
V
= 5V
S
1
k
.01
0.1
1
10
100
100k
1M
10M
100M
FREQUENCY (Hz)
OUTPUT SOURCING CURRENT (mA)
Figure 37. CrossTalk
Figure 36. Output Sourcing Current
vs. Frequency (LMH6655 only)
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
-20
100
90
80
70
60
50
40
30
20
10
0
25:
V
= ±5V
S
-30
R
ISO
-
+
-40
1 k:
×
-50
C
L
-60
-70
-80
-90
-100
-110
-120
100k
1M
10M
100M
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
CAPACITIVE LOAD, C (pF)
L
Figure 38. CrossTalk
vs. Frequency (LMH6655 only)
Figure 39. Isolation Resistance
vs. Capacitive Load
100
90
80
70
60
50
40
30
20
10
0
180
144
PHASE
108
72
36
0
-36
-72
GAIN
-108
-144
-180
-10
-20
1k
1M
FREQUENCY (Hz)
100M
500M
10k
100k
10M
Figure 40. Open Loop Gain and Phase
vs. Frequency
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7 Application and Implementation
7.1 Application Information
The LMH6654 single and LMH6655 dual high speed, voltage feedback amplifiers are manufactured on TI’s new
VIP10™ (Vertically Integrated PNP) complementary bipolar process. These amplifiers can operate from ±2.5 V to
±6 V power supply. They offer low supply current, wide bandwidth, very low voltage noise and large output
swing. Many of the typical performance plots found in the datasheet can be reproduced if 50 Ω coax and 50 Ω
RIN/ROUT resistors are used.
7.2 Typical Application
7.2.1 Design Requirements
7.2.1.1 Components Selection and Feedback Resistor
It is important in high-speed applications to keep all component leads short since wires are inductive at high
frequency. For discrete components, choose carbon composition axially leaded resistors and micro type
capacitors. Surface mount components are preferred over discrete components for minimum inductive effect.
Never use wire wound type resistors in high frequency applications.
Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as
ringing or oscillation in high-speed amplifiers. Keep resistors as low as possible consistent with output loading
consideration. For a gain of 2 and higher, 402 Ω feedback resistor used for the typical performance plots gives
optimal performance. For unity gain follower, a 25 Ω feedback resistor is recommended rather than a direct short.
This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the
parasitic capacitance at the inverting input.
7.2.2 Detailed Design Procedure
7.2.2.1 Driving Capacitive Loads
Capacitive loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as
shown in Figure 41 below. At frequencies above
1
F =
2 S RISO CLOAD
(1)
the load impedance of the Amplifier approaches RISO. The desired performance depends on the value of the
isolation resistor. The isolation resistance vs. capacitance load graph in the typical performance characteristics
provides the means for selection of the value of RS that provides ≤ 3 dB peaking in closed loop AV = 1 response.
In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation,
a 50Ω isolation resistor is recommended.
25:
-
R
ISO
V
OUT
+
V
IN
Figure 41. Isolation Resistor Placement
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Typical Application (continued)
7.2.2.2 Bias Current Cancellation
In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain
setting Rg and feedback Rf resistors should equal the equivalent source resistance Rseq as defined in Figure 42.
Combining this constraint with the non-inverting gain equation, allows both Rf and Rg to be determined explicitly
from the following equations:
Rf = AVRseq and Rg = Rf/(AV−1)
(2)
For inverting configuration, bias current cancellation is accomplished by placing a resistor Rb on the non-inverting
input equal in value to the resistance seen by the inverting input (Rf//(Rg+Rs). The additional noise contribution of
Rb can be minimized through the use of a shunt capacitor.
Figure 42. Non-Inverting Amplifier Configuration
Figure 43. Inverting Amplifier Configuration
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Typical Application (continued)
7.2.2.3 Total Input Noise vs. Source Resistance
The noise model for the non-inverting amplifier configuration showing all noise sources is described in Figure 44.
In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in−) sources, there also exits
et = 4kTR
thermal voltage noise
associated with each of the external resistors. Equation 3 provides the general
form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that
assumes Rf || Rg = Rseq for bias current cancellation. Figure 45 illustrates the equivalent noise model using this
assumption. The total equivalent output voltage noise (eno) is eni * AV.
Figure 44. Non-Inverting Amplifier Noise Model
eni
=
en2 + (in+ · RSeq)2 + 4kTRSeq + (in- · (Rf || Rg))2 + 4kT(Rf || Rg)
(3)
Figure 45. Noise Model with Rf || Rg = Rseq
en2 + 2 (in · RSeq)2 + 4kT (2RSeq
eni =
)
(4)
If bias current cancellation is not a requirement, then Rf || Rg does not need to equal Rseq. In this case, according
to Equation 3, Rf and Rg should be as low as possible in order to minimize noise. Results similar to Equation 3
are obtained for the inverting configuration on if Rseq is replaced by Rb || Rg is replaced by Rg + Rs. With these
substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is
easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
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Typical Application (continued)
7.2.2.3.1 Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
2
e
S /N
ni
e 2
i
i
= 10LOG
NF = 10LOG
S /N
o
o
t
(5)
The noise figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF.
The NF is increased because the RT reduces the input signal amplitude thus reducing the input SNR.
en2 + in2 (RSeq + (Rf || Rg))2 + 4KTRSeq + 4kt (Rf || Rg)
4kTRSeq
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg.
To minimize noise figure, the following steps are recommended:
1. Minimize Rf||Rg
2. Choose the Optimum Rs (ROPT
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
OPT ≈ (en/in)
)
R
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8 Power Supply Recommendations
8.1 Power Dissipation
The package power dissipation should be taken into account when operating at high ambient temperature and/or
high power dissipative conditions. In determining maximum operable temperature of the device, make sure the
total power dissipation of the device is considered; this power dissipated in the device with a load connected to
the output as well as the nominal dissipation of the op amp.
9 Layout
9.1 Layout Guidelines
With all high frequency devices, board layouts with stray capacitance have a strong influence on the AC
performance. The LMH6654/LMH6655 are not exception and the inverting input and output pins are particularly
sensitive to the coupling of parasitic capacitance to AC ground. Parasitic capacitances on the inverting input and
output nodes to ground could cause frequency response peaking and possible circuit oscillation. Therefore, the
power supply, ground traces and ground plan should be placed away from the inverting input and output pins.
Also, it is very important to keep the parasitic capacitance across the feedback to an absolute minimum.
The PCB should have a ground plane covering all unused portion of the component side of the board to provide
a low impedance path. All trace lengths should be minimized to reduce series inductance.
Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance
return current path at the supply pins. They also provide high frequency filtering on the power supply traces. It is
recommended that a ceramic decoupling capacitor 0.1 µF chip should be placed with one end connected to the
ground plane and the other side as close as possible to the power pins. An additional 10 µF tantalum electrolytic
capacitor should be connected in parallel, to supply current for fast large signal changes at the output.
+
V
10 µF
+
0.1 µF
0.1 µF
+
10 µF
-
V
Figure 46. Supply Bypass Capacitors
9.1.1 Evaluation Boards
TI provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
DEVICE
PACKAGE
5-Pin SOT-23
8-Pin SOIC
EVALULATION BOARD PN
LMH730216
LMH6654MF
LMH6654MA
LMH6655MA
LMH6655MM
LMH730227
8-Pin SOIC
LMH730036
8-Pin VSSOP (DGK)
LMH730123
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
Components Needed to Evaluate the LMH6654 on the LMH730227 Evaluation Board:
•
•
•
•
•
Rf, Rg use the datasheet to select values.
RIN, ROUT typically 50 Ω (Refer to the Basic Operation section of the evaluation board datasheet for details)
Rf is an optional resistor for inverting again configurations (select Rf to yield desired input impedance = Rg||Rf)
C1, C2 use 0.1 µF ceramic capacitors
C3, C4 use 10 µF tantalum capacitors
Components not used:
1. C5, C6, C7, C8
2. R1 thru R8
The evaluation boards are designed to accommodate dual supplies. The board can be modified to provide single
operation. For best performance;
1) Do not connect the unused supply.
2) Ground the unused supply pin.
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
10.1.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LMH6654
LMH6655
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6654MA/NOPB
LMH6654MAX/NOPB
LMH6654MF
ACTIVE
SOIC
SOIC
D
D
8
8
5
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH66
54MA
ACTIVE
NRND
2500 RoHS & Green
SN
LMH66
54MA
SOT-23
DBV
1000
Non-RoHS
& Green
Call TI
A66A
LMH6654MF/NOPB
LMH6654MFX/NOPB
LMH6655MA
ACTIVE
ACTIVE
NRND
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-235C-UNLIM
-40 to 85
-40 to 85
-40 to 85
A66A
A66A
3000 RoHS & Green
95
95
Non-RoHS
& Green
Call TI
LMH66
55MA
LMH6655MA/NOPB
LMH6655MAX/NOPB
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMH66
55MA
2500 RoHS & Green
LMH66
55MA
LMH6655MM/NOPB
LMH6655MMX/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A67A
A67A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6654MAX/NOPB
LMH6654MF
SOIC
SOT-23
SOT-23
SOT-23
SOIC
D
8
5
5
5
8
8
8
2500
1000
1000
3000
2500
1000
3500
330.0
178.0
178.0
178.0
330.0
178.0
330.0
12.4
8.4
6.5
3.2
3.2
3.2
6.5
5.3
5.3
5.4
3.2
3.2
3.2
5.4
3.4
3.4
2.0
1.4
1.4
1.4
2.0
1.4
1.4
8.0
4.0
4.0
4.0
8.0
8.0
8.0
12.0
8.0
Q1
Q3
Q3
Q3
Q1
Q1
Q1
DBV
DBV
DBV
D
LMH6654MF/NOPB
LMH6654MFX/NOPB
LMH6655MAX/NOPB
LMH6655MM/NOPB
LMH6655MMX/NOPB
8.4
8.0
8.4
8.0
12.4
12.4
12.4
12.0
12.0
12.0
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6654MAX/NOPB
LMH6654MF
SOIC
SOT-23
SOT-23
SOT-23
SOIC
D
8
5
5
5
8
8
8
2500
1000
1000
3000
2500
1000
3500
367.0
208.0
208.0
208.0
367.0
208.0
367.0
367.0
191.0
191.0
191.0
367.0
191.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DBV
DBV
DBV
D
LMH6654MF/NOPB
LMH6654MFX/NOPB
LMH6655MAX/NOPB
LMH6655MM/NOPB
LMH6655MMX/NOPB
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6654MA/NOPB
LMH6655MA
D
D
D
D
SOIC
SOIC
SOIC
SOIC
8
8
8
8
95
95
95
95
495
495
495
495
8
8
8
8
4064
4064
4064
4064
3.05
3.05
3.05
3.05
LMH6655MA
LMH6655MA/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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