LMH6672 [TI]
双路、高输出电流、高速运算放大器;
| 型号： | LMH6672 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、高输出电流、高速运算放大器 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：1398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6672
SNOS957H –APRIL 2001–REVISED AUGUST 2014
LMH6672 Dual, High Output Current, High Speed Op Amp
1 Features
2 Applications
1
•
High Output Drive
•
•
•
ADSL PCI Modem Cards
xDSL External Modems
Line Drivers
–
19.2 VPP Differential Output Voltage,
RL = 50 Ω
–
9.6 VPP Single-ended Output Voltage,
3 Description
RL = 25 Ω
The LMH6672 is a low cost, dual high speed op amp
capable of driving signals to within 1 V of the power
supply rails. It features the high output drive with low
distortion required for the demanding application of a
single supply xDSL line driver.
•
•
High Output Current
–
±200 mA @ VO = 9 VPP, VS = 12 V
Low Distortion
–
105 dB SFDR @ 100 kHz, VO = 8.4 VPP,
RL = 25Ω
When connected as a differential output driver, the
LMH6672 can drive a 50-Ω load to 16.8 VPP swing
with only −98 dBc distortion, fully supporting the peak
upstream power levels for upstream full-rate ADSL.
The LMH6672 is fully specified for operation with 5-V
and 12-V supplies. Ideal for PCI modem cards and
xDSL modems.
–
98 dB SFDR @ 1MHz, VO = 2 VPP
RL = 100 Ω
,
•
•
High Speed
–
–
90 MHz 3 dB Bandwidth (G = 2)
135 V/µs Slew Rate
Low Noise
Device Information(1)
–
–
3.1 nV/√Hz: Input Noise Voltage
1.8 pA/√Hz: Input Noise Current
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMH6672
SOIC (8)
4.89 mm × 3.90 mm
•
•
•
•
Low Supply Current: 7.2mA/amp
Single-supply Operation: 5 V to 12 V
Stable for Gain of +2V/V or Higher
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Available in 8-pin SOIC and SO PowerPAD (DDA)
Typical Application
+
+
1/2
LMH6672
-
-
R
12.5
O
Rf1
1:N
R
= 100:
L
.
A
V
V
IN
V
OUT
VIN (V
)
PP
Rg
(1.2)
Rf2
Note: Supply and Bypassing not shown.
R
O
12.5
-
1/2
LMH6672
-
+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6672
SNOS957H –APRIL 2001–REVISED AUGUST 2014
www.ti.com
Table of Contents
6.6 ±2.5V Electrical Characteristics ................................ 6
6.7 Typical Performance Characteristics ........................ 7
Detailed Description ............................................ 15
7.1 Functional Block Diagram ....................................... 15
Power Supply Recommendations...................... 16
8.1 Thermal Management............................................. 16
Device and Documentation Support.................. 18
9.1 Trademarks............................................................. 18
9.2 Electrostatic Discharge Caution.............................. 18
9.3 Glossary.................................................................. 18
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
7
8
9
10 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March 2013) to Revision H
Page
•
Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device
Information Table, Application and Implementation; Device and Documentation Support; Mechanical, Packaging,
and Ordering Information ....................................................................................................................................................... 1
•
•
Added "Stable for Gain of +2V/V or Higher" in Features ....................................................................................................... 1
Changed from "Junction Temperature Range" to "Operating Temperature Range" in Recommended Operating
Conditions............................................................................................................................................................................... 4
•
•
•
•
•
•
•
•
•
•
•
•
•
Deleted TJ = 25°C in Electrical Characteristics ...................................................................................................................... 5
Deleted TJ = 25°C and "Slew Rate" in ±2.5V Electrical Characteristics................................................................................. 6
Added condition "Av = + 2V/V" in Typical Performance Characteristics................................................................................ 7
Added "Vs= +/-2.5V" and "Vs=+/-6V" as curve labels for Figure 36 .................................................................................... 11
Changed curve label from 31 MHz to 13 MHz. Changed title from +5V to +5V/V in Figure 37........................................... 12
Changed "10V" to + "10V/V" in caption title for Figure 38.................................................................................................... 12
Added "Vs = 12V" to Figure 39 caption title ......................................................................................................................... 13
Added "Vs = 5V" to Figure 40 caption title ........................................................................................................................... 13
Changed from "40 = 346 mW" to "40 mW lower or 346 mW" in Thermal Management...................................................... 17
Changed from 41 mW to 17 mW.......................................................................................................................................... 17
Added "from ambient"........................................................................................................................................................... 17
Changed sentence beginning with "Using the same PDRIVER as above..." ........................................................................... 17
Added caution note............................................................................................................................................................... 17
Changes from Revision F (March 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 17
2
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
5 Pin Configuration and Functions
8-Pin
SOIC (D) / SO PowerPAD (DDA)
(Top View)
1
+
8
V
OUT A
A
-
+
2
3
4
7
6
5
OUT B
-IN B
-IN A
+IN A
B
+
-
-
+IN B
V
Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUT A
-IN A
+IN A
V-
1
2
3
4
5
6
7
8
O
I
ChA Output
ChA Inverting Input
ChA Non-inverting Input
Negative Supply
I
I
+IN B
-IN B
OUT B
V+
I
ChB Non-inverting Input
ChB Inverting Input
ChB Output
I
O
I
Positive Supply
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN Differential
±1.2
V
Output Short Circuit Duration
Supply Voltage (V+ − V−)
See(2)
13.2
V
V
V+ +0.8
Voltage at Input/Output pins
Junction Temperature
V− −0.8
+150(3)
°C
°C
°C
Soldering Information
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235
260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Shorting the output to either supply or ground will exceed the absolute maximum TJ and can result in failure.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 Handling Ratings
MIN
−65
2
MAX
+150
2000
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(2)
V(ESD)
Electrostatic discharge(1)
V
Machine Model (MM)l(3)
200
(1) Human body model, 1.5 kΩ in series with 100 pF. Machine model, 200 Ω in series with 100 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
±6.5
150
UNIT
V
Supply Voltage (V+ - V−)
±2.5
Operating Temperature Range
−40
°C
6.4 Thermal Information
SOIC
Package D
SO PowerPAD
Package DDA
THERMAL METRIC(1)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
172
58.6
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
6.5 Electrical Characteristics
Unless otherwise specified, all limits are ensured for G = +2, VS = ±2.5 to ±6V, RF = RIN = 470Ω, RL = 100Ω.
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
−3dB Bandwidth
0.1dB Bandwidth
90
12
MHz
MHz
V/μs
ns
VS = ±6V
Slew Rate
VS = ±6V, 4V Step, 10-90%
VS = 6V, 4V Step, 10-90%
135
23.5
Rise and Fall Time
DISTORTION and NOISE RESPONSE
2nd Harmonic Distortion
VO = 8.4 VPP, f = 100 kHz, RL = 25Ω
VO = 8.4 VPP, f = 1 MHz, RL = 100Ω
VO = 8.4 VPP, f = 100 kHz, RL = 25Ω
VO = 8.4 VPP, f = 1 MHz, RL = 100Ω
f = 100 kHz
−105
−90
−110
−87
3.1
dBc
dBc
3rd Harmonic Distortion
dBc
dBc
Input Noise Voltage
Input Noise Current
nV√Hz
pA/√Hz
f = 100 kHz
1.8
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TJ = −40°C to 125°C
−5.5
−4
0.1
−0.2
8
5.5
4
mV
IB
Input Bias Current
TJ = −40°C to 125°C
TJ = −40°C to 125°C
VS = ±6V
16
2.1
4.5
µA
µA
IOS
Input Offset Current
−2.1
0
CMVR
CMRR
Common Voltage Range
Common-Mode Rejection Ratio
−6.0 −5.7 to 4.5
V
VS = ±6V, TJ = −40°C to 125°C
150
7.5
µV/V
TRANSFER CHARACTERISTICS
AVOL
Voltage Gain
RL = 1k, TJ = −40°C to 125°C
RL = 25Ω, TJ = −40°C to 125°C
RL = 25Ω, VS = ±6V
1.0
0.67
−4.5
5
3.4
V/mV
V/mV
VO
Output Swing
±4.8
4.5
4.4
4.8
4.7
V
V
RL = 25Ω, TJ = −40°C to 125°C,
VS = ±6V
−4.4
−4.8
−4.7
350
±4.8
±4.8
±4.8
525
600
VO
Output Swing
RL = 1k, VS = ±6V
RL = 1k, TJ = −40°C to 125°C,
VS = ±6V
ISC
Output Current(3)
VO = 0, VS = ±6V
mA
mA
VO = 0, VS = ±6V,
TJ = −40°C to 125°C
260
POWER SUPPLY
IS
Supply Current/Amp
VS = ±6V
8
9
mA
dB
VS = ±6V, TJ = −40°C to 125°C
7.2
PSRR
Power Supply Rejection Ratio
VS = ±2.5V to ±6V,
TJ = −40°C to 125°C
72
88.5
(1) All limits are specified by testing, characterization or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Shorting the output to either supply or ground will exceed the absolute maximum TJ and can result in failure.
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6.6 ±2.5V Electrical Characteristics
Unless otherwise specified, all limits are ensured for G = +2, VS = ±2.5 to ±6V, RF = RIN = 470Ω, RL = 100Ω.
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
−3 dB Bandwidth
0.1 dB Bandwidth
80
12
14
MHz
MHz
ns
Rise and Fall Time
2V Step, 10-90%
DISTORTION and NOISE RESPONSE
2nd Harmonic Distortion
VO = 2 VPP, f = 100 kHz, RL = 25Ω
VO = 2 VPP, f = 1 MHz, RL = 100Ω
VO = 2 VPP, f = 100 kHz, RL = 25Ω
VO = 2 VPP, f = 1 MHz, RL = 100Ω
−96
−85
−98
−87
dBc
dBc
dBc
dBc
3rd Harmonic Distortion
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TJ = −40°C to 125°C
TJ = −40°C to 125°C
TJ = −40°C to 125°C
−5.5
−4.0
5.5
4.0
16
mV
0.02
8.0
IB
Input Bias Current
µA
V
CMVR
CMRR
Common-Mode Voltage Range
Common-Mode Rejection Ratio
−2.5
1.0
150
8
µV/V
TRANSFER CHARACTERISTICS
AVOL Voltage Gain
RL = 25Ω, TJ = −40°C to 125°C
RL = 1k, TJ = −40°C to 125°C
0.67
1.0
3
4
V/mV
V
OUTPUT CHARACTERISTICS
VO Output Voltage Swing
RL = 25Ω
1.20
1.10
1.30
1.25
1.45
1.35
1.60
1.50
RL = 25Ω, TJ = −40°C to 125°C
RL = 1k
RL = 1k, TJ = −40°C to 125°C
POWER SUPPLY
IS Supply Current/Amp
8.0
9.0
mA
TJ = −40°C to 125°C
6.7
(1) All limits are specified by testing, characterization or statistical analysis.
(2) Typical values represent the most likely parametric norm.
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
6.7 Typical Performance Characteristics
Av = + 2V/V
14
1.2
1.0
0.8
0.6
0.4
-40°C
1k:
12
10
85°C
25°C
25:
8
6
4
2
0
0.2
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
14
±V
SUPPLY
(V)
V
(V)
S
Figure 2. Positive Output Swing into 1kΩ
Figure 1. Output Swing RL = 25Ω, 1 kΩ @ −40°C, 25°C, 85°C
1.0
-40°C
0.9
1.6
1.4
-40°C
1.2
0.8
0.7
0.6
1.0
85°C
25°C
85°C
0.8
0.5
0.4
0.3
25°C
0.6
0.4
0.2
0
0.2
0.1
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
±V
SUPPLY
(V)
±V
SUPPLY
(V)
Figure 3. Negative Output Swing into 1 kΩ
Figure 4. Positive Output Swing into 25Ω
1.4
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
V
S
= ±6V
1.2
-40°C
1.0
25°C
25°C
0.8
85°C
85°C
0.6
0.4
0.2
0
-40°C
0
1
2
3
4
5
6
7
0
50
100
150
(mA)
200
250
±V
SUPPLY
(V)
I
LOAD
Figure 5. Negative Output Swing into 25Ω
Figure 6. +VOUT vs. ILOAD
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Typical Performance Characteristics (continued)
Av = + 2V/V
5.5
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
V
S
= ±2.5V
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
V
= ±6V
S
85°C
85°C
25°C
50
25°C
-40°C
100
-40°C
0
150
200
250
0
50
100
150
200
250
I
(mA)
I
(mA)
LOAD
LOAD
Figure 7. −VOUT vs. ILOAD
Figure 8. +VOUT vs. ILOAD
16
14
12
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
85°C
V
S
= ±2.5V
25°C
-40°C
85°C
10
8
6
25°C
4
-40°C
2
0
0
2
4
6
8
10 12 14 16
0
50
100
150
200
250
SUPPLY VOLTAGE (V)
I
(mA)
LOAD
Figure 10. Supply Current vs. Supply Voltage
Figure 9. −VOUT vs. ILOAD
700
600
500
400
300
200
700
-40°C
-40°C
600
500
25°C
85°C
25°C
85°C
400
300
200
3
4
5
6
7
8
9
10 11 12 13
3
4
5
6
7
8
9
10 11 12 13
V
S
(V)
V (V)
S
Figure 11. Sourcing Current vs. Supply Voltage
Figure 12. Sinking Current vs. Supply Voltage
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
Typical Performance Characteristics (continued)
Av = + 2V/V
1
3
2
1
0.5
-40°C
25°C
25°C
-40°C
0
0
-1
-2
-3
85°C
-0.5
-1
85°C
3
5
6
7
8
9
10 11 12 13 14 15
4
-0.5
1
2.5
4
5.5
7
8.5 10 11.5 13
V
(V)
S
V
CM
(V)
Figure 13. VOS vs. VS
Figure 14. VOS vs. VCM, VS = 12V
10
8
3
85°C
25°C
2
1
-40°C
25°
-40°C
85°C
6
4
2
0
-1
-2
-3
0
-0.5
0
0.5
1
1.5
2
2.5
(V)
3
3.5
4
4.5
5
2
4
6
8
10
12
14
V
SUPPLY VOLTAGE (V)
CM
Figure 16. Bias Current vs. VSUPPLY
Figure 15. VOS vs. VCM, VS = 5V
0.1
0.08
0.06
3
T
= -40°C to 85°C
J
2
1
-40°C
25°C
0
-1
85°C
0.04
0.02
-2
-3
R
= 1k:
L
2
4
6
8
10
(V)
12
14
-2.5 -2 -1.5 -1 -0.5
0
0.5
(V)
1
1.5 2 2.5
V
V
SUPPLY
OUT
Figure 17. Offset Current vs. VSUPPLY
Figure 18. VOUT vs. VIN
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Typical Performance Characteristics (continued)
Av = + 2V/V
3
-45
-55
-65
-75
-85
V
= ±6V
S
f = 1 MHz
2
V
= 2 V
OUT
PP
1
-40°C
25°C
0
2ND
-1
85°C
-95
-105
-115
-2
-3
R
= 25:
L
3RD
0
100
200
300
400
500
-2.5 -2 -1.5 -1 -0.5
0
0.5
(V)
1
1.5
2
2.5
LOAD RESISTANCE
V
OUT
Figure 20. Harmonic Distortion vs. Load
Figure 19. VOUT vs. VIN
-45
-55
-65
-75
-85
-45
V
= ±2.5V
S
V
f
= ±6V
= 1 MHz
S
f = 1 MHz
-55
-65
-75
-85
V
= 2 V
OUT
PP
3RD
3RD
-95
-105
-115
-95
-105
-115
2ND
2ND
0
100
200
300
400
500
0
1
2
3
4
5
6
7
8
9
10 11
LOAD RESISTANCE
OUTPUT VOLTAGE PEAK TO PEAK
Figure 21. Harmonic Distortion vs. Load
Figure 22. Harmonic Distortion vs. Output Voltage
-35
-45
V
= ±2.5V
S
V
= ±6V
S
f = 1 MHz
-45 f = 1 MHz
-55
-65
R
= 25:
L
-55
-65
-75
-75
-85
-95
2ND
2ND
-85
-95
3RD
-105
-115
3RD
-105
0
1
2
3
4
5
6
7
8
9
10 11
0.0
0.5
1.0
2.0
2.5
3.0
1.5
OUTPUT VOLTAGE PEAK TO PEAK
OUTPUT VOLTAGE PEAK TO PEAK
Figure 24. Harmonic Distortion vs. Output Voltage
Figure 23. Harmonic Distortion vs. Output Voltage
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Typical Performance Characteristics (continued)
Av = + 2V/V
-45
-55
-65
V
= ±2.5V
S
V
= ±6V
S
f = 1 MHz
-55
-65
f = 100 kHz
R
= 25:
L
-75
-85
-75
-85
-95
2ND
-95
2ND
-105
3RD
-115
-125
-105
-115
3RD
7
0.0
0.5
1.0
2.0
2.5
3.0
1.5
0
1
2
3
4
5
6
8
9 10 11
OUTPUT VOLTAGE PEAK TO PEAK
OUTPUT VOLTAGE PEAK TO PEAK
Figure 25. Harmonic Distortion vs. Output Voltage
Figure 26. Harmonic Distortion vs. Output Voltage
-35
-20
V
= ±6V
S
V
V
= ±6V
S
-30
-40
f = 100 kHz
-45
-55
= 2 V
PP
OUT
R
= 25:
L
-50
-65
-60
-75
-70
2ND
-85
-80
-95
-90
2ND
3RD
-105
-100
-110
-120
-115
-125
3RD
0
1
2
3
4
5
6
7
8
9
10 11
0.1
1
10
100
FREQUENCY (MHz)
OUTPUT VOLTAGE PEAK TO PEAK
Figure 28. Harmonic Distortion vs. Frequency
Figure 27. Harmonic Distortion vs. Output Voltage
-20
-20
V
V
= ±2.5V
S
V
= ±6V
S
-30
-40
-30
-40
= 2 V
PP
OUT
R
= 25:
L
V
= 2 V
PP
OUT
-50
-50
-60
-60
3RD
-70
-70
2ND
-80
-80
-90
-90
2ND
-100
-110
-120
-100
-110
-120
3RD
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. Harmonic Distortion vs. Frequency
Figure 30. Harmonic Distortion vs. Frequency
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Typical Performance Characteristics (continued)
Av = + 2V/V
-20
V
= ±2.5V
S
-30
-40
R
= 25:
L
V
= 2 V
PP
OUT
-50
2ND
-60
0
-70
-80
-90
-100
-110
-120
3RD
20 ns/DIV
0.1
1
10
100
FREQUENCY (MHz)
Figure 32. Pulse Response, VS= ±6V
Figure 31. Harmonic Distortion vs. Frequency
0
0
20 ns/DIV
20 ns/DIV
Figure 33. Pulse Response, VS= ±2.5V, ±6V
Figure 34. Pulse Response, AVCL = −1, VS= ±6V
7
6.8
6.7
6.6
6.5
6.4
Vs = 6 V
6
5
Vs = 2.5 V
Vs = -6 V
4
3
0
2
6.3
6.2
1
0
6.1
6
0.1 dB/div
-1
-2
-3
5.9
5.8
20 ns/DIV
0.1
1
10
100
FREQUENCY (MHz)
Figure 35. Pulse Response, AVCL = −1, VS= ±2.5V, ±6V
Figure 36. Frequency Response
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
Typical Performance Characteristics (continued)
Av = + 2V/V
26
23
20
17
14
11
8
13 MHz
12V
5
2
-1
5V
-4
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 37. Frequency Response, AVCL = +5V/V
Figure 38. Frequency Response, AVCL = +10V/V
120
100
120
100
80
80
60
40
60
40
20
0
20
0
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. CMRR vs. Frequency, Vs = 12V
Figure 40. CMRR vs. Frequency, Vs = 5V
100
90
100
90
80
80
70
60
50
40
30
70
60
50
40
30
20
10
0
20
10
0
10M
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. PSRR+ vs. Frequency, VS = 5V and 12V
Figure 42. PSRR− vs. Frequency VS = 5V and 12V
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Typical Performance Characteristics (continued)
Av = + 2V/V
100
100
10
10
e
n
i
n
1
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 43. en & in vs. Frequency, VS = 5V and 12V
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LMH6672
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
7 Detailed Description
7.1 Functional Block Diagram
+
+
1/2
LMH6672
-
-
R
12.5
O
Rf1
1:N
R
= 100:
L
.
A
V
V
IN
V
OUT
VIN (V
)
PP
Rg
(1.2)
Rf2
Note: Supply and Bypassing not shown.
R
O
12.5
-
1/2
LMH6672
-
+
Figure 44. LMH6672 Block Diagram
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8 Power Supply Recommendations
8.1 Thermal Management
The LMH6672 is a high-speed, high power, dual operational amplifier with a very high slew rate and very low
distortion. For ease of use, it uses conventional voltage feedback. These characteristics make the LMH6672
ideal for applications where driving low impedances of 25 to 100 Ω such as xDSL and active filters.
A class AB output stage allows the LMH6672 to deliver high currents to low impedance loads with low distortion
while consuming low quiescent supply current. For most op-amps, class AB topology means that internal power
dissipation is rarely an issue, even with the trend to smaller surface mount packages. However, the LMH6672
has been designed for applications where high levels of power dissipation may be encountered.
Several factors contribute to power dissipation and consequently higher junction temperatures. These factors
need to be well understood if the LMH6672 is to perform to specifications in all applications. This section will
examine the typical application shown in Figure 44 as an example. Because both amplifiers are in a single
package, the calculations are for the total power dissipated by both amplifiers.
There are two separate contributors to the internal power dissipation:
1. The product of the supply voltage and the quiescent current when no signal is being delivered to the external
load.
2. The additional power dissipated while delivering power to the external load.
The first of these components appears easy to calculate simply by inspecting the data sheet. The typical
quiescent supply current for this part is 7.2 mA per amplifier. Therefore, with a ±6 volt supply, the total power
dissipation is:
PD = VS × 2 × lQ = 12 × (14.4×10-3) = 173 mW
where
•
(VS = VCC + VEE
)
(1)
With a thermal resistance of 172°C/W for the SOIC package, this level of internal power dissipation will result in a
junction temperature (TJ) of 30°C above ambient.
Using the worst-case maximum supply current of 18 mA and an ambient of 85°C, a similar calculation results in a
power dissipation of 216 mW, or a TJ of 122°C.
This is approaching the maximum allowed TJ of 150°C before a signal is applied. Fortunately, in normal
operation, this term is reduced, for reasons that will soon be explained.
The second contributor to high TJ is the power dissipated internally when power is delivered to the external load.
This cause of temperature rise is more difficult to calculate, even when the actual operating conditions are
known.
To maintain low distortion, in a Class AB output stage, an idle current, IQ, is maintained through the output
transistors when there is little or no output signal. In the LMH6672, about 4.8 mA of the total quiescent supply
current of 14.4 mA flows through the output stages.
Under normal large signal conditions, as the output voltage swings positive, one transistor of the output pair will
conduct the load current, while the other transistor shuts off, and dissipates no power. During the negative signal
swing this situation is reversed, with the lower transistor sinking the load current while the upper transistor is cut
off. The current in each transistor will approximate a half wave rectified version of the total load current.
Because the output stage idle current is now routed into the load, 4.8 mA can be subtracted from the quiescent
supply current when calculating the quiescent power when the output is driving a load.
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SNOS957H –APRIL 2001–REVISED AUGUST 2014
Thermal Management (continued)
The power dissipation caused by driving a load in a DSL application, using a 1:2 turns ratio transformer driving
20 mW into the subscriber line and 20 mW into the back termination resistors, can be calculated as follows:
PDRIVER = PTOT – (PTERM + PLINE
)
Where
•
•
•
•
•
PDRIVER is the LMH6672 power dissipation
PTOT is the total power drawn from the power supply
PTERM is the power dissipated in the back termination resistors
PLINE is the power sent into the subscriber line
At full specified power, PTERM = PLINE = 20 mW, PTOT = VS × IS
(2)
In this application, VS = 12V.
IS = IQ + AVG |IOUT
|
(3)
(4)
(5)
IQ = the LMH6672 quiescent current minus the output stage idle current.
IQ = 14.4 – 4.8 = 9.6 mA
(40 mW/50:)
Average (AVG) |IOUT| for a full-rate ADSL CPE application, using a 1:2 turns ratio transformer, is
mA RMS.
= 28.28
2/S x I
RMS
For a Gaussian signal, which the DMT ADSL signal approximates, AVG |IOUT| =
PTOT = (22.6 mA + 9.6 mA) × 12V = 386 mW and PDRIVER is 40 mW lower or 346 mW.
= 22.6 mA. Therefore,
In the SOIC package, with a θJA of 172°C/W, this causes a temperature rise of 60°C. With an ambient
temperature at the maximum recommended 85°C, the TJ is at 145°C, which is below the specified 150°C
maximum.
Even if it is assumed that the absolute maximum IS over temperature of 18 mA, when the IQ is scaled up
proportionally to 7 mA, the PDRIVER only goes up by 17 mW causing a 62°C rise from ambient to 147°C.
Although very few CPE applications will ever operate in an environment as hot as 85°C, if a lower TJ is desired
or the LMH6672 is to be used in an application where the power dissipation is higher, the SO PowerPAD (DDA)
package provides a much lower RθJA of only 58.6° C/W. Using the same PDRIVER as above, we find that the
temperature rise is only about 21°C, resulting in TJ of 106°C with 85°C ambient.
NOTE
Since the exposed PAD (or DAP) of the SO PowerPAD (DDA) package is internally
floating, the footprint for DAP could be connected to ground plane in PCB for better heat
dissipation.
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9 Device and Documentation Support
9.1 Trademarks
All trademarks are the property of their respective owners.
9.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6672MA/NOPB
LMH6672MAX/NOPB
LMH6672MR/NOPB
LMH6672MRX/NOPB
ACTIVE
SOIC
SOIC
D
8
8
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
LMH66
72MA
ACTIVE
D
2500 RoHS & Green
95 RoHS & Green
2500 RoHS & Green
SN
SN
SN
LMH66
72MA
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
LMH66
72MR
LMH66
72MR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6672MAX/NOPB
LMH6672MRX/NOPB
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
SO
DDA
PowerPAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6672MAX/NOPB
LMH6672MRX/NOPB
SOIC
D
8
8
2500
2500
367.0
356.0
367.0
356.0
35.0
35.0
SO PowerPAD
DDA
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6672MA/NOPB
LMH6672MR/NOPB
D
SOIC
8
8
95
95
495
495
8
8
4064
4064
3.05
3.05
DDA
HSOIC
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.287
1.673
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.287
1.673
4218820/A 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
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EXAMPLE BOARD LAYOUT
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.287)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(4.9)
NOTE 9
SYMM
(2.287)
(1.3)
SOLDER MASK
TYP
OPENING
6X (1.27)
5
4
(
0.2) TYP
VIA
SYMM
(5.4)
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218820/A 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.287)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(2.287)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.557 X 2.557
2.287 X 2.287 (SHOWN)
2.088 X 2.088
0.125
0.150
0.175
1.933 X 1.933
4218820/A 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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