LMH6683MT/NOPB [TI]
三通道 190MHz 单电源运算放大器 | PW | 14 | -40 to 85;
| 型号： | LMH6683MT/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 三通道 190MHz 单电源运算放大器 | PW | 14 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总35页 (文件大小：1529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
LMH6682/6683 190MHz Single Supply, Dual and Triple Operational Amplifiers
Check for Samples: LMH6682, LMH6683
1
FEATURES
DESCRIPTION
The LMH6682 and LMH6683 are high speed
operational amplifiers designed for use in modern
video systems. These single supply monolithic
amplifiers extend TI's feature-rich, high value video
portfolio to include a dual and a triple version. The
important video specifications of differential gain (±
0.01% typ.) and differential phase (±0.08 degrees)
combined with an output drive current in each
amplifier of 85mA make the LMH6682 and LMH6683
2
VS = ±5V, TA = 25°C, RL = 100Ω, A = +2 (Typical
Values Unless Specified)
•
•
•
•
•
•
•
DG error 0.01%
DP error 0.08°
−3dB BW (A = +2) 190MHz
Slew rate (VS = ±5V) 940V/μs
Supply Current 6.5mA/amp
Output Current +80/−90mA
excellent choices for
applications.
a
full range of video
Input Common Mode Voltage 0.5V Beyond
V−,1.7V from V+
Voltage feedback topology in operational amplifiers
assures maximum flexibility and ease of use in high
speed amplifier designs. The LMH6682/83 is
fabricated in TI's VIP10 process. This advanced
•
•
Output Voltage Swing (RL = 2kΩ) 0.8V from
Rails
Input Voltage Noise (100KHz) 12nV/√Hz
process provides
a superior ratio of speed to
quiescient current consumption and assures the user
of high-value amplifier designs. Advanced technology
and circuit design enables in these amplifiers a −3db
bandwidth of 190MHz, a slew rate of 940V/μsec, and
stability for gains of less than −1 and greater than +2.
APPLICATIONS
•
•
•
•
•
CD/DVD ROM
ADC Buffer Amp
Portable Video
The input stage design of the LM6682/83 enables an
input signal range that extends below the negative
rail. The output stage voltage range reaches to within
0.8V of either rail when driving a 2kΩ load. Other
attractive features include fast settling and low
distortion. Other applications for these amplifiers
include servo control designs. These applications are
sensitive to amplifiers that exhibit phase reversal
when the inputs exceed the rated voltage range. The
LMH6682/83 amplifiers are designed to be immune to
phase reversal when the specified input range is
exceeded. See applications section. This feature
makes for design simplicity and flexibility in many
industrial applications.
Current Sense Buffer
Portable Communications
The LMH6682 dual operational amplifier is offered in
miniature surface mount packages, SOIC-8, and
VSSOP-8. The LMH6683 triple amplifier is offered in
SOIC-14 and TSSOP-14.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 1. SOIC-8/VSSOP-8 (LMH6682)
Top View
Figure 2. SOIC-14/TSSOP-14 (LMH6683)
Top View
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance
Human Body Model
Machine Model
2KV(3)
200V(4)
VIN Differential
±2.5V
Output Short Circuit Duration
Input Current
See(5)(6)
±10mA
Supply Voltage (V+ - V−)
Voltage at Input/Output pins
Soldering Information
12.6V
V+ +0.8V, V− −0.8V
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
235°C
260°C
Storage Temperature Range
Junction Temperature(7)
−65°C to +150°C
+150°C
(1) Absolute maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human body model, 1.5kΩ in series with 100pF.
(4) Machine Model, 0Ω in series with 200pF.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(6) Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(7) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Supply Voltage (V+ – V−)
Operating Temperature Range(2)
Package Thermal Resistance(2)
3V to 12V
−40°C to +85°C
190°C/W
SOIC-8
VSSOP-8
SOIC-14
TSSOP-14
235°C/W
145°C/W
155°C/W
(1) Absolute maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
2
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2, and RL = 100Ω to V+/2, RF
= 510Ω. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
A = +2, VOUT = 200mVPP
A = −1, VOUT = 200mVPP
Min(1)
Typ(2)
Max(1)
Units
MHz
dB
SSBW
−3dB BW
140
180
180
GFP
GFR
Gain Flatness Peaking
Gain Flatness Rolloff
A = +2, VOUT = 200mVPP
DC to 100MHz
2.1
A = +2, VOUT = 200mVPP
DC to 100MHz
0.1
dB
LPD 1°
GF 0.1dB
FPBW
DG
1° Linear Phase Deviation
0.1dB Gain Flatness
A = +2, VOUT = 200mVPP, ±1°
A = +2, ±0.1dB, VOUT = 200mVPP
A = +2, VOUT = 2VPP
A = +2, RL = 150Ω to V+/2
Pos video only VCM = 2V
40
25
MHz
MHz
MHz
%
Full Power −1dB Bandwidth
110
0.03
Differential Gain
NTSC 3.58MHz
DP
Differential Phase
NTSC 3.58MHz
A = +2, RL = 150Ω to V+/2
Pos video only VCM = 2V
0.05
deg
Time Domain Response
Tr/Tf
Rise and Fall Time
20-80%, VO = 1VPP, AV = +2
20-80%, VO = 1VPP, AV = −1
A = +2, VO = 100mVPP
VO = 2VPP, ±0.1%, AV = +2
A = +2, VOUT = 3VPP
2.1
2
ns
OS
Ts
Overshoot
22
%
Settling Time
Slew Rate(3)
49
ns
SR
520
500
V/μs
A = −1, VOUT = 3VPP
Distortion and Noise Response
HD2
HD3
THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−60
−61
dBc
dBc
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−77
−54
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−60
−53
dBc
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
en
in
Input Referred Voltage Noise
Input Referred Current Noise
Cross-Talk Rejection (Amplifier)
f = 1kHz
17
12
8
nV/√Hz
f = 100kHz
f = 1kHz
pA/√Hz
f = 100kHz
3
CT
f = 5MHz, A = +2, SND: RL = 100Ω
RCV: RF = RG = 510Ω
−77
dB
Static, DC Performance
AVOL
Large Signal Voltage Gain
VO = 1.25V to 3.75V,
85
75
70
95
85
RL = 2kΩ to V+/2
VO = 1.5V to 3.5V,
dB
V
RL = 150Ω to V+/2
VO = 2V to 3V,
80
RL = 50Ω to V+/2
CMVR
Input Common-Mode Voltage
Range
CMRR ≥ 50dB
−0.2
−0.1
−0.5
3.3
3.0
2.8
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2, and RL = 100Ω to V+/2, RF
= 510Ω. Boldface limits apply at the temperature extremes.
Symbol
VOS
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
Input Offset Voltage
±1.1
±5
±7
mV
TC VOS
IB
Input Offset Voltage Average
Drift
See(4)
See(5)
±2
μV/°C
Input Bias Current
−5
−20
−30
μA
nA/°C
nA
TC IB
IOS
Input Bias Current Drift
Input Offset Current
0.01
50
300
500
CMRR
Common Mode Rejection Ratio
Positive Power Supply Rejection V+ = 4.5V to 5.5V, VCM = 1V
Ratio
VCM Stepped from 0V to 3.0V
72
70
82
76
dB
dB
+PSRR
IS
Supply Current (per channel)
No load
6.5
9
11
mA
Miscellaneous Performance
VO
Output Swing
High
RL = 2kΩ to V+/2
RL = 150Ω to V+/2
RL = 75Ω to V+/2
RL = 2kΩ to V+/2
RL = 150Ω to V+/2
R L = 75Ω to V+/2
4.10
3.8
4.25
4.19
4.15
800
870
885
3.90
3.70
V
3.75
3.50
Output Swing
Low
920
1100
970
1200
mV
1100
1250
IOUT
ISC
Output Current
VO = 1V from either supply rail
Sourcing to V+/2
±40
+80/−75
−155
mA
mA
Output Short Circuit
Current(6)(7)(8)
−100
−80
Sinking from V+/2
100
220
80
RIN
CIN
Common Mode Input Resistance
3
MΩ
Common Mode Input
Capacitance
1.6
pF
ROUT
Output Resistance Closed Loop
f = 1kHz, A = +2, RL = 50Ω
f = 1MHz, A = +2, RL = 50Ω
0.02
0.12
Ω
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) Short circuit test is a momentary test. See next note.
(7) Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(8) Positive current corresponds to current flowing into the device.
4
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5V, V− = −5V, VO = VCM = 0V, and RL = 100Ω to 0V, RF =
510Ω. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
A = +2, VOUT = 200mVPP
A = −1, VOUT = 200mVPP
Min(1)
Typ(2)
Max(1)
Units
MHz
dB
SSBW
−3dB BW
150
190
190
GFP
GFR
Gain Flatness Peaking
Gain Flatness Rolloff
A = +2, VOUT = 200mVPP
DC to 100MHz
1.7
A = +2, VOUT = 200mVPP
DC to 100MHz
0.1
dB
LPD 1°
GF 0.1dB
FPBW
DG
1° Linear Phase Deviation
0.1dB Gain Flatness
A = +2, VOUT = 200mVPP, ±1°
A = +2, ±0.1dB, VOUT = 200mVPP
A = +2, VOUT = 2VPP
40
25
MHz
MHz
MHz
%
Full Power −1dB Bandwidth
120
0.01
Differential Gain
NTSC 3.58MHz
A = +2, RL = 150Ω to 0V
DP
Differential Phase
NTSC 3.58MHz
A = +2, RL = 150Ω to 0V
0.08
deg
Time Domain Response
Tr/Tf
Rise and Fall Time
20-80%, VO = 1VPP, A = +2
20-80%, VO = 1VPP, A = −1
A = +2, VO = 100mVPP
VO = 2VPP, ±0.1%, A = +2
A = +2, VOUT = 6VPP
1.9
2
ns
OS
Ts
Overshoot
19
%
Settling Time
Slew Rate(3)
42
ns
SR
940
900
V/μs
A = −1, VOUT = 6VPP
Distortion and Noise Response
HD2
HD3
THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−63
−66
dBc
dBc
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−82
−54
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
f = 5MHz, VO = 2VPP, A = +2, RL = 2kΩ
−63
−54
dBc
f = 5MHz, VO = 2VPP, A = +2, RL
=
100Ω
en
in
Input Referred Voltage Noise
Input Referred Current Noise
Cross-Talk Rejection (Amplifier)
f = 1kHz
18
12
6
nV/√Hz
f = 100kHz
f = 1kHz
pA/√Hz
f = 100kHz
3
CT
f = 5MHz, A = +2, SND: RL = 100Ω
RCV: RF = RG = 510Ω
−78
dB
Static, DC Performance
AVOL
Large Signal Voltage Gain
VO = −3.75V to 3.75V,
RL = 2kΩ to V+/2
87
80
75
100
90
VO = −3.5V to 3.5V,
RL = 150Ω to V+/2
dB
V
VO = −3V to 3V,
RL = 50Ω to V+/2
85
CMVR
Input Common Mode Voltage
Range
CMRR ≥ 50dB
−5.2
−5.1
−5.5
3.3
3.0
2.8
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5V, V− = −5V, VO = VCM = 0V, and RL = 100Ω to 0V, RF =
510Ω. Boldface limits apply at the temperature extremes.
Symbol
VOS
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
Input Offset Voltage
±1
±5
±7
mV
TC VOS
IB
Input Offset Voltage Average
Drift
See(4)
See(5)
±2
μV/°C
Input Bias Current
−5
−20
−30
μA
nA/°C
nA
TC IB
IOS
Input Bias Current Drift
Input Offset Current
0.01
50
300
500
CMRR
Common Mode Rejection Ratio
Positive Power Supply Rejection V+ = 8.5V to 9.5V,
Ratio
VCM Stepped from −5V to 3.0V
75
75
84
82
dB
dB
+PSRR
V− = −1V
−PSRR
Negative Power Supply Rejection V− = −4.5V to −5.5V,
Ratio
78
85
dB
V+ = 5V
No load
IS
Supply Current (per channel)
6.5
9.5
11
mA
Miscellaneous Performance
VO
Output Swing
High
RL = 2kΩ to 0V
RL = 150Ω to 0V
RL = 75Ω to 0V
RL = 2kΩ to 0V
RL = 150Ω to 0V
R L = 75Ω to 0V
4.10
3.80
4.25
4.20
3.90
3.70
V
3.75
3.50
4.18
Output Swing
Low
−4.19
−4.05
−4.00
−4.07
−3.80
−3.89
−3.65
mV
−3.70
−3.50
IOUT
ISC
Output Current
VO = 1V from either supply rail
Sourcing to 0V
±45
+85/−80
−180
mA
mA
Output Short Circuit
Current(6)(7)(8)
−120
−100
Sinking from 0V
120
230
100
RIN
CIN
Common Mode Input Resistance
4
MΩ
Common Mode Input
Capacitance
1.6
pF
ROUT
Output Resistance Closed Loop
f = 1kHz, A = +2, RL = 50Ω
f = 1MHz, A = +2, RL = 50Ω
0.02
0.12
Ω
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) Short circuit test is a momentary test. See next note.
(7) Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
(8) Positive current corresponds to current flowing into the device.
6
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Typical Schematic
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
Non-Inverting Frequency Response
Inverting Frequency Response
Figure 3.
Figure 4.
Non-Inverting Frequency Response for Various Gain
Inverting Frequency Response for Various Gain
Figure 5.
Figure 6.
Non-Inverting Phase vs. Frequency for Various Gain
Inverting Phase vs. Frequency for Various Gain
Figure 7.
Figure 8.
8
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
Open Loop Gain and Phase vs. Frequency Over
Open Loop Gain & Phase vs. Frequency
Temperature
Figure 9.
Figure 10.
Non-Inverting Frequency Response Over Temperature
Inverting Frequency Response Over Temperature
Figure 11.
Figure 12.
Gain Flatness 0.1dB
Differential Gain & Phase for A = +2
Figure 13.
Figure 14.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
Transient Response Negative
Transient Response Positive
Figure 15.
Figure 16.
Noise vs. Frequency
Noise vs. Frequency
Figure 17.
Figure 18.
Harmonic Distortion vs. VOUT
Harmonic Distortion vs. VOUT
Figure 19.
Figure 20.
10
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
Harmonic Distortion vs. VOUT
THD vs. for Various Frequencies
Figure 21.
Figure 22.
Harmonic Distortion vs. Frequency
Crosstalk vs. Frequency
Figure 23.
Figure 24.
ROUT vs. Frequency
IOS vs. VSUPPLY Over Temperature
Figure 25.
Figure 26.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
VOS vs. VS @ −40°C
VOS vs. VS @ 25°C
Figure 27.
Figure 28.
VOS vs. VS @ 85°C
VOS vs. VS @ 125°C
Figure 29.
Figure 30.
VOS vs. VOUT
VOS vs. VOUT
Figure 31.
Figure 32.
12
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
ISUPPLY/Amp vs. VCM
ISUPPLY/Amp vs. VSUPPLY
Figure 33.
Figure 34.
VOUT vs. ISOURCE
VOUT vs. ISINK
Figure 35.
Figure 36.
VOUT vs. ISOURCE
VOUT vs. ISINK
Figure 37.
Figure 38.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
VOS vs. VCM
|IB|vs. VS
Figure 39.
Figure 40.
Short Circuit ISOURCE vs. VS
Short Circuit ISINK vs. VS
Figure 41.
Figure 42.
Linearity Input vs. Output
Linearity Input vs. Output
Figure 43.
Figure 44.
14
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Typical Performance Characteristics (continued)
At TA = 25°C, V+ = +5V, V− = −5V, RF = 510Ω for A = +2; unless otherwise specified.
CMRR vs. Frequency
PSRR vs. Frequency
Figure 45.
Figure 46.
Small Signal Pulse Response for A = +2
Small Signal Pulse Response A = −1
Figure 47.
Figure 48.
Large Signal Pulse Response
Large Signal Pulse Response
Figure 49.
Figure 50.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
APPLICATIONS SECTION
LARGE SIGNAL BEHAVIOR
Amplifying high frequency signals with large amplitudes (as in video applications) has some special aspects to
look after. The bandwidth of the Op Amp for large amplitudes is less than the small signal bandwidth because of
slew rate limitations. While amplifying pulse shaped signals the slew rate properties of the OpAmp become more
important at higher amplitude ranges. Due to the internal structure of an Op Amp the output can only change with
a limited voltage difference per time unit (dV/dt). This can be explained as follows: To keep it simple, assume
that an Op Amp consists of two parts; the input stage and the output stage. In order to stabilize the Op Amp, the
output stage has a compensation capacitor in its feedback path. This Miller C integrates the current from the
input stage and determines the pulse response of the Op Amp. The input stage must charge/discharge the
feedback capacitor, as can be seen in Figure 51.
Figure 51.
When a voltage transient is applied to the non inverting input of the Op Amp, the current from the input stage will
charge the capacitor and the output voltage will slope up. The overall feedback will subtract the gradually
increasing output voltage from the input voltage. The decreasing differential input voltage is converted into a
current by the input stage (Gm).
I*Δt = C *ΔV
ΔV/Δt = I/C
I=ΔV*Gm
(1)
(2)
(3)
where I = current
t = time
C = capacitance
V = voltage
Gm = transconductance
Slew rate ΔV/Δt = volt/second
In most amplifier designs the current I is limited for high differential voltages (Gm becomes zero). The slew rate
will than be limited as well:
ΔV/Δt = Imax/C
(4)
The LMH6682/83 has a different setup of the input stage. It has the property to deliver more current to the output
stage when the input voltage is higher (class AB input). The current into the Miller capacitor exhibits an
exponential character, while this current in other Op Amp designs reaches a saturation level at high input levels:
(see Figure 52)
16
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Figure 52.
This property of the LMH6682/83 guaranties a higher slew rate at higher differential input voltages.
ΔV/Δt = ΔV*Gm/C
(5)
In Figure 53 one can see that a higher transient voltage than will lead to a higher slew rate.
Figure 53.
HANDLING VIDEO SIGNALS
When handling video signals, two aspects are very important especially when cascading amplifiers in a NTSC- or
PAL video system. A composite video signal consists of both amplitude and phase information. The amplitude
represents saturation while phase determines color (color burst is 3.59MHz for NTSC and 4.58MHz for PAL
systems). In this case it is not only important to have an accurate amplification of the amplitude but also it is
important not to add a varying phase shift to the video signals. It is a known phenomena that at different dc
levels over a certain load the phase of the amplified signal will vary a little bit. In a video chain many amplifiers
will be cascaded and all errors will be added together. For this reason, it is necessary to have strict requirements
for the variation in gain and phase in conjunction to different dc levels. As can be seen in the tables the number
for the differential gain for the LMH6682/83 is only 0.01% and for the differential phase it is only 0.08° at a supply
voltage of ±5V. Note that the phase is very dependent of the load resistance, mainly because of the dc current
delivered by the parts output stage into the load. For more information about differential gain and phase and how
to measure it see Application Note OA-24 SNOA370 which can be found on via TI's home page
http://www.ti.com
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
OUTPUT PHASE REVERSAL
This is a problem with some operational amplifiers. This effect is caused by phase reversal in the input stage due
to saturation of one or more of the transistors when the inputs exceed the normal expected range of voltages.
Some applications, such as servo control loops among others, are sensitive to this kind of behavior and would
need special safeguards to ensure proper functioning. The LMH6682/6683 is immune to output phase reversal
with input overload. With inputs exceeded, the LMH6682/6683 output will stay at the clamped voltage from the
supply rail. Exceeding the input supply voltages beyond the Absolute Maximum Ratings of the device could
however damage or otherwise adversely effect the reliability or life of the device.
DRIVING CAPACITIVE LOADS
The LMH6682/6683 can drive moderate values of capacitance by utilizing a series isolation resistor between the
output and the capacitive load. Capacitive load tolerance will improve with higher closed loop gain values.
Applications such as ADC buffers, among others, present complex and varying capacitive loads to the Op Amp;
best value for this isolation resistance is often found by experimentation and actual trial and error for each
application.
DISTORTION
Applications with demanding distortion performance requirements are best served with the device operating in
the inverting mode. The reason for this is that in the inverting configuration, the input common mode voltage
does not vary with the signal and there is no subsequent ill effects due to this shift in operating point and the
possibility of additional non-linearity. Moreover, under low closed loop gain settings (most suited to low
distortion), the non-inverting configuration is at a further disadvantage of having to contend with the input
common voltage range. There is also a strong relationship between output loading and distortion performance
(i.e. 2kΩ vs. 100Ω distortion improves by about 15dB @1MHz) especially at the lower frequency end where the
distortion tends to be lower. At higher frequency, this dependence diminishes greatly such that this difference is
only about 5dB at 10MHz. But, in general, lighter output load leads to reduced HD3 term and thus improves
THD. (See Harmonic Distortion plots, Figures 19 through 23).
PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT VALUES SELECTION
Generally it is a good idea to keep in mind that for a good high frequency design both the active parts and the
passive ones are suitable for the purpose you are using them for. Amplifying frequencies of several hundreds of
MHz is possible while using standard resistors but it makes life much easier when using surface mount ones.
These resistors (and capacitors) are smaller and therefore parasitics have lower values and will have less
influence on the properties of the amplifier. Another important issue is the PCB, which is no longer a simple
carrier for all the parts and a medium to interconnect them. The board becomes a real part itself, adding its own
high frequency properties to the overall performance of the circuit. It's good practice to have at least one ground
plane on a PCB giving a low impedance path for all decouplings and other ground connections. Care should be
taken especially that on board transmission lines have the same impedance as the cables they are connected to
(i.e. 50Ω for most applications and 75Ω in case of video and cable TV applications). These transmission lines
usually require much wider traces on a standard double sided PCB than needed for a 'normal' connection.
Another important issue is that inputs and outputs must not 'see' each other or are routed together over the PCB
at a small distance. Furthermore it is important that components are placed as flat as possible on the surface of
the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can
even form a transformer. Careful design of the PCB avoids oscillations or other unwanted behavior. When
working with really high frequencies, the only components which can be used will be the surface mount ones (for
more information see OA-15 SNOA367).
As an example of how important the component values are for the behavior of your circuit, look at the following
case: On a board with good high frequency layout, an amplifier is placed. For the two (equal) resistors in the
feedback path, 5 different values are used to set the gain to +2. The resistors vary from 200Ω to 3kΩ.
18
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
www.ti.com
SNOSA43A –MAY 2004–REVISED APRIL 2013
Figure 54.
In Figure 54 it can be seen that there's more peaking with higher resistor values, which can lead to oscillations
and bad pulse responses. On the other hand the low resistor values will contribute to higher overall power
consumption.
TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
Device
Package
8-Pin SOIC
Evaluation Board PN
CLC730036
LMH6682MA
LMH6682MM
LMH6683MA
LMH6683MT
8-Pin VSSOP
14-Pin SOIC
14-Pin TSSOP
CLC730123
CLC730031
CLC730131
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LMH6682 LMH6683
LMH6682, LMH6683
SNOSA43A –MAY 2004–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
20
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6682 LMH6683
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6682MA/NOPB
LMH6682MAX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMH66
82MA
Samples
Samples
ACTIVE
2500 RoHS & Green
SN
LMH66
82MA
LMH6682MM/NOPB
LMH6682MMX/NOPB
LMH6683MA/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
A90A
Samples
Samples
Samples
A90A
14
55
2500 RoHS & Green
94 RoHS & Green
2500 RoHS & Green
RoHS & Green
NIPDAU | SN
LMH66
83MA
LMH6683MAX/NOPB
LMH6683MT/NOPB
LMH6683MTX/NOPB
ACTIVE
ACTIVE
ACTIVE
SOIC
D
14
14
14
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH66
83MA
Samples
Samples
Samples
TSSOP
TSSOP
PW
PW
LMH66
83MT
LMH66
83MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6682MAX/NOPB
LMH6682MM/NOPB
LMH6682MMX/NOPB
LMH6683MAX/NOPB
LMH6683MTX/NOPB
LMH6683MTX/NOPB
SOIC
VSSOP
VSSOP
SOIC
D
8
8
2500
1000
3500
2500
2500
2500
330.0
178.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
16.4
12.4
12.4
6.5
5.3
5.4
3.4
3.4
9.35
5.6
5.6
2.0
1.4
1.4
2.3
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
DGK
DGK
D
8
5.3
14
14
14
6.5
TSSOP
TSSOP
PW
PW
6.95
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6682MAX/NOPB
LMH6682MM/NOPB
LMH6682MMX/NOPB
LMH6683MAX/NOPB
LMH6683MTX/NOPB
LMH6683MTX/NOPB
SOIC
VSSOP
VSSOP
SOIC
D
8
8
2500
1000
3500
2500
2500
2500
367.0
208.0
367.0
367.0
367.0
356.0
367.0
191.0
367.0
367.0
367.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
DGK
DGK
D
8
14
14
14
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6682MA/NOPB
LMH6683MA/NOPB
LMH6683MA/NOPB
LMH6683MT/NOPB
LMH6683MT/NOPB
D
D
SOIC
SOIC
8
95
55
55
94
94
495
495
495
495
530
8
8
4064
4064
3.05
3.05
3.05
4.06
3.5
14
14
14
14
D
SOIC
8
4064
PW
PW
TSSOP
TSSOP
8
2514.6
3600
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明