LMH6704MFX/NOPB [TI]
具有禁用功能的 650MHz 可选增益缓冲器 | DBV | 6 | -40 to 85;
| 型号： | LMH6704MFX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有禁用功能的 650MHz 可选增益缓冲器 | DBV | 6 | -40 to 85 |
| 文件： | 总25页 (文件大小：1345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6704
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SNOSAD0C –FEBRUARY 2005–REVISED MARCH 2013
LMH6704 650 MHz Selectable Gain Buffer with Disable
Check for Samples: LMH6704
1
FEATURES
DESCRIPTION
23
•
Wideband operation
The LMH™6704 is a very wideband, DC coupled
selectable gain buffer designed specifically for wide
dynamic range systems requiring exceptional signal
fidelity. The LMH6704 includes on chip feedback and
gain set resistors, simplifying PCB layout while
providing user selectable gains of +1, +2 and −1 V/V.
The LMH6704 provides a disable pin, which places
the amplifier in a high output impedance, low power
mode. The Disable pin may be allowed to float high.
–
–
–
AV = +1, VO = 0.5 VPP 650 MHz
AV = +2, VO = 0.5 VPP 450 MHz
AV = +2, VO = 2 VPP 400 MHz
•
High output current ±90 mA
Very low distortion
•
–
2nd/3rd harmonics (10 MHz, RL = 100Ω):
−62/−78dBc
–
Differential gain/Differential phase:
0.02%/0.02°
With a 650 MHz Small Signal Bandwidth (AV = +1),
full power gain flatness to 200 MHz, and excellent
Differential Gain and Phase, the LMH6704 is
optimized for video applications. High resolution video
systems will benefit from the LMH6704 ability to drive
multiple video loads at low levels of differential gain
or differential phase distortion.
•
•
•
Low noise 2.3nV/√Hz
High slew rate 3000 V/μs
Supply current 11.5 mA
APPLICATIONS
The LMH6704 is constructed with proprietary high
speed complementary bipolar process using proven
current feedback circuit architectures. It is available in
8 Pin SOIC and 6 Pin SOT-23 packages.
•
•
•
•
•
•
HDTV, NTSC and PAL video systems
Video switching and distribution
ADC driver
DAC buffer
RGB driver
High speed multiplexer
CONNECTION DIAGRAM
6 Pin SOT-23
Top View
8 Pin SOIC
Top View
1
2
3
6
5
4
+
OUT
V
S
465W
1
2
8
N/C
-IN
DIS
465W
465W
7
6
+
S
-
V
-
S
DIS
V
3
4
OUT
N/C
+IN
+
+
-
-IN
+IN
5
-
V
S
465W
See Package Number D0008A
See Package Number DBV0006A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LMH6704
SNOSAD0C –FEBRUARY 2005–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
ESD Tolerance
(2)
Human Body Model
2000V
200V
Machine Model
Supply Voltage
13.5V
(3)
IOUT
+
Common-Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
VS− to VS
150°C
−65°C to 150°C
235°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Soldering Information
260°C
Lead Temp. (soldering 10 sec.)
300°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum output current (IOUT) is determined by device power dissipation limitations.
Operating Ratings(1)
Nominal Supply Voltage
±4V to ±6V
−40°C to 85°C
(2)
Temperature Range
Thermal Resistance
Package
(θJC
)
(θJA)
8-Pin SOIC
75°C/W
160°C/W
187°C/W
6-Pin SOT23
120°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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(1)
Electrical Characteristics
TA = +25°C , AV = +2, VS = ±5V, RL = 100Ω; unless specified.
(2)
(2)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Dynamic Performance
SSBW
VOUT = 0.5 VPP, AV = +1
VOUT = 0.5 VPP
650
SSBW
LSBW
GF0.1dB
SR
-3 dB Bandwidth
450
400
MHz
VOUT = 2 VPP
0.1 dB Gain Bandwidth
Slew Rate
VOUT = 2 VPP
200
MHz
V/µs
(3)
VOUT = 4 VPP, 40% to 60%
3000
Rise and Fall Time
(10% to 90%)
TRS/TRL
ts
2V Step
2V Step
0.9
10
ns
ns
Settling Time to 0.1%
Distortion and Noise Response
HD2L
HD2H
HD3L
HD3H
IMD
2nd Harmonic Distortion
3rd Harmonic Distortion
Two-Tone Intermodulation
Output Noise Voltage
VOUT = 2.0 VPP, f = 10 MHz
VOUT = 2.0 VPP, f = 40 MHz
VOUT = 2.0 VPP, f = 10 MHz
VOUT = 2.0 VPP, f = 40 MHz
−62
−52
−78
−65
−65
10.5
9.3
dBc
dBc
dBc
f = 10 MHz, POUT = 10 dBm/tone
AV = +2
AV = +1
AV = −1
VN
f = 100 kHz
nV/√Hz
10.5
3
INN
DG
DP
Non-Inverting Input Noise Current
Differential Gain
pA/√Hz
%
RL = 150Ω, f = 4.43 MHz
RL = 150Ω, f = 4.43 MHz
.02
Differential Phase
0.02
deg
Static, DC Performance
1.98
1.96
2.00
2
2.02
2.04
AV
Gain
V/V
%
−1
−2
+1
+2
Gain Error
±7
±8.3
VIO
Input Offset Voltage
mV
μV/°C
μA
DVIO
IBN
Input Offset Voltage Average Drift
Input Bias Current
35
(4)
Non-Inverting
−5
±15
±18
±22
±31
IBI
Input Bias Current
Inverting
5
CMIR
PSRR
Common Mode Input Range
Power Supply Rejection Ratio
V
IO ≤ 15 mV
±1.9
±2
52
V
DC
48
dB
47
RL = ∞
RL = 100Ω
±3.3
±3.18
±3.5
±3.5
VO
Output Voltage Swing
V
±3.2
±3.12
IO
Linear Output Current
V
OUT ≤ 80 mV
±55
±90
mA
mA
11.5
12.5
13.7
Supply Current (Enabled)
DIS = 2V, RL = ∞
IS
0.25
0.9
0.925
Supply Current (Disabled)
DIS = 0.8V, RL = ∞
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. Parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested on shipped production material.
(3) Slew Rate is the average of the rising and falling edges.
(4) Negative current implies current flowing out of the device.
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Electrical Characteristics (1) (continued)
TA = +25°C , AV = +2, VS = ±5V, RL = 100Ω; unless specified.
(2)
(2)
(2)
Symbol
RF & RG
ROUT
Parameter
Internal RF and RG
Conditions
Min
375
Typ
465
Max
563
Units
Ω
Closed Loop Output Resistance
Input Resistance
DC
0.05
1
Ω
RIN+
MΩ
pF
CIN+
Input Capacitance
1
Enable/Disable Performance (Disabled Low)
TON
Enable Time
10
10
50
ns
ns
TOFF
Disable Time
Output Glitch
mVPP
V
VIH
VIL
IIH
Enable Voltage
DIS ≥ VIH
DIS ≤ VIL
DIS = V+,
DIS = 0V
2.0
Disable Voltage
0.8
±50
(4)
(4)
Disable Input Bias Current, High
Disable Input Bias Current, Low
−1
µA
µA
IIL
0
−100
−350
±25
±50
IOZ
Disabled Output Leakage Current
AV = +1, VOUT = ±1.8V
0.2
µA
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Typical Performance Characteristics
(TA = 25°C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified).
Small Signal Frequency Response
Frequency Response
vs.
vs.
Gain
VOUT
4
3
7
6
A
= +1
V
2
5
A
V
= -1
1
4
V
OUT
= 4 V
PP
0
3
-1
-2
-3
-4
-5
-6
2
V
= 2 V
PP
OUT
A
V
= +2
1
0
V
= 0.5 V
PP
OUT
-1
-2
-3
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1.
Figure 2.
Small Signal Frequency Response
vs.
RLOAD
Large Signal Gain Flatness
7
6
6.5
6.4
6.3
6.2
6.1
6
V
= 2 V
PP
OUT
5
4
R
= 50W
L
3
2
R
= 100W
L
1
5.9
5.8
5.7
5.6
5.5
0
R
L
= 1kW
-1
-2
-3
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Small Signal Frequency Response
Series Output Isolation Resistance
vs.
vs.
Capacitive Load
Capacitive Load
70
60
50
8
7
C
= 4.7 pF, R = 56W
ISO
L
6
5
C
= 15 pF, R
ISO
= 39W
= 22W
L
4
40
30
20
3
C
= 47 pF, R
ISO
L
2
1
C
= 100 pF, R = 15W
ISO
L
0
10
0
-1
-2
20
40
80
100 120
1
10
100
1000
0
60
CAPACITIVE LOAD (pF)
FREQUENCY (MHz)
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified).
Large Signal Pulse Response
Small Signal Pulse Response
2.5
0.5
0.4
0.3
0.2
0.1
0
2
1.5
1
0.5
0
-0.5
-1
-0.1
-0.2
-0.3
-0.4
-0.5
-1.5
-2
-2.5
TIME (2 ns/div)
Figure 7.
TIME (2 ns/div)
Figure 8.
Harmonic Distortion
vs.
Harmonic Distortion
vs.
Frequency
Load
-45
-55
-65
-75
-85
-20
V
= 2 V
PP
OUT
f = 10 MHz
-30
-40
V
OUT
= 2 V
PP
nd
2
-50
-60
-70
nd
2
-80
-90
-95
rd
3
rd
-100
-110
-120
3
-105
-115
0
200
400
600
800
1000
1
10
100
FREQUENCY (MHz)
LOAD RESISTANCE (W)
Figure 9.
Figure 10.
Harmonic Distortion
vs.
Output Voltage
DG/DP
0.025
0.2
-45
-55
0.025
0.2
nd
2
f = 4.43 MHz
= 150W
R
L
0.015
0.015
0.01
-65
0.01
DP
0.005
0.005
0
-75
-85
DG
0
-0.005
-0.01
-0.015
-0.005
-0.01
rd
3
-95
-0.015
f = 10 MHz
-105
-0.02
-0.02
R
L
= 100W
-0.025
-0.025
-115
-1 -0.75 -0.5 -0.25
V
0
0.25 0.5 0.75
)
1
0
1
2
3
4
5
6
7
(V
OUTPUT VOLTAGE PEAK TO PEAK
OUT DC
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified).
PSRR
DC Errors
vs.
vs.
(1)
Frequency
Temperature (A Typical Unit,
)
100
-3
10
90
-4
9
I
BN
80
70
-5
8
7
6
5
4
3
2
1
0
PSRR -
PSRR +
-6
60
50
40
-7
-8
-9
30
20
-10
-11
-12
-13
V
OS
10
0
10M
10k
100k
1M
100M
1G
-75 -50 -25
0
25 50 75 100 125 150
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 13.
Figure 14.
Disable Timing
Disable Output Glitch
1V
0V
20 mV
0V
-1V
-20 mV
-40 mV
3V
2V
1V
0V
3V
2V
1V
0V
TIME (10 ns/div)
TIME (10 ns/div)
Figure 15.
Figure 16.
(1) Negative current implies current flowing out of the device.
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APPLICATION INFORMATION
+5V
+5V
6.8 µF
.01 µF
6.8 µF
.01 µF
V
V
IN
IN
C
C
POS
POS
6
6
3
4
3
4
+
+
C
SS
1
1
C
SS
0.1 µF
V
OUT
V
OUT
LMH6704
LMH6704
R
R
IN
IN
0.1 µF
-
-
NC
C
NEG
C
NEG
2
2
.01 µF
6.8 µF
.01 µF
6.8 µF
-5V
-5V
Figure 17. Recommended Gain of +2 Circuit
Figure 18. Recommended Gain of +1 Circuit
+5V
6.8 µF
.01 µF
6
C
POS
3
4
+
C
SS
0.1 µF
1
V
LMH6704
OUT
-
V
IN
C
NEG
2
R
IN
.01 µF
6.8 µF
-5V
Figure 19. Recommended Gain of −1 Circuit
GENERAL INFORMATION
The LMH6704 is a high speed current feedback Selectable Gain Buffer (SGB), optimized for very high speed and
low distortion. With its internal feedback and gain-setting resistors the LMH6704 offers excellent AC performance
while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6704
has no internal ground reference so single or split supply configurations are both equally useful.
SETTING THE CLOSED LOOP GAIN
The LMH6704 is a current feedback amplifier with on-chip RF = RG = 465Ω. As such it can be configured with an
AV = +2, AV = +1, or an AV = −1 by connecting pins 3 and 4 as described in Table 1.
Table 1.
Input Connections
GAIN AV
Non-Inverting (Pin 3, SOT-23)
Ground
Inverting (Pin 4, SOT-23)
Input Signal
−1 V/V
+1 V/V
+2 V/V
Input Signal
NC (Open)
Input Signal
Ground
The gain accuracy of the LMH6704 is accurate over temperature to within ±1%. The internal gain setting
resistors, RFand RG, match very well. The LMH6704 architecture takes advantage of the fact that the internal
gain setting resistors track each other well over a wide range of temperature and process variation to keep the
overall gain constant, despite the fact that the individual resistors have nominal temperature drifts. Therefore,
using external resistors in series with RG to change the gain will result in poor gain accuracy over temperature.
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+5V
6.8 µF
.01 µF
V
IN
C
POS
6
3
4
+
C
SS
0.1 µF
1
V
OUT
LMH6704
R
IN
-
C
NEG
2
.01 µF
6.8 µF
-5V
Figure 20. Alternate Unity Gain Configuration
UNITY GAIN COMPENSATION
With a current feedback Selectable Gain Buffer like the LMH6704, the feedback resistor is a compromise
between the value needed for stability at unity gain and the optimized value needed at a gain of two. In standard
open-loop current feedback operational amplifiers the feedback resistor, RF, is external and its value can be
adjusted to match the required gain. Since the feedback resistor is integrated in the LMH6704, it is not possible
to adjust it’s value. However, we can employ the circuit shown in Figure 20. This circuit modifies the noise gain of
the amplifier to eliminate the peaking associated with using the circuit shown in Figure 18. The frequency
response is shown in Figure 21. The decreased peaking does come at a price as the output referred voltage
noise density increases by a factor of 1.1.
4
STANDARD CIRCUIT
3
(FIGURE 2)
2
1
0
-1
ALTERNATE CIRCUIT
-2
-3
-4
-5
-6
(FIGURE 4)
1
10
100
1000
FREQUENCY (MHz)
Figure 21. Unity Gain Frequency Response
OUTPUT VOLTAGE NOISE
Open-loop operational amplifiers specify three input referred noise parameters: input voltage noise, non-inverting
input current noise, and inverting input current noise. These specifications are used to calculate the total voltage
noise produced at the output of the amplifier. The LMH6704 is a closed loop amplifier with internal resistors, thus
only the non-inverting input current noise flows through external components. All other noise sources are internal
to the part. There are four possible values for the noise at the output depending on the gain configuration as
shown in Table 2. For more information on calculating noise in current feedback amplifiers see Application Notes
OA-12 and AN104 available at www.ti.com.
The total noise voltage at the output can be calculated using Equation 1:
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(4kTRSOURCE + (IBN * RSOURCE)2) * GN2 + (OUTPUT REFERRED NOISE VOLTAGE)2, Where
EO =
GN = Noise Gain and 4kT = 16E-21 Joules @ Room Temperature
(1)
For example, if an AV = +2 configuration is used with a source impedance of 37.5Ω (parallel combination of 75Ω
source and 75Ω termination impedances), where “IBN” is 18.5pA/√Hz and the output referred voltage noise
(excluding non-inverting input noise current) can be found in Table 2. The total noise (EO) at the output can be
calculated as:
(16E-21*37.5 + (18.5 pA*37.5)2)*22 + (10.5 nV)2
EO
=
= 10.6 nV/
Hz
(2)
Table 2. Measured Output Noise Voltage(1)
Output Referred Voltage Noise
(nV/√Hz), excluding non-inverting noise current
Gain (AV)
+2
+1
10.5
9.3
+1, alternate method shown in Figure 20
-1
10.5
10.5
(1) Note: f ≥ 100 kHz
ENABLE/DISABLE
PIN 6
+
V
S
20 kW
SUPPLY
MID-POINT
PULL-UP
20 kW
BIAS CIRCUITRY
RESISTOR
PIN 5
DIS
Q
Q
1
2
+
S
-
S
V
- V
20 kW
2
I TAIL
PIN 2
-
V
S
NOTE: PINS 2, 5, 6 ARE EXTERNAL
Figure 22. DIS Pin Simplified Schematic
The LMH6704 has a TTL logic compatible disable function. Apply a logic low (<.8V) to the DS pin and the
LMH6704 is disabled. Apply a logic high (>2.0V), or let the pin float and the LMH6704 is enabled. Voltage, not
current, at the Disable pin (DS) determines the enable/disable state. Care must be exercised to prevent the
disable pin voltage from going more than .8V below the midpoint of the supply voltages (0V with split supplies,
V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener resulting in damage to the disable
circuit (See Figure 22 or the simplified internal schematic diagram using SOT-23 package pin numbers). The
core amplifier is unaffected by this, but the disable operation could become permanently slower as a result.
Disabled, the LMH6704 inputs and output become high impedances. While disabled the LMH6704 quiescent
current is approximately 250 µA. Because of the pull up resistor on the disable circuit, the ICC and IEE currents
(positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply
current (ICC) is approximately 350 µA while the negative supply current (IEE) is only 250 µA. The remaining IEE
current of 100 µA flows through the disable pin.
The disable function can be used to create analog switches or multiplexers. Implement a single analog switch
with one LMH6704 positioned between an input and output. Create an analog multiplexer with several
LMH6704’s. Use the circuit shown in for multiplexer applications because there is no RG to shunt signals to
ground.
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EVALUATION BOARDS
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the data sheet plots were measured with these boards.
Device
Package
SOIC-8
Evaluation Board Part Number
CLC730227
LMH6704MA
LMH6704MF
SOT23-6
CLC730216
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 23 shows
the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The chart “Suggested RISO vs. Cap Load” gives a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of RISO can be reduced slightly
from the recommended values.
R
ISO
50W
+
-
V
IN
+
-
V
OUT
R
IN
50W
CL
10 pF
R
L
1 kW
Figure 23. Decoupling Capacitive Loads
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. To reduce parasitic capacitances
ground and power planes should be removed near the input and output pins. For long signal paths controlled
impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors
should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in
pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic
capacitors should be placed as close to the device as possible. In Figure 17, Figure 18, and Figure 19 CSS is
optional, but is recommended for best second order harmonic distortion. Another option to using CSS is to use
pairs of 0.01 μF and 0.1 µF ceramic capacitors for each supply bypass.
6.8 mF
C2
.01 mF
C1
+
-
V
IN
+
-
V
OUT
R
IN
R
OUT
75W
75W
.01 mF
C3
6.8 mF
C4
Figure 24. Typical Video Application
Copyright © 2005–2013, Texas Instruments Incorporated
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11
Product Folder Links: LMH6704
LMH6704
SNOSAD0C –FEBRUARY 2005–REVISED MARCH 2013
www.ti.com
VIDEO PERFORMANCE
The LMH6704 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless
with DG of 0.02% and DP of 0.02°. Best performance will be obtained with back terminated loads. The back
termination reduces reflections from the transmission line and effectively masks transmission line and other
parasitic capacitances from the amplifier output stage. Figure 24 shows a typical configuration for driving a 75Ω
Cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT
.
POWER DISSIPATION
Follow these steps to determine the Maximum power dissipation for the LMH6704:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
(3)
(4)
(5)
where VS = V+ - V−
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms ((VS - VOUT) x IOUT
)
where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current
3. Calculate the total RMS power:
PT = PAMP+PD
The maximum power that the LMH6704, package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction
to ambient, for a given package (°C/W). For the SOT-23 package θJA is 187°C/W.
ESD PROTECTION
The LMH6704 is protected against electrostatic discharge (ESD) on all pins. The LMH6704 will survive 2000V
Human Body model and 200V Machine model events. Input and Output pins have ESD diodes to either supply
pin (V+ and V−) which are reverse biased and essentially have no effect under most normal operating conditions.
There are occasions, however, when the ESD diodes will be evident. If the LMH6704 is driven by a large signal
while the device is powered down, the ESD diodes might enter forward operating region and conduct. The
current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the
device, hence it is possible to inadvertently power up the LMH6704 with a large signal applied to the input pins.
Shorting the power pins to each other will prevent the chip from being powered up through the input.
12
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LMH6704
LMH6704
www.ti.com
SNOSAD0C –FEBRUARY 2005–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Links: LMH6704
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6704MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH67
04MA
LMH6704MF/NOPB
LMH6704MFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
1000 RoHS & Green
3000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
B07A
B07A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6704MF/NOPB
LMH6704MFX/NOPB
SOT-23
SOT-23
DBV
DBV
6
6
1000
3000
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6704MF/NOPB
LMH6704MFX/NOPB
SOT-23
SOT-23
DBV
DBV
6
6
1000
3000
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6704MA/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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