LMH6715 MDC [TI]
双路宽带视频运算放大器 | Y | 0 | -40 to 85;
| 型号： | LMH6715 MDC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路宽带视频运算放大器 | Y | 0 | -40 to 85 放大器 运算放大器 |
| 文件： | 总24页 (文件大小：1512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6715
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SNOSA10C –MAY 2002–REVISED APRIL 2013
LMH6715 Dual Wideband Video Op Amp
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1
FEATURES
DESCRIPTION
The LMH6715 combines TI's VIP10 high speed
complementary bipolar process with TI's current
feedback topology to produce a very high speed dual
op amp. The LMH6715 provides 400MHz small signal
bandwidth at a gain of +2V/V and 1300V/μs slew rate
while consuming only 5.8mA per amplifier from ±5V
supplies.
2
•
TA = 25°C, RL = 100Ω, Typical Values Unless
Specified.
•
•
Very Low Diff. Gain, Phase: 0.02%, 0.02°
Wide Bandwidth: 480MHz (AV = +1V/V);
400MHz (AV = +2V/V)
•
•
•
•
•
•
0.1dB Gain Flatness to 100MHz
Low Power: 5.8mA/Channel
The LMH6715 offers exceptional video performance
with its 0.02% and 0.02° differential gain and phase
errors for NTSC and PAL video signals while driving
up to four back terminated 75Ω loads. The LMH6715
also offers a flat gain response of 0.1dB to 100MHz
and very low channel-to-channel crosstalk of −70dB
at 10MHz. Additionally, each amplifier can deliver
70mA of output current. This level of performance
makes the LMH6715 an ideal dual op amp for high
density, broadcast quality video systems.
−70dB Channel-to-Channel Crosstalk (10MHz)
Fast Slew Rate: 1300V/μs
Unity Gain Stable
Improved Replacement for CLC412
APPLICATIONS
•
•
•
•
•
•
HDTV, NTSC & PAL Video Systems
Video Switching and Distribution
IQ Amplifiers
The LMH6715's two very well matched amplifiers
support a number of applications such as differential
line drivers and receivers. In addition, the LMH6715
is well suited for Sallen Key active filters in
applications such as anti-aliasing filters for high
speed A/D converters. Its small 8-pin SOIC package,
low power requirement, low noise and distortion allow
the LMH6715 to serve portable RF applications such
as IQ channels.
Wideband Active Filters
Cable Drivers
DC Coupled Single-to-Differential Conversions
Differential Gain & Phase with Multiple Video Loads
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
LMH6715
SNOSA10C –MAY 2002–REVISED APRIL 2013
www.ti.com
Frequency Response vs. VOUT
Figure 2.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
Human Body Model
2000V
150V
Machine Model
VCC
±6.75V
IOUT
See(4)
Common-Mode Input Voltage
Differential Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
±VCC
2.2V
+150°C
−65°C to +150°C
+300°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω In series with 200pF.
(4) The maximum output current (IOUT) is determined by device power dissipation limitations. See the POWER DISSIPATION section for
more details.
Operating Ratings
Thermal Resistance
Package
(θJC
)
(θJA
)
SOIC
65°C/W
145°C/W
Operating Temperature Range
Nominal Operating Voltage
−40°C to +85°C
±5V to ±6V
2
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Electrical Characteristics(1)
AV = +2, RF = 500Ω, VCC = ±5 V, RL = 100Ω; unless otherwise specified. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
SSBW
LSBW
-3dB Bandwidth
-3dB Bandwidth
Gain Flatness
Peaking
VOUT < 0.5VPP, RF = 300Ω
VOUT < 4.0VPP, RF = 300Ω
VOUT < 0.5VPP
280
400
170
MHz
MHz
GFP
GFR
LPD
DG
DC to 100MHz, RF = 300Ω
DC to 100MHz, RF = 300Ω
DC to 100MHz, RF = 300Ω
RL = 150Ω, 4.43MHz
0.1
0.1
dB
dB
Rolloff
Linear Phase Deviation
Differential Gain
Differential Phase
0.25
0.02
0.02
deg
%
DP
RL = 150Ω, 4.43MHz
deg
Time Domain Response
Tr
Rise and Fall Time
0.5V Step
4V Step
2V Step
0.5V Step
2V Step
1.4
3
ns
ns
Ts
Settling Time to 0.05%
Overshoot
12
ns
OS
SR
1
%
Slew Rate
1300
V/μs
Distortion And Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Input Noise
Non-Inverting Voltage
Inverting Current
2VPP, 20MHz
2VPP, 20MHz
−60
−75
dBc
dBc
VN
>1MHz
3.4
10.0
1.4
nV/√Hz
pA/√Hz
pA/√Hz
dB1Hz
dB
IN
>1MHz
INN
Non-Inverting Current
Noise Floor
>1MHz
SNF
XTLKA
>1MHz
−153
−70
Crosstalk
Input Referred 10MHz
Static, DC Performance
VIO
Input Offset Voltage
±2
±6
mV
±8
DVIO
IBN
Average Drift
±30
±5
μV/°C
μA
Input Bias Current
Non-Inverting
Inverting
±12
±20
DIBN
IBI
Average Drift
±30
±6
nA/°C
Input Bias Current
±21
μA
±35
DIBI
Average Drift
±20
60
nA/°C
dB
PSRR
Power Supply Rejection Ratio
DC
46
44
CMRR
ICC
Common Mode Rejection Ratio
Supply Current per Amplifier
DC
50
47
56
dB
RL = ∞
4.7
5.8
7.6
mA
4.1
8.1
Miscellaneous Performance
RIN
Input Resistance
Input Capacitance
Output Resistance
Non-Inverting
Non-Inverting
Closed Loop
1000
1.0
kΩ
pF
Ω
CIN
ROUT
.06
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Application Section for information on temperature de-rating of this device."
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
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Electrical Characteristics(1) (continued)
AV = +2, RF = 500Ω, VCC = ±5 V, RL = 100Ω; unless otherwise specified. Boldface limits apply at the temperature extremes.
Symbol
VO
Parameter
Conditions
Min
Typ
±4.0
±3.9
Max
Units
Output Voltage Range
RL = ∞
V
V
VOL
RL = 100Ω
±3.5
±3.4
CMIR
IO
Input Voltage Range
Output Current
Common Mode
±2.2
70
V
mA
Connection Diagram
Figure 3. 8-Pin SOIC, Top View
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Typical Performance Characteristics
(TA = 25°C, VCC = ±5V, AV = ±2V/V, RF = 500Ω, RL = 100Ω, unless otherwise specified).
Non-Inverting Freq·uency Response
Inverting Frequency Response
Figure 4.
Figure 5.
Non-Inverting Frequency Response
vs.
VOUT
Small Signal Channel Matching
Figure 6.
Figure 7.
Frequency Response
vs.
Load Resistance
Non-Inverting Frequency Response
vs.
RF
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
(TA = 25°C, VCC = ±5V, AV = ±2V/V, RF = 500Ω, RL = 100Ω, unless otherwise specified).
Small Signal Pulse Response
Large Signal Pulse Response
Figure 10.
Figure 11.
Settling Time
vs.
Accuracy
Input-Referred Crosstalk
Figure 12.
Figure 13.
−3dB Bandwidth
DC Errors
vs.
Temperature
vs.
VOUT
Figure 14.
Figure 15.
6
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Typical Performance Characteristics (continued)
(TA = 25°C, VCC = ±5V, AV = ±2V/V, RF = 500Ω, RL = 100Ω, unless otherwise specified).
Equivalent Input Noise
vs.
Frequency
Open Loop Transimpedance, Z(s)
Figure 16.
Figure 17.
Differential Gain & Phase
Differential Gain
vs.
vs.
Load
Frequency
Figure 18.
Figure 19.
Differential Phase
vs.
Frequency
Gain Flatness & Linear Phase Deviation
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
(TA = 25°C, VCC = ±5V, AV = ±2V/V, RF = 500Ω, RL = 100Ω, unless otherwise specified).
2nd Harmonic Distortion
vs.
3rd Harmonic Distortion
vs.
Output Voltage
Output Voltage
Figure 22.
Figure 23.
Closed Loop Output Resistance
PSRR & CMRR
Figure 24.
Figure 25.
Suggested RS
vs.
CL
Figure 26.
8
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APPLICATION SECTION
Figure 27. Non-Inverting Configuration with Power Supply Bypassing
Figure 28. Inverting Configuration with Power Supply Bypassing
Application Introduction
Offered in an 8-pin package for reduced space and cost, the wideband LMH6715 dual current-feedback op amp
provides closely matched DC and AC electrical performance characteristics making the part an ideal choice for
wideband signal processing. Applications such as broadcast quality video systems, IQ amplifiers, filter blocks,
high speed peak detectors, integrators and transimedance amplifiers will all find superior performance in the
LMH6715 dual op amp.
FEEDBACK RESISTOR SELECTION
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Performance plots specify an RF of 500Ω, a gain of +2V/V and ±5V power supplies
(unless otherwise specified). Generally, lowering RF from it's recommended value will peak the frequency
response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off
faster. Reducing the value of RF too far below it's recommended value will cause overshoot, ringing and,
eventually, oscillation.
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Frequency Response vs. RF
Figure 29.
Figure 29 shows the LMH6715's frequency response as RF is varied (RL = 100Ω, AV = +2). This plot shows that
an RF of 200Ω results in peaking and marginal stability. An RF of 300Ω gives near maximal bandwidth and gain
flatness with good stability, but with very light loads (RL > 300Ω) the device may show some peaking. An RF of
500Ω gives excellent stability with good bandwidth and is the recommended value for most applications. Since all
applications are slightly different it is worth some experimentation to find the optimal RF for a given circuit. For
more information see Application Note OA-13 (Literature Number SNOA366) which describes the relationship
between RF and closed-loop frequency response for current feedback operational amplifiers.
When configuring the LMH6715 for gains other than +2V/V, it is usually necessary to adjust the value of the
feedback resistor. The two plots labeled shown in Figure 30 and Figure 31 provide recommended feedback
resistor values for a number of gain selections.
RF vs. Non-Inverting Gain
Figure 30.
Both plots show the value of RF approaching a minimum value (dashed line) at high gains. Reducing the
feedback resistor below this value will result in instability and possibly oscillation. The recommended value of RF
is depicted by the solid line, which begins to increase at higher gains. The reason that a higher RF is required at
higher gains is the need to keep RG from decreasing too far below the output impedance of the input buffer. For
the LMH6715 the output resistance of the input buffer is approximately 160Ω and 50Ω is a practical lower limit for
RG. Due to the limitations on RG the LMH6715 begins to operate in a gain bandwidth limited fashion for gains of
±5V/V or greater.
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RF vs. Inverting Gain
Figure 31.
When using the LMH6715 as a replacement for the CLC412, identical bandwidth can be obtained by using an
appropriate value of RF . The chart “Frequency Response vs. RF” (see Figure 29) shows that an RF of
approximately 700Ω will provide bandwidth very close to that of the CLC412. At other gains a similar increase in
RF can be used to match the new and old parts.
CIRCUIT LAYOUT
With all high frequency devices, board layouts with stray capacitances have a strong influence over AC
performance. The LMH6715 is no exception and its input and output pins are particularly sensitive to the coupling
of parasitic capacitances (to AC ground) arising from traces or pads placed too closely (<0.1”) to power or
ground planes. In some cases, due to the frequency response peaking caused by these parasitics, a small
adjustment of the feedback resistor value will serve to compensate the frequency response. Also, it is very
important to keep the parasitic capacitance across the feedback resistor to an absolute minimum.
The performance plots in the data sheet can be reproduced using the evaluation boards available from Texas
Instruments. The LMH730036 board uses all SMT parts for the evaluation of the LMH6715. The board can serve
as an example layout for the final production printed circuit board.
Care must also be taken with the LMH6715's layout in order to achieve the best circuit performance, particularly
channel-to-channel isolation. The decoupling capacitors (both tantalum and ceramic) must be chosen with good
high frequency characteristics to decouple the power supplies and the physical placement of the LMH6715's
external components is critical. Grouping each amplifier's external components with their own ground connection
and separating them from the external components of the opposing channel with the maximum possible distance
is recommended. The input (RIN) and gain setting resistors (RF) are the most critical. It is also recommended that
the ceramic decoupling capacitor (0.1μF chip or radial-leaded with low ESR) should be placed as closely to the
power pins as possible.
POWER DISSIPATION
Follow these steps to determine the Maximum power dissipation for the LMH6715:
1. Calculate the quiescent (no-load) power: PAMP = ICC (VCC - VEE
)
2. Calculate the RMS power at the output stage: PO = (VCC -VLOAD)(ILOAD), where VLOAD and ILOAD are the voltage
and current across the external load.
3. Calculate the total RMS power: Pt = PAMP + PO
The maximum power that the LMH6715, package can dissipate at a given temperature can be derived with the
following equation:
Pmax = (150º - Tamb)/ θJA, where Tamb = Ambient temperature (°C) and θJA = Thermal resistance, from junction to
ambient, for a given package (°C/W). For the SOIC package θJA is 145°C/W.
(1)
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MATCHING PERFORMANCE
With proper board layout, the AC performance match between the two LMH6715's amplifiers can be tightly
controlled as shown in Typical Performance plot labeled “Small-Signal Channel Matching”.
The measurements were performed with SMT components using a feedback resistor of 300Ω at a gain of +2V/V.
The LMH6715's amplifiers, built on the same die, provide the advantage of having tightly matched DC
characteristics.
SLEW RATE AND SETTLING TIME
One of the advantages of current-feedback topology is an inherently high slew rate which produces a wider full
power bandwidth. The LMH6715 has a typical slew rate of 1300V/µs. The required slew rate for a design can be
calculated by the following equation: SR = 2πfVpk.
Careful attention to parasitic capacitances is critical to achieving the best settling time performance. The
LMH6715 has a typical short term settling time to 0.05% of 12ns for a 2V step. Also, the amplifier is virtually free
of any long term thermal tail effects at low gains.
When measuring settling time, a solid ground plane should be used in order to reduce ground inductance which
can cause common-ground-impedance coupling. Power supply and ground trace parasitic capacitances and the
load capacitance will also affect settling time.
Placing a series resistor (Rs) at the output pin is recommended for optimal settling time performance when
driving a capacitive load. The Typical Performance plot labeled “RS and Settling Time vs. Capacitive Load”
provides a means for selecting a value of Rs for a given capacitive load.
DC & NOISE PERFORMANCE
A current-feedback amplifier's input stage does not have equal nor correlated bias currents, therefore they
cannot be canceled and each contributes to the total DC offset voltage at the output by the following equation:
(2)
The input resistance is the resistance looking from the non-inverting input back toward the source. For inverting
DC-offset calculations, the source resistance seen by the input resistor Rg must be included in the output offset
calculation as a part of the non-inverting gain equation. Application note OA-07 (Literature Number SNOA365)
gives several circuits for DC offset correction. The noise currents for the inverting and non-inverting inputs are
graphed in the Typical Performance plot labeled “Equivalent Input Noise”. A more complete discussion of
amplifier input-referred noise and external resistor noise contribution can be found in OA-12 (Literature Number
SNOA375).
DIFFERENTIAL GAIN & PHASE
The LMH6715 can drive multiple video loads with very low differential gain and phase errors. Figure 19 and
Figure 20 show performance for loads from 1 to 4. The Electrical Characteristics table also specifies performance
for one 150Ω load at 4.43MHz. For NTSC video, the performance specifications also apply. Application note OA-
24 (Literature Number SNOA370) “Measuring and Improving Differential Gain & Differential Phase for Video”,
describes in detail the techniques used to measure differential gain and phase.
I/O VOLTAGE & OUTPUT CURRENT
The usable common-mode input voltage range (CMIR) of the LMH6715 specified in the Electrical Characteristics
table of the data sheet shows a range of ±2.2 volts. Exceeding this range will cause the input stage to saturate
and clip the output signal.
The output voltage range is determined by the load resistor and the choice of power supplies. With ±5 volts the
class A/B output driver will typically drive ±3.9V into a load resistance of 100Ω. Increasing the supply voltages
will change the common-mode input and output voltage swings while at the same time increase the internal
junction temperature.
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Applications Circuits
SINGLE-TO-DIFFERENTIAL LINE DRIVER
The LMH6715's well matched AC channel-response allows a single-ended input to be transformed to highly
matched push-pull driver. From a 1V single-ended input the circuit of Figure 32 produces 1V differential signal
between the two outputs. For larger signals the input voltage divider (R1 = 2R2) is necessary to limit the input
voltage on channel 2.
Figure 32. Single-to-Differential Line Driver
DIFFERENTIAL LINE RECEIVER
Figure 33 and Figure 34 show two different implementations of an instrumentation amplifier which convert
differential signals to single-ended. Figure 34 allows CMRR adjustment through R2.
Figure 33. Differential Line Receiver
Figure 34. Differential Line Receiver with CMRR Adjustment
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NON-INVERTING CURRENT-FEEDBACK INTEGRATOR
The circuit of Figure 35 achieves its high speed integration by placing one of the LMH6715's amplifiers in the
feedback loop of the second amplifier configured as shown.
Figure 35. Current Feedback Integrator
LOW NOISE WIDE-BANDWIDTH TRANSIMPEDANCE AMPLIFIER
Figure 36 implements a low noise transimpedance amplifier using both channels of the LMH6715. This circuit
takes advantage of the lower input bias current noise of the non-inverting input and achieves negative feedback
through the second LMH6715 channel. The output voltage is set by the value of RF while frequency
compensation is achieved through the adjustment of RT.
Figure 36. Low-Noise, Wide Bandwidth, Transimpedance Amp.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6715 MDC
ACTIVE
ACTIVE
DIESALE
SOIC
Y
D
0
8
400
95
RoHS & Green
RoHS & Green
Call TI
Level-1-NA-UNLIM
-40 to 85
-40 to 85
LMH6715MA/NOPB
SN
SN
Level-1-260C-UNLIM
LMH67
15MA
LMH6715MAX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
Level-1-260C-UNLIM
-40 to 85
LMH67
15MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6715MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH6715MAX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6715MA/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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