LMH6733 [TI]
单电源、1.0 GHz、三路运算放大器;
| 型号： | LMH6733 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单电源、1.0 GHz、三路运算放大器 放大器 运算放大器 |
| 文件： | 总28页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6733
www.ti.com
SNOSAW0D –JANUARY 2007–REVISED MAY 2013
LMH6733 Single Supply, 1.0 GHz, Triple Operational Amplifier
Check for Samples: LMH6733
1
FEATURES
DESCRIPTION
The LMH6733 is a triple, wideband, operational
amplifier designed specifically for use where high
speed and low power are required. Input voltage
range and output voltage swing are optimized for
operation on supplies as low as 3V and up to ±6V.
Benefiting from TI’s current feedback architecture, the
LMH6733 offers a gain range of ±1 to ±10 while
2
•
•
•
Supply Range 3 to 12V Single Supply
Supply Range ±1.5V to ±6V Split Supply
1.0 GHz −3 dB Small Signal Bandwidth
–
(AV = +1, VS = ±5V)
650 MHz −3 dB Small Signal Bandwidth
(AV = +2, VS = 5V)
•
•
–
providing
stable
operation
without
external
compensation, even at unity gain. These amplifiers
provide 650 MHz small signal bandwidth at a gain of
2 V/V , a low 2.1 nV/√Hz input referred noise and
only consume 5.5 mA (per amplifier) from a single 5V
supply.
Low Supply Current (5.5 mA per op Amp, VS =
5V)
•
•
•
•
2.1 nV/√Hz Input Noise Voltage
3750 V/μs Slew Rate
70 mA Linear Output Current
The LMH6733 is offered in a 16-Pin SSOP package
with flow through pinout for ease of layout and is also
pin compatible with the LMH6738. Each amplifier has
an individual shutdown pin.
CMIR and Output Swing to 1V from Each
Supply Rail
APPLICATIONS
Connection Diagram
Top View
•
•
•
•
•
•
•
•
•
HDTV Component Video Driver
High Resolution Projectors
Flash A/D Driver
-IN A
D/A Transimpedance Buffer
Wide Dynamic Range IF Amp
Radar/Communication Receivers
DDS Post-Amps
1
2
3
4
5
6
7
8
16
15
DIS A
-
+
+V
S
+IN A
DIS B
-IN B
+IN B
DIS C
-IN C
14 OUT A
Wideband Inverting Summer
Line Driver
-V
13
S
-
+
12 OUT B
+V
11
S
10 OUT C
-
+
-V
+IN C
9
S
Figure 1. 16-Pin SSOP Package
See Package Number DBQ0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH6733
SNOSAW0D –JANUARY 2007–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
Machine Model
2000V
200V
Supply Voltage (V+ - V–)
13.2V
(4)
IOUT
Common Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Soldering Information
±VCC
+150°C
−65°C to +150°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Storage Temperature Range
235°C
260°C
−65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Applications Information for more details.
(1)
Operating Ratings
Thermal Resistance
Package
(θJC
)
(θJA)
16-Pin SSOP
Temperature Range
Supply Voltage (V+ - V–)
36°C/W
−40°C
3V
120°C/W
+85°C
12V
(2)
to
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(1)
5V Electrical Characteristics
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MHz
MHz
MHz
Frequency Domain Performance
UGBW
SSBW
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
Unity Gain, VOUT = 200 mVPP
VOUT = 200 mVPP, RL = 100Ω
VOUT = 200 mVPP, RL = 150Ω
VOUT = 2 VPP
870
650
685
480
320
0.1 dB
BW
0.1 dB Gain Flatness
VOUT = 200 mVPP
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
2
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SNOSAW0D –JANUARY 2007–REVISED MAY 2013
5V Electrical Characteristics (1) (continued)
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Time Domain Response
TRS
Rise and Fall Time
(10% to 90%)
2V Step
0.8
ns
SR
Slew Rate
2V Step
2V Step
1900
10
V/µs
ns
ts
Settling Time to 0.1%
Enable Time
te
From Disable = Rising Edge
From Disable = Falling Edge
10
ns
td
Disable Time
15
ns
Distortion
HD2L
HD3L
2nd Harmonic Distortion
3rd Harmonic Distortion
2 VPP, 10 MHz
2 VPP, 10 MHz
−63
−73
dBc
dBc
Equivalent Input Noise
VN
Non-Inverting Voltage
>10 MHz
>10 MHz
>10 MHz
2.1
nV/√Hz
pA/√Hz
pA/√Hz
ICN
NCN
Inverting Current
18.6
26.9
Non-Inverting Current
Video Performance
DG
DP
Differential Gain
Differential Phase
4.43 MHz, RL = 150Ω
4.43 MHz, RL = 150Ω
0.03
%
0.025
deg
Static, DC Performance
(2)
VIO
Input Offset Voltage
0.4
16.7
1.0
2.0
2.5
mV
µA
μA
(2)
IBN
Input Bias Current
Input Bias Current
Non-Inverting
Inverting
+PSRR
2
28
32
(2)
IBI
17
19
PSRR
Power Supply Rejection Ratio
59
59
61
(2)
dB
−PSRR
58
61
57
(2)
CMRR
XTLK
ICC
Common Mode Rejection Ratio
Crosstalk
52
51.5
54.5
−80
dB
dB
Input Referred, f = 10 MHz, Drive
Channels A,C Measure Channel B
(2)
Supply Current
All Three Amps Enabled, No Load
16.7
1.54
0.75
18
1.8
1.8
mA
mA
mA
Supply Current Disabled V+
Supply Current Disabled V−
RL = ∞
RL = ∞
Miscellaneous Performance
RIN
CIN
RIN
RO
VO
+
+
−
Non-Inverting Input Resistance
200
1
kΩ
pF
Ω
Non-Inverting Input Capacitance
Inverting Input Impedance
Output Impedance
Output Impedance of Input Buffer.
27
DC
0.05
Ω
(2)
Output Voltage Range
RL = 100Ω
1.25-3.75
1.3-3.7
1.12-3.88
V
RL = ∞
1.11-3.89 1.03-3.97
1.15-3.85
CMIR
IO
Common Mode Input Range
CMRR > 40 dB
VIN = 0V, VOUT < ±42 mV
1.1-3.9
1.2-3.8
1.0–4.0
±60
V
(2)
Linear Output Current
±50
mA
(3) (2)
(2) Parameter 100% production tested at 25° C.
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Applications Information for more details.
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5V Electrical Characteristics (1) (continued)
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified.
Symbol
ISC
Parameter
Conditions
VIN = 2V Output Shorted to Ground
Disable Pin = V+
Min
Typ
170
−72
−360
3.2
Max
Units
mA
μA
μA
V
(4)
Short Circuit Current
IIH
Disable Pin Bias Current High
Disable Pin Bias Current Low
Voltage for Disable
IIL
Disable Pin = 0V
VDMAX
VDMIM
Disable Pin ≤ VDMAX
Disable Pin ≥ VDMIN
Voltage for Enable
3.6
V
(4) Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application
Section for more details.
(1)
±5V Electrical Characteristics
AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MHz
MHz
MHz
Frequency Domain Performance
UGBW
SSBW
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
Unity Gain, VOUT = 200 mVPP
VOUT = 200 mVPP, RL = 100Ω
VOUT = 200 mVPP, RL = 150Ω
VOUT = 2 VPP
1000
830
950
600
350
0.1 dB BW 0.1 dB Gain Flatness
VOUT = 200 mVPP
Time Domain Response
TRS
TRL
SR
Rise and Fall Time
(10% to 90%)
2V Step
0.7
0.8
3750
10
ns
5V Step
Slew Rate
4V Step
V/µs
ns
ts
Settling Time to 0.1%
Enable Time
2V Step
te
From Disable = Rising Edge
From Disable = Falling Edge
10
ns
td
Disable Time
15
ns
Distortion
HD2L
HD3L
2nd Harmonic Distortion
3rd Harmonic Distortion
2 VPP, 10 MHz
2 VPP, 10 MHz
−72
−63
dBc
dBc
Equivalent Input Noise
VN
Non-Inverting Voltage
>10 MHz
>10 MHz
>10 MHz
2.1
nV/√Hz
pA/√Hz
pA/√Hz
ICN
NCN
Inverting Current
18.6
26.9
Non-Inverting Current
Video Performance
DG
DP
Differential Gain
Differential Phase
4.43 MHz, RL = 150Ω
4.43 MHz, RL = 150Ω
0.03
0.03
%
Deg
Static, DC Performance
(2)
VIO
Input Offset Voltage
0.6
3.5
5
2.2
2.5
mV
µA
μA
(2)
IBN
Input Bias Current
Input Bias Current
Non-Inverting
Inverting
−14
−19
19
24
(2)
IBI
23
26
PSRR
Power Supply Rejection Ratio
+PSRR
59
58
61.5
61
(2)
dB
dB
−PSRR
(2)
CMRR
Common Mode Rejection Ratio
53
52.5
55
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Parameter 100% production tested at 25° C.
4
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SNOSAW0D –JANUARY 2007–REVISED MAY 2013
±5V Electrical Characteristics (1) (continued)
AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
XTLK
Crosstalk
Input Referred, f = 10 MHz, Drive
Channels A,C Measure Channel B
−80
dB
(2)
ICC
Supply Current
All Three Amps Enabled, No Load
19.5
20.8
mA
22.0
Supply Current Disabled V+
Supply Current Disabled V−
RL = ∞
RL = ∞
1.54
0.75
1.8
1.8
mA
mA
Miscellaneous Performance
RIN
CIN
RIN
RO
VO
+
+
−
Non-Inverting Input Resistance
Non-Inverting Input Capacitance
Inverting Input Impedance
Output Impedance
200
1
kΩ
pF
Ω
Output Impedance of Input Buffer
30
DC
0.05
Ω
(2)
Output Voltage Range
RL = 100Ω
±3.55
±3.5
±3.7
V
RL = ∞
±3.85
±4.0
±4.0
CMIR
IO
Common Mode Input Range
CMRR > 43 dB
±3.9
V
(2)
±3.8
Linear Output Current
VIN = 0V, VOUT < ±42 mV
70
±80
mA
(3) (2)
(4)
ISC
Short Circuit Current
VIN = 2V Output Shorted to Ground
Disable Pin = V+
237
−72
−360
3.2
mA
μA
μA
V
IIH
Disable Pin Bias Current High
Disable Pin Bias Current Low
Voltage for Disable
IIL
Disable Pin = 0V
VDMAX
VDMIM
Disable Pin ≤ VDMAX
Disable Pin ≥ VDMIN
Voltage for Enable
3.6
V
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Applications Information for more details.
(4) Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application
Section for more details.
Copyright © 2007–2013, Texas Instruments Incorporated
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Typical Performance Characteristics
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified).
Large Signal Frequency Response
Large Signal Frequency Response
1
0
1
0
A
= 1, R = 324W
F
V
-1
-2
-3
-4
-1
-2
-3
-4
A
= -1, R = 340W
F
A
= 2, R = 340W
V
V
F
A
V
= -2, R = 340W
F
A
= -5, R = 340W
F
A
= 5, R = 340W
V
V
F
-5
-6
-7
-8
-9
-5
-6
-7
-8
-9
V
= 2 V
V
= 2 V
OUT PP
OUT
PP
10
100
10
100
1000
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 2.
Figure 3.
Small Signal Frequency Response
Frequency Response vs. VOUT
1
0
2
V
OUT
= 1 V
PP
1
0
-1
-2
-3
-4
V
= 2 V
PP
OUT
-1
-2
-3
-4
-5
-6
-7
-8
-9
A
= 1, R = 324W
F
V
V
= 0.5 V
PP
OUT
A
= 2, R = 340W
F
V
-5
-6
-7
-8
-9
A
= 5, R = 340W
F
V
A
= 2 V/V
V
R
= 340W
V
= 0.25 V
PP
F
OUT
100
10
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4.
Figure 5.
Frequency Response vs. Supply Voltage
Gain Flatness
0.5
0.4
0.3
1
A
= 1, R = 324W
F
V
S
= 6V
V
0
-1
-2
-3
-4
V
= 4.3V
S
0.2
0.1
0
A
= 2, R = 340W
F
V
V
= 4.5V
S
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-6
-7
-8
-9
A
= 5, R = 340W
V
F
V
= 2 V
PP
V
= 1 V
OUT
OUT
PP
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified).
Pulse Response
Crosstalk vs. Frequency
-10
-20
-30
-40
-50
-60
-70
-80
1.2
CH A & C V
OUT
= 1 V
PP
MEASURE CH B
0.8
0.4
0
-0.4
A
= 2V/V
= 2.0 V
V
-0.8
-1.2
V
OUT
PP
-90
1
10
100
1000
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (MHz)
TIME (ns)
Figure 8.
Figure 9.
Distortion vs. Frequency
Distortion vs. Output Voltage
-10
-20
-30
-40
-50
V
= 2 V
R
= 100W
OUT
PP
L
f = 10 MHz
HD3
-60
-70
-80
-40
-50
-60
HD2
HD3
HD2
-70
-90
-80
-90
-100
0
1
2
3
4
5
1
10
100
V (V )
OUT PP
FREQUENCY (MHz)
Figure 10.
Figure 11.
Small Signal Frequency Response vs. RL
4
Frequency Response vs. Capacitive Load
1
V
OUT
= 1 V
PP
3
2
C
L
|| 1 kW
-1
R
= 1 kW
L
1
0
-3
-5
R
L
= 150W
-1
-2
-3
-4
-5
-6
C
= 100 pF, R = 17W
S
L
L
L
R
= 100W
C
C
= 47 pF, R = 23W
S
L
= 33 pF, R = 26W
S
-7
-9
C
C
= 15 pF, R = 38W
L
S
V
OUT
= 0.2 V
PP
= 4.7 pF, R = 75W
L
S
10
100
1000
10000
100
1000
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified).
Series Output Resistance vs. Capacitive Load
PSRR vs. Frequency
70
-70
LOAD = 1 kW || C
L
60
50
40
30
20
-60
-50
-PSRR
+PSRR
-40
-30
-20
-10
10
0
0
0
20
40
60
80
100 120
0.1
1
10
100
1000
CAPACITIVE LOAD (pF)
FREQUENCY (MHz)
Figure 14.
Figure 15.
CMRR vs. Frequency
Closed Loop Output Impedance |Z|
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
10
1
A
V
= 2 V/V
V
= 0 V
PP
IN
0.1
0.01
0
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16.
Figure 17.
Disabled Channel Isolation vs. Frequency
Disable Timing
-30
0.6
V
V
= 2 V
PP
VOUT
IN
0.4
0.2
= ±2.5V
S
-40
-50
0.0
-0.2
-0.4
-0.6
-60
-70
-80
-90
2
1
DISABLE
0
-100
0.1
1
10
100
0
10 20 30 40 50 60 70
TIME (ns)
90
1000
80
FREQUENCY (MHz)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified).
DC Errors vs. Temperature
Open Loop Transimpedance
110
100
90
0.8
0.75
0.7
13
11
9
I
BN
MAGNITUDE
80
V
OS
0.65
0.6
7
70
5
0
60
0.55
0.5
3
50
-45
PHASE
1
40
-90
0.45
0.4
-1
-3
30
-135
-180
I
BI
20
0.1
1
10
100
1000
-40 -20
0
20 40 60 80 100 120
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 20.
Figure 21.
Input Noise vs. Frequency
8
7
6
5
4
3
2
1
0
120
105
90
75
60
45
30
15
0
NON-INVERTING VOLTAGE
NON-INVERTING CURRENT
INVERTING CURRENT
0.1
10
0.0001
0.01
1
100
0.001
FREQUENCY (MHz)
Figure 22.
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Typical Performance Characteristics
AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise specified).
Large Signal Frequency Response
Large Signal Frequency Response
3
1
0
A
= -1, R = 383W
F
A
= 1, R = 324W
F
V
V
2
1
A
V
= 2, R = 383W
F
-1
-2
-3
-4
A
V
= -2, R = 383W
F
0
-1
-2
-3
A
V
= 5, R = 383W
F
A
V
= -5, R = 383W
F
A
V
= 10, R = 383W
F
-4
-5
-6
-5
-6
-7
-8
-9
A
V
= -10, R = 383W
F
-7
-8
-9
V
OUT
= 2 V
PP
V
= 2 V
PP
OUT
100
10
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23.
Figure 24.
Small Signal Frequency Response
Frequency Response vs. VOUT
1
4
3
2
A
= 1, R = 324W
F
V
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
1
0
A
= 4 V
PP
V
-1
-2
-3
-4
-5
-6
A
= 2 V
PP
A
V
= 0.5 V
PP
V
A
= 2, R = 383W
V
F
A
= 1 V
PP
A
= 5, R = 383W
V
V
F
-7
-8
A
= 2 V/V
V
R
= 383W
V
= 0.25 V
F
OUT
PP
-9
10
10
100
1000
10000
1000
100
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25.
Figure 26.
Frequency Response vs. Supply Voltage
Gain Flatness
0.5
0.4
0.3
1
0
A
V
= 1, R = 324W
F
-1
V
S
= 7V
-2
-3
-4
0.2
0.1
0
A
= 2, R = 383W
F
V
V
= 9V
S
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-6
-7
-8
-9
V
= 12.5V
A
= 5, R = 383W
S
V
F
V
= 2 V
PP
V
= 1 V
PP
OUT
OUT
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27.
Figure 28.
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Typical Performance Characteristics (continued)
AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise specified).
Pulse Response
Crosstalk vs. Frequency
-10
-20
-30
-40
-50
-60
-70
-80
-90
1.2
CH A & C V
OUT
= 1 V
PP
MEASURE CH B
0.8
0.4
0
-0.4
A
= 2V/V
= 2.0 V
V
-0.8
-1.2
V
OUT
PP
1
10
100
1000
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FREQUENCY (MHz)
Figure 29.
Figure 30.
Distortion vs. Output Voltage
Distortion vs. Frequency
-50
-60
-70
-80
-90
-40
-50
A
= 2 V/V
V
V
= 2 V
PP
OUT
f = 10 MHz
HD3
HD2
-60
-70
-80
HD3
HD2
-90
-100
1
10
100
0
1
2
3
4
FREQUENCY (MHz)
V (V )
OUT PP
Figure 31.
Figure 32.
DC Errors vs. Temperature
0.8
11
0.75
0.7
9
I
BI
7
0.65
0.6
5
V
OS
3
0.55
0.5
1
-1
-3
-5
0.45
0.4
I
BN
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 33.
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APPLICATION INFORMATION
+2.5V
6.8 mF
A
V
= 1 +R /R = V
/V
OUT IN
F
G
0.1 mF
V
IN
C
POS
+
-
V
OUT
C
SS
0.01 mF
R
IN
C
NEG
R
F
0.1 mF
6.8 mF
R
G
-2.5V
Figure 34. Recommended Non-Inverting Gain Circuit
+2.5V
6.8 mF
R
R
V
OUT
F
0.1 mF
-
A
V
=
=
V
IN
G
C
POS
+
-
V
OUT
C
SS
0.01 mF
25W
C
NEG
R
F
V
IN
R
G
0.1 mF
6.8 mF
SELECT R TO
T
YIELD DESIRED
R
T
-2.5V
R
= R ||R
T G
IN
Figure 35. Recommended Inverting Gain Circuit
General Information
The LMH6733 is a high speed current feedback amplifier, optimized for very high speed and low distortion. The
LMH6733 has no internal ground reference so single or split supply configurations are both equally useful.
Feedback Resistor Selection
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using the appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Performance plots specify an RF of 340Ω, a gain of +2 V/V and ±2.5V power supplies
(unless otherwise specified). Generally, lowering RF from its recommended value will peak the frequency
response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off
faster. Reducing the value of RF too far below its recommended value will cause overshoot, ringing and,
eventually, oscillation.
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450
400
350
300
INVERTING (A < 0)
V
250
200
150
NON-INVERTING (A > 0)
V
100
50
0
1
2
3
4
5
6
7
8
9
10
|GAIN| (V/V)
Figure 36. Recommended RF vs. Gain
See Figure 36 for selecting a feedback resistor value for gains of ±1 to ±10. Since each application is slightly
different it is worth some experimentation to find the optimal RF for a given circuit. In general a value of RF that
produces about 0.1 dB of peaking is the best compromise between stability and maximal bandwidth. Note that it
is not possible to use a current feedback amplifier with the output shorted directly to the inverting input. The
buffer configuration of the LMH6733 requires a 324Ω feedback resistor for stable operation.
The LMH6733 has been optimized for high speed operation. As shown in Figure 36 the suggested value for RF
decreases for higher gains. Due to the impedance of the input buffer there is a practical limit for how small RF
can go, based on the lowest practical value of RG. This limitation applies to both inverting and non-inverting
configurations. For the LMH6733 the input resistance of the inverting input is approximately 30Ω and 20Ω is a
practical (but not hard and fast) lower limit for RG. The LMH6733 begins to operate in a gain bandwidth limited
fashion in the region where RG is nearly equal to the input buffer impedance. Note that the amplifier will operate
with RG values well below 20Ω, however results may be substantially different than predicted from ideal models.
In particular the voltage potential between the inverting and non-inverting inputs cannot be expected to remain
small.
Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially
if maximum bandwidth is required). The impedance seen by the source is RG || RT (RT is optional). The value of
RG is RF /gain. Thus for an inverting gain of −5 V/V and an optimal value for RF the input impedance is equal to
55Ω. Using a termination resistor this can be brought down to match a 25Ω source; however, a 150Ω source
cannot be matched. To match a 150Ω source would require using a 1050Ω feedback resistor and would result in
reduced bandwidth.
For more information see Application Note OA-13 which describes the relationship between RF and closed-loop
frequency response for current feedback operational amplifiers. The value for the inverting input impedance for
the LMH6733 is approximately 30Ω. The LMH6733 is designed for optimum performance at gains of +1 to +10
V/V and −1 to −9 V/V. Higher gain configurations are still useful; however, the bandwidth will fall as gain is
increased, much like a typical voltage feedback amplifier.
Active Filter
The choice of reactive components requires much attention when using any current feedback operational
amplifier as an active filter. Reducing the feedback impedance, especially at higher frequencies, will almost
certainly cause stability problems. Likewise capacitance on the inverting input should be avoided. See
Application Notes OA-07 and OA-26 for more information on Active Filter applications for Current Feedback Op
Amps.
When using the LMH6733 as a low pass filter the value of RF can be substantially reduced from the value
recommended in the RF vs. Gain charts. The benefit of reducing RF is increased gain at higher frequencies,
which improves attenuation in the stop band. Stability problems are avoided because in the stop band additional
device bandwidth is used to cancel the input signal rather than amplify it. The benefit of this change depends on
the particulars of the circuit design. With a high pass filter configuration reducing RF will likely result in device
instability and is not recommended.
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6.8 mF
+ V
SUPPLY
C2
0.1 mF
C1
X1
R
IN
75W
+
-
V
IN
+
-
V
OUT
R
OUT
75W
R
G
340W
R
F
340W
0.1 mF
C3
6.8 mF
- V
SUPPLY
C4
Figure 37. Typical Video Application
X1
R
OUT
+
-
51W
+
-
C
10 pF
R
R
IN
51W
R
L
L
G
1 kW
340W
R
F
340W
Figure 38. Decoupling Capacitive Loads
Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. shows the use of
a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to
120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The chart
“Frequency Response vs. Capacitive Load” give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
CAT5 High Definition Video Transmission
The LMH6733 can be used to send component 1080i High Definition (HD) video over CAT5 twisted-pairs. As
shown Figure 39 , the LMH6733 can be utilized to perform all three video transmitter, video receiver, and
equalization circuitry. The equalization circuitry enhances the video signal to accomodate for the CAT5
attenuation over various cable lengths. Refer to application note AN-1822 for more details regarding this
application.
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HD
Component
Video Input
(Y, Pr, Pb)
VIDEO
EQUALIZER
VIDEO
RECEIVER
CAT5 CABLE
LMH6733
VIDEO
LMH6733
LMH6733
TRANSMITTER
RT
RL
Figure 39. CAT5 High Definition Video Transmission
+5V
C
2
C
3
R
1
0.1 mF
100 mF
5 kW
C
10 mF
1
R
5 kW
2
C
0
R
0
V
1000 mF
75W
IN
V
+
LOAD
-
+
IN
LMH6733
C
R
3
10 kW
U1
R
T
47 mF
-
75W
(OPTIONAL)
R
L
75W
R
4
680W
+5V
R
340W
C
3
1 mF
F
R
680W
G
Figure 40. AC Coupled Single Supply Video Amplifier
AC-Coupled Video
The LMH6733 can be used as an AC-coupled single supply video amplifier for driving 75Ω coax with a gain of 2.
The input signal is nominally 0.7V or 1.0V for component YPRPB and RGB, depending on the presence of a sync.
R1, R2, and R3 simply set the input to the center of the input linear range while CIN AC couples the video onto the
op amp’s input.
As can be seen in , Figure 40 amplifier U1 is used in a positive gain configuration set for a closed loop gain of 2.
The feedback resistor RF is 340Ω. The gain resistor is created from the parallel combination of RG and R4, giving
a Thevenin equivalent of 340Ω connected to 2.5V.
The 75Ω back termination resistor RO divides the signal such that VOUT equals a buffered version of VIN. The
back termination will eliminate any reflection of the signal that comes from the load. The input termination
resistor, RT, is optional – it is used only if matching of the incoming line is necessary. In some applications, it is
recommended that a small valued ceramic capacitor be used in parallel with CO which is itself electrolytic
because of its rather large value. The ceramic cap will tend to shunt the inductive behavior of this electrolytic
cap, CO, at higher frequencies for an improved overall, low-impedance output.
Inverting Input Parasitic Capacitance
Parasitic capacitance is any capacitance in a circuit that was not intentionally added. It comes about from
electrical interaction between conductors. Parasitic capacitance can be reduced but never entirely eliminated.
Most parasitic capacitances that cause problems are related to board layout or lack of termination on
transmission lines. Please see the section on Layout Considerations for hints on reducing problems due to
parasitic capacitances on board traces. Transmission lines should be terminated in their characteristic
impedance at both ends.
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High speed amplifiers are sensitive to capacitance between the inverting input and ground or power supplies.
This shows up as gain peaking at high frequency. The capacitor raises device gain at high frequencies by
making RG appear smaller. Capacitive output loading will exaggerate this effect. In general, avoid introducing
unnecessary parasitic capacitance at both the inverting input and the output.
One possible remedy for this effect is to slightly increase the value of the feedback (and gain set) resistor. This
will tend to offset the high frequency gain peaking while leaving other parameters relatively unchanged. If the
device has a capacitive load as well as inverting input capacitance using a series output resistor as described in
the section on “Driving Capacitive Loads” will help.
Layout Considerations
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation
board supplied with samples of the LMH6733.
To reduce parasitic capacitances ground and power planes should be removed near the input and output pins.
Components in the feedback loop should be placed as close to the device as possible. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the
smaller ceramic capacitors should be placed as close to the device as possible. The LMH6733 has multiple
power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass
capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the
supply traces are thin and /or long. In Figure 34 and Figure 35 CSS is optional, but is recommended for best
second harmonic distortion. Another option to using CSS is to use pairs of .01 μF and .1 μF ceramic capacitors
for each supply bypass.
Video Performance
The LMH6733 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless.
Best performance will be obtained with back terminated loads. The back termination reduces reflections from the
transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier
output stage. Figure 37 shows a typical configuration for driving a 75Ω cable. The amplifier is configured for a
gain of two to make up for the 6 dB of loss in ROUT
.
2
1.8
1.6
1.4
1.2
1
225 LFPM FORCED AIR
STILL AIR
0.8
0.6
0.4
0.2
0
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
Figure 41. Maximum Power Dissipation
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Power Dissipation
The LMH6733 is optimized for maximum speed and performance in the small form factor of the standard SSOP-
16 package. To achieve its high level of performance, the LMH6733 consumes an appreciable amount of
quiescent current which cannot be neglected when considering the total package power dissipation limit. The
quiescent current contributes to about 40° C rise in junction temperature when no additional heat sink is used (VS
= ±5V, all 3 channels on). Therefore, it is easy to see that proper precautions need to be taken in order to make
sure the junction temperature’s absolute maximum rating of 150°C is not violated.
To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3
channels).
With the LMH6733 used in a back-terminated 75Ω RGB analog video system (with 2 VPP output voltage), the
total power dissipation is around 305 mW of which 220 mW is due to the quiescent device dissipation (output
black level at 0V). With no additional heat sink used, that puts the junction temperature to about 120° C when
operated at 85°C ambient.
To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An
external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal
(copper) area can be utilized as heat-sink.
An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to
use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is
from the die through the metal lead frame (inside the package) and onto the surrounding copper through the
interconnecting leads. Since high frequency performance requires limited metal near the device pins the best
way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal
conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a
ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination
of front side copper and vias to the back side can be combined as well.
Follow these steps to determine the maximum power dissipation for the LMH6733:
1. Calculate the quiescent (no-load) power:
PAMP = ICC X (VS)
where
•
VS = V+-V−
(1)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms ((VS - VOUT) X IOUT
)
where
•
•
VOUT and IOUT are the voltage and the current across the external load
VS is the total supply voltage
(2)
(3)
3. Calculate the total RMS power:
PT = PAMP+PD
The maximum power that the LMH6733, package can dissipate at a given temperature can be derived with the
following equation (See Figure 41):
PMAX = (150°C/W– TAMB)/ θJA
where
•
•
•
TAMB = ambient temperature (°C)
θJA = thermal resistance, from junction to ambient, for a given package (°C/W)
For the SSOP package θJA is 120°C/W
(4)
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ESD Protection
The LMH6733 is protected against electrostatic discharge (ESD) on all pins. The LMH6733 will survive 2000V
Human Body Model and 200V Machine Model events.
Under closed loop operation the ESD diodes have no affect on circuit performance. There are occasions,
however, when the ESD diodes will be evident. If the LMH6733 is driven by a large signal while the device is
powered down the ESD diodes will conduct.
The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through
the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the
power pins to each other will prevent the chip from being powered up through the input.
Evaluation Boards
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with these boards.
Device
Package
Evaluation Board Part Number
LMH6733MQ
SSOP
LMH730275
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6733MQ/NOPB
LMH6733MQX/NOPB
ACTIVE
SSOP
SSOP
DBQ
16
16
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LH67
33MQ
ACTIVE
DBQ
2500 RoHS & Green
SN
LH67
33MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6733MQX/NOPB
SSOP
DBQ
16
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
LMH6733MQX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6733MQ/NOPB
16
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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