LMH6739 [TI]
非常宽带、低失真三路视频缓冲器;
| 型号： | LMH6739 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 非常宽带、低失真三路视频缓冲器 |
| 文件： | 总22页 (文件大小：1293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
LMH6739 Very Wideband, Low Distortion Triple Video Buffer
Check for Samples: LMH6739
1
FEATURES
DESCRIPTION
2
•
750 MHz −3 dB small signal bandwidth
The LMH6739 is a very wideband, DC coupled
monolithic selectable gain buffer designed specifically
for ultra high resolution video systems as well as wide
dynamic range systems requiring exceptional signal
fidelity. Benefiting from current feedback architecture,
the LMH6739 offers gains of −1, 1 and 2. At a gain of
+2 the LMH6739 supports ultra high resolution video
systems with a 400 MHz 2 VPP3 dB Bandwidth. With
12-bit distortion level through 30 MHz (RL = 100Ω),
2.3nV/√Hz input referred noise, the LMH6739 is the
ideal driver or buffer for high speed flash A/D and D/A
converters. Wide dynamic range systems such as
(AV = +1)
•
•
•
•
•
•
•
−85 dBc 3rd harmonic distortion (20 MHz)
2.3 nV/√Hz input noise voltage
3300 V/μs slew rate
32 mA supply current (10.6 mA per op amp)
90 mA linear output current
0.02/0.01 Diff. Gain/ Diff. Phase (RL = 150Ω)
2mA shutdown current
APPLICATIONS
radar and communication receivers requiring
a
wideband amplifier offering exceptional signal purity
will find the LMH6739 low input referred noise and
low harmonic distortion make it an attractive solution.
The LMH6739 is offered in a space saving SSOP
package.
•
•
•
•
•
•
•
•
•
RGB video driver
High resolution projectors
Flash A/D driver
D/A transimpedance buffer
Wide dynamic range IF amp
Radar/communication receivers
DDS post-amps
Wideband inverting summer
Line driver
CONNECTION DIAGRAM
16-Pin SSOP
Top View
-IN A
+IN A
DIS B
-IN B
+IN B
DIS C
-IN C
1
2
3
4
5
6
7
8
16
15
DIS A
-
+
+V
S
14 OUT A
-V
13
S
-
+
12 OUT B
+V
11
S
10 OUT C
-
+
-V
+IN C
9
S
See Package Number DBQ0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LMH6739
SNOSAD2G –MAY 2004–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
ESD Tolerance
(2)
Human Body Model
Machine Model
2000V
200V
Supply Voltage (V+ - V–)
13.2V
(3)
IOUT
Common Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Soldering Information
±VCC
+150°C
−65°C to +150°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Storage Temperature Range
235°C
260°C
−65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Information for more details.
Operating Ratings(1)(2)
(3)
Temperature Range
Supply Voltage (V+ - V–)
Thermal Resistance
Package
−40°C to +85°C
8V to 12V
(θJC
)
(θJA
)
16-Pin SSOP
36°C/W
120°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
(1)
Electrical Characteristics
TA = 25°C, AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Frequency Domain Performance
UGBW
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
Unity Gain, VOUT = 200 mVPP
VOUT = 200 mVPP
750
480
400
150
1.0
MHz
MHz
VOUT = 2 VPP
0.1 dB Bandwidth
Rolloff
VOUT = 2 VPP
MHz
dB
GFR2
at 300 MHz, VOUT = 2 VPP
Time Domain Response
TRS
TRL
SR
Rise and Fall Time
(10% to 90%)
2V Step
0.9
1.7
ns
5V Step
Slew Rate
5V Step
3300
10
V/µs
ns
ts
Settling Time to 0.1%
Enable Time
2V Step
te
From Disable = rising edge.
From Disable = falling edge.
7.3
ns
td
Disable Time
4.5
ns
Distortion
HD2L
HD2
HD2H
HD3L
HD3
HD3H
2 VPP, 5 MHz
2 VPP, 20 MHz
2 VPP, 50 MHz
2 VPP, 5 MHz
2 VPP, 20 MHz
2 VPP, 50 MHz
−80
−71
−55
−90
−85
−65
2nd Harmonic Distortion
3rd Harmonic Distortion
dBc
dBc
Equivalent Input Noise
VN
Non-Inverting Voltage
>1 MHz
>1 MHz
>1 MHz
2.3
12
3
nV/√Hz
pA/√Hz
pA/√Hz
ICN
NCN
Inverting Current
Non-Inverting Current
Video Performance
DG
DP
Differential Gain
Differential Phase
4.43 MHz, RL = 150Ω
4.43 MHz, RL = 150Ω
.02
.01
%
degree
Static, DC Performance
VOS Input Offset Voltage
(4)
0.5
−8
−2
53
50
32
±2.5
±4.5
mV
µV
μA
dB
dB
mA
(4)
IBN
Input Bias Current
Input Bias Current
Non-Inverting
Inverting
−16
−21
0
+5
(4)
IBI
±30
±40
(4)
PSRR
CMRR
ICC
Power Supply Rejection Ratio
50
48.5
(4)
Common Mode Rejection Ratio
46
44
(4)
Supply Current
All three amps Enabled, No Load
35
40
Supply Current Disabled V+
Supply Current Disabled V−
RL = ∞
RL = ∞
1.9
1.1
2.2
1.3
mA
mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. Parametric performance is indicated in the electrical tables under conditions of
internal self heating where TJ> TA. See Applications Information for information on temperature de-rating of this device. Min/Max ratings
are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are through correlations using the Statistical
Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested on shipped production material.
(4) Parameter 100% production tested at 25° C.
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Electrical Characteristics (1) (continued)
TA = 25°C, AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Internal Feedback & Gain Set
Resistor Value
375
450
525
Ω
Gain Error
RL = ∞
0.2
±1.1
%
Miscellaneous Performance
RIN
CIN
RIN
RO
+
+
−
Non-Inverting Input Resistance
Non-Inverting Input Capacitance
Inverting Input Impedance
Output Impedance
1000
.8
kΩ
pF
Ω
Output impedance of input buffer.
DC
30
0.05
±3.5
Ω
±3.25
±3.1
RL = 100Ω
(4)
VO
Output Voltage Range
V
±3.65
±3.5
±3.8
±2.0
RL = ∞
(4)
CMIR
IO
Common Mode Input Range
CMRR > 40 dB
±1.9
±1.7
V
(5) (4)
Linear Output Current
80
60
VIN = 0V, VOUT < ±30 mV
90
mA
(6)
ISC
Short Circuit Current
VIN = 2V Output Shorted to Ground
Disable Pin = V+
160
10
mA
μA
μA
V
IIH
Disable Pin Bias Current High
Disable Pin Bias Current Low
Voltage for Disable
IIL
Disable Pin = 0V
−350
VDMAX
VDMIM
Disable Pin ≤ VDMAX
Disable Pin ≥ VDMIN
0.8
Voltage for Enable
2.0
V
(5) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Information for more details.
(6) Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application
Information for more details.
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
Typical Performance Characteristics
AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified).
Large Signal Frequency Response
Small Signal Frequency Response
4
4
V
= 2 V
PP
A
= +1
OUT
V
2
0
2
0
A
= +1
V
-2
-4
-2
-4
A
= -1
A
= -1
V
V
-6
-6
A
= +2
V
-8
-8
A
= +2
V
-10
-10
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1.
Figure 2.
Frequency Response
vs.
Frequency Response vs.
Supply Voltage
VOUT
1
0
1
0
-1
-1
V
= 4 V
PP
V
= 7V
OUT
S
-2
-3
-4
-2
-3
-4
V
= 2 V
PP
V
= 9V
OUT
V
S
-5
-6
-7
-8
-9
-5
-6
-7
-8
-9
= 1 V
PP
V
= 12.5V
OUT
S
V
OUT
= 0.5 V
PP
A
V
= 2 V/V
V
= 2 V
PP
OUT
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Gain Flatness
Gain Flatness, Dual Input Buffer
0.5
0.5
0.4
0.3
0.2
0.1
0
V
= 0.5 V
PP
V
œ 250 mV
PP
OUT
OUT
GAIN = +1
0.4
0.3
0.2
0.1
0
A
= +1
V
NON-INVERTING
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
BOTH
A
= -1
V
A
= +2
V
1000
1000
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified).
Frequency Response vs.
Capacitive Load
Pulse Response
2
1.5
C
= 4.7 pF, R = 70W
S
L
1
0
C
L
= 15 pF, R = 44W
S
0.5
0
-2
C
L
= 47 pF, R = 24W
S
-4
-6
C
= 100 pF, R = 17W
S
L
-0.5
-1
-8
V
OUT
= 1 V , C || 1 kW
PP
L
-1.5
-10
0
4
8
12
16
20
1
10
100
1000
FREQUENCY (MHz)
TIME (ns)
Figure 7.
Figure 8.
Series Output Resistance vs.
Capacitive Load
Open Loop Gain and Phase
80
120
110
LOAD = 1 kW || C
L
70
60
50
40
30
20
10
0
MAGNITUDE
100
90
80
70
60
50
40
0
-45
-90
PHASE
-135
-180
10
0.01
0.1
1
100
1000
0
20
40
80
100
60
120
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 9.
Figure 10.
Distortion vs.
Frequency
10 MHz HD vs.
Output Level
-40
-45
-50
-40
f = 10 MHz
V
= 2 V
PP
OUT
-45
-50
-55
-60
-65
-70
-55
-60
HD3
HD2
-65
-70
HD2
-75
-80
-75
-80
-85
-85
HD3
-90
-90
-95
-95
-100
-100
10
1
100
0
1
2
3
4
5
6
7
8
FREQUENCY (MHz)
OUTPUT VOLTAGE (V
)
PP
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified).
Distortion vs.
Supply Voltage
CMRR vs.
Frequency
-65
50
45
40
V
= 2V
PP
OUT
f = 10 MHz
HD2
-70
-75
-80
35
30
25
20
15
10
HD3
-85
-90
-95
5
0
-100
10
0.01
0.1
1
100
1000
6.8 7.6 8.4 9.2
10 10.8 11.6 12.4
FREQUENCY (MHz)
TOTAL SUPPLY VOLTAGE (V)
Figure 13.
Figure 14.
PSRR vs.
Frequency
Closed Loop Output Impedance |Z|
100
10
60
50
40
30
20
10
0
PSRR +
A
V
= 2 V/V
= 0V
V
IN
PSRR -
1
0.1
0.01
1
0.001
0.1
10
100 1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15.
Figure 16.
DC Errors vs.
Temperature
Disable Timing
0.6
1
6
4
I
BI
0.4
0.2
0.0
0.8
V
OUT
0.6
0.4
2
0
V
OS
-0.2
-0.4
-0.6
0.2
0
-2
-4
-0.2
-0.4
-0.6
-6
3
1
-8
I
DISABLE
BN
80 100
-1
-10
0
10
20
30
40
50
60
70
-40 -20
0
20
40
60
TIME (ns)
TEMPERATURE (°C)
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
AV = +2, VCC = ±5V, RL = 100Ω; unless otherwise specified).
Crosstalk vs.
Disabled Channel Isolation vs.
Frequency
Frequency
-30
-30
V
V
= 2 V
IN
PP
CH A & C V
OUT
= 2 V
PP
= ±5V
S
MEASURE CH B
-40
-50
-40
-50
-60
-70
-60
-70
-80
-90
-80
-90
-100
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
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APPLICATION INFORMATION
+5V
+5V
6.8 µF
6.8 µF
0.01 µF
0.01 µF
V
IN
V
IN
C
C
POS
POS
+
+
-
C
SS
C
SS
0.1 µF
V
OUT
V
OUT
R
IN
R
IN
0.1 µF
-
NC
C
NEG
C
NEG
0.01 µF
6.8 µF
0.01 µF
6.8 µF
-5V
-5V
Figure 21. Recommended Non-Inverting Gain
Circuit, Gain = +2
Figure 22. Recommended Non-Inverting Gain
Circuit, Gain +1
+5V
6.8 µF
0.01 µF
C
POS
+
-
C
SS
0.1 µF
V
OUT
V
IN
C
NEG
R
IN
0.01 µF
6.8 µF
-5V
Figure 23. Recommended Inverting Gain Circuit,
Gain = –1
GENERAL INFORMATION
The LMH6739 is a high speed current feedback selectable gain buffer (SGB), optimized for very high speed and
low distortion. With its internal feedback and gain-setting resistors the LMH6739 offers excellent AC performance
while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6739
has no internal ground reference so single or split supply configurations are both equally useful.
SETTING THE CLOSED LOOP GAIN
The LMH6739 is a current feedback amplifier with on-chip RF = RG = 450Ω. As such it can be configured with an
AV = +2, AV = +1, or an AV = −1 by connecting pins 3 and 4 as described in Table 1.
Table 1. Input Connections for all 3 Gain Possibilities
INPUT CONNECTIONS
GAIN AV
Non-Inverting
Ground
Inverting
Input Signal
NC (Open)
Ground
−1 V/V
+1 V/V
+2 V/V
Input Signal
Input Signal
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The gain of the LMH6739 is accurate to ±1% and stable over temperature. The internal gain setting resistors, RF
and RG, match very well. However, over process and temperature their absolute value will change. Using
external resistors in series with RG to change the gain will result in poor gain accuracy over temperature and
from part to part.
4
3
R
S
R
OUT
50W
100W
UNCOMPENSATED
V
IN
+
-
2
C
P
R
IN
50W
V
OUT
1
3.3 pF
0
-1
-2
-3
-4
-5
-6
C
= 1.7 pF
P
C
= 3.3 pF
P
-7
-8
V
= 250 mV
10
OUT
PP
100
1000
1
FREQUENCY (MHz)
Figure 24. Correction for Unity Gain Peaking
UNITY GAIN COMPENSATION
Figure 25. Frequency Response for Circuit in
Figure 24
With a current feedback Selectable Gain Buffer like the LMH6739, the feedback resistor is a compromise
between the value needed for stability at unity gain and the optimized value used at a gain of two. The result of
this compromise is substantial peaking at unity gain. If this peaking is undesirable a simple RC filter at the input
of the buffer will smooth the frequency response shown as Figure 24. Figure 25 shows the results of a simple
filter placed on the non-inverting input. See Figure 26 and Figure 27 for another method for reducing unity gain
peaking.
+5V
4
6.8 µF
3
PIN 4 FLOATING
2
0.01 µF
1
0
-1
-2
-3
-4
-5
-6
V
IN
C
POS
+
-
C
SS
0.1 µF
V
OUT
R
IN
PIN 4 SHORTED TO PIN 3
C
NEG
0.01 µF
6.8 µF
V
= 250 mV
PP
OUT
-7 GAIN = +1
-8
1
10
100
1000
FREQUENCY (MHz)
-5V
Figure 26. Alternate Unity Gain Compensation
Figure 27. Frequency Response for Circuit in
Figure 26
X1
R
OUT
51W
+
-
+
-
CL
10 pF
R
R
IN
51W
L
1 kW
Figure 28. Decoupling Capacitive Loads
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DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 28 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The charts “Suggested ROUT vs. Cap Load” give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation
board for the LMH6739.
To reduce parasitic capacitances ground and power planes should be removed near the input and output pins.
Components in the feedback loop should be placed as close to the device as possible. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the
smaller ceramic capacitors should be placed as close to the device as possible. The LMH6739 has multiple
power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass
capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the
supply traces are thin and /or long. In Figure 21 and Figure 22 CSS is optional, but is recommended for best
second harmonic distortion. Another option to using CSS is to use pairs of .01 μF and 0.1 μF ceramic capacitors
for each supply bypass.
VIDEO PERFORMANCE
The LMH6739 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless.
Best performance will be obtained with back terminated loads. The back termination reduces reflections from the
transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier
output stage. Figure 24 shows a typical configuration for driving a 75Ω Cable. The amplifier is configured for a
gain of two to make up for the 6 dB of loss in ROUT
.
2
1.8
1.6
1.4
1.2
1
225 LFPM FORCED AIR
STILL AIR
0.8
0.6
0.4
0.2
0
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
Figure 29. Maximum Power Dissipation
Copyright © 2004–2013, Texas Instruments Incorporated
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LMH6739
SNOSAD2G –MAY 2004–REVISED MARCH 2013
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POWER DISSIPATION
The LMH6739 is optimized for maximum speed and performance in the small form factor of the standard SSOP-
16 package. To achieve its high level of performance, the LMH6739 consumes an appreciable amount of
quiescent current which cannot be neglected when considering the total package power dissipation limit. The
quiescent current contributes to about 40° C rise in junction temperature when no additional heat sink is used (VS
= ±5V, all 3 channels on). Therefore, it is easy to see the need for proper precautions to be taken in order to
make sure the junction temperature’s absolute maximum rating of 150°C is not violated.
To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3
channels).
With the LMH6739 used in a back-terminated 75Ω RGB analog video system (with 2 VPP output voltage), the
total power dissipation is around 435 mW of which 340 mW is due to the quiescent device dissipation (output
black level at 0V). With no additional heat sink used, that puts the junction temperature to about 140° C when
operated at 85°C ambient.
To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An
external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal
(copper) area can be utilized as heat-sink.
An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to
use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is
from the die through the metal lead frame (inside the package) and onto the surrounding copper through the
interconnecting leads. Since high frequency performance requires limited metal near the device pins the best
way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal
conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a
ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination
of front side copper and vias to the back side can be combined as well.
Follow these steps to determine the maximum power dissipation for the LMH6739:
1. Calculate the quiescent (no-load) power:
PAMP = ICC x (VS) VS = V+-V−
(1)
(2)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms ((VS - VOUT)*IOUT
)
where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current
3. Calculate the total RMS power:
PT = PAMP+PD
(3)
The maximum power that the LMH6739 package can dissipate at a given temperature can be derived with the
following equation (See Figure 29):
PMAX = (150º – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction
to ambient, for a given package (°C/W). For the SSOP package θJA is 120°C/W.
ESD PROTECTION
The LMH6739 is protected against electrostatic discharge (ESD) on all pins. The LMH6739 will survive 2000V
Human Body model and 200V Machine model events.
Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions,
however, when the ESD diodes will be evident. If the LMH6739 is driven by a large signal while the device is
powered down the ESD diodes will conduct.
The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through
the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the
power pins to each other will prevent the chip from being powered up through the input.
12
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Product Folder Links: LMH6739
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision F (March 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2004–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6739MQ/NOPB
LMH6739MQX/NOPB
ACTIVE
SSOP
SSOP
DBQ
16
16
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LH67
39MQ
ACTIVE
DBQ
2500 RoHS & Green
SN
LH67
39MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6739MQX/NOPB
SSOP
DBQ
16
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
LMH6739MQX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6739MQ/NOPB
16
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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