LMK00804BQWRGTRQ1 [TI]
汽车类、1.5V 至 3.3V、1 至 4 高性能 LVCMOS 扇出缓冲器和电平转换器 | RGT | 16 | -40 to 125;
| 型号： | LMK00804BQWRGTRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、1.5V 至 3.3V、1 至 4 高性能 LVCMOS 扇出缓冲器和电平转换器 | RGT | 16 | -40 to 125 转换器 电平转换器 |
| 文件： | 总29页 (文件大小：998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
LMK00804B-Q1 1.5V 至 3.3V、1 路至 4 路高性能 LVCMOS 扇出缓冲器
和电平转换器
1 特性
•
封装：16 引脚 VQFN
1
•
下列性能符合 AEC-Q100 标准：
器件温度等级 1：–40°C 至 +125°C，TA
2 应用
–
•
高级驾驶辅助系统 (ADAS)
•
支持 1.5V 至 3.3V 电平范围的四路
LVCMOS/LVTTL 输出
–
–
–
前向式远距离雷达
中等/短距离雷达
超短距离雷达
–
附加抖动：在 40MHz 时为 0.1ps RMS（典型
值）
–
本底噪声：在 40MHz 时为 –168dBc/Hz（典型
值）
3 说明
LMK00804B-Q1 是一款高性能时钟扇出缓冲器和电平
转换器，通过可接受差动或单端输入的两个可选输入之
一提供最多四种 LVCMOS/LVTTL 输出（3.3V、
2.5V、1.8V 或 1.5V 电平）。时钟使能输入在内部同
步，以便在时钟使能端子被置为有效或无效时，消除输
出上的欠幅脉冲或毛刺脉冲。禁用时钟后，输出将保持
逻辑低电平状态。LMK00804B-Q1 也能在四个收发器
之间分配低抖动时钟，并提高级联毫米波雷达系统中的
总体目标检测率和分辨率。
–
–
–
输出频率：350MHz（最大值）
输出偏斜：35ps（最大值）
器件间偏移：550ps（最大值）
•
两个可选输入
–
CLK_P、CLK_N 组合可接受 LVPECL、
LVDS、HCSL、SSTL、LVHSTL 或
LVCMOS/LVTTL
–
LVCMOS_CLK 可接受 LVCMOS/LVTTL
•
•
同步时钟使能端
核心/输出电源：
器件信息(1)
–
–
–
–
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
器件型号
封装
VQFN (16)
封装尺寸（标称值）
LMK00804B-Q1
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS784
LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
9.3 Do's and Don'ts....................................................... 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Supply Characteristics ................................... 5
6.6 LVCMOS / LVTTL DC Electrical Characteristics ...... 6
6.7 Differential Input DC Electrical Characteristics ......... 6
6.8 Switching Characteristics.......................................... 7
6.9 Pin Characteristics .................................................... 7
6.10 Typical Characteristics............................................ 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 18
10.1 Power Supply Considerations............................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 接收文档更新通知 ................................................. 20
12.3 社区资源................................................................ 20
12.4 商标....................................................................... 20
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2019) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
将器件间偏移最大值从 700ps 更改为 550ps .......................................................................................................................... 1
将前置远距离雷达应用更改为前向式远距离雷达 .................................................................................................................... 1
更改了简化原理图 图示........................................................................................................................................................... 1
Changed pin 2 in the RGT package from: OE to: NC ........................................................................................................... 3
Changed the pin descriptions................................................................................................................................................. 3
Changed Changed CDM ESD ratings from: +/-250 V to: +/-750 V........................................................................................ 4
Added the Typical Characteristics section back to the data sheet......................................................................................... 8
Changed Differential Input Level timing diagram .................................................................................................................. 9
Changed the Overview section ............................................................................................................................................ 10
Changed Functional Block Diagram..................................................................................................................................... 10
Added the Typical Connection Diagram............................................................................................................................... 12
Changed the Power Considerations section to Power Dissipation Calculations.................................................................. 16
Moved the Thermal Management section to Do's and Don'ts.............................................................................................. 16
Changed the recommendations for unused output pins ..................................................................................................... 17
Changed the Input Slew Rate Considerations section......................................................................................................... 17
Added content to the Ground Planes section....................................................................................................................... 18
Changed the Layout Example section.................................................................................................................................. 19
Changes from Original (March 2019) to Revision A
Page
•
将数据表状态从“预告信息”更改为“生产数据” ......................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
LMK00804B-Q1
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ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
5 Pin Configuration and Functions
RGT Package
16-Pin VQFN
Top View
GND
NC
1
2
3
4
12
11
10
9
Q2
VDDO
Q3
Thermal
Pad
VDD
CLK_EN
GND
Not to scale
Pin Functions(1)
PIN
TYPE(2)
DESCRIPTION
NAME
NO.
Synchronous clock enable input. CLK_EN must be held low until a valid
reference clock is provided. Typically connected to VDD with an external
1-kΩ pullup. When unused, leave floating.
CLK_EN
4
I, PU
0 = Outputs are forced to logic low state
1 = Outputs are enabled with LVCMOS/LVTTL levels
Inverting differential clock input with internal 51-kΩ (typ) pullup resistor to
VDD and internal 51-kΩ (typ) pulldown resistor to GND. Typically
connected to the inverting clock input. When unused, leave floating.
Internally biased to VDD/2 when left floating.
CLK_N
6
5
7
I, PD, PU
I, PD
Noninverting differential clock input with internal 51-kΩ (typ) pulldown
resistor to GND. Typically connected to the noninverting clock input. A
single-ended clock input can also be connected to CLK_P. When unused,
leave floating.
CLK_P
Clock select input. Typically connected to VDD with an external 1-kΩ
pullup. When unused, leave floating.
0 = Select LVCMOS_CLK (pin 8)
CLK_SEL
I, PU
1 = Select CLK_P, CLK_N (pins 5, 6)
GND
1, 9, 13
8
G
Power supply ground.
Single-ended clock input with internal 51-kΩ (typ) pulldown resistor to
GND. Typically connected to a single-ended clock input. When unused,
leave floating. Accepts LVCMOS/LVTTL levels.
LVCMOS_CLK
I, PD
NC
NC
Q0
Q1
Q2
Q3
2
No connect pin. Typically left floating. Do not connect to GND.
16
14
12
10
Single-ended clock outputs with LVCMOS/LVTTL levels at 7-Ω output
impedance. Typically connected to a receiver with a 43-Ω series
termination. When unused, leave floating.
O
(1) See Recommendations for Unused Input and Output Pins, if applicable.
(2) G = Ground, I = Input, O = Output, P = Power, PU = 51-kΩ pullup, PD = 51-kΩ pulldown. NC = No connect
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Pin Functions(1) (continued)
PIN
TYPE(2)
DESCRIPTION
NAME
NO.
Power supply terminal. Typically connected to a 3.3-V supply. The VDD
pin is typically connected GND with an external 0.1-uF capacitor.
VDD
3
P
Output supply terminals. Typically connected to a 3.3-V, 2.5-V, 1.8-V, or
1.5-V supply. The VDDO pins are typically connected GND with external
0.1-uF capacitors.
VDDO
11, 15
P
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
3.6
UNIT
V
VDD
Supply input voltage
Supply output voltage
VDDO
3.6
V
VDD
+ 0.3
Input voltage
Input voltage
CLK_EN, CLK_SEL, CLK_P, CLK_N, LVCMOS_CLK
Q0, Q1, Q2, Q3
–0.3
–0.3
V
V
VI
VDDO
+ 0.3
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3.135
3.135
2.375
1.71
NOM
3.3
MAX
3.465
3.465
2.625
1.89
UNIT
VDD
Supply input voltage
Supply output voltage
V
3.3
2.5
VDDO
V
1.8
1.425
–40
1.5
1.575
125
TA
Ambient temperature
°C
°C
TJ
Junction temperature
–40
135
fOUT
Maximum output frequency(1)
350
MHz
(1) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.
4
Copyright © 2019, Texas Instruments Incorporated
LMK00804B-Q1
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ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
6.4 Thermal Information
LMK00804B-Q1
THERMAL METRIC(1)(2)
RGT (VQFN)
16 PINS
48.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
58.6
Junction-to-board thermal resistance
22.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
ψJB
22.6
RθJC(bot)
6.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).
6.5 Power Supply Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
Power supply current through VDD
Power supply current through VDDO
MIN
TYP
MAX
21
UNIT
mA
IDD
IDDO
5
mA
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6.6 LVCMOS / LVTTL DC Electrical Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD
UNIT
CLK_EN,
CLK_SEL
+
2
V
0.3
VIH
VIL
IIH
Input high voltage
VDD
+
LVCMOS_CLK
2
V
V
0.3
CLK_EN,
CLK_SEL
–0.3
–0.3
0.8
1.3
15
Input low voltage
Input high current
LVCMOS_CLK
CLK_EN,
CLK_SEL
VIH = VDD
µA
µA
VDD = 3.465 V,
VIN = 3.465 V
LVCMOS_CLK
150
CLK_EN,
CLK_SEL
VIL = GND
–150
–150
IIL
Input low current
VDD = 3.465 V,
VIN = 0 V
LVCMOS_CLK
VDDO = 3.3 V ± 5%
VDDO = 2.5 V ± 5%
VDDO = 1.8 V ± 5%
VDDO = 1.5 V ± 5%
VDDO = 3.3 V ± 5%
VDDO = 2.5 V ± 5%
VDDO = 1.8 V ± 5%
VDDO = 1.5 V ± 5%
2.64
2
VOH
Output high voltage(1)
V
1.44
1.2
0.66
0.5
VOL
Output low voltage(1)
V
0.36
0.3
IOZL
IOZH
Output Hi-Z current low
Output Hi-Z current high
–5
µA
5
(1) Outputs terminated with 50 Ω to VDDO/2.
6.7 Differential Input DC Electrical Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID
VIC
Differential input voltage swing, (VIH – VIL)(1)
0.15
1.4
V
VDD
–
Input common-mode voltage(1)(2)
Input high current(3)
0.5
V
0.85
VDD = 3.465 V,
VIN = 3.465 V
IIH
IIL
CLK_N, CLK_P
CLK_N, CLK_P
150
µA
µA
VDD = 3.465 V ,
VIN = 0 V
Input low current(3)
–150
(1) VIL should not be less than –0.3 V.
(2) Input common-mode voltage is defined as VIH
.
(3) For IIH and IIL measurements on CLK_Por CLK_N, one must comply with VID and VIC specifications by using the appropriate bias on
CLK_N or CLK.
6
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LMK00804B-Q1
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ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
6.8 Switching Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
LVCMOS_CLK(1)
CLK_P/CLK_N(2)
MIN
TYP
MAX
UNIT
Propagation delay,
Low-to-high
,
tPDLH
–40°C to 125°C
1
2.5
ns
tSK(O)
tSK(PP)
tR/tF
Output skew(3)(4)
Part-to-part skew(4)(5)
Output rise/fall time
Measured on rising edge
20% to 80%, CL= 5 pF
35
550
600
ps
ps
ps
100
310
115
f = 40 MHz,
Input slew rate = 1.25 V/ns,
tJIT
Additive jitter(6)
200 fs RMS
12-kHz to 20-MHz integration band
10-kHz offset
–151
–160
–162
–162
–162
100-kHz offset
1-MHz offset
10-MHz offset
20-MHz offset
f = 40 MHz,
Input slew rate = 1.25
V/ns
PNFLOOR
Phase noise floor(7)
dBc/Hz
REF = CLK_P/CLK_N, 50% input duty cycle, f <
166 MHz
45%
42%
55%
58%
DO
Output duty cycle
REF = LVCMOS_CLK, 50% input duty cycle, f >
166 MHz
(1) Measured from the VDD/2 of the input to the VDDO/2 of the output.
(2) Measured from the differential input crossing point to VDDO/2 of the output.
(3) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.
(4) Parameter is defined in accordance with JEDEC Standard 65.
(5) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, various supply voltages,
operating at the same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
(6) Buffer additive jitter: tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE2), where t JIT_SYS is the RMS jitter of the system output (source+buffer) and
tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter
should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the
case for high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source
and measurement details.
(7) Buffer phase noise floor: PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)], where PNSYSTEM is the phase noise
floor of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should
be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for
high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and
measurement details.
6.9 Pin Characteristics
MIN
TYP
1
MAX
UNIT
pF
CI
Input capacitance
RPU
RPD
CPD
ROUT
Input pullup resistance
51
51
2
kΩ
kΩ
pF
Input pulldown resistance
Power dissipation capacitance (per output)
Output impedance
7
Ω
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6.10 Typical Characteristics
ICCO vs. Temperature
Propagation Delay vs. Temeprature
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
VCCO = 3.3V
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
1.6
1.55
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
D001
D002
图 1. Propagation Delay vs. Temperature and Supply
图 2. ICCO vs. Temperature and Supply Voltage
Voltage
ICC vs. Temperature
Additive Jitter vs. Temperature
18.6
140
130
120
110
100
90
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
18.55
18.5
18.45
18.4
18.35
18.3
18.25
18.2
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
80
18.15
70
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
D003
D004
图 3. ICC vs. Temperature and Supply Voltage
图 4. Additive Jitter vs. Temperature and Supply Voltage
8
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ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
7 Parameter Measurement Information
NOTE: VCM = VIC – VID/2 = (V IH + VIL)/2
图 5. Differential Input Level
space
VOH
VOUT
VOL
80%
20%
Q
tR
tF
图 6. Output Voltage, and Rise and Fall Times
space
LVCMOS
Input
LVCMOS_CLK
CLK_N
CLK_P
Differential
Input
tPD
LVCMOS
Outputx
Qx
Qy
tSK
LVCMOS
Outputy
图 7. Output Skew and Propagation Delay
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8 Detailed Description
8.1 Overview
The LMK00804B-Q1 is a clock fan-out buffer with two selectable clock inputs and four LVCMOS outputs. The
LVCMOS_CLK input accepts a single-ended clock input, and the CLK_P/CLK_N input accepts a differential or
single-ended clock input. The LMK00804B-Q1 has a synchronous clock enable feature that allows the device to
synchronously enable or disable the outputs using the CLK_EN pin.
8.2 Functional Block Diagram
10
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LMK00804B-Q1
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ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
8.3 Feature Description
8.3.1 Clock Enable Timing
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in
图 8.
LVCMOS_CLK
CLK_N
CLK_P
Disabled
Enabled
CLK_EN
Qx
图 8. Clock Enable Timing Diagram
8.4 Device Functional Modes
The device can provide fan-out and level translation from a differential or single-ended input to a
LVCMOS/LVTTL output where the output VOH and VOL levels are applied to the VDDO pin and output load
condition.
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9 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMK00804B-Q1 enables the distribution of up to four LVCMOS copies of a low-noise source designed for
general-purpose and high-performance applications. For best jitter performance, TI recommends to use the
appropriate matching networks for the clock driver and receiver format, as detailed in the Typical Applications
section. Practice good high-speed layout design outlined in the High-speed Layout Guidelines application report
(SCAA082).
The LMK00804B-Q1 is designed to drive 50-Ω controlled-impedance traces. TI recommends to design these
clock traces as 50-Ω, single-ended controlled impedance traces. Use a series 43-Ω resistor at the clock outputs
Q[3:0] to match the driver impedance and series resistance to the trace impedance.
9.2 Typical Applications
Refer to the following sections for output clock and input clock interface circuits.
43O
VDDO [11]
VDDO [15]
[16] Q0
[14] Q1
[12] Q2
[10] Q3
10µF
10µF
1µF
1µF
0.1µF
0.1µF
43O
43O
43O
LVCMOS
Clock Outputs
VDD [3]
10µF
1µF
0.1µF
CLK_P [5]
Differential
Clock Input
100O
CLK_N [6]
Single-Ended
Clock Input
LVCMOS_CLK [8]
[1] GND
[9] GND
NC [2]
CLK_EN [4]
CLK_SEL [7]
[13] GND
[17] GND
图 9. Typical Connection Diagram
12
版权 © 2019, Texas Instruments Incorporated
LMK00804B-Q1
www.ti.com.cn
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
Typical Applications (接下页)
9.2.1 Output Clock Interface Circuit
VDDO
RS= 43Ω
LVCMOS
Input
Zo = 50Ω
LMK00804
Parasitic Input Capacitance
图 10. LVCMOS Output Configuration
9.2.1.1 Design Requirements
For high-performance devices, limitations of the equipment can affect phase-noise measurements. The noise
floor of the equipment is often higher than the noise floor of the device. The real noise floor of the device is
probably lower. It is important to understand that system-level phase noise measured at the DUT output is
influenced by the input source and the measurement equipment.
For 图 11 and system-level phase noise plots, a Rohde & Schwarz SMA100A low-noise signal generator was
cascaded with an Agilent 70429A K95 single-ended-to-differential converter block with ultra-low phase noise and
fast-edge slew rate (>3 V/ns) to provide a low-noise clock input source to the LMK00804B-Q1. An Agilent E5052
source signal analyzer with an ultra-low measurement noise floor was used to measure the phase noise of the
input source (SMA100A + 70429A K95) and system output (input source + LMK00804B-Q1). The light blue trace
shows the input source phase noise, and the dark blue trace in 图 11 shows the system output phase noise.
版权 © 2019, Texas Instruments Incorporated
13
LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Typical Applications (接下页)
9.2.1.2 Detailed Design Procedure
Use 公式 1 to calculate the additive phase noise or noise floor of the buffer (PNFLOOR):
PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)]
where
•
•
PNSYSTEM is the phase noise of the system output (source+buffer)
PNSOURCE is the phase noise of the input source
(1)
(2)
Use 公式 2 to calculate the additive jitter of the buffer (tJIT):
2
tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE
)
where:
•
•
tJIT_SYS is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz
tJIT_SOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz
9.2.1.3 Application Curve
9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
图 11. 40-MHz Input Phase Noise (181 fs rms, Light Blue),
and Output Phase Noise (196 fs rms, Dark Blue),
Additive Jitter = 77 fs rms
14
版权 © 2019, Texas Instruments Incorporated
LMK00804B-Q1
www.ti.com.cn
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
Typical Applications (接下页)
9.2.2 Input Detail
LMK00804
LVCMOS_CLK
51k
51k
CLK_P
VDD
51k
CLK_N
51k
图 12. Clock Input Components
9.2.3 Input Clock Interface Circuits
3.3V
3.3 V
LMK00804B
R
s
LVMOS
_CLK
Z
= 50Ω
Z
o
o
Clock generator:
+ R = 50Ω
Z
o
s
图 13. LVCMOS_CLK Input Configuration
3.3V
3.3V
3.3V
3.3V
LMK00804B
R = 100Ω
R = 1kΩ
R
s
CLK_P
DUT
CLK_N
Z
= 50Ω
Z
o
o
R = 100Ω
R = 1kΩ
C = 0.1µF
Clock generator:
+ R = 50Ω
Z
o
s
(1) The Thevenin/split termination values (R = 100 Ω) at the CLK_P input may be adjusted to provide a small differential
offset voltage (50 mV, for example) between the CLK_P and CLK_N inputs to prevent input chatter if the LVCMOS
driver in a tri-state condition. For example, the engineer can use 105 Ω 1% to the 3.3-V rail and 97.6 Ω 1% to GND to
receive a –60-mV offset voltage (VCLK_N – VCLK_P) . Ensure a logic low state if the LVCMOS driver enters a tri-state
condition.
图 14. Single-Ended/LVCMOS Input DC Configuration
版权 © 2019, Texas Instruments Incorporated
15
LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
9.3 Do's and Don'ts
9.3.1 Power Dissipation Calculations
The following power considerations refer to the device-consumed power consumption only. The device power
consumption is the sum of static and dynamic power. The dynamic power usage consists of two components:
•
•
Power used by the device as it switches states
Power required to charge any output load
The output load can be capacitive-only or capacitive and resistive. Use 公式 3 through 公式 5 to calculate the
power consumption of the device:
PDev = Pstat + Pdyn + PCload
(3)
(4)
Pstat = (IDD × VDD) + (IDDO × VDDO
)
Pdyn + PCload = (IDDO,dyn + IDDO,Cload) × VDDO
where:
•
•
IDDO,dyn = CPD × VDDO × f × n [mA]
IDDO,Cload = Cload × VDDO × f × n [mA]
(5)
Example for power consumption of the LMK00804B-Q1: 4 outputs are switching, f = 100 MHz,
VDD = VDDO = 3.465 V and assuming Cload = 5 pF per output:
PDev = 90 mW + 34 mW = 124 mW
(6)
(7)
Pstat = (21 mA × 3.465 V) + (5 mA × 3.465 V) = 90 mW
Pdyn + PCload = (2.8 mA + 6.9 mA) × 3.465 V = 34 mW
IDD,dyn = 2 pF × 3.465 V × 100 MHz × 4 = 2.8 mA
IDD,Cload = 5 pF × 3.465 V × 100 MHz × 4 = 6.9 mA
(8)
(9)
(10)
注
For dimensioning the power supply, consider the total power consumption. The total
power consumption is the sum of device power consumption and the power consumption
of the load.
9.3.2 Thermal Management
For reliability and performance reasons, limit the die temperature to a maximum of 125°C. That is, as an
estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125°C.
Assuming the conditions in the Power Dissipation Calculations section and operating at an ambient temperature
of 70°C with all outputs loaded, 公式 11 shows the estimate of the LMK00804B-Q1 junction temperature:
TJ = TA + PTotal × RθJA = 70°C + (124 mW × 48°C/W) = 70°C + 6.0°C = 76.0°C
(11)
Here are some recommendations to improve heat flow away from the die:
•
•
•
Use multi-layer boards
Specify a higher copper thickness for the board
Increase the number of vias from the top level ground plane under and around the device to internal layers
and to the bottom layer with as much copper area flow on each level as possible
•
•
Apply air flow
Leave unused outputs floating
16
版权 © 2019, Texas Instruments Incorporated
LMK00804B-Q1
www.ti.com.cn
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
Do's and Don'ts (接下页)
9.3.3 Recommendations for Unused Input and Output Pins
•
CLK_SEL and CLK_EN: CLK_EN must be held low until a valid reference clock is provided before the
engineer can use the pin to enable the outputs. These inputs both have an internal pullup (PU) according to
表 1. 表 1 shows the default floating state of these inputs:
表 1. Input Floating Default States
INPUT
CLK_SEL
CLK_EN
FLOATING STATE SELECTION
CLK_P/CLK_N selected
Synchronous outputs enable
•
CLK_P/CLK_N Inputs: See 图 12 for the internal connections. When using a single-ended input, take note of
the internal pullup and pulldown to make sure the unused input is properly biased. To interface a single-
ended input to the CLK_P/CLK_N input, the configuration shown in 图 14 is recommended.
•
•
LVCMOS_CLK Input: See 图 12 for the internal connection. The internal pulldown (PD) resistor ensures a
low state when this input is left floating.
Outputs: Any unused output may be left floating.
9.3.4 Input Slew Rate Considerations
LMK00804B-Q1 employs high-speed and low-latency circuit topology to allow ultra-low additive jitter/phase noise
and high-frequency operation. To take advantage of these benefits in the system application, it is optimal for the
input signal to have a high slew rate of 3 V/ns or greater. Driving the input with a slower slew rate can degrade
the additive jitter and noise floor performance. For this reason, a differential signal input is recommended over a
single-ended signal, because a differential signal typically provides a higher slew rate and common-mode-
rejection.
版权 © 2019, Texas Instruments Incorporated
17
LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
10 Power Supply Recommendations
10.1 Power Supply Considerations
While there is no strict power supply sequencing requirement, it is generally best practice to sequence the supply
input voltage (VDD) before the supply output voltage (VDDO).
10.1.1 Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
The use of bypass capacitors eliminates the low-frequency noise from power supply, because they can provide a
very low-impedance path for high-frequency noise and guard the power-supply system against induced
fluctuations. The bypass capacitors also provide instantaneous current surges as required by the device, and
should have low ESR. To use the bypass capacitors properly, place them close to the power supply terminals
and lay out traces with short loops to minimize inductance. TI recommends that the engineer add as many high-
frequency (for example, 0.1-µF) bypass capacitors as there are supply terminals in the package. TI recommends
that the engineer insert a ferrite bead between the board power supply and the chip power supply to isolate the
high-frequency switching noises generated by the clock driver. This would prevent leakage into the board supply.
It is important to choose an appropriate ferrite bead with low DC resistance, because the bead must provide
adequate isolation between the board supply and the chip supply. It is also important to maintain a voltage at the
supply terminals that is greater than the minimum voltage required for proper operation.
图 15. Power-Supply Decoupling
11 Layout
11.1 Layout Guidelines
11.1.1 Ground Planes
Solid ground planes are recommended because these planes provide a low-impedance return paths between the
device and bypass capacitors, along with the clock source and destination devices.
LMK00804B-Q1 has a die attach pad (DAP) for enhanced thermal and electrical performance. Use five VIAs to
connect the DAP to a solid GND plane. Full-through VIAs are preferred.
Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and
so forth) from passing through the local ground of the device to minimize noise coupling. Remember that noise
coupling can lead to added jitter and spurious noise.
11.1.2 Power Supply Pins
Follow the power supply schematic and layout example described in Power-Supply Filtering.
18
版权 © 2019, Texas Instruments Incorporated
LMK00804B-Q1
www.ti.com.cn
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
Layout Guidelines (接下页)
11.1.3 Differential Input Termination
•
•
Place input termination or biasing resistors as close to the CLK_P/CLK_N pins as possible.
Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities. Intra-pair skew should
also be minimized on the differential input traces.
•
If not used, CLK_P/CLK_N inputs may be left as no connect.
11.1.4 LVCMOS Input Termination
•
Input termination is not necessary when the LVCMOS_CLK input is driven from a LVCMOS driver that is
series-terminated to match the characteristic impedance of the trace. Otherwise, place the input termination
resistor as close to the LVCMOS_CLK input as possible.
•
•
Avoid or minimize vias in the 50-Ω input trace to minimize impedance discontinuities.
If not used, LVCMOS_CLK input may be left as no connect.
11.1.5 Output Termination
•
•
•
Place 43-Ω series termination resistors close to the Qx outputs at the launch of the 50-Ω traces.
Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities.
If not used, any Qx output should be left as no connect.
11.2 Layout Example
图 16 shows the recommended PCB design for good electrical and thermal performance. To maximize the heat
dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be
incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure
adequate heat conduction to of the package. Refer to the Example Board Layout in the Package Option
Addendum.
图 16. General PCB Ground Layout for Thermal Reliability
版权 © 2019, Texas Instruments Incorporated
19
LMK00804B-Q1
ZHCSJG9B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
《高速布局指南》 (SCAA082)
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK00804BQWRGTRQ1
LMK00804BQWRGTTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
16
16
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
804BQ
804BQ
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK00804BQWRGTRQ1 VQFN
LMK00804BQWRGTTQ1 VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK00804BQWRGTRQ1
LMK00804BQWRGTTQ1
VQFN
VQFN
RGT
RGT
16
16
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016J
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
A
-
A
4
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.66 0.1
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
A
A
17
1.5
1
12
0.3
16X
0.2
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4224573/B 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.66)
SYMM
13
16
16X (0.6)
12
1
16X (0.25)
SYMM
17
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224573/B 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.25)
17
SYMM
(2.8)
METAL
ALL AROUND
12X (0.5)
9
4
5
8
(R0.05) TYP
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
THERMAL PAD 17:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4224573/B 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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