LMK03033CISQX/NOPB [TI]
具有集成 VCO 的 1843 至 2160MHz、800FS RMS 抖动、精密时钟调节器 | RHS | 48 | -40 to 85;
| 型号： | LMK03033CISQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成 VCO 的 1843 至 2160MHz、800FS RMS 抖动、精密时钟调节器 | RHS | 48 | -40 to 85 时钟 调节器 |
| 文件： | 总45页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
LMK03000 Family Precision Clock Conditioner with Integrated VCO
Check for Samples: LMK03000, LMK03000C, LMK03000D, LMK03001, LMK03001C, LMK03001D, LMK03033, LMK03033C
1 FEATURES
12
• Integrated VCO with Very Low Phase Noise
Floor
• Integrated Integer-N PLL with Outstanding
Normalized Phase Noise Contribution of -224
dBc/Hz
• VCO Divider Values of 2 to 8 (All Divides)
• Channel Divider Values of 1, 2 to 510 (even
divides)
• Partially Integrated Loop Filter
• Dedicated Divider and Delay Blocks on Each
Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
• 200 fs RMS Clock Generator Performance (10
Hz to 20 MHz) with a Clean Input Clock
• LVDS and LVPECL Clock Outputs
1.1 TARGET APPLICATIONS
VCO
•
•
•
•
•
•
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Wireless Infrastructure
Medical
Device
Outputs
Tuning Range
(MHz)
RMS Jitter
(fs)
LMK03000C
LMK03000
LMK03000D
LMK03001C
LMK03001
LMK03001D
LMK03033C
LMK03033
400
800
1185 - 1296
Test and Measurement
Military / Aerospace
1200
400
3 LVDS
5 LVPECL
1470 - 1570
1843 - 2160
800
1200
500
4 LVDS
4 LVPECL
800
CLKout0
CLKout1
CLKout4
CLKout7
Recovered
—dirty“ clock or
clean clock
Serializer/
Deserializer
LMK0300xx
Precision Clock
Conditioner
OSCin
LMX2531
PLL+VCO
FPGA
Fout
> 1 Gsps
Multiple —clean“ clocks at
different frequencies
DAC
ADC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
1.2 DESCRIPTION
The LMK03000 family of precision clock conditioners combine the functions of jitter
cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a
Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO
Divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a
programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple
integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking
devices in the same family.
1
2
3
FEATURES ............................................... 1
1.1 TARGET APPLICATIONS ........................... 1
1.2 DESCRIPTION ...................................... 2
Device Information ...................................... 3
2.1 Functional Block Diagram ........................... 3
2.2 Connection Diagram ................................. 4
Electrical Specifications ............................... 6
3.1 Absolute Maximum Ratings .......................... 6
3.2 Recommended Operating Conditions ............... 6
3.3 Package Thermal Resistance ....................... 6
3.4 Electrical Characteristics ............................ 7
3.5 Serial Data Timing Diagram ........................ 11
Measurement Definitions ............................ 12
6.10 POWER ON RESET ............................... 17
6.11 DIGITAL LOCK DETECT ........................... 18
General Programming Information ................ 19
7
7.1
RECOMMENDED PROGRAMMING SEQUENCE . 19
7.2 REGISTER R0 to R7 ............................... 22
7.3 REGISTER R8 ..................................... 24
7.4 REGISTER R9 ...................................... 24
7.5 REGISTER R11 .................................... 24
7.6 REGISTER R13 .................................... 24
7.7 REGISTER R14 .................................... 25
7.8 REGISTER R15 .................................... 27
Application Information .............................. 28
8.1 SYSTEM LEVEL DIAGRAM ........................ 28
8.2 BIAS PIN ........................................... 28
8.3 LDO BYPASS ...................................... 28
8.4 LOOP FILTER ...................................... 29
8
4
4.1
Charge Pump Current Specification Definitions .... 12
5
6
Typical Performance Characteristics ............. 13
Functional Description ............................... 15
6.1 BIAS PIN ........................................... 15
6.2 LDO BYPASS ...................................... 15
8.5
CURRENT CONSUMPTION / POWER
DISSIPATION CALCULATIONS ................... 30
8.6 THERMAL MANAGEMENT ........................ 31
6.3
OSCILLATOR INPUT PORT (OSCin, OSCin*) .... 15
LOW NOISE, FULLY INTEGRATED VCO ......... 15
8.7
TERMINATION AND USE OF CLOCK OUTPUTS
6.4
(DRIVERS) ......................................... 32
6.5 CLKout DELAYS ................................... 15
6.6 LVDS/LVPECL OUTPUTS ......................... 16
8.8 OSCin INPUT ...................................... 36
8.9
MORE THAN EIGHT OUTPUTS WITH AN
6.7
GLOBAL CLOCK OUTPUT SYNCHRONIZATION 16
LMK03000 FAMILY DEVICE ....................... 37
Revision History ............................................ 38
6.8 CLKout OUTPUT STATES ......................... 17
6.9
GLOBAL OUTPUT ENABLE AND LOCK DETECT 17
2
Contents
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
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SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
2 Device Information
2.1 Functional Block Diagram
Partially
Internal
VCO
Integrated
Loop Filter
OSCin
OSCin*
R Divider
Phase
Detector
Fout
N Divider
VCO
Divider
Distribution
Path
CLKout0
CLKout0*
CLKout4
CLKout4*
Mux
Mux
Mux
Mux
Divider
Divider
Divider
Divider
Divider
Mux
Mux
Mux
Mux
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
CLKout1
CLKout1*
CLKout5
CLKout5*
Divider
Divider
Divider
CLKout2
CLKout2*
CLKout6
CLKout6*
CLKout3
CLKout3*
CLKout7
CLKout7*
Low Clock Buffers
High Clock Buffers
CLK
GOE
LD
mWire
Port
Control
Registers
Device
Control
DATA
LE
SYNC*
Copyright © 2006–2013, Texas Instruments Incorporated
Device Information
3
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
2.2 Connection Diagram
48
47
46
45
44
43
42
41
40
39
38
37
GND
Fout
1
2
36
35
34
33
32
31
30
29
28
27
26
25
Bias
NC
Vcc1
3
NC
CLKuWire
DATAuWire
LEuWire
NC
4
Vcc10
CPout
Vcc9
Vcc8
OSCin*
OSCin
SYNC*
Vcc7
GND
5
6
Top Down View
7
Vcc2
8
LDObyp1
LDObyp2
GOE
9
10
11
12
DAP
LD
13
14
15
16
17
18
19
20
21
22
23
24
Figure 2-1. 48-Pin WQFN Package
4
Device Information
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
Table 2-1. PIN DESCRIPTIONS
Pin #
Pin Name
GND
I/O
-
Description
1, 25
2
Ground
Fout
O
Internal VCO Frequency Output
3, 8, 13, 16, 19, 22,
26, 30, 31, 33, 37,
40, 43, 46
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10,
Vcc11, Vcc12, Vcc13, Vcc14
-
Power Supply
4
5
CLKuWire
DATAuWire
LEuWire
I
I
MICROWIRE Clock Input
MICROWIRE Data Input
MICROWIRE Latch Enable Input
No Connection to these pins
LDO Bypass
6
I
7, 34, 35
9, 10
11
NC
-
LDObyp1, LDObyp2
GOE
-
I
Global Output Enable
12
LD
O
O
O
O
Lock Detect and Test Output
LVDS Clock Output 0
14, 15
17, 18
20, 21
CLKout0, CLKout0*
CLKout1, CLKout1*
CLKout2, CLKout2*
LVDS Clock Output 1
LVDS Clock Output 2
Clock Output 3
23, 24
CLKout3, CLKout3*
O
(LVDS for LMK03033C/LMK03033
LVPECL for all other parts)
27
SYNC*
I
I
Global Clock Output Synchronization
Oscillator Clock Input; Should be AC
coupled
28, 29
OSCin, OSCin*
32
CPout
O
I
Charge Pump Output
Bias Bypass
36
Bias
38, 39
41, 42
44, 45
47, 48
DAP
CLKout4, CLKout4*
CLKout5, CLKout5*
CLKout6, CLKout6*
CLKout7, CLKout7*
DAP
O
O
O
O
-
LVPECL Clock Output 4
LVPECL Clock Output 5
LVPECL Clock Output 6
LVPECLClock Output 7
Die Attach Pad is Ground
Copyright © 2006–2013, Texas Instruments Incorporated
Device Information
5
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LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
3 Electrical Specifications
3.1 Absolute Maximum Ratings(1)(2)(3)
Parameter
Power Supply Voltage
Symbol
VCC
VIN
Ratings
-0.3 to 3.6
-0.3 to (VCC + 0.3)
-65 to 150
+260
Units
V
Input Voltage
V
Storage Temperature Range
Lead Temperature (solder 4 s)
Junction Temperature
TSTG
TL
°C
°C
°C
TJ
125
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
3.2 Recommended Operating Conditions
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
Min
-40
Typ
25
Max
85
Units
°C
VCC
3.15
3.3
3.45
V
3.3 Package Thermal Resistance
Package
θJA
27.4° C/W
θJ-PAD (Thermal Pad)
(1)
48-Lead WQFN
5.8° C/W
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in
the board layout.
6
Electrical Specifications
Copyright © 2006–2013, Texas Instruments Incorporated
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LMK03001C, LMK03001D, LMK03033, LMK03033C
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SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
(1)
3.4 Electrical Characteristics
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol
Parameter
Conditions
Current Consumption
Min
Typ
Max
Units
Entire device; one LVDS and one
LVPECL clock enabled; no divide; no
delay.
161.8
(2)
ICC
Power Supply Current
mA
mA
Entire device; All Outputs Off (no
emitter resistors placed)
86
1
ICCPD
Power Down Current
POWERDOWN = 1
Reference Oscillator
Reference Oscillator Input Frequency
Range for Square Wave
fOSCinsquare
VOSCinsquare
1
200
1.6
MHz
Vpp
AC coupled; Differential (VOD
)
Square Wave Input Voltage for OSCin
and OSCin*
0.2
PLL
fPD
Phase Detector Frequency
40
MHz
µA
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
0.5 V < VCPout < Vcc - 0.5 V
100
400
ISRCECPout
Charge Pump Source Current
1600
3200
-100
-400
-1600
-3200
2
ISINKCPout
Charge Pump Sink Current
µA
ICPoutTRI
Charge Pump TRI-STATE Current
10
nA
%
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
VCPout = Vcc / 2
TA = 25°C
ICPout%MIS
3
4
4
Magnitude of Charge Pump
Current vs. Charge Pump Voltage
Variation
0.5 V < VCPout < Vcc - 0.5 V
TA = 25°C
ICPoutVTUNE
%
Magnitude of Charge Pump Current vs.
Temperature Variation
ICPoutTEMP
PN10kHz
%
(3)
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
-117
-122
-219
-224
PLL 1/f Noise at 10 kHz Offset
Normalized to 1 GHz Output Frequency
dBc/Hz
Normalized Phase Noise Contribution
PN1Hz
dBc/Hz
(4)
(1) The Electrical Characteristics table lists ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) See Section 8.5 for more current consumption / power dissipation calculation information.
(3) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(4) A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined
as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a
1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure
LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid
a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if
a low power or noisy source is used.
Copyright © 2006–2013, Texas Instruments Incorporated
Electrical Specifications
7
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LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
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Electrical Characteristics (1) (continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MHz
°C
VCO
LMK03000C/LMK03000/LMK03000D 1185
LMK03001C/LMK03001/LMK03001D 1470
1296
1570
2160
fFout
VCO Tuning Range
LMK03033C/LMK03033
1843
After programming R15 for lock, no
changes to output configuration are
permitted to ensure continuous lock.
Allowable Temperature Drift for
Continuous Lock
|ΔTCL
|
125
(1)
LMK03000C/LMK03000/LMK03000D;
TA = 25 °C
3.3
2.7
Output Power to a 50 Ω load driven by
Fout
pFout
LMK03001C/LMK03001/LMK03001D;
TA = 25 °C
dBm
(2)
LMK03033C/LMK03033;TA = 25 °C
LMK03000C/LMK03000/LMK03000D
LMK03001C/LMK03001/LMK03001D
-5 to 0
7 to 9
9 to 11
(3)
KVCO
Fine Tuning Sensitivity
MHz/V
14 to
26
LMK03033C/LMK03033
LMK03000C/LMK03001C
LMK03000/LMK03001
LMK03000D/LMK03001D
LMK03033C
400
800
Fout RMS Period Jitter
(12 kHz to 20 MHz bandwidth)
JRMSFout
1200
500
fs
LMK03033
800
(1) Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient
temperature and programmed state at which the device was when register R15 was programmed. The action of programming the R15
register, even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire
frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to
reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature the device was initially programmed
at, the ambient temperature can never drift outside the range of -40 °C ≤ TA ≤ 85 °C without violating specifications. For this
specification to be valid, the programmed state of the device must not change after R15 is programmed.
(2) Output power varies as a function of frequency. When a range is shown, the higher output power applies to the lower frequency and the
lower output power applies to the higher frequency.
(3) The lower sensitivity indicates the typical sensitivity at the lower end of the tuning range, the higher sensitivity at the higher end of the
tuning range
8
Electrical Specifications
Copyright © 2006–2013, Texas Instruments Incorporated
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LMK03033C
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LMK03001C, LMK03001D, LMK03033, LMK03033C
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SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
Electrical Characteristics (1) (continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCO (Continued)
10 kHz Offset
-91.4
-116.8
-137.8
-156.9
-93.5
-118.5
-139.4
-158.4
-89.6
-115.2
-136.5
-156.0
-91.6
-116.0
-137.9
-156.2
-83
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
LMK03000C
fFout = 1296 MHz
(1)
(1)
(1)
(1)
(1)
(1)
LMK03000C
fFout = 1185 MHz
LMK03001C
fFout = 1570 MHz
L(f)Fout
Fout Single Side Band Phase Noise
dBc/Hz
LMK03001C
fFout = 1470 MHz
-109
LMK03033C
fFout = 2160 MHz
-131
-152
-86
-111
LMK03033C
fFout = 1843 MHz
-134
-153
(1) VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the
phase noise typically varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over
temperature, the phase noise typically varies by 1 to 2 dB, assuming the device is not reprogrammed. Reprogramming R15 will run the
frequency calibration routine for optimum phase noise.
Copyright © 2006–2013, Texas Instruments Incorporated
Electrical Specifications
9
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LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (1) (continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Distribution Section (1) (2) - LVDS Clock Outputs
CLKoutX_MUX
= Bypass (no
divide or delay)
20
RL = 100 Ω
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
(1)
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV
= 4
JitterADD
Additive RMS Jitter
fs
75
Equal loading and identical clock
configuration
(3)
tSKEW
CLKoutX to CLKoutY
-30
±4
30
ps
RL = 100 Ω
VOD
Differential Output Voltage
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
250
-50
350
450
50
mV
mV
V
Change in magnitude of VOD for
complementary output states
ΔVOD
VOS
Output Offset Voltage
1.070
-35
1.25
1.370
35
Change in magnitude of VOS for
complementary output states
ΔVOS
mV
ISA
ISB
Clock Output Short Circuit Current
single-ended
Single-ended outputs shorted to GND
Complementary outputs tied together
-24
-12
24
12
mA
mA
Clock Output Short Circuit Current
differential
ISAB
Clock Distribution Section (1) (2)- LVPECL Clock Outputs
CLKoutX_MUX
= Bypass (no
divide or delay)
20
75
±3
RL = 100 Ω
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
(1)
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV
= 4
JitterADD
Additive RMS Jitter
fs
Equal loading and identical clock
configuration
(3)
tSKEW
CLKoutX to CLKoutY
-30
30
ps
V
Termination = 50 Ω to Vcc - 2 V
Vcc -
0.98
VOH
Output High Voltage
Output Low Voltage
Termination = 50 Ω to Vcc - 2 V
Vcc -
1.8
VOL
VOD
V
Differential Output Voltage
RL = 100 Ω
660
2.0
810
965
mV
(4)
Digital LVTTL Interfaces
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Vcc
0.8
5.0
5.0
V
V
VIH = Vcc
VIL = 0
-5.0
µA
µA
IIL
-40.0
Vcc -
0.4
VOH
VOL
High-Level Output Voltage
Low-Level Output Voltage
IOH = +500 µA
IOL = -500 µA
V
V
0.4
(1) The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications
apply to the clock distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO.
(2) For CLKout frequencies above 1 GHz, the delay should be limited to one half of a period. For 1 GHz and below, the maximum delay can
be used.
(3) Specification is ensured by characterization and is not tested in production.
(4) Applies to GOE, LD, and SYNC*.
10
Electrical Specifications
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Electrical Characteristics (1) (continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
Digital MICROWIRE Interfaces
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
1.6
Vcc
0.4
5.0
5.0
V
V
VIH = Vcc
VIL = 0
-5.0
-5.0
µA
µA
IIL
MICROWIRE Timing
tCS
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
See Data Input Timing
25
8
ns
ns
ns
ns
ns
ns
ns
tCH
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
tCWH
tCWL
tES
25
25
25
25
25
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
tCES
tEWH
(1) Applies to CLKuWire, DATAuWire, and LEuWire.
3.5 Serial Data Timing Diagram
MSB
LSB
A0
DATAuWire
CLKuWire
LEuWire
D27
D26
D25
D24
D23
D0
A3
A2
A1
t
t
CWH
CS
t
t
ES
t
CH
CES
t
CWL
t
EWH
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of
the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to
the addressed register determined by the LSB bits. After the programming is complete the CLKuWire,
DATAuWire, and LEuWire signals should be returned to a low state. It is recommended that the slew rate
of CLKuWire, DATAuWire, and LEuWire should be at least 30 V/µs.
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Electrical Specifications
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4 Measurement Definitions
4.1 Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
4.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
4.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
4.1.3 Charge Pump Output Current Magnitude Variation vs. Temperature
12
Measurement Definitions
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5 Typical Performance Characteristics
NOTE
These plots show performance at frequencies beyond what the part is ensured to operate at to give
the user an idea of the capabilities of the part, but they do not imply any sort of ensured
specification.
1000
1000
Vboost = 1
900
900
800
700
600
500
800
700
600
500
Vboost = 0
Vboost = 1
400
300
400
300
Vboost = 0
200
100
0
200
100
0
0
200 400 600 800 10001200140016001800 2000
FREQUENCY (MHz)
0
200 400 600 800 10001200140016001800 2000
FREQUENCY (MHz)
Figure 5-1. LVDS Differential Output Voltage (VOD
)
Figure 5-2. LVPECL Differential Output Voltage (VOD)
-146
-148
-146
-148
Vboost = 0
-150
Vboost = 0
-150
-152
-154
-156
-152
-154
-156
Vboost = 1
-158
-158
Vboost = 1
-160
-160
0
200 400 600 800 10001200140016001800 2000
FREQUENCY (MHz)
0
200 400 600 800 10001200140016001800 2000
FREQUENCY (MHz)
To estimate this noise, only the output frequency is required. Divide
To estimate this noise, only the output frequency is required. Divide
value and input frequency are not integral.
Figure 5-3. LVDS Output Buffer Noise Floor
value and input frequency are not integral.
Figure 5-4. LVPECL Output Buffer Noise Floor
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Typical Performance Characteristics
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-135
Delay = 2250 ps
Delay=1800 ps
-140
-145
-150
-155
-160
-165
-170
Delay = 900 ps
Delay = 450 ps
Delay = 0 ps
10
100
1000
FREQUENCY (MHz)
To estimate this noise, only the output frequency is required. Divide value and input frequency are not integral.
The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor due to the distribution
section accounting for the delay nise can be calculated as: Total Output Noise = 10 × log(10Output Buffer Noise/10 + 10Delay Noise Floor/10).
Figure 5-5. Delay Noise Floor (Adds to Output Noise Floor)
14
Typical Performance Characteristics
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6 Functional Description
The LMK03000 family of precision clock conditioners combine the functions of jitter
cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a
Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks.
The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious
performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop
filter bandwidths.
The LMK03000 family has multiple options for VCO frequencies. The VCO output is optionally accessible
on the Fout port. Internally, the VCO output goes through an VCO Divider to feed the various clock
distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a
programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple
integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking
devices in the same family.
6.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This
is important for low noise performance.
6.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a
0.1 µF capacitor.
6.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference signal. Due to an internal DC bias the OSCin
port should be AC coupled, refer to the Section 8.1 in the Section 8 section. The OSCin port may be
driven single-endedly by AC grounding OSCin* with a 0.1 µF capacitor.
6.4 LOW NOISE, FULLY INTEGRATED VCO
The LMK03000 family of devices contain a fully integrated VCO. In order for proper operation the VCO
uses a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the
R15 register is programmed. Once R15 is programmed the temperature may not drift more than the
maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not ensured to stay in lock.
For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15
is programmed.
6.5 CLKout DELAYS
Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY)
support a 150 ps step size and range from 0 to 2250 ps of total delay.
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Functional Description
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6.6 LVDS/LVPECL OUTPUTS
By default all the clock outputs are disabled until programmed.
Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the
outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global
to 0.
The duty cycle of the LVDS and LVPECL clock outputs are shown in the table below.
VCO_DIV
CLKoutX_MUX
Divided, or Divided and Delayed
Any
Duty Cycle
50%
Any
2, 4, 6, 8
50%
3
5
7
Bypassed, or Delayed
Bypassed, or Delayed
Bypassed, or Delayed
33%
40%
43%
6.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the
divided outputs are also held in a logic low state. The bypassed outputs will continue to operate normally.
Shortly after the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a
high state simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the
bypassed state are not affected by SYNC* and are always synchronized with the divided outputs.
The SYNC* pin must be held low for greater than one clock cycle of the output of the VCO Divider, also
known as the distribution path. Once this low event has been registered, the outputs will not reflect the low
state for four more cycles. This means that the outputs will be low on the fifth rising edge of the
distribution path. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously
transition high until four more distribution path clock cycles have passed, which is the fifth rising edge of
the distribution path. See the timing diagram in Figure 6-1 for further detail. The clocks are programmed
as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided,
and CLKout2_DIV = 4. To synchronize the outputs, after the low SYNC* event has been registered, it is
not required to wait for the outputs to go low before SYNC* is set high.
Distribution
Path
SYNC*
CLKout0
CLKout1
CLKout2
Figure 6-1. SYNC* Timing Diagram
The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the
SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not
used, clock output synchronization is not ensured.
16
Functional Description
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6.8 CLKout OUTPUT STATES
Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable
control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit
(EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or
EN_CLKout_Global is set to 0.
CLKoutX_EN bit
EN_CLKout_Global bit
GOE pin
CLKoutX Output State
1
1
Low
Low
Off
Don't care
0
Don't care
1
Don't care
0
1
Don't care
Off
High / No Connect
Enabled
When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an
LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.
6.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
The GOE pin provides an internal pull-up resistor as shown on the functional block diagram. If it is not
terminated externally, the clock output states are determined by the Clock Output Enable bits
(CLKoutX_EN) and the EN_CLKout_Global bit.
By programming the PLL_MUX register to Digital Lock Detect Active High, the Lock Detect (LD) pin can
be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not
locked.
6.10 POWER ON RESET
When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit
sets all registers to their default values, see the Section 7 section for more information on default register
values. Voltage should be applied to all Vcc pins simultaneously.
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Functional Description
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6.11 DIGITAL LOCK DETECT
The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase
detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε
RC delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ.
To indicate an out of lock state, the phase error must become greater δ. The values of ε and δ are shown
in the table below:
ε
δ
10 ns
20 ns
To utilize the digital lock detect feature, PLL_MUX must be programmed for "Digital Lock Detect (Active
High)" or "Digital Lock Detect (Active Low)." When one of these modes is programmed the state of the LD
pin will be set high or low as determined by the description above as shown in Figure 6-2.
When the device is in power down mode and the LD pin is programmed for a digital lock detect function,
LD will show a "no lock detected" condition which is low or high given active high or active low circuitry
respectively.
The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4
word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to
divide the comparison frequency presented to the lock detect circuit by 4.
NO
NO
YES
YES
Lock Detected =
False
START
Phase Error < g
Phase Error < g
NO
NO
NO
YES
Phase Error > *
NO
YES
YES
YES
Lock Detected =
True
Phase Error < g
Phase Error < g
Phase Error < g
Figure 6-2. Digital Lock Detect Flowchart
18
Functional Description
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7 General Programming Information
The LMK03000 family of devices are programmed using several 32-bit registers which control the device's
operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0]
form the address field. The remaining 28 bits form the data field DATA[27:0].
During programming, LEuWire is low and serial data is clocked in on the rising edge of CLKuWire (MSB
first). When LE goes high, data is transferred to the register bank selected by the address field. Only
registers R0 to R7, R11, and R13 to R15 need to be programmed for proper device operation.
For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15
is programmed. Any changes to the PLL R divider or OSCin require R15 to be programmed again to
activate the frequency calibration routine.
7.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to
ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed
again, the reset bit is programmed clear (RESET = 0). Registers are programmed in order with R15 being
the last register programmed. An example programming sequence is shown below.
•
Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the
reset bit is set in R0, the other R0 bits are ignored.
–
If R0 is programmed again, the reset bit is programmed clear (RESET = 0).
•
Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay
settings.
•
•
•
•
•
Program R8 for optimum phase noise performance.
Program R9 with Vboost setting if necessary. Optional, only needed to set Vboost = 1.
Program R11 with DIV4 setting if necessary.
Program R13 with oscillator input frequency and internal loop filter values
Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and
PLL R divider.
•
Program R15 with PLL charge pump gain, VCO divider, and PLL N divider. Also starts frequency
calibration routine.
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General Programming Information
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Table 7-1. REGISTER MAP
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Data [27:0]
A3 A2 A1 A0
CLKout0
_MUX
[1:0]
CLKout0_DIV
[7:0]
CLKout0_DLY
[3:0]
R0
R1
R2
R3
R4
R5
R6
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CLKout1
_MUX
[1:0]
CLKout1_DIV
[7:0]
CLKout1_DLY
[3:0]
0
0
0
0
0
0
CLKout2
_MUX
[1:0]
CLKout2_DIV
[7:0]
CLKout2_DLY
[3:0]
CLKout3
_MUX
[1:0]
CLKout3_DIV
[7:0]
CLKout3_DLY
[3:0]
CLKout4
_MUX
[1:0]
CLKout4_DIV
[7:0]
CLKout4_DLY
[3:0]
CLKout5
_MUX
[1:0]
CLKout5_DIV
[7:0]
CLKout5_DLY
[3:0]
CLKout6
_MUX
[1:0]
CLKout6_DIV
[7:0]
CLKout6_DLY
[3:0]
CLKout7
_MUX
[1:0]
CLKout7_DIV
[7:0]
CLKout7_DLY
[3:0]
R7
R8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
20
General Programming Information
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Table 7-1. REGISTER MAP (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R9
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
1
R11
R13
0
0
0
DIV4
0
0
0
VCO_
R4_LF
[2:0]
VCO_
R3_LF
[2:0]
VCO_
C3_C4_LF
[3:0]
OSCin_FREQ
[7:0]
PLL_MUX
[3:0]
PLL_R
[11:0]
R14
R15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
PLL_
CP_
GAIN
[1:0]
VCO_DIV
[3:0]
PLL_N
[17:0]
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7.2 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1
controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the
functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be from 0 to 7.
Table 7-2. Default Register Settings after Power on Reset
Default
Bit Value
Bit
Location
Bit Name
Bit State
Bit Description
Register
RESET
0
0
No reset, normal operation
Bypassed
Reset to power on defaults
CLKoutX mux mode
R0
31
18:17
16
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
Vboost
0
Disabled
CLKoutX enable
R0 to R7
1
Divide by 2
CLKoutX clock divide
CLKoutX clock delay
Output Power Control
Phase Detector Frequency
OSCin Frequency in MHz
R4 internal loop filter values
R3 internal loop filter values
C3 and C4 internal loop filter values
Fout enable
15:8
7:4
0
0 ps
0
Normal Mode
PDF ≤ 20 MHz
10 MHz OSCin
Low (~200 Ω)
Low (~600 Ω)
C3 = 0 pF, C4 = 10 pF
Fout disabled
Normal - CLKouts normal
Normal - Device active
Disabled
R9
16
DIV4
0
R11
15
OSCin_FREQ
VCO_R4_LF
VCO_R3_LF
VCO_C3_C4_LF
EN_Fout
10
0
21:14
13:11
10:8
7:4
R13
0
0
0
28
EN_CLKout_Global
POWERDOWN
PLL_MUX
1
Global clock output enable
Device power down
27
0
R14
R15
26
0
Multiplexer control for LD pin
PLL R divide value
23:20
19:8
31:30
29:26
25:8
PLL_R
10
0
R divider = 10
100 µA
PLL_CP_GAIN
VCO_DIV
Charge pump current
VCO divide value
2
Divide by 2
PLL_N
760
N divider = 760
PLL N divide value
7.2.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting
this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this
bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its
proper values and RESET = 0.
7.2.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock output. Changing between the different
modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode.
The different MUX modes and associated delays are listed below.
CLKoutX_MUX[1:0]
Mode
Bypassed (default)
Divided
Added Delay Relative to Bypass Mode
0
1
0 ps
100 ps
400 ps
2
3
Delayed
(In addition to the programmed delay)
500 ps
Divided and Delayed
(In addition to the programmed delay)
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7.2.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for these dividers to be active, the respective
CLKoutX_MUX bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are
programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned. The
Clock Output Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock
Output Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is
incurred.
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.
CLKoutX_DIV[7:0]
Clock Output Divider value
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
1
1
.
0
0
1
1
0
0
.
0
1
0
1
0
1
.
Invalid
2 (default)
4
6
8
10
...
1
1
1
1
1
1
1
1
510
7.2.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In order for these delays to be active, the
respective CLKoutX_MUX (See Section 7.2.2) bit must be set to either "Delayed" or "Divided and
Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is
incurred in addition to the delay shown in the table below.
CLKoutX_DLY[3:0]
Delay (ps)
0 (default)
150
0
1
2
300
3
450
4
600
5
750
6
900
7
1050
1200
1350
1500
1650
1800
1950
2100
2250
8
9
10
11
12
13
14
15
7.2.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See
Section 7.7.4) is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all
clock outputs will be disabled.
CLKoutX_EN bit
Conditions
CLKoutX State
Disabled (default)
Enabled
0
1
EN_CLKout_Global bit = 1
GOE pin = High / No Connect
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7.3 REGISTER R8
The programming of register R8 provides optimum phase noise performance.
7.4 REGISTER R9
The programming of register R9 is optional. If it is not programmed the bit Vboost will be defaulted to 0,
which is the test condition for all electrical characteristics.
7.4.1 Vboost -- Voltage Boost
By enabling this bit, the voltage output levels for all clock outputs is increased. Also, the noise floor is
improved
Vboost
Typical LVDS Voltage Output (mV)
Typical LVPECL Voltage Output (mV)
0
1
350
390
810
865
7.5 REGISTER R11
This register only has one bit and only needs to be programmed in the case that the phase detector
frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to
the correct values.
7.5.1 DIV4 -- High Phase Detector Frequencies and Lock Detect
This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a
reliable output from the digital lock detect output in the case of a phase detector frequency frequency
greater than 20 MHz.
DIV4
Digital Lock Detect Circuitry Mode
Not divided
0
Phase Detector Frequency ≤ 20 MHz (default)
Divided by 4
Phase Detector Frequency > 20 MHz
1
7.6 REGISTER R13
7.6.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4
These bits control the capacitor values for C3 and C4 in the internal loop filter.
Loop Filter Capacitors
VCO_C3_C4_LF[3:0]
C3 (pF)
C4 (pF)
10 (default)
60
0
0 (default)
1
0
2
50
10
3
0
110
4
50
110
5
100
0
110
6
160
7
50
160
8
9
100
100
150
150
10
60
10
110
11
60
12 to 15
Invalid
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7.6.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3
These bits control the R3 resistor value in the internal loop filter. The recommended setting for
VCO_R3_LF[2:0] = 0 for optimum phase noise and jitter.
VCO_R3_LF[2:0]
R3 Value (kΩ)
0
Low (~600 Ω) (default)
1
10
20
2
3
30
4
40
5 to 7
Invalid
7.6.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4
These bits control the R4 resistor value in the internal loop filter. The recommended setting for
VCO_R4_LF[2:0] = 0 for optimum phase noise and jitter.
VCO_R4_LF[2:0]
R4 Value (kΩ)
0
Low (~200 Ω) (default)
1
10
20
2
3
30
4
40
5 to 7
Invalid
7.6.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment
These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral
multiple of 1 MHz, then round to the closest value.
OSCin_FREQ[7:0]
OSCin Frequency
1
1 MHz
2 MHz
2
...
10
...
10 MHz (default)
...
...
200
200 MHz
Invalid
201 to 255
7.7 REGISTER R14
7.7.1 PLL_R[11:0] -- R Divider Value
These bits program the PLL R Divider and are programmed in binary fashion. Any changes to PLL_R
require R15 to be programmed again to active the frequency calibration routine.
PLL_R[11:0]
PLL R Divide Value
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
Invalid
1
2
...
10 (default)
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
4095
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7.7.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below lists several different modes.
PLL_MUX[3:0]
Output Type
LD Pin Function
Disabled (default)
Logic High
0
1
2
3
4
5
Hi-Z
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Logic Low
Digital Lock Detect (Active High)
Digital Lock Detect (Active Low)
Analog Lock Detect
Open Drain
NMOS
6
7
Analog Lock Detect
Analog Lock Detect
Open Drain
PMOS
8
9
Invalid
Invalid
Invalid
Push-Pull
Push-Pull
N Divider Output/2 (50% Duty Cycle)
R Divider Output/2 (50% Duty Cycle)
10
11
12 to 15
7.7.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers down the entire device and all blocks,
regardless of the state of any of the other bits or pins.
POWERDOWN bit
Mode
0
1
Normal Operation (default)
Entire Device Powered Down
7.7.4 EN_CLKout_Global bit -- Global Clock Output Enable
This bit overrides the individual CLKoutX_EN bits. When this bit is set to 0, all clock outputs are disabled,
regardless of the state of any of the other bits or pins.
EN_CLKout_Global bit
Clock Outputs
0
1
All Off
Normal Operation (default)
7.7.5 EN_Fout bit -- Fout port enable
This bit enables the Fout pin.
EN_Fout bit
Fout Pin Status
Disabled (default)
Enabled
0
1
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7.8 REGISTER R15
Programming R15 also activates the frequency calibration routine.
7.8.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and
precedes the PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the
PLL Phase Detector, the total N divide value, NTotal, is also influenced by the VCO Divider value. NTotal
=
PLL N Divider × VCO Divider. The VCO frequency is calculated as, fVCO = fOSCin × PLL N Divider × VCO
Divider / PLL R Divider. Since the PLL N divider is a pure binary counter there are no illegal divide values
for PLL_N[17:0] except for 0.
PLL_N[17:0]
PLL N Divider Value
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Invalid
1
...
760 (default)
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
1
.
1
.
1
.
1
.
0
.
0
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
262143
7.8.2 VCO_DIV[3:0] -- VCO Divider
These bits program the divide value for the VCO Divider. The VCO Divider follows the VCO output and
precedes the clock distribution blocks. Since the VCO Divider is in the feedback path from the VCO to the
PLL phase detector the VCO Divider contributes to the total N divide value, NTotal. NTotal = PLL N Divider ×
VCO Divider. The VCO Divider can not be bypassed. See Section 7.8.1 for more information on setting
the VCO frequency.
VCO_DIV[3:0]
VCO Divider Value
0
0
0
0
0
0
0
0
1
1
.
0
0
0
0
1
1
1
1
0
0
.
0
0
1
1
0
0
1
1
0
0
.
0
1
0
1
0
1
0
1
0
1
.
Invalid
Invalid
2 (default)
3
4
5
6
7
8
Invalid
...
1
1
1
1
Invalid
7.8.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
PLL_CP_GAIN[1:0]
Charge Pump Gain
0
1
2
3
1x (default)
4x
16x
32x
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8 Application Information
8.1 SYSTEM LEVEL DIAGRAM
Vcc
1 mF
0.1 mF
OSCin
CLKout0
CLKout0*
100Ö
CLKout1
CLKout1*
OSCin*
0.1 mF
CLKout2
CLKout2*
LEuWire
CLKuWire
CLKout3
CLKout3*
DATAuWire
CLKout4
CLKout4*
To System
To Host
SYNC*
LMK0300xx
CLKout5
CLKout5*
LD
(optional)
CLKout6
CLKout6*
GOE
LDObyp1
LDObyp2
CLKout7
CLKout7*
10 mF
0.1 mF
Figure 8-1. Typical Application
Figure 8-1 shows an LMK03000 family device used in a typical application. In this setup the clock may be
multiplied, reconditioned, and redistributed. Both the OSCin/OSCin* and CLKoutX/CLKoutX* pins can be
used in a single-ended or a differential fashion, which is discussed later in this datasheet. The GOE pin
needs to be high for the outputs to operate. One technique sometimes used is to take the output of the LD
(Lock Detect) pin and use this as an input to the GOE pin. If this is done, then the outputs will turn off if
lock detect circuit detects that the PLL is out of lock. The loop filter actually consists of seven components,
but four of these components that for the third and fourth poles of the loop filter are integrated in the chip.
The first and second pole of the loop filter are external.
8.2 BIAS PIN
See Section 6.1 for bias pin information.
8.3 LDO BYPASS
See Section 6.2 for LDO bypass information.
28
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8.4 LOOP FILTER
LMK0300xx
R3
R4
Phase
Detector
C3
C4
Internal Loop Filter
C2
C1
External Loop Filter
R2
Figure 8-2. Loop Filter
The internal charge pump is directly connected to the integrated loop filter components. The first and
second pole of the loop filter are externally attached as shown in Figure 8-2. When the loop filter is
designed, it must be stable over the entire frequency band, meaning that the changes in KVtune from the
low to high band specification will not make the loop filter unstable. The design of the loop filter is
application specific and can be rather involved, but is discussed in depth in the Clock Conditioner Owner's
Manual provided by Texas Instruments. When designing with the integrated loop filter of the LMK03000
family, considerations for minimum resistor thermal noise often lead one to the decision to design for the
minimum value for integrated resistors, R3 and R4. Both the integrated loop filter resistors and capacitors
(C3 and C4) also restrict how wide the loop bandwidth the PLL can have. However, these integrated
components do have the advantage that they are closer to the VCO and can therefore filter out some
noise and spurs better than external components. For this reason, a common strategy is to minimize the
internal loop filter resistors and then design for the largest internal capacitor values that permit a wide
enough loop bandwidth. In some situations where spurs requirements are very stringent and there is
margin on phase noise, it might make sense to design for a loop filter with integrated resistor values that
are larger than their minimum value.
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8.5 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS
Due to the myriad of possible configurations the following table serves to provide enough information to
allow the user to calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3
V, TA = 25 °C.
Table 8-1. Block Current Consumption
Power
Current
Consumption at
3.3 V (mA)
Power
Dissipated in
device (mW)
Dissipated in
LVPECL emitter
resistors (mW)
Block
Condition
Entire device,
core current
All outputs off; No LVPECL emitter resistors connected
86.0
9
283.8
29.7
29.7
-
-
-
Low clock buffer
(internal)
The low clock buffer is enabled anytime one of CLKout0
through CLKout3 are enabled
High clock buffer The high clock buffer is enabled anytime one of the
(internal)
9
CLKout4 through CLKout7 are enabled
Fout buffer, EN_Fout = 1
14.5
17.8
47.8
58.7
-
-
LVDS output, Bypassed mode
LVPECL output, Bypassed mode (includes 120 Ω emitter
resistors)
40
17.4
0
72
38.3
0
60
19.1
-
Output buffers
LVPECL output, disabled mode (includes 120 Ω emitter
resistors)
LVPECL output, disabled mode. No emitter resistors
placed; open outputs
Divide enabled, divide = 2
5.3
8.5
17.5
28.0
19.1
32.7
474
-
-
Divide circuitry
per output
Divide enabled, divide > 2
Delay enabled, delay < 8
5.8
-
Delay circuitry per
output
Delay enabled, delay > 7
9.9
-
Entire device
CLKout0 & CLKout4 enabled in Bypassed mode
161.8
60
From Table 8-1 the current consumption can be calculated in any configuration. For example, the current
for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output in Bypassed mode can be
calculated by adding up the following blocks: core current, low clock buffer, high clock buffer, one LVDS
output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output
drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω
resistors which doesn't add to the power dissipation budget for the device. If delays or divides are
switched in, then the additional current for these stages needs to be added as well.
For power dissipated by the device, the total current entering the device is multiplied by the voltage at the
device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no
emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the
case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) operating at 3.3 volts, we calculate 3.3 V × (86 + 9 + 9
+ 17.8 + 40) mA = 3.3 V × 161.8 mA = 533.9 mW. Because the LVPECL output (CLKout4) has the emitter
resistors hooked up and the power dissipated by these resistors is 60 mW, the total device power
dissipation is 533.9 mW - 60 mW = 473.9 mW.
When the LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the
LVPECL Voh & Vol typical specification. Therefore the power dissipated in each emitter resistor is
approximately (1.9 V)2 / 120 Ω = 30 mW. When the LVPECL output is disabled, the emitter resistor
voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120
Ω = 9.5 mW.
30
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
8.6 THERMAL MANAGEMENT
Power consumption of the LMK03000 family of devices can be high enough to require attention to thermal
management. For reliability and performance reasons the die temperature should be limited to a maximum
of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA
should not exceed 125 °C.
The package of the device has an exposed pad that provides the primary heat removal path as well as
excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the
package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB
within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat
conduction out of the package. A recommended land and via pattern is shown in Figure 8-3. More
information on soldering WQFN packages can be obtained at www.ti.com.
5.0 mm, min
0.33 mm, typ
1.2 mm, typ
Figure 8-3. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the
ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on
the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent
corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The
vias shown in Figure 8-3 should connect these top and bottom copper layers and to the ground layer.
These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to
where it can be more effectively dissipated.
Copyright © 2006–2013, Texas Instruments Incorporated
Application Information
31
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
8.7 TERMINATION AND USE OF CLOCK OUTPUTS (DRIVERS)
When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter
performance:
•
•
Transmission line theory should be followed for good impedance matching to prevent reflections.
Clock drivers should be presented with the proper loads. For example:
–
–
LVDS drivers are current drivers and require a closed current loop.
LVPECL drivers are open emitter and require a DC path to ground.
•
Receivers should be presented with a signal biased to their specified DC bias level (common mode
voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the
proper voltage level. In this case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the
above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the
best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage
(common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK03000 family,
OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level,
see Figure 8-1. This is only slightly different from the AC coupled cases described in 3.7.2 because the
DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept
remains the same, which is the receiver (OSCin/OSCin*) set the input to the optimum DC bias voltage
(common mode voltage), not the driver.
8.7.1 Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS
receiver as shown in Figure 8-4. To ensure proper LVDS operation when DC coupling it is recommend to
use LVDS receivers without fail-safe or internal input bias such as DS90LV110T. The LVDS driver will
provide the DC bias level for the LVDS receiver. For operation with LMK03000 family LVDS drivers it is
recommend to use AC coupling with LVDS receivers that have an internal DC bias voltage. Some fail-safe
circuitry will present a DC bias (common mode voltage) which will prevent the LVDS driver from working
correctly. This precaution does not apply to the LVPECL drivers.
CLKoutX
100W Trace
(Differential)
LVDS
Receiver
LVDS
Driver
CLKoutX*
Figure 8-4. Differential LVDS Operation, DC Coupling
32
Application Information
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 8-5.
Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω
resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as
shown in Figure 8-6 for Vcc = 3.3 V.
Vcc - 2 V
CLKoutX
100W Trace
(Differential)
LVPECL
Driver
LVPECL
Receiver
CLKoutX*
Vcc - 2 V
Figure 8-5. Differential LVPECL Operation, DC Coupling
Vcc
CLKoutX
100W Trace
(Differential)
LVPECL
Driver
LVPECL
Receiver
CLKoutX*
Vcc
Figure 8-6. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent
Copyright © 2006–2013, Texas Instruments Incorporated
Application Information
33
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
8.7.2 Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver
standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is
important to ensure the receiver is biased to its ideal DC level.
When driving LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking
capacitors, however the proper DC bias point needs to be established at the receiver. If the receiver does
not automatically bias its input, one way to do this is with the termination circuitry in Figure 8-7.
When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output
due to capacitor charging. Figure 8-7 employs 0.1 µF capacitors. This value may need to be adjusted to
meet the startup requirements for a particular application.
0.1 mF
100W Trace
CLKoutX
(Differential)
LVDS
Receiver
LVDS
Driver
Vbias
CLKoutX*
0.1 mF
Figure 8-7. Differential LVDS Operation, AC Coupling
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter
resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 8-8. For proper
receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by
the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. A
Thevenin equivalent circuit (82 Ω resistor connected to Vcc and a 120 Ω resistor connected to ground with
the driver connected to the junction of the 82 Ω and 120 Ω resistors) is a valid termination as shown in
Figure 8-8 for Vcc = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 8-
6.
Vcc
CLKoutX
0.1 mF
100W Trace
(Differential)
LVPECL
Reciever
LVPECL
Driver
0.1 mF
CLKoutX*
Vcc
Figure 8-8. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent
34
Application Information
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LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
8.7.3 Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into
an unbalanced, single-ended signal.
It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one
of the LMK03000 family clock LVPECL drivers, the termination should still be 50 ohms to Vcc - 2 V as
shown in Figure 8-9. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω
resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) is a
valid termination as shown in Figure 8-10 for Vcc = 3.3 V.
Vcc - 2V
CLKoutX
50W Trace
LVPECL
Driver
Vcc - 2V
Load
CLKoutX*
50W
Figure 8-9. Single-Ended LVPECL Operation, DC Coupling
Vcc
CLKoutX
Vcc
50W Trace
LVPECL
Driver
CLKoutX*
Load
Figure 8-10. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent
When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and
ensure a 50 ohm termination with the proper DC bias level for the receiver. The typical DC bias voltage for
LVPECL receivers is 2 V (See Section 8.7.2). If the other driver is not used it should be terminated with
either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal
can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise
analyzer. When using most RF test equipment no DC bias (0 V DC) is expected for safe and proper
operation. The internal 50 ohm termination the test equipment provides correctly terminates the LVPECL
driver being measured as shown Figure 8-11. When using only one LVPECL driver of
CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver.
a
CLKoutX
50W Trace
0.1 mF
LVPECL
Driver
0.1 mF
CLKoutX*
Load
Figure 8-11. Single-Ended LVPECL Operation, AC Coupling
Copyright © 2006–2013, Texas Instruments Incorporated
Application Information
35
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LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
8.7.4 Conversion to LVCMOS Outputs
To drive an LVCMOS input with an LMK03000 family LVDS or LVPECL output, an LVPECL/LVDS to
LVCMOS converter such as TI's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best
noise performance, LVPECL provides a higher voltage swing into input of the converter.
8.8 OSCin INPUT
In addition to LVDS and LVPECL inputs, OSCin can also be driven with a sine wave. The OSCin input can
be driven single-ended or differentially with sine waves. The configurations for these are shown in
Figure 8-12 and Figure 8-13. Figure 8-14 shows the recommended power level for sine wave operation for
both differential and single-ended sources over frequency. The part will operate at power levels below the
recommended power level, but as power decreases the PLL noise performance will degrade. The VCO
noise performance will remain constant. At the recommended power level the PLL phase noise
degradation from full power operation (8 dBm) is less than 2 dB.
0.1 mF
50W Trace
LMK
Input
Clock Source
0.1 mF
Figure 8-12. Single-Ended Sine Wave Input
0.1 mF
100W Trace
(Differential)
LMK
Input
0.1 mF
Clock Source
Figure 8-13. Differential Sine Wave Input
10
5
0
Minimum Recommended
Power for Single-Ended
Operation
-5
Minimum Recommended
Power for Differential
Operation
-10
-15
-20
20
30
40
60
90
10
50
70
80
100
FREQUENCY (MHz)
Figure 8-14. Recommended OSCin Power for Operation with a Sine Wave Input
36
Application Information
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
8.9 MORE THAN EIGHT OUTPUTS WITH AN LMK03000 FAMILY DEVICE
The LMK03000 family devices include eight or less outputs. When more than 8 outputs are required the
footprint compatible LMK01000 family may be used for clock distribution. By using an LMK03000 device
with eight LMK01000 family devices up to 64 clocks may be distributed in many different LVDS / LVPECL
combinations. It's possible to distribute more than 64 clocks by adding more LMK01000 family devices.
Refer to AN-1864 (literature number SNAA060) for more details on how to do this.
Copyright © 2006–2013, Texas Instruments Incorporated
Application Information
37
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (March 2013) to Revision O
Page
•
Changed layout of National Data Sheet to TI format .......................................................................... 37
38
Application Information
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK03000CISQ/NOPB
LMK03000CISQX/NOPB
LMK03000DISQ/NOPB
LMK03000DISQE/NOPB
LMK03000DISQX/NOPB
LMK03000ISQ/NOPB
LMK03001CISQ/NOPB
LMK03001CISQX/NOPB
LMK03001DISQ/NOPB
LMK03001DISQE/NOPB
LMK03001DISQX/NOPB
LMK03001ISQ/NOPB
LMK03033CISQ/NOPB
LMK03033CISQE/NOPB
LMK03033CISQX/NOPB
LMK03033ISQ/NOPB
LMK03033ISQE/NOPB
LMK03033ISQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
K03000CI
2500 RoHS & Green
1000 RoHS & Green
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
K03000CI
K03000DI
K03000DI
K03000DI
K03000 I
K03001CI
K03001CI
K03001DI
K03001DI
K03001DI
K03001 I
K03033CI
K03033CI
K03033CI
K03033 I
K03033 I
K03033 I
250
RoHS & Green
2500 RoHS & Green
250
250
RoHS & Green
RoHS & Green
2500 RoHS & Green
1000 RoHS & Green
250
2500 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
RoHS & Green
2500 RoHS & Green
1000 RoHS & Green
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK03000CISQ/NOPB
WQFN
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
250
2500
1000
250
178.0
330.0
330.0
178.0
330.0
178.0
178.0
330.0
330.0
178.0
330.0
178.0
330.0
178.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LMK03000CISQX/NOPB WQFN
LMK03000DISQ/NOPB WQFN
LMK03000DISQE/NOPB WQFN
LMK03000DISQX/NOPB WQFN
2500
250
LMK03000ISQ/NOPB
LMK03001CISQ/NOPB
WQFN
WQFN
250
LMK03001CISQX/NOPB WQFN
LMK03001DISQ/NOPB WQFN
2500
1000
250
LMK03001DISQE/NOPB WQFN
LMK03001DISQX/NOPB WQFN
2500
250
LMK03001ISQ/NOPB
LMK03033CISQ/NOPB
WQFN
WQFN
1000
250
LMK03033CISQE/NOPB WQFN
LMK03033CISQX/NOPB WQFN
2500
1000
LMK03033ISQ/NOPB
WQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK03033ISQE/NOPB
LMK03033ISQX/NOPB
WQFN
WQFN
RHS
RHS
48
48
250
178.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.3
1.3
12.0
12.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK03000CISQ/NOPB
LMK03000CISQX/NOPB
LMK03000DISQ/NOPB
LMK03000DISQE/NOPB
LMK03000DISQX/NOPB
LMK03000ISQ/NOPB
LMK03001CISQ/NOPB
LMK03001CISQX/NOPB
LMK03001DISQ/NOPB
LMK03001DISQE/NOPB
LMK03001DISQX/NOPB
LMK03001ISQ/NOPB
LMK03033CISQ/NOPB
LMK03033CISQE/NOPB
LMK03033CISQX/NOPB
LMK03033ISQ/NOPB
LMK03033ISQE/NOPB
LMK03033ISQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
250
2500
1000
250
208.0
356.0
356.0
208.0
356.0
208.0
208.0
356.0
356.0
208.0
356.0
208.0
356.0
208.0
356.0
356.0
208.0
356.0
191.0
356.0
356.0
191.0
356.0
191.0
191.0
356.0
356.0
191.0
356.0
191.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
250
250
2500
1000
250
2500
250
1000
250
2500
1000
250
2500
Pack Materials-Page 3
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