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LMK03806BISQ

更新时间：2024-09-18 11:57:59
品牌：TI
描述：Ultra Low Jitter Clock Generator with 14 Programmable Outputs

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LMK03806BISQ 概述

Ultra Low Jitter Clock Generator with 14 Programmable Outputs 超低抖动时钟发生器，提供14路可编程输出

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LMK03806  
LMK03806 Ultra Low Jitter Clock Generator with 14 Programmable Outputs  
Literature Number: SNAS522E  
November 22, 2011  
LMK03806  
Ultra Low Jitter Clock Generator with 14 Programmable  
Outputs  
1.0 General Description  
3.0 Features  
The LMK03806 is a high performance, ultra low-jitter, multi-  
rate clock generator capable of synthesizing 8 different fre-  
quencies on 14 outputs at frequencies of up to 2.6 GHz. Each  
output clock is programmable in LVDS, LVPECL or LVCMOS  
format. The LMK03806 integrates a high performance inte-  
ger-N PLL, low noise VCO, and programmable output di-  
viders to generate multiple reference clocks for SONET,  
Ethernet, Fiber Channel, XAUI, Backplane, PCIe, SATA and  
Network Processors from a low cost crystal.  
High performance, ultra low jitter clock generator  
■
■
Low Jitter  
< 50 fs jitter (1.875 MHz - 20 MHz) at 312.5 MHz Output  
Frequency  
—
< 150 fs jitter (12 kHz - 20 MHz) at 312.5 MHz Output  
Frequency  
—
Generates multiple clocks from a low cost crystal or  
external clock.  
14 outputs with programmable output format (LVDS,  
LVPECL, CMOS)  
■
■
2.0 Target Applications  
Up to 8 unique output frequencies.  
■
■
■
■
Ultra High Speed Serial Interfaces in SONET/SDH  
■
■
■
■
Industrial Temperature Range: -40 to 85 °C  
Tunable VCO frequency from 2.37 - 2.6 GHz  
Multi-Gigabit Ethernet & Fiber Channel Line Cards  
Base Band Units (BBUs) for RAN applications  
Programmable dividers to generate multiple clocks from a  
low cost crystal.  
GPON OLT/ONU , High Speed Serial Interface such as  
PCIe, XAUI, SATA, SAS  
3.15 V to 3.45 V operation  
■
■
Clocking ADC and DACs  
■
■
Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)  
Clocking DSP, Microprocessors and FPGAs  
30170163  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2011 Texas Instruments Incorporated  
301701  
www.ti.com  
4.0 Common Frequency Plans  
Standard/Application  
Infiniband  
Output Frequencies (MHz)  
VCO Frequency  
Recommended Crystal Value  
100, 200  
75, 150, 300, 600  
37.5, 75, 120, 150  
25  
SATA  
2400 MHz  
SAS  
Fast Ethernet  
1 GbE  
125  
20 MHz  
10 GbE  
156.25, 312.5, 625  
78.125, 156.25, 312.5  
227.27...  
2500 MHz  
XAUI  
Backplane  
2G/4G/16G Fiber Channel  
10G Fiber Channel  
106.25, 212.5  
159.375  
2550 MHz  
2578.125 MHz  
2488.32 MHz  
2457.6 MHz  
644.53125, 322.265625,  
161.1328125  
40/100 GbE  
SONET  
12.5 MHz  
19.44, 38.88, 77.76, 155.52,  
311.04, 622.08  
19.44 MHz  
30.72, 61.44, 122.88, 153.6,  
245.76, 491.52, 983.04  
19.2 MHz or  
12.288 MHz  
A/D Clocking  
5.0 Achievable Frequencies  
By using the tunable range of the VCO followed by a programmable divider, the LMK03806 can achieve any of the frequencies in  
the table below  
Output Divider Value  
Achieved Frequency (MHz)  
1
2370 - 2600  
1185 - 1300  
2
3
790 - 866.7  
4
592.5 - 650  
5
474 - 520  
6
395.7 - 433  
7
338.6 - 371.4  
8
296.25 - 325  
9
10  
263.3 - 288.9  
237 - 260  
11 to 1045  
Any frequency in the range of 2.27 - 236.36  
www.ti.com  
2
6.0 Functional Block Diagrams  
6.1 10 Gigabit Ethernet Reference Clocks  
30170109  
FIGURE 1.  
6.2 Fiber Channel Reference Clocks  
30170110  
FIGURE 2.  
3
www.ti.com  
6.3 SONET/SDH Reference Clocks  
30170111  
FIGURE 3.  
6.4 Detailed LMK03806 Block Diagram  
Figure 4 illustrates the complete LMK03806 block diagram.  
30170101  
FIGURE 4. Detailed LMK03806 Block Diagram  
www.ti.com  
4
 
7.0 Connection Diagram  
64-Pin LLP Package  
30170102  
5
www.ti.com  
8.0 Pin Descriptions  
Pin Number  
Name(s)  
I/O  
Type  
Description  
CLKout0,  
CLKout0*  
1, 2  
O
Programmable  
Clock output 0 (clock group 0).  
CLKout1*,  
CLKout1  
3, 4  
O
-
Programmable  
Do Not Connect  
Clock output 1 (clock group 0).  
5, 7, 8, 9, 25, 26,  
28,29, 34  
NC  
These pins must be left floating. Do NOT ground.  
6
SYNC  
Vcc1  
I
CMOS  
PWR  
Clock synchronization input.  
Power supply for VCO LDO.  
10  
-
LDO Bypass, bypassed to ground with 10 µF  
capacitor.  
11  
12  
LDObyp1  
LDObyp2  
-
-
ANLG  
ANLG  
LDO Bypass, bypassed to ground with a 0.1 µF  
capacitor.  
CLKout2,  
CLKout2*  
13, 14  
15, 16  
17  
O
O
-
Programmable  
Programmable  
PWR  
Clock output 2 (clock group 1).  
Clock output 3 (clock group 1).  
CLKout3*,  
CLKout3  
Power supply for clock group 1: CLKout2 and  
CLKout3.  
Vcc2  
Vcc3  
Power supply for clock group 2: CLKout4 and  
CLKout5.  
18  
-
PWR  
CLKout4,  
CLKout4*  
19, 20  
21, 22  
O
O
Programmable  
Programmable  
Clock output 4 (clock group 2).  
Clock output 5 (clock group 2).  
CLKout5*,  
CLKout5  
23  
24  
27  
30  
GND  
Vcc4  
-
-
PWR  
PWR  
Ground  
Power supply for digital.  
Readback  
Vcc5  
O
-
CMOS  
PWR  
Pin that can be used to readback register information.  
Power supply for clock inputs.  
OSCout1,  
OSCout1*  
31, 32  
O
LVPECL  
Buffered output 1 of OSCin port.  
33  
35  
Ftest/LD  
Vcc6  
O
-
Programmable  
PWR  
Multiplexed Lock Detect and Test output pin.  
Power supply. No bypassing required on this pin.  
Reference input to PLL. Reference input may be:  
A Crystal for use with the internal crystal oscillator  
circuit.  
—
36, 37  
OSCin, OSCin*  
I
ANLG  
A XO, TCXO, or other external clock. Must be AC  
Coupled.  
—
38  
Vcc7  
-
PWR  
Power supply for OSCin port.  
OSCout0,  
OSCout0*  
39, 40  
O
Programmable  
Buffered output 0 of OSCin port.  
41  
42  
43  
44  
45  
46  
Vcc8  
CPout  
-
O
-
PWR  
ANLG  
PWR  
Power supply for PLL charge pump.  
Charge pump output.  
Vcc9  
Power supply for PLL.  
LEuWire  
CLKuWire  
DATAuWire  
I
CMOS  
CMOS  
CMOS  
MICROWIRE Latch Enable Input.  
MICROWIRE Clock Input.  
MICROWIRE Data Input.  
I
I
Power supply for clock group 3: CLKout6 and  
CLKout7.  
47  
Vcc10  
-
PWR  
CLKout6,  
CLKout6*  
48, 49  
O
Programmable  
Clock output 6 (clock group 3).  
www.ti.com  
6
Pin Number  
Name(s)  
I/O  
Type  
Description  
CLKout7*,  
CLKout7  
50, 51  
O
Programmable  
Clock output 7 (clock group 3).  
Power supply for clock group 4: CLKout8 and  
CLKout9.  
52  
Vcc11  
-
PWR  
CLKout8,  
CLKout8*  
53, 54  
55, 56  
57  
O
O
-
Programmable  
Programmable  
PWR  
Clock output 8 (clock group 4).  
Clock output 9 (clock group 4).  
CLKout9*,  
CLKout9  
Power supply for clock group 5: CLKout10 and  
CLKout11.  
Vcc12  
CLKout10,  
CLKout10*  
58, 59  
60, 61  
62, 63  
O
O
O
Programmable  
Programmable  
CMOS  
Clock output 10 (clock group 5).  
Clock output 11 (clock group 5).  
CLKout11*,  
CLKout11  
These pins can be programmed for general purpose  
output.  
GPout0, GPout1  
Power supply for clock group 0: CLKout0 and  
CLKout1.  
64  
Vcc13  
DAP  
-
-
PWR  
GND  
DAP  
DIE ATTACH PAD, connect to GND.  
7
www.ti.com  
9.0 Absolute Maximum Ratings (Note 1, Note 2, Note 3)  
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for  
availability and specifications.  
Parameter  
Supply Voltage (Note 4)  
Symbol  
VCC  
VIN  
Ratings  
Units  
V
-0.3 to 3.6  
-0.3 to (VCC + 0.3)  
Input Voltage  
V
TSTG  
TL  
Storage Temperature Range  
Lead Temperature (solder 4 seconds)  
Junction Temperature  
-65 to 150  
+260  
150  
°C  
°C  
TJ  
°C  
IIN  
Differential Input Current (OSCin/OSCin*)  
Moisture Sensitivity Level  
± 5  
mA  
MSL  
3
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device  
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.  
The guaranteed specifications apply only to the test conditions listed.  
Note 2: This device is a high performance RF integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V  
Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.  
Note 3: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.  
Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure  
to absolute maximum ratings for extended periods can adversely affect device reliability.  
Note 4: Never to exceed 3.6 V.  
10.0 Recommended Operating Conditions  
Parameter  
Symbol  
Condition  
Min  
Typical  
Max  
Unit  
Ambient  
Temperature  
TA  
VCC = 3.3 V  
-40  
25  
85  
°C  
Junction  
Temperature  
TJ  
VCC = 3.3 V  
125  
°C  
V
Supply Voltage  
VCC  
3.15  
3.3  
3.45  
www.ti.com  
8
 
 
 
 
11.0 Electrical Characteristics  
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Junction Temperature TJ ≤ 125 °C. Typical values represent most likely parametric  
norms at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not  
guaranteed.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Current Consumption  
No DC path to ground on OSCout1/1*  
ICC_PD  
Power Down Supply Current  
1
mA  
mA  
(Note 5)  
CLKoutX_Y_DIV = 16,  
CLKoutX_TYPE = 1 (LVDS),  
PLL locked  
Supply Current with all clocks enabled  
ICC_CLKS  
445  
(Note 6)  
External Clock (OSCin) Specifications  
PLL Reference Input  
fOSCin  
SLEWOSCin  
VOSCin  
1
500  
2.4  
MHz  
V/ns  
Vpp  
(Note 8)  
PLL Reference Clock minimum slew  
20% to 80%  
0.15  
0.2  
0.5  
rate on OSCin(Note 13)  
Input Voltage for OSCin or OSCin*  
AC coupled; Single-ended (Unused  
pin AC coupled to GND)  
(Note 13)  
VIDOSCin  
VSSOSCin  
0.2  
0.4  
1.55  
3.1  
|V|  
Differential voltage swing  
AC coupled  
Figure 6  
Vpp  
DC offset voltage between OSCin/  
OSCin*  
VOSCin-offset  
Each pin AC coupled  
20  
mV  
OSCinX* - OSCinX  
EN_PLL_REF_2X = 1;  
OSCin Duty Cycle 40% to 60%  
fdoubler_max  
Doubler input frequency (Note 13)  
155  
MHz  
Crystal Oscillator Mode Specifications  
RESR ≤ 40 Ω  
CL ≤ 20 pF  
16  
6
20.5  
16  
MHz  
MHz  
Crystal Frequency Range  
fXTAL  
(Note 13)  
RESR ≤ 80 Ω  
CL ≤ 22 pF  
Vectron VXB1 crystal, 20.48 MHz,  
RESR ≤ 40 Ω  
CL ≤ 20 pF  
PXTAL  
Crystal Power Dissipation  
120  
6
µW  
pF  
CIN  
Input Capacitance of the OSCin port  
-40 to +85 °C  
9
www.ti.com  
 
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
RMS Jitter Performance  
156.25 MHz, LVDS/LVPECL  
81  
85  
Integration Bandwidth  
10 kHz to 1 MHz  
312.5 MHz, LVDS/LVPECL  
100 MHz, LVDS  
139  
117  
145  
126  
111  
100  
108  
95  
100 MHz, LVPECL  
106.25 MHz, LVDS  
106.25 MHz, LVPECL  
156.25 MHz, LVDS  
156.25 MHz, LVPECL  
312.5 MHz, LVDS  
Integration Bandwidth  
12 kHz to 20 MHz  
XO Mode  
(Note 18)  
(Note 19)  
(Note 20)  
fs  
312.5 MHz, LVPECL  
622.08 MHz, LVDS/LVPECL  
106.25 MHz, LVDS  
106.25 MHz, LVPECL  
156.25 MHz, LVDS  
156.25 MHz, LVPECL  
312.5 MHz, LVDS  
141  
78  
Integration Bandwidth  
637 kHz to 10 MHz  
60  
70  
57  
Integration Bandwidth  
1.875 MHz to 20 MHz  
57  
312.5 MHz, LVPECL  
156.25 MHz, LVDS/LVPECL  
312.5 MHz, LVDS/LVPECL  
100 MHz, LVDS  
43  
190  
200  
235  
210  
280  
250  
200  
195  
220  
190  
255  
90  
Integration Bandwidth  
10 kHz to 1 MHz  
100 MHz, LVPECL  
106.25 MHz, LVDS  
106.25 MHz, LVPECL  
156.25 MHz, LVDS  
156.25 MHz, LVPECL  
312.5 MHz, LVDS  
Integration Bandwidth  
12 kHz to 20 MHz  
Crystal Mode  
Jitter  
(Note 14)  
(Note 15)  
(Note 16)  
fs  
312.5 MHz, LVPECL  
622.08 MHz, LVDS/LVPECL  
106.25 MHz, LVDS  
106.25 MHz, LVPECL  
156.25 MHz, LVDS  
156.25 MHz, LVPECL  
312.5 MHz, LVDS  
Integration Bandwidth  
637 kHz to 10 MHz  
65  
75  
65  
Integration Bandwidth  
1.875 MHz to 20 MHz  
60  
312.5 MHz, LVPECL  
45  
www.ti.com  
10  
Symbol  
Parameter  
Conditions  
Phase Noise Performance  
10 kHz  
Min  
Typ  
Max  
Units  
-142  
-143  
-157  
-159  
-160  
-160  
-161  
-141  
-140  
-156  
-159  
-160  
-162  
-163  
-139  
-140  
-153  
-159  
-159  
-160  
-160  
-132  
-133  
-148  
-154  
-155  
-157  
-158  
-123  
-121  
-143  
-154  
-154  
-157  
-158  
100 kHz  
1 MHz  
100 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 18)  
100 kHz  
1 MHz  
106.25 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 19)  
100 kHz  
1 MHz  
XO Mode Phase  
Noise  
156.25 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
dBc/Hz  
(Note 18)  
100 kHz  
1 MHz  
312.5 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 18)  
100 kHz  
1 MHz  
622.08 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
(Note 20)  
11  
www.ti.com  
Symbol  
Parameter  
Conditions  
10 kHz  
Min  
Typ  
-129  
-137  
-156  
-158  
-159  
-160  
-161  
-124  
-137  
-156  
-158  
-159  
-160  
-161  
-125  
-132  
-153  
-158  
-159  
-160  
-160  
-119  
-126  
-147  
-153  
-154  
-156  
-157  
-110  
-120  
-140  
-153  
-153  
-154  
-154  
Max  
Units  
100 kHz  
1 MHz  
100 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 14)  
100 kHz  
1 MHz  
106.25 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 15)  
100 kHz  
1 MHz  
Crystal Mode  
Phase Noise  
156.25 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
dBc/Hz  
(Note 14)  
100 kHz  
1 MHz  
312.5 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
10 kHz  
(Note 14)  
100 kHz  
1 MHz  
622.08 MHz (LVDS/LVPECL)  
10 MHz (LVDS)  
20 MHz (LVDS)  
10 MHz (LVPECL)  
20 MHz (LVPECL)  
(Note 16)  
www.ti.com  
12  
Symbol  
Parameter  
PLL Phase Detector and Charge Pump Specifications  
Phase Detector Frequency  
Conditions  
Min  
Typ  
Max  
Units  
fPD  
155  
MHz  
VCPout=VCC/2, PLL_CP_GAIN = 0  
VCPout=VCC/2, PLL_CP_GAIN = 1  
VCPout=VCC/2, PLL_CP_GAIN = 2  
VCPout=VCC/2, PLL_CP_GAIN = 3  
VCPout=VCC/2, PLL_CP_GAIN = 0  
VCPout=VCC/2, PLL_CP_GAIN = 1  
VCPout=VCC/2, PLL_CP_GAIN = 2  
VCPout=VCC/2, PLL_CP_GAIN = 3  
VCPout=VCC/2, TA = 25 °C  
100  
400  
ICPoutSOURCE  
PLL Charge Pump Source Current  
µA  
µA  
1600  
3200  
-100  
-400  
-1600  
-3200  
3
ICPoutSINK  
PLL Charge Pump Sink Current  
ICPout%MIS  
ICPoutVTUNE  
Charge Pump Sink/Source Mismatch  
10  
10  
%
%
0.5 V < VCPout < VCC - 0.5 V  
TA = 25 °C  
Magnitude of Charge Pump Current  
vs. Charge Pump Voltage Variation  
4
4
Charge Pump Current vs.  
Temperature Variation  
ICPout%TEMP  
ICPoutTRI  
%
0.5 V < VCPout < VCC - 0.5 V  
PLL_CP_GAIN = 400 µA  
Charge Pump Leakage  
nA  
PLL 1/f Noise at 10 kHz offset  
(Note 9). Normalized to  
1 GHz Output Frequency  
-118  
-121  
PN10kHz  
PN1Hz  
dBc/Hz  
dBc/Hz  
PLL_CP_GAIN = 3200 µA  
PLL_CP_GAIN = 400 µA  
PLL_CP_GAIN = 3200 µA  
1 kHz Offset  
-222.5  
-227  
-93  
Normalized Phase Noise Contribution  
(Note 10)  
PLL Phase Noise  
(Assumes a very wide bandwidth,  
noiseless crystal, 2500 MHz output  
frequency, and 25 MHz phase  
detector frequency)  
10 kHz  
-103  
-116  
L(f)  
dBc/Hz  
100 kHz Offset  
1 MHz Offset  
-116  
Internal VCO Specifications  
fVCO  
VCO Tuning Range  
2370  
2600  
MHz  
Fine Tuning Sensitivity  
(The range displayed in the typical  
column indicates the lower sensitivity  
is typical at the lower end of the tuning  
range, and the higher tuning  
KVCO  
16 to 21  
MHz/V  
sensitivity is typical at the higher end  
of the tuning range).  
After programming R30 for lock, no  
changes to output configuration are  
permitted to guarantee continuous  
lock  
Allowable Temperature Drift for  
Continuous Lock  
|ΔTCL  
|
125  
°C  
(Note 11, Note 13)  
10 kHz Offset  
100 kHz Offset  
1 MHz Offset  
-87  
Phase Noise  
(Assumes a very narrow loop  
bandwidth)  
L(f)  
-112  
-133  
dBc/Hz  
13  
www.ti.com  
Symbol  
Parameter  
Conditions  
Clock Skew  
Min  
Typ  
Max  
Units  
LVDS-to-LVDS, T = 25 °C,  
fCLK = 800 MHz, RL= 100 Ω  
AC coupled  
30  
LVPECL-to-LVPECL,  
T = 25 °C,  
Maximum CLKoutX to CLKoutY  
(Note 12, Note 13)  
fCLK = 800 MHz, RL= 100 Ω  
emitter resistors =  
240 Ω to GND  
|TSKEW  
|
30  
ps  
AC coupled  
RL = 50 Ω, CL = 5 pF,  
T = 25 °C, FCLK = 100 MHz.  
(Note 12)  
Maximum skew between any two  
LVCMOS outputs, same CLKout or  
different CLKout (Note 12, Note 13)  
100  
750  
Same device, T = 25 °C,  
250 MHz  
MixedSKEW  
LVDS or LVPECL to LVCMOS  
ps  
LVDS Clock Outputs (CLKoutX), CLKoutX_TYPE = 1  
Operating Frequency  
(Note 13, Note 17)  
fCLKout  
RL = 100 Ω  
1300  
MHz  
VOD  
VSS  
250  
500  
400  
800  
450  
900  
|mV|  
Differential Output Voltage  
Figure 7  
mVpp  
Change in Magnitude of VOD for  
complementary output states  
T = 25 °C, DC measurement  
AC coupled to receiver input  
R = 100 Ω differential termination  
ΔVOD  
VOS  
-50  
50  
1.375  
35  
mV  
V
Output Offset Voltage  
1.125  
1.25  
200  
Change in VOS for complementary  
output states  
ΔVOS  
|mV|  
Output Rise Time  
Output Fall Time  
20% to 80%, RL = 100 Ω  
80% to 20%, RL = 100 Ω  
TR / TF  
ps  
ISA  
ISB  
Output short circuit current - single- Single-ended output shorted to GND,  
-24  
-12  
24  
12  
mA  
mA  
ended  
T = 25 °C  
Output short circuit current -  
differential  
Complimentary outputs tied together,  
T = 25 °C  
ISAB  
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14  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
LVPECL Clock Outputs (CLKoutX)  
Operating Frequency  
(Note 13, Note 17)  
fCLKout  
1300  
MHz  
20% to 80% Output Rise  
RL = 100 Ω, emitter resistors = 240 Ω  
to GND  
CLKoutX_TYPE = 4 or 5  
(1600 or 2000 mVpp)  
TR / TF  
150  
ps  
80% to 20% Output Fall Time  
700 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 2  
VCC  
-
VOH  
VOL  
Output High Voltage  
V
V
1.03  
T = 25 °C, DC measurement  
Termination = 50 Ω to  
VCC - 1.4 V  
VCC  
-
Output Low Voltage  
1.41  
VOD  
VSS  
305  
610  
380  
760  
440  
880  
|mV|  
Output Voltage  
Figure 7  
mVpp  
1200 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 3  
VCC  
-
VOH  
VOL  
Output High Voltage  
V
V
1.07  
T = 25 °C, DC measurement  
VCC  
-
Output Low Voltage  
Termination = 50 Ω to  
1.69  
VCC - 1.7 V  
VOD  
VSS  
545  
625  
705  
|mV|  
Output Voltage  
Figure 7  
1090  
1250  
1410  
mVpp  
1600 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 4  
VCC  
-
VOH  
VOL  
Output High Voltage  
V
V
1.10  
T = 25 °C, DC Measurement  
VCC  
-
Output Low Voltage  
Termination = 50 Ω to  
1.97  
VCC - 2.0 V  
VOD  
VSS  
660  
870  
965  
|mV|  
Output Voltage  
Figure 7  
1320  
1740  
1930  
mVpp  
2000 mVpp LVPECL (2VPECL) Clock Outputs (CLKoutX), CLKoutX_TYPE = 5  
VCC  
1.13  
VCC  
-
VOH  
VOL  
Output High Voltage  
Output Low Voltage  
V
V
T = 25 °C, DC Measurement  
Termination = 50 Ω to  
VCC - 2.3 V  
-
2.20  
1070  
2140  
VOD  
VSS  
800  
1200  
2400  
|mV|  
Output Voltage  
Figure 7  
1600  
mVpp  
15  
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Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
LVCMOS Clock Outputs (CLKoutX)  
Operating Frequency  
fCLKout  
VOH  
5 pF Load  
250  
MHz  
V
(Note 13)  
VCC  
0.1  
-
Output High Voltage  
1 mA Load  
1 mA Load  
VOL  
IOH  
IOL  
Output Low Voltage  
Output High Current (Source)  
Output Low Current (Sink)  
0.1  
55  
V
VCC = 3.3 V, VO = 1.65 V  
VCC = 3.3 V, VO = 1.65 V  
28  
28  
mA  
mA  
VCC/2 to VCC/2, FCLK = 100 MHz, T =  
25 °C  
Output Duty Cycle  
DUTYCLK  
45  
50  
%
ps  
ps  
(Note 13)  
20% to 80%, RL = 50 Ω,  
TR  
TF  
Output Rise Time  
Output Fall Time  
400  
400  
CL = 5 pF  
80% to 20%, RL = 50 Ω,  
CL = 5 pF  
Digital Outputs (Ftest/LD, Readback, GPoutX)  
VCC  
0.4  
-
VOH  
VOL  
IOH = -500 µA  
High-Level Output Voltage  
Low-Level Output Voltage  
V
V
IOL = 500 µA  
0.4  
Digital Inputs (SYNC)  
VIH  
VIL  
VCC  
0.4  
High-Level Input Voltage  
Low-Level Input Voltage  
1.6  
1.6  
V
V
Digital Inputs (CLKuWire, DATAuWire, LEuWire)  
High-Level Input Voltage  
VIH  
VIL  
IIH  
VCC  
0.4  
25  
5
V
V
Low-Level Input Voltage  
High-Level Input Current  
Low-Level Input Current  
VIH = VCC  
VIL = 0  
5
µA  
µA  
IIL  
-5  
www.ti.com  
16  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
MICROWIRE Interface Timing  
TECS  
TDCS  
TCDH  
TCWH  
TCWL  
TCES  
TEWH  
TCR  
LE to Clock Set Up Time  
Data to Clock Set Up Time  
Clock to Data Hold Time  
Clock Pulse Width High  
Clock Pulse Width Low  
Clock to LE Set Up Time  
LE Pulse Width  
See MICROWIRE Input Timing  
25  
25  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
See MICROWIRE Input Timing  
See MICROWIRE Input Timing  
See MICROWIRE Input Timing  
See MICROWIRE Input Timing  
See MICROWIRE Input Timing  
See MICROWIRE Input Timing  
See MICROWIRE Readback Timing  
25  
25  
25  
25  
25  
Falling Clock to Readback Time  
Note 5: If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase.  
Note 6: Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Section 16.4.1 Current Consumption / Power Dissipation  
Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.  
Note 7: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is  
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the  
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible  
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest  
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.  
Note 8: FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.  
Note 9: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10  
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker  
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade  
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f)  
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of  
LPLL_flicker(f) and LPLL_flat(f).  
Note 10: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) -  
20log(N) - 10log(fPD). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPD is the phase detector frequency  
of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).  
Note 11: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that  
the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a  
frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift  
for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed  
at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.  
Note 12: Equal loading and identical clock output configuration on each clock output is required for specification to be valid.  
Note 13: Guaranteed by characterization.  
Note 14: Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values  
are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re  
=
240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 20 MHz the loop bandwidth = 62 kHz and phase margin =  
76°.  
Note 15: Jitter and phase noise data for 106.25 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2  
= 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler  
disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 32 kHz and phase margin = 69°.  
Note 16: Jitter and phase noise data for 622.08 MHz collected using a Vectron crystal, part number VXB1-1137-15M360. Loop filter values are C1 = 100 pF, C2  
= 120 nF, R2 = 470 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference  
doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 54 kHz and phase margin = 86°.  
Note 17: Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.  
Note 18: Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values  
are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240  
Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 100 MHz the loop bandwidth = 80 kHz and phase margin = 60°.  
Note 19: Jitter and phase noise data for 106.25 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39pF, C2  
= 3.3 nF, R2 = 820Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler  
disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 80 kHz and phase margin = 60°.  
Note 20: Jitter and phase noise data for 622.08 MHz collected using a Crystec oscillator, part number CVHD-950. Loop filter values are C1 = 39 pF, C2 = 3.3  
nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler  
enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 80 kHz and phase margin = 60°.  
17  
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12.0 Measurement Definitions  
12.1 SERIAL MICROWIRE TIMING DIAGRAM AND TERMINOLOGY  
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal.  
On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A few programming  
considerations are listed below:  
•
•
•
A slew rate of at least 30 V/us is recommended for the programming signals  
After the programming is complete, the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state  
If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared  
with other parts, the phase noise may be degraded during this programming.  
30170103  
FIGURE 5. MICROWIRE Timing Diagram  
12.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 21)  
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading  
datasheets or communicating with other engineers. This section will address the measurement and description of a differential  
signal so that the reader will be able to understand and discern between the two different definitions when used.  
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and  
non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being  
described.  
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to  
the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this  
signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes  
with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.  
Figure 6 illustrates the two different definitions side-by-side for inputs and Figure 7 illustrates the two different definitions side-by-  
side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between  
with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference,  
the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the  
peak-to-peak voltage of the differential signal can be measured.  
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).  
30170175  
30170174  
FIGURE 6. Two Different Definitions for Differential Input  
Signals  
FIGURE 7. Two Different Definitions for Differential  
Output Signals  
Note 21: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.  
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18  
 
 
 
13.0 Typical Performance Characteristics  
13.2 CLOCK OUTPUT AC CHARACTERISTICS  
LVDS VOD vs. Frequency  
LVPECL /w 240 ohm emitter resistors VOD vs. Frequency  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
1200  
1000  
800  
600  
400  
200  
0
2000 mVpp  
1600 mVpp  
1200 mVpp  
700 mVpp  
0
0
500 1000 1500 2000 2500 3000  
FREQUENCY (MHz)  
0
500 1000 1500 2000 2500 3000  
FREQUENCY (MHz)  
30170141  
30170142  
LVPECL /w 120 ohm emitter resistors VOD vs. Frequency  
1200  
1000  
2000 mVpp  
800  
600  
1600 mVpp  
400  
200  
0
0
500 1000 1500 2000 2500 3000  
FREQUENCY (MHz)  
30170143  
19  
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LVPECL, or LVCMOS output type. OSCout1 is fixed as  
LVPECL.  
14.0 Features  
Any LVPECL output type can be programmed to 700, 1200,  
1600, or 2000 mVpp amplitude levels. The 2000 mVpp  
LVPECL output type is a National Semiconductor proprietary  
configuration that produces a 2000 mVpp differential swing  
for compatibility with many data converters and is also known  
as 2VPECL.  
14.1 CRYSTAL SUPPORT WITH BUFFERED OUTPUTS  
The LMK03806 provides 2 dedicated outputs which are a  
buffered copy of the PLL reference input. This reference input  
is typically a low noise external clock or Crystal.  
The OSCout0 buffer output type is programmable to LVDS,  
LVPECL, or LVCMOS. The OSCout1 buffer is fixed to  
LVPECL.  
14.4.3 CLOCK OUTPUT SYNCHRONIZATION  
The dedicated output buffers OSCout0 and OSCout1 can  
output frequency lower than the Input frequency by program-  
ming the OSC Divider. The OSC Divider value range is 1 to  
8. Each OSCoutX can individually choose to use the OSC  
Divider output or to bypass the OSC Divider.  
Using the SYNC input causes all active clock outputs to share  
a rising edge.  
By toggling the SYNC_POL_INV bit, it is possible to generate  
a SYNC through uWire eliminating the need for connecting  
the external SYNC pin to external circuitry.  
Crystal buffered outputs cannot be synchronized to the VCO  
clock distribution outputs. The assertion of SYNC will still  
cause these outputs to become low. Since these outputs will  
turn off and on asynchronously with respect to the VCO  
sourced clock outputs during a SYNC, it is possible for glitch-  
es to occur on the buffered clock outputs when SYNC is  
asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits  
are set these outputs will not be affected by the SYNC event  
except that the phase relationship will change with the other  
synchronized clocks unless a buffered clock output is used as  
a qualification clock during SYNC.  
14.5 DEFAULT STARTUP CLOCKS  
Before the LMK03806 is programmed some clocks will oper-  
ate at default frequencies upon power up. The active output  
clocks depend upon the reference input type. If a crystal ref-  
erence is used with OSCin, only CLKout8 will operate at a  
nominal VCO frequency /25. When an XO or other external  
reference is used as a reference with OSCin, OSCout0 will  
buffer the OSCin frequency in addition to CLKout8 operating  
at a nominal VCO frequency /25. These clocks can be used  
to clock external devices such as microcontrollers, FPGAs,  
CPLDs, etc. before the LMK03806 is programmed. Refer to  
Figure 8 or Figure 9 for illustration of startup clocks.  
14.2 INTEGRATED LOOP FILTER POLES  
The LMK03806 features programmable 3rd and 4th order  
loop filter poles for PLL. These internal resistors and capacitor  
values may be selected from a fixed range of values to  
achieve either a 3rd or 4th order loop filter response. The in-  
tegrated programmable resistors and capacitors compliment  
external components mounted near the chip.  
The nominal VCO frequency of CLKout8 on power up will  
typically be 98 MHz.  
Note during programming CLKout8 may momentarily stop or  
glitch during the VCO calibration routine.  
These integrated components can be effectively disabled by  
programming the integrated resistors and capacitors to their  
minimum values.  
14.3 INTEGRATED VCO  
The output of the internal VCO is routed to a mux which allows  
the user to select either the direct VCO output or a divided  
version of the VCO for the Clock Distribution Path. This same  
selection is also fed back to the PLL phase detector through  
a prescaler and N-divider.  
30170196  
14.4 CLOCK DISTRIBUTION  
The LMK03806 features a total of 12 outputs driven from the  
internal or external VCO.  
FIGURE 8. Startup Clock using Crystal Reference  
All VCO driven outputs have programmable output types.  
They can be programmed to LVPECL, LVDS, or LVCMOS.  
When all distribution outputs are configured for LVCMOS or  
single-ended LVPECL a total of 24 outputs are available.  
14.4.1 CLKout DIVIDER  
Each clock group, which is a pair of outputs such as CLKout0  
and CLKout1, has a single clock output divider. The divider  
supports a divide range of 1 to 1045 (even and odd) with 50%  
output duty cycle. When divides of 26 or greater are used, the  
divider block uses extended mode.  
30170197  
14.4.2 PROGRAMMABLE OUTPUT TYPE  
FIGURE 9. Startup Clock using XO or other External  
Reference  
For increased flexibility all LMK03806 clock outputs (CLK-  
outX) and OSCout0 can be programmed to an LVDS,  
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20  
 
 
8. R13: Readback pin & GPout0.  
9. R14: GPout1.  
15.0 General Programming  
Information  
10. R16: Undisclosed bits.  
Program this register as shown in the register map for  
proper operation.  
LMK03806 devices are programmed using 32-bit registers.  
Each register consists of a 5-bit address field and 27-bit data  
field. The address field is formed by bits 0 through 4 (LSBs)  
and the data field is formed by bits 5 through 31 (MSBs). The  
contents of each register is clocked in MSB first (bit 31), and  
the LSB (bit 0) last. During programming, the LEuWire signal  
should be held low. The serial data is clocked in on the rising  
edge of the CLKuWire signal. After the LSB (bit 0) is clocked  
in the LEuWire signal should be toggled low-to-high-to-low to  
latch the contents into the register selected in the address  
field. It is recommended to program registers in numeric or-  
der, for example R0 to R14, R16, R24, R26, and R28 to R31  
to achieve proper device operation. Refer to the electric spec-  
ifications sections for the timing for the programming.  
—
11. R24: Partially integrated PLL filter values.  
12. R26, R28, R29, and R30: PLL.  
13. R31: uWire readback and uWire lock.  
15.3 READBACK  
At no time should the MICROWIRE registers be programmed  
to any value other than what is specified in the datasheet.  
For debug of the MICROWIRE interface or programming, it is  
recommended to simply program an LD_MUX to active low  
and then toggle the output type register between output and  
inverting output while observing the output pin for a low to high  
transition. For example, to verify MICROWIRE programming,  
set the LD_MUX = 0 (Low) and then toggle the LD_TYPE  
register between 3 (Output, push-pull) and 4 (Output inverted,  
pushpull). The result will be that the Ftest/LD pin will toggle  
from low to high.  
To achieve proper frequency calibration, the OSCin port must  
be driven with a valid signal before programming register R30.  
Changes to PLL R divider or the OSCin port frequency require  
register R30 to be reloaded in order to activate the frequency  
calibration process.  
Readback from the MICROWIRE programming registers is  
available. The MICROWIRE readback function can be ac-  
cessed on the Readback pin. The READBACK_TYPE regis-  
ter can be programmed to "Output (push-pull)" for active  
output, or for communication with FPGAs/microcontrollers  
with lower voltage rails than 3.3 V the READBACK_TYPE  
register can be programmed to "Output (Open-Drain)" while  
connecting an external pull-up resistor to the voltage rail  
needed.  
15.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for  
CLKoutX_Y_DIV > 25  
When programming register R0 to R5 to change the  
CLKoutX_Y_DIV divide value, the register must be pro-  
grammed twice if the CLKoutX_Y_DIV value is greater than  
25.  
15.2 RECOMMENDED INITIAL PROGRAMMING  
SEQUENCE  
To perform a readback operation:  
The registers are to be programmed in numeric order with R0  
being the first and R31 being the last register programmed as  
shown below:  
1. Write the register address to be read back by  
programming the READBACK_ADDR register in R31.  
2. With the LEuWire pin held low continue to clock the  
CLKuWire pin. On every rising edge of the CLKuWire pin  
a new data bit is clocked onto the Readback pin.  
1. Program R0 with RESET bit = 1. This ensures that the  
device is configured with default settings. When RESET  
= 1, all other R0 bits are ignored.  
3. Data is clocked out MSB first. After 32 clocks all the data  
values will have been read and the read operation is  
complete. The 5 LSB bits which are the address will be  
undefined during readback.  
If R0 is programmed again during the initial  
configuration of the device, the RESET bit must be  
cleared.  
—
2. R0 through R5: CLKouts.  
Program as necessary to configure the clock outputs,  
15.3.1 Readback example  
—
To readback register R3 perform the following steps:  
CLKout0 to CLKout11 as desired. These registers  
configure clock output controls such as powerdown,  
divider value, and clock source select.  
1. Write R31 with READBACK_ADDR = 3. DATAuWire and  
CLKuWire are toggled as shown in Figure 5 with new  
data being clocked in on rising edges of CLKuWire  
3. R6 through R8: CLKouts.  
Program as necessary to configure the clock outputs,  
2. Toggle LEuWire high and low as shown in Figure 5.  
—
CLKout0 to CLKout11 as desired. These registers  
configure the output format for each clock output.  
3. Toggle CLKuWire high and then low 32 times to read  
back all 32 bits of register R3. Data is read MSB first.  
Data is valid on falling edge of CLKuWire.  
4. R9: Undisclosed bits.  
Program this register as shown in the register map for  
—
15.4 REGISTER MAP  
proper operation.  
Table 1 provides the register map for device programming. At  
no time should registers be programmed to undefined values.  
Only valid register values should be written.  
5. R10: OSCouts.  
6. R11: SYNC, and XTAL.  
7. R12: LD pin and SYNC.  
21  
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RESET POWERDOWN  
OSCout0_MUX  
OSCout1_MUX  
EN_OSCout0  
EN_OSCout1  
OSCout1  
_TYPE  
[31:30]  
CLKout  
0_1_PD  
CLKout  
2_3_PD  
CLKout CLKout CLKout CLKout  
4_5_PD 6_7_PD 8_9_PD 10_11_PD  
Register  
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22  
 
EN_PLL_XTAL  
uWire_LOCK  
SYNC_TYPE  
[13:12]  
SYNC_POL_INV  
NO_SYNC_CLKout0_1  
NO_SYNC_CLKout2_3  
NO_SYNC_CLKout4_5  
NO_SYNC_CLKout6_7  
NO_SYNC_CLKout8_9  
NO_SYNC_CLKout10_11  
1
SYNC_PLL  
_DLD  
EN_PLL_  
REF_2X  
Register  
23  
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15.5 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON RESET  
Table 2 illustrates the default register settings programmed in silicon for the LMK03806 after power on or asserting the reset bit.  
Capital X and Y represent numeric values.  
TABLE 2. Default Device Register Settings after Power On/Reset  
Default  
Value  
(decimal)  
Bit Location  
(MSB:LSB)  
Field Name  
Default State Field Description  
Register  
CLKout0_1_PD  
CLKout2_3_PD  
CLKout4_5_PD  
CLKout6_7_PD  
CLKout8_9_PD  
CLKout10_11_PD  
RESET  
1
1
1
0
0
1
0
PD  
PD  
R0  
R1  
R2  
R3  
R4  
R5  
R0  
PD  
Normal  
Normal  
PD  
Powerdown control for divider, and both  
output buffers  
31  
Not in reset  
Performs power on reset for device  
Device power down control  
17  
17  
Disabled  
(device is  
active)  
POWERDOWN  
0
R1  
CLKout0_1_DIV  
CLKout2_3_DIV  
CLKout4_5_DIV  
CLKout6_7_DIV  
CLKout8_9_DIV  
CLKout10_11_DIV  
CLKout3_TYPE  
CLKout7_TYPE  
CLKout11_TYPE  
CLKout2_TYPE  
25  
25  
25  
1
Divide-by-25  
Divide-by-25  
Divide-by-25  
Divide-by-1  
Divide-by-25  
Divide-by-25  
Powerdown  
Powerdown  
Powerdown  
Powerdown  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R6  
Divide for clock outputs  
15:5 [11]  
25  
25  
0
0
31:28 [4]  
27:24 [4]  
23:20 [4]  
0
0
LVCMOS  
(Norm/Norm)  
CLKout6_TYPE  
8
R7  
Individual clock output format. Select  
from LVDS/LVPECL/LVCMOS.  
CLKout10_TYPE  
CLKout1_TYPE  
CLKout5_TYPE  
CLKout9_TYPE  
CLKout0_TYPE  
CLKout4_TYPE  
CLKout8_TYPE  
0
0
0
0
0
0
1
Powerdown  
Powerdown  
Powerdown  
Powerdown  
Powerdown  
Powerdown  
LVDS  
R8  
R6  
R7  
R8  
R6  
R7  
R8  
19:16 [4]  
31:30 [2]  
1600 mVpp  
LVPECL  
OSCout1_TYPE  
2
Set LVPECL amplitude  
R10  
OSCout0_TYPE  
EN_OSCout1  
EN_OSCout0  
1
0
1
LVDS  
OSCout0 default clock output  
Disable OSCout1 output buffer  
Enable OSCout0 output buffer  
R10  
R10  
R10  
27:24 [4]  
23  
Disabled  
Enabled  
22  
Select OSCout divider for OSCout1 or  
bypass  
OSCout1_MUX  
0
Bypass Divider  
R10  
21  
Select OSCout divider for OSCout0 or  
bypass  
OSCout0_MUX  
OSCout_DIV  
0
0
Bypass Divider  
Divide-by-8  
R10  
R10  
20  
OSCout divider value  
18:16 [3]  
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24  
 
Default  
Value  
(decimal)  
Bit Location  
(MSB:LSB)  
Field Name  
Default State Field Description  
Register  
NO_SYNC_CLKout10_11  
NO_SYNC_CLKout8_9  
NO_SYNC_CLKout6_7  
NO_SYNC_CLKout4_5  
NO_SYNC_CLKout2_3  
NO_SYNC_CLKout0_1  
0
1
1
0
0
0
Will sync  
R11  
R11  
R11  
R11  
R11  
R11  
25  
24  
23  
22  
21  
20  
Will not sync  
Will not sync  
Will sync  
Disable individual clock groups from  
becoming synchronized.  
Will sync  
Will sync  
Sets the polarity of the SYNC pin when  
input. (Use for software SYNC)  
SYNC_POL_INV  
SYNC_TYPE  
1
1
Logic Low  
R11  
R11  
16  
Input /w  
Pull-up  
SYNC IO pin type  
13:12 [2]  
EN_PLL_XTAL  
LD_MUX  
0
3
Disabled  
Reserved  
Enable Crystal oscillator for OSCin  
Ftest/LD pin selection when output  
R11  
R12  
5
31:27 [5]  
Output  
(Push-Pull)  
LD_TYPE  
3
0
3
LD IO pin type  
R12  
R12  
R13  
26:24 [3]  
23  
SYNC_PLL_DLD  
READBACK_TYPE  
No effect  
When set, force SYNC until PLL locks  
Readback Pin Type  
Output (Push-  
Pull)  
26:24 [3]  
Weak pull-  
down  
GPout0  
GPout1  
2
2
GPout0 output state  
GPout1 output state  
R13  
R14  
18:16 [3]  
28:26 [3]  
Weak pull-  
down  
PLL_C4_LF  
0
0
0
0
0
3
10 pF  
10 pF  
200 Ω  
200 Ω  
PLL integrated capacitor C4 value  
PLL integrated capacitor C3 value  
PLL integrated resistor R4 value  
PLL integrated resistor R3 value  
R24  
R24  
R24  
R24  
R26  
R26  
31:28 [4]  
27:24 [4]  
22:20 [3]  
18:16 [3]  
29  
PLL_C3_LF  
PLL_R4_LF  
PLL_R3_LF  
EN_PLL_REF_2X  
PLL_CP_GAIN  
Disabled, 1x Doubles reference frequency of PLL.  
3.2 mA  
PLL Charge Pump Gain  
27:26 [2]  
Number of PDF cycles which phase  
PLL_DLD_CNT  
8192  
8192 Counts error must be within DLD window before  
LD state is asserted.  
R26  
19:6 [14]  
PLL_R  
4
7
Divide-by-4  
PLL R Divider (1 to 4095)  
R28  
R29  
R29  
R30  
R30  
31:20 [12]  
26:24 [3]  
22:5 [18]  
26:24 [3]  
22:5 [18]  
OSCin_FREQ  
PLL_N_CAL  
PLL_P  
448 to 500 MHz OSCin frequency range  
48  
2
Divide-by-48 Must be programmed to PLL_N value.  
Divide-by-2  
Divide-by-48 PLL N Divider (1 to 262143)  
The values of registers R0 to R30 are  
lockable  
PLL N Divider Prescaler (2 to 8)  
PLL_N  
48  
uWire_LOCK  
0
Writable  
R31  
5
25  
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15.6 REGISTER R0 TO R5  
15.6.3 POWERDOWN  
Registers R0 through R5 control the 12 clock outputs CLK-  
out0 to CLKout11. Register R0 controls CLKout0 and CLK-  
out1, Register R1 controls CLKout2 and CLKout3, and so on.  
The X and Y in CLKoutX_Y_PD, CLKoutX_Y_DIV denote the  
actual clock output which may be from 0 to 11 where X is even  
and Y is odd. Two clock outputs CLKoutX and CLKoutY form  
a clock output group and are often run together in bit names  
as CLKoutX_Y.  
The POWERDOWN bit is located in register R1 only. Setting  
the bit causes the device to enter powerdown mode. Normal  
operation is resumed by clearing this bit with MICROWIRE.  
POWERDOWN  
R1[17]  
State  
0
1
Normal operation  
Powerdown  
Two additional bits within the R0 to R5 register range are:  
•
•
The RESET bit, which is only in register R0.  
The POWERDOWN bit, which is only in register R1.  
15.6.4 CLKoutX_Y_DIV, Clock Output Divide  
CLKoutX_Y_DIV sets the divide value for the clock group.  
The divide may be even or odd. Both even and odd divides  
output a 50% duty cycle clock.  
15.6.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output  
Path  
Using a divide value of 26 or greater will cause the clock group  
to operate in extended mode.  
This bit powers down the clock group as specified by CLKoutX  
and CLKoutY. This includes the divider and output buffers.  
Programming CLKoutX_Y_DIV can require special attention.  
CLKoutX_Y_PD  
CLKoutX_Y_DIV, 11 bits  
R0-R5[31]  
State  
R0-R5[15:5]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
...  
Divide Value  
Power Mode  
0
1
Power up clock group  
Power down clock group  
Reserved  
1
15.6.2 RESET  
2 (Note 22)  
The RESET bit is located in register R0 only. Setting this bit  
will cause the silicon default values to be loaded. When pro-  
gramming register R0 with the RESET bit set, all other pro-  
grammed values are ignored. After resetting the device, the  
register R0 must be programmed again (with RESET = 0) to  
set non-default values in register R0.  
3
4 (Note 22)  
Normal Mode  
5 (Note 22)  
6
...  
The reset occurs on the falling edge of the LEuWire pin which  
loaded R0 with RESET = 1.  
24 (0x18)  
25 (0x19)  
26 (0x1A)  
27 (0x1B)  
...  
24  
25  
The RESET bit is automatically cleared upon writing any other  
register. For instance, when R0 is written to again with default  
values.  
26  
27  
RESET  
...  
Extended Mode  
1044 (0x414)  
1045 (0x415)  
1044  
1045  
R0[17]  
State  
0
1
Normal operation  
Reset (automatically cleared)  
Note 22: After programming PLL_N value, a SYNC must occur on channels  
using this divide value. Programming PLL_N does generate a SYNC event  
automatically which satisfies this requirement, but NO_SYNC_CLKoutX_Y  
must be set to 0 for these clock groups.  
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26  
 
15.7 REGISTERS R6 TO R8  
15.7.1 CLKoutX_TYPE  
15.8 REGISTER R9  
Register 9 contains no user programmable bits, but must be  
programmed as described in the register map.  
The clock output types of the LMK03806 are individually pro-  
grammable. The CLKoutX_TYPE registers set the output  
type of an individual clock output to LVDS, LVPECL, LVC-  
MOS, or powers down the output buffer. Note that LVPECL  
supports four different amplitude levels and LVCMOS sup-  
ports single LVCMOS outputs, inverted, and normal polarity  
of each output pin for maximum flexibility.  
15.9 REGISTER R10  
15.9.1 OSCout1_TYPE, LVPECL Output Amplitude  
Control  
The OSCout1 clock output can only be used as an LVPECL  
output type. OSCout1_TYPE sets the LVPECL output ampli-  
tude of the OSCout1 clock output.  
The programming addresses table shows at what register and  
address the specified clock output CLKoutX_TYPE register is  
located.  
OSCout1_TYPE, 2 bits  
R10[31:30]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
Output Format  
The CLKoutX_TYPE table shows the programming definition  
for these registers.  
LVPECL (700 mVpp)  
LVPECL (1200 mVpp)  
LVPECL (1600 mVpp)  
LVPECL (2000 mVpp)  
CLKoutX_TYPE Programming Addresses  
CLKoutX  
CLKout0  
CLKout1  
CLKout2  
CLKout3  
CLKout4  
CLKout5  
CLKout6  
CLKout7  
CLKout8  
CLKout9  
CLKout10  
CLKout11  
Programming Address  
R6[19:16]  
15.9.2 OSCout0_TYPE  
R6[23:20]  
The OSCout0 clock output has a programmable output type.  
The OSCout0_TYPE register sets the output type to LVDS,  
LVPECL, LVCMOS, or powers down the output buffer. Note  
that LVPECL supports four different amplitude levels and  
LVCMOS supports dual and single LVCMOS outputs with in-  
verted, and normal polarity of each output pin for maximum  
flexibility.  
R6[27:24]  
R6[31:28]  
R7[19:16]  
R7[23:20]  
R7[27:24]  
R7[31:28]  
To turn on the output, the OSCout0_TYPE must be set to a  
non-power down setting and enabled with Section 15.9.3  
EN_OSCoutX, OSCout Output Enable.  
R8[19:16]  
R8[23:20]  
R8[27:24]  
OSCout0_TYPE, 4 bits  
R8[31:28]  
R10[27:24]  
0 (0x00)  
Definition  
Powerdown  
CLKoutX_TYPE, 4 bits  
1 (0x01)  
LVDS  
R6-R8[31:28, 27:24, 23:20]  
0 (0x00)  
Definition  
2 (0x02)  
LVPECL (700 mVpp)  
LVPECL (1200 mVpp)  
LVPECL (1600 mVpp)  
LVPECL (2000 mVpp)  
LVCMOS (Norm/Inv)  
LVCMOS (Inv/Norm)  
LVCMOS (Norm/Norm)  
LVCMOS (Inv/Inv)  
LVCMOS (Low/Norm)  
LVCMOS (Low/Inv)  
LVCMOS (Norm/Low)  
LVCMOS (Inv/Low)  
LVCMOS (Low/Low)  
Power down  
3 (0x03)  
1 (0x01)  
LVDS  
4 (0x04)  
2 (0x02)  
LVPECL (700 mVpp)  
LVPECL (1200 mVpp)  
LVPECL (1600 mVpp)  
LVPECL (2000 mVpp)  
LVCMOS (Norm/Inv)  
LVCMOS (Inv/Norm)  
LVCMOS (Norm/Norm)  
LVCMOS (Inv/Inv)  
LVCMOS (Low/Norm)  
LVCMOS (Low/Inv)  
LVCMOS (Norm/Low)  
LVCMOS (Inv/Low)  
LVCMOS (Low/Low)  
5 (0x05)  
3 (0x03)  
6 (0x06)  
4 (0x04)  
7 (0x07)  
5 (0x05)  
8 (0x08) (Note 24)  
9 (0x09) (Note 24)  
10 (0x0A) (Note 24)  
11 (0x0B) (Note 24)  
12 (0x0C) (Note 24)  
13 (0x0D) (Note 24)  
14 (0x0E) (Note 24)  
6 (0x06)  
7 (0x07)  
8 (0x08) (Note 23)  
9 (0x09) (Note 23)  
10 (0x0A) (Note 23)  
11 (0x0A) (Note 23)  
12 (0x0C) (Note 23)  
13 (0x0D) (Note 23)  
14 (0x0E) (Note 23)  
Note 24: It is recommended to use one of the complementary LVCMOS  
modes. Best noise performance is achieved using LVCMOS (Norm/Inv) or  
LVCMOS (Inv/Norm) due to the differential switching of the outputs. The next  
best performance is achieved using an LVCMOS mode with only one output  
on. Finally, LVCMOS (Norm/Norm) or LVCMOS (Inv/Inv) have the create  
the most switching noise.  
Note 23: It is recommended to use one of the complementary LVCMOS  
modes. Best noise performance is achieved using LVCMOS (Norm/Inv) or  
LVCMOS (Inv/Norm) due to the differential switching of the outputs. The next  
best performance is achieved using an LVCMOS mode with only one output  
on. Finally, LVCMOS (Norm/Norm) or LVCMOS (Inv/Inv) have the create  
the most switching noise.  
27  
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15.9.3 EN_OSCoutX, OSCout Output Enable  
15.10 REGISTER R11  
EN_OSCoutX is used to enable an oscillator buffered output.  
15.10.1 NO_SYNC_CLKoutX_Y  
EN_OSCout1  
The NO_SYNC_CLKoutX_Y bits prevent individual clock  
groups from becoming synchronized during a SYNC event. A  
reason to prevent individual clock groups from becoming syn-  
chronized is that during synchronization, the clock output is  
in a fixed low state or can have a glitch pulse.  
R10[23]  
Output State  
OSCout1 Disabled  
OSCout1 Enabled  
0
1
By disabling SYNC on a clock group, it will continue to operate  
normally during a SYNC event.  
EN_OSCout0  
R10[22]  
Output State  
OSCout0 Disabled  
OSCout0 Enabled  
Setting the NO_SYNC_CLKoutX_Y bit has no effect on  
clocks already synchronized together.  
0
1
NO_SYNC_CLKoutX_Y Programming Addresses  
OSCout0 note: In addition to enabling the output with EN_OS-  
Cout0. The OSCout0_TYPE must be programmed to a non-  
power down value for the output buffer to power up.  
NO_SYNC_CLKoutX_Y  
CLKout0 and 1  
Programming Address  
R11:20  
CLKout2 and 3  
R11:21  
15.9.4 OSCoutX_MUX, Clock Output Mux  
CLKout4 and 5  
R11:22  
Sets OSCoutX buffer to output a divided or bypassed OSCin  
signal. .  
CLKout6 and 7  
R11:23  
CLKout8 and 9  
R11:24  
OSCout1_MUX  
CLKout10 and 11  
R11:25  
R10[21]  
Mux Output  
Bypass divider  
Divided  
NO_SYNC_CLKoutX_Y  
0
1
R11[25, 24, 23, 22, 21, 20]  
Definition  
0
CLKoutX_Y will synchronize  
OSCout0_MUX  
CLKoutX_Y will not  
synchronize  
1
R10[20]  
Mux Output  
Bypass divider  
Divided  
0
1
15.10.2 SYNC_POL_INV  
Sets the polarity of the SYNC pin when input. When SYNC is  
asserted the clock outputs will transition to a low state.  
15.9.5 OSCout_DIV, Oscillator Output Divide  
The OSCout divider can be programmed from 2 to 8. Divide  
by 1 is achieved by bypassing the divider with Section 15.9.4  
OSCoutX_MUX, Clock Output Mux.  
SYNC_POL_INV  
R11[16]  
Polarity  
0
1
SYNC is active high  
SYNC is active low  
OSCout_DIV, 3 bits  
R10[18:16]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
7 (0x07)  
Divide  
15.10.3 SYNC_TYPE  
8
2
2
3
4
5
6
7
Sets the IO type of the SYNC pin.  
SYNC_TYPE, 2 bits  
R11[13:12]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
Polarity  
Input  
Input /w pull-up resistor  
Input /w pull-down resistor  
15.10.4 EN_PLL_XTAL  
If an external crystal is being used to implement a discrete  
VCXO, the internal feedback amplifier must be enabled with  
this bit in order to complete the oscillator circuit.  
EN_PLL_XTAL  
R11[5]  
Oscillator Amplifier State  
Disabled  
0
1
Enabled  
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28  
 
 
15.11 REGISTER R12  
15.12 REGISTER R13  
15.11.1 LD_MUX  
15.12.1 READBACK_TYPE  
LD_MUX sets the output value of the Ftest/LD pin.  
Sets the IO format of the readback pin. The open drain output  
type can be used to interface the LMK03806 with low voltage  
IO rails.  
All the outputs logic is active high when LD_TYPE = 3 (Out-  
put). All the outputs logic is active low when LD_TYPE = 4  
(Output Inverted). For example, when LD_MUX = 0 (Logic  
Low) and LD_TYPE = 3 (Output) then Ftest/LD pin outputs a  
logic low. When LD_MUX = 0 (Logic Low) and LD_TYPE = 4  
(Output Inverted) then Ftest/LD pin outputs a logic high.  
READBACK_TYPE, 3 bits  
R13[26:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
Polarity  
Reserved  
Reserved  
LD_MUX, 5 bits  
Reserved  
R12[31:27]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
...  
Divide  
Logic Low  
Reserved  
PLL DLD  
Reserved  
...  
Output (push-pull)  
Output inverted (push-pull)  
Output (open source)  
Output (open drain)  
15.12.2 GPout0  
12 (0x0C)  
13 (0x0D)  
14 (0x0E)  
15 (0x0F)  
16 (0x10)  
17 (0x11)  
18 (0x12)  
Reserved  
PLL N  
Sets the output state of the GPout0 pin.  
GPout0, 3 bits  
PLL N/2  
R13[18:16]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
Output State  
Reserved  
Reserved  
PLL R (Note 25)  
PLL R/2 (Note 25)  
Reserved  
Reserved  
Weak pull-down  
Low (0 V)  
Note 25: Only valid when LD_MUX is not set to 2 (PLL_DLD).  
High (3.3 V)  
15.11.2 LD_TYPE  
15.13 REGISTER 14  
15.13.1 GPout1  
Sets the IO type of the LD pin.  
LD_TYPE, 3 bits  
Sets the output state of the GPout1 pin.  
R12[26:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
Polarity  
Reserved  
GPout1, 3 bits  
R14[26:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
Output State  
Reserved  
Reserved  
Reserved  
Reserved  
Output (push-pull)  
Output inverted (push-pull)  
Output (open source)  
Output (open drain)  
Weak pull-down  
Low (0 V)  
High (3.3 V)  
15.11.3 SYNC_PLL_DLD  
By setting SYNC_PLL_DLD a SYNC mode will be engaged  
(asserted SYNC) until the PLL locks.  
SYNC_PLL_DLD  
R12[23]  
Sync Mode Forced  
0
1
No  
Yes  
29  
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15.14 REGISTER 16  
7 (0x07)  
8 (0x08)  
25 pF  
29 pF  
Register 16 contains no user programmable bits, but must be  
programmed as described in the register map.  
9 (0x09)  
30 pF  
15.15 REGISTER 24  
10 (0x0A)  
11 (0x0B)  
12 (0x0C)  
13 (0x0D)  
14 (0x0E)  
15 (0x0F)  
33 pF  
34 pF  
15.15.1 PLL_C4_LF, PLL Integrated Loop Filter  
Component  
38 pF  
Internal loop filter components are available for the PLL, en-  
abling either 3rd or 4th order loop filters without requiring  
external components.  
39 pF  
Reserved  
Reserved  
Internal loop filter capacitor C4 can be set according to the  
following table.  
15.15.3 PLL_R4_LF, PLL Integrated Loop Filter  
Component  
PLL_C4_LF, 4 bits  
Internal loop filter components are available for the PLL, en-  
abling either 3rd or 4th order loop filters without requiring  
external components.  
R24[31:28]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
7 (0x07)  
8 (0x08)  
9 (0x09)  
10 (0x0A)  
11 (0x0B)  
12 (0x0C)  
13 (0x0D)  
14 (0x0E)  
15 (0x0F)  
Loop Filter Capacitance (pF)  
10 pF  
15 pF  
Internal loop filter resistor R4 can be set according to the fol-  
lowing table.  
29 pF  
34 pF  
PLL_R4_LF, 3 bits  
47 pF  
R24[22:20]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
7 (0x07)  
Resistance  
200 Ω  
52 pF  
66 pF  
1 kΩ  
71 pF  
2 kΩ  
103 pF  
108 pF  
122 pF  
126 pF  
141 pF  
146 pF  
Reserved  
Reserved  
4 kΩ  
16 kΩ  
Reserved  
Reserved  
Reserved  
15.15.4 PLL_R3_LF, PLL Integrated Loop Filter  
Component  
Internal loop filter components are available for the PLL, en-  
abling either 3rd or 4th order loop filters without requiring  
external components.  
15.15.2 PLL_C3_LF, PLL Integrated Loop Filter  
Component  
Internal loop filter components are available for the PLL, en-  
abling either 3rd or 4th order loop filters without requiring  
external components.  
Internal loop filter resistor R3 can be set according to the fol-  
lowing table.  
PLL_R3_LF, 3 bits  
Internal loop filter capacitor C3 can be set according to the  
following table.  
R24[18:16]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
7 (0x07)  
Resistance  
200 Ω  
PLL_C3_LF, 4 bits  
1 kΩ  
R24[27:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
Loop Filter Capacitance (pF)  
2 kΩ  
10 pF  
11 pF  
15 pF  
16 pF  
19 pF  
20 pF  
24 pF  
4 kΩ  
16 kΩ  
Reserved  
Reserved  
Reserved  
www.ti.com  
30  
15.16 REGISTER 26  
15.17 REGISTER 28  
15.16.1 EN_PLL_REF_2X, PLL Reference Frequency  
Doubler  
15.17.1 PLL_R, PLL R Divider  
The reference path into the PLL phase detector includes the  
PLL R divider.  
Enabling the PLL reference frequency doubler allows for high-  
er phase detector frequencies on the PLL than would normally  
be allowed with the given VCXO or Crystal frequency.  
The valid values for PLL_R are shown in the table below.  
PLL_R, 12 bits  
Higher phase detector frequencies reduces the PLL N values  
which makes the design of wider loop bandwidth filters pos-  
sible.  
R28[31:20]  
0 (0x00)  
Divide  
Not Valid  
EN_PLL_REF_2X  
1 (0x01)  
1
2
2 (0x02)  
R26[29]  
Description  
3 (0x03)  
3
0
Reference frequency normal  
...  
...  
Reference frequency  
doubled (2x)  
1
4,094 (0xFFE)  
4,095 (0xFFF)  
4,094  
4,095  
15.16.2 PLL_CP_GAIN, PLL Charge Pump Current  
This bit programs the PLL charge pump output current level.  
PLL_CP_GAIN, 2 bits  
R26[27:26]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
Charge Pump Current (µA)  
100  
400  
1600  
3200  
15.16.3 PLL_DLD_CNT  
The reference and feedback of the PLL must be within the  
window of acceptable phase error for PLL_DLD_CNT cycles  
before PLL digital lock detect is asserted.  
PLL_DLD_CNT, 14 bits  
R26[19:6]  
0 (0x00)  
Divide  
Reserved  
1 (0x01)  
1
2 (0x02)  
2
3
3 (0x03)  
...  
...  
16,382 (0x3FFE)  
16,383 (0x3FFF)  
16,382  
16,383  
31  
www.ti.com  
15.18 REGISTER 29  
PLL_N, 18 bits  
R30[22:5]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
Divide  
15.18.1 OSCin_FREQ, PLL Oscillator Input Frequency  
Register  
Not Valid  
The frequency of the PLL reference input to the PLL Phase  
Detector (OSCin/OSCin* port) must be programmed in order  
to support proper operation of the frequency calibration rou-  
tine which locks the internal VCO to the target frequency.  
1
2
...  
262,143 (0x3FFFF)  
262,143  
OSCin_FREQ, 3 bits  
15.20 REGISTER 31  
R29[26:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
OSCin Frequency  
0 to 63 MHz  
15.20.1 READBACK_ADDR  
>63 MHz to 127 MHz  
>127 MHz to 255 MHz  
Reserved  
READBACK_ADDR  
R31[20:16]  
State  
R0  
0
1
>255 MHz to 500 MHz  
R1  
15.18.2 PLL_N_CAL, PLL N Calibration Divider  
2
R2  
During the frequency calibration routine, the PLL uses the di-  
vide value of the PLL_N_CAL register instead of the divide  
value of the PLL_N register to lock the VCO to the target fre-  
quency.  
3
R3  
4
R4  
5
R5  
6
R6  
PLL_N_CAL, 18 bits  
7
R7  
R29[22:5]  
0 (0x00)  
Divide  
8
R8  
Not Valid  
9
R9  
1 (0x01)  
1
10  
11  
12  
13  
14  
15  
16  
17  
...  
23  
24  
25  
26  
27  
28  
29  
30  
R10  
2 (0x02)  
2
...  
R11  
...  
R12  
262,143 (0x3FFFF)  
262,143  
R13  
15.19 REGISTER 30  
R14  
Programming Register 30 triggers the frequency calibration  
routine. This calibration routine will also generate a SYNC  
event.  
Reserved  
R16  
Reserved  
...  
15.19.1 PLL_P, PLL N Prescaler Divider  
The PLL N Prescaler divides the output of the VCO and is  
connected to the PLL N divider.  
Reserved  
R24  
PLL_P, 3 bits  
Reserved  
R26  
R30[26:24]  
0 (0x00)  
1 (0x01)  
2 (0x02)  
3 (0x03)  
4 (0x04)  
5 (0x05)  
6 (0x06)  
7 (0x07)  
Divide Value  
8
2
2
3
4
5
6
7
Reserved  
R28  
R29  
R30  
15.20.2 uWire_LOCK  
Setting uWire_LOCK will prevent any changes to uWire reg-  
isters R0 to R30. Only by clearing the uWire_LOCK bit in R31  
can the uWire registers be unlocked and written to once more.  
It is not necessary to lock the registers to perform a readback  
operation.  
15.19.2 PLL_N, PLL N Divider  
The feeback path into the PLL phase detector includes the  
PLL N divider.  
uWire_LOCK  
Each time register 30 is updated via the MICROWIRE inter-  
face, a frequency calibration routine runs to lock the VCO to  
the target frequency. During this calibration PLL_N is substi-  
tuted with PLL_N_CAL.  
R31[5]  
State  
0
1
Registers unlocked  
Registers locked, Write-  
protect  
The valid values for PLL_N are shown in the table below.  
www.ti.com  
32  
level with RLIM shorted, then a zero value for RLIM can be used.  
As a starting point, a suggested value for RLIM is 1.5 kΩ.  
16.0 Application Information  
16.1 Crystal Interface  
16.2 External Reference Interface  
The LMK03806 has an integrated crystal oscillator circuit on  
that supports a fundamental mode, AT-cut crystal. The crystal  
interface is shown in Figure 10.  
The LMK03806 has an the ability to be driven by an external  
reference. Typical external reference interfaces are shown in  
Figure 11 and Figure 12.  
In applications where the external reference amplitude is less  
than the VOSCin specification of 2.4 Vpp Figure 11 is an appro-  
priate method of interfacing the reference to the LMK03806.  
In applications where the external reference amplitude is  
greater than the VOSCin specification of 2.4 Vpp Figure 12 is an  
appropriate method of interfacing the reference to the  
LMK03806.  
In both cases C1 and C2 should be present a low impedance  
at the reference frequency. A typical value for C1 and C2 is  
0.1 µF.  
30170194  
FIGURE 10. Crystal Interface  
The load capacitance (CL) is specific to the crystal, but usually  
on the order of 18 - 20 pF. While CL is specified for the crystal,  
the OSCin input capacitance (CIN = 6 pF typical) of the device  
and PCB stray capacitance (CSTRAY ~ 1~3 pF) can affect the  
discrete load capacitor values, C1 and C2.  
For the parallel resonant circuit, the discrete capacitor values  
can be calculated as follows:  
30170198  
CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY  
(1)  
FIGURE 11. LVCMOS External Reference Interface  
Typically, C1 = C2 for optimum symmetry, so Equation 1 can  
be rewritten in terms of C1 only:  
CL = C12 / (2 * C1) + CIN + CSTRAY  
Finally, solve for C1:  
C1 = (CL – CIN – CSTRAY)*2  
(2)  
(3)  
Section 11.0 Electrical Characteristics provides crystal inter-  
face specifications with conditions that ensure start-up of the  
crystal, but it does not specify crystal power dissipation. The  
designer will need to ensure the crystal power dissipation  
does not exceed the maximum drive level specified by the  
crystal manufacturer. Overdriving the crystal can cause pre-  
mature aging, frequency shift, and eventual failure. Drive level  
should be held at a sufficient level necessary to start-up and  
maintain steady-state operation.  
30170199  
FIGURE 12. 3.3 Vpp External Reference Interface  
Using an external reference, such as a crystal oscillator (XO),  
may provide better phase noise than a crystal at offsets below  
the loop bandwidth. If the jitter integration bandwidth for the  
application of interest is above the loop filter bandwidth, the  
added phase noise of a crystal will not be a significant jitter  
contributor and may be a more cost effective solution than an  
XO. Also, operating at higher reference frequencies allows  
higher phase detector frequencies, which also improves in  
band PLL phase noise performance.  
The power dissipated in the crystal, PXTAL, can be computed  
by:  
PXTAL = IRMS2 * RESR*(1 + C0/CL)2  
(4)  
Where:  
•
•
IRMS is the RMS current through the crystal.  
RESR is the max. equivalent series resistance specified for  
the crystal  
•
•
CL is the load capacitance specified for the crystal  
C0 is the min. shunt capacitance specified for the crystal  
IRMS can be measured using a current probe (e.g. Tektronix  
CT-6 or equivalent) placed on the leg of the crystal connected  
to OSCin* with the oscillation circuit active.  
As shown in Figure 10, an external resistor, RLIM, can be used  
to limit the crystal drive level, if necessary. If the power dissi-  
pated in the selected crystal is higher than the drive level  
specified for the crystal with RLIM shorted, then a larger resis-  
tor value is mandatory to avoid overdriving the crystal. How-  
ever, if the power dissipated in the crystal is less than the drive  
33  
www.ti.com  
 
 
 
 
16.3 DIGITAL LOCK DETECT  
A user specified ppm accuracy for lock detect is pro-  
grammable using a lock count register. By using Equation 5,  
values for a "lock count" and "window size" can be chosen to  
set the frequency accuracy required by the system in ppm  
The digital lock detect circuit is used to determine the lock  
status of the PLL. The flowchart in Figure 13 shows the gen-  
eral way this circuit works.  
before the digital lock detect event occurs. Units of  
Hertz:  
are  
PD  
TABLE 3.  
Event  
PLL  
Lock count  
Window size (ε)  
(5)  
PLL  
Locked  
PLL  
3.7 ns  
PLL_DLD_CNT  
The effect of the "lock count" value is that it shortens the ef-  
fective lock window size by dividing the "window size" by "lock  
count".  
For a digital lock detect event to occur there must be a number  
of PLL phase detector cycles during which the time/phase er-  
ror of the PLL_R reference and PLL_N feedback signal edges  
are within the 3.7 ns window size of the LMK03806. “Lock  
count” is the term which is used to specify how many PLL  
phase detector cycles have been within the window size of  
3.7 ns at any given time. Since there must be a specified  
number phase detector events before a lock event occurs, a  
minimum digital lock event time can be calculated as "lock  
If at any time the PLL_R reference and PLL_N feedback sig-  
nals are outside the time window set by "window size", then  
the “lock count” value is reset to 0.  
For example, to calculate the minimum PLL digital lock time  
given a PLL phase detector frequency of 40 MHz and  
PLL_DLD_CNT = 10,000. Then the minimum lock time of PLL  
will be 10,000 / 40 MHz = 250 µs.  
count" / fPD  
.
30170128  
FIGURE 13. Digital Lock Detect Flow Diagram  
www.ti.com  
34  
 
 
16.4 POWER SUPPLY  
For total current consumption of the device, add up the sig-  
nificant functional blocks. In this example, 212.9 mA =  
16.4.1 Current Consumption / Power Dissipation  
Calculations  
•
•
•
•
•
•
122 mA (core current)  
17.3 mA (base clock distribution)  
2.8 mA (CLKout group for 2 outputs)  
25.5 mA (CLKout0 & 1 divider)  
14.3 mA (LVDS buffer)  
31 mA (LVPECL 1.6 Vpp buffer /w 240 ohm emitter  
resistors)  
From Table 4 the current consumption can be calculated for  
any configuration.  
For example, the current for the entire device with 1 LVDS  
(CLKout0) and 1 LVPECL 1.6 Vpp /w 240 ohm emitter resis-  
tors (CLKout1) output active with a clock output divide = 1,  
and no other features enabled can be calculated by adding  
up the following blocks: core current, base clock distribution,  
clock output group, clock divider, one LVDS output buffer cur-  
rent, and one LVPECL output buffer current. There will also  
be one LVPECL output drawing emitter current, which means  
some of the power from the current draw of the device is dis-  
sipated in the external emitter resistors which doesn't add to  
the thermal power dissipation budget for the device. In addi-  
tion to emitter resistor power, power dissipated in the load for  
LVDS/LVPECL do not contribute to the thermal power dissi-  
pation budget for the device.  
Once total current consumption has been calculated, power  
dissipated by the device can be calculated. The power dissi-  
pation of the device is equation to the total current entering  
the device multiplied by the voltage at the device minus the  
power dissipated in any emitter resistors connected to any of  
the LVPECL outputs or any other external load power dissi-  
pation. Continuing the above example which has 212.9 mA  
total Icc and one output with 240 ohm emitter resistors and  
one LVDS output. Total IC power = 666 mW = 3.3 V * 212.9  
mA - 35 mW - 1.5 mW.  
TABLE 4. Typical Current Consumption for Selected Functional Blocks (TA = 25 °C, VCC = 3.3 V)  
Power  
Power  
Typical ICC  
(mA)  
dissipated dissipated  
Block  
Condition  
in device  
(mW)  
externally  
(mW)  
Core and Functional Blocks  
Core  
Internal VCO Locked  
122  
403  
-
-
Base Clock  
Distribution  
At least 1 CLKoutX_Y_PD = 0  
17.3  
57.1  
Each CLKout group (CLKout0/1 & 10/11, CLKout2/3 & 4/5, CLKout  
6/7 & 8/9)  
CLKout Group  
Clock Divider  
2.8  
9.2  
-
Divide < 25  
25.5  
29.6  
1.7  
84.1  
97.7  
5.6  
-
-
-
-
-
Divide >= 25  
SYNC Asserted  
Crystal Mode  
While SYNC is asserted, this extra current is drawn  
Crystal Oscillator Buffer  
1.8  
5.9  
OSCin Doubler  
EN_OSCin_2X = 1  
2.8  
9.2  
Clock Output Buffers  
LVDS  
100 ohm differential termination  
14.3  
32  
45.7  
70.6  
67.3  
91.8  
59  
1.5  
35  
35  
60  
40  
40  
-
LVPECL 2.0 Vpp, AC coupled using 240 ohm emitter resistors  
LVPECL 1.6 Vpp, AC coupled using 240 ohm emitter resistors  
LVPECL 1.6 Vpp, AC coupled using 120 ohm emitter resistors  
LVPECL 1.2 Vpp, AC coupled using 240 ohm emitter resistors  
LVPECL 0.7 Vpp, AC coupled using 240 ohm emitter resistors  
31  
LVPECL  
(Note 26)  
46  
30  
29  
55.7  
79.2  
87.5  
LVCMOS Pair  
(CLKoutX_Y_TYPE  
= 6 to 10)  
3 MHz  
24  
30 MHz  
26.5  
-
150 MHz  
36.5  
120.5  
-
CL = 5 pF  
LVCMOS  
LVCMOS Single  
(CLKoutX_Y_TYPE  
= 11 to 13)  
3 MHz  
15  
16  
49.5  
52.8  
-
-
30 MHz  
150 MHz  
21.5  
71  
-
CL = 5 pF  
Note 26: Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level of one LVPECL  
clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2 / Rem.  
Note 27: Assuming θJA = 15 °C/W, the total power dissipated on chip must be less than (125 °C – 85 °C) / 16 °C/W = 2.5 W to guarantee a junction temperature  
is less than 125 °C.  
Note 28: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.15.  
35  
www.ti.com  
 
 
 
16.5 THERMAL MANAGEMENT  
To minimize junction temperature it is recommended that a  
simple heat sink be built into the PCB (if the ground plane  
layer is not exposed). This is done by including a copper area  
of about 2 square inches on the opposite side of the PCB from  
the device. This copper area may be plated or solder coated  
to prevent corrosion but should not have conformal coating (if  
possible), which could provide thermal insulation. The vias  
shown in Figure 14 should connect these top and bottom  
copper layers and to the ground layer. These vias act as “heat  
pipes” to carry the thermal energy away from the device side  
of the board to where it can be more effectively dissipated.  
Power consumption of the LMK03806 can be high enough to  
require attention to thermal management. For reliability and  
performance reasons the die temperature should be limited  
to a maximum of 125 °C. That is, as an estimate, TA (ambient  
temperature) plus device power consumption times θJA  
should not exceed 125 °C.  
The package of the device has an exposed pad that provides  
the primary heat removal path as well as excellent electrical  
grounding to a printed circuit board. To maximize the removal  
of heat from the package a thermal land pattern including  
multiple vias to a ground plane must be incorporated on the  
PCB within the footprint of the package. The exposed pad  
must be soldered down to ensure adequate heat conduction  
out of the package.  
A recommended land and via pattern is shown in Figure 14.  
More information on soldering LLP packages and gerber foot-  
prints can be obtained: http:// www.national.com/analog/  
packaging/.  
A recommended footprint including recommended solder  
mask and solder paste layers can be found at: http://  
www.national.com/analog/packaging/gerber for the SQA64  
package.  
30170173  
FIGURE 14. Recommended Land and Via Pattern  
www.ti.com  
36  
 
17.0 Physical Dimensions inches (millimeters) unless otherwise noted  
18.0 Ordering Information  
Order Number  
LMK03806BISQE  
LMK03806BISQ  
LMK03806BISQX  
Packaging  
250 Unit Tape and Reel  
1000 Unit Tape and Reel  
2500 Unit Tape and Reel  
37  
www.ti.com  
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LMK04000BISQ/NOPB TI 具有级联 PLL 的精密时钟调节器低噪声时钟抖动消除器 | RHS | 48 | -40 to 85 获取价格

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