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LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

具有双环路 PLL 的 LMK04228 超低噪声且符合 JESD204B 标准的时钟抖

动清除器

1 特性

3 说明

1

•

JEDEC JESD204B 支持

超低 RMS 抖动

LMK04228 器件是支持 JEDEC JESD204B 且在业界

具有高性能的时钟调节器。

–

156fs RMS 抖动（12kHz 至 20MHz）

245fs RMS 抖动（100Hz 至 20MHz）

245.76MHz 时具有 –162.5dBc/Hz 本底噪声

PLL2 可以配置 14 个时钟输出以驱动 7 个 JESD204B

转换器或其他逻辑器件（使用器件和 SYSREF 时

钟）。SYSREF 可以通过直流和交流耦合提供。不只

是 JESD204B 应用，14 个输出中的每一个输出都可以

单独配置为用于传统时钟系统的高性能输出。

•

PLL2 提供多达 14 个差动器件时钟

–

多达 7 个 SYSREF 时钟

最高时钟输出频率：1.25GHz

PLL2 提供 LVPECL、LVDS 可编程输出

LMK04228 既具有出色的性能，又具有多种特性，如

功率和性能均衡调节、双 VCO、保持模式和可根据输

出调节的模拟和数字延迟，是提供灵活的高性能时钟树

的理想器件。

•

PLL1 提供缓冲的 VCXO 或晶体输出

LVPECL、LVDS、2xLVCMOS 可编程输出

–

•

双环路 PLLatinum™锁相环 (PLL) 架构

器件信息⁽¹⁾

PLL1

–

多达 3 个冗余输入时钟

器件型号

封装

封装尺寸（标称值）

LMK04228

WQFN (64)

9.00mm x 9.00mm

–

自动和手动切换模式

无中断切换和 LOS

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

集成低噪声晶体振荡器电路

输入时钟丢失时采用保持模式

频率输出

•

PLL2

器件型号

VCO0 频率

2370MHz 至

2630MHz

VCO1 频率

–

标准 [1Hz] PLL 本底噪声为 -224dBc/Hz

LMK04228

2920MHz 至 3080MHz

相位检测器频率高达 155MHz

OSCin 倍频器

简化原理图

两个集成低噪声 VCO

Multiple —clean“

clocks at

different

VCXO

Recovered

—dirty“ clock or

clean clock

50% 占空比输出分配，1 至 32

（偶数和奇数）

frequencies

CLKin0

Backup

Clock

•

精密数字延迟

CLKout10

CLKout11

FPGA

Reference

LMK04228

CLKin1

25ps 步长模拟延迟

多模式：双 PLL 或单 PLL

工业温度范围：–40°C 至 85°C

3.15V 至 3.45V 工作电压

封装：64 引脚 WQFN (9.0 × 9.0 × 0.8mm)

CLKout6,

CLKout7,

CLKout8,

CLKout9

CLKout4,

CLKout5

DAC

ADC

CLKout0,

CLKout1,

CLKout2,

CLKout3

ADC

Serializer/

Deserializer

2 应用

•

无线基础设施

数据转换器时钟

网络、SONET/SDH、DSLAM

医疗/视频/军事/航天

测试和测量

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS689

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

9.3 Feature Description................................................. 23

9.4 Programming........................................................... 32

9.5 Register Maps ........................................................ 33

10 Application and Implementation........................ 75

10.1 Application Information.......................................... 75

10.2 Typical Application ................................................ 78

10.3 Do's and Don'ts..................................................... 79

11 Power Supply Recommendations ..................... 80

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics........................................... 7

7.6 SPI Interface Timing ............................................... 13

7.7 Timing Diagram....................................................... 13

Parameter Measurement Information ................ 15

8.1 Charge Pump Current Specification Definitions...... 15

8.2 Differential Voltage Measurement Terminology ..... 16

Detailed Description ............................................ 17

9.1 Overview ................................................................. 17

9.2 Functional Block Diagrams ..................................... 20

11.1 Current Consumption / Power Dissipation

Calculations.............................................................. 80

12 Layout................................................................... 81

12.1 Layout Guidelines ................................................. 81

12.2 Layout Example .................................................... 82

13 器件和文档支持 ..................................................... 83

13.1 器件支持................................................................ 83

13.2 社区资源................................................................ 83

13.3 商标....................................................................... 83

13.4 静电放电警告......................................................... 83

13.5 Glossary................................................................ 83

14 机械、封装和可订购信息....................................... 83

8

9

4 修订历史记录

Changes from Original (October 2017) to Revision A

Page

•

将数据表版本状态从产品定制更改为产品目录........................................................................................................................ 1

已删除删除了有关分配模式的参考内容（不支持）................................................................................................................ 1

已删除删除了有关动态延迟的参考内容（不支持）................................................................................................................ 1

Updated default output table note ........................................................................................................................................ 11

Added missing cross reference to differential voltage definition .......................................................................................... 12

Removed typical phase noise plots ..................................................................................................................................... 13

Updated description for improved clarity .............................................................................................................................. 17

Deleted reference to distribution mode (unsupported)......................................................................................................... 17

Updated delay circuit descriptions for improved clarity ........................................................................................................ 18

Deleted reference to dynamic delay (unsupported) ............................................................................................................. 19

Deleted reference to dynamic delay, bypass mode in clock output block diagram (unsupported) ...................................... 21

Deleted reference to distribution mode in SYNC/SYSREF clocking path diagram (unsupported) ...................................... 22

Clarified digital lock detect for cases where phase detector frequency exceeds default PLL1_WND_SIZE ...................... 29

Removed device functional modes section .......................................................................................................................... 32

Clarified requirements for unused registers in recommended programming sequence....................................................... 32

Added registers 0x171 and 0x172 to default register programming .................................................................................... 32

Deleted redundant user-inaccessible registers in register map ........................................................................................... 33

Changed address bits to clarify address position relative to data bits ................................................................................. 33

Deleted references to dynamic delay in register map (unsupported)................................................................................... 33

Corrected CLKinX_R register size in register map............................................................................................................... 35

Corrected PLL1_N register size in register map .................................................................................................................. 35

Deleted reference to DCLKoutX_MUX bypass mode (unsupported)................................................................................... 40

Corrected delay value descriptions for SDCLKoutY_ADLY ................................................................................................. 41

Deleted reference to dynamic delay (unsupported) ............................................................................................................. 42

2

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

修订历史记录 (接下页)

•

Updated missing cross-reference......................................................................................................................................... 49

Corrected CLKinX_R register length .................................................................................................................................... 59

Corrected PLL1_N register length........................................................................................................................................ 60

Corrected PLL2_R register length........................................................................................................................................ 64

Split PLL2_FCAL_DIS and PLL2_N register tables into separate definitions...................................................................... 66

Added register 0x171 and 0x172 to register descriptions .................................................................................................... 72

Corrected RB_PLL1_LD and RB_PLL2_LD polarity ........................................................................................................... 73

Added note clarifying PLL1_WND_SIZE and impact on holdover exit................................................................................. 75

Changed references to deprecated software tools to point to TICS Pro.............................................................................. 78

Removed application curves section.................................................................................................................................... 79

Deleted unused column in typical current consumption table .............................................................................................. 80

Fixed truncated layout example image ................................................................................................................................ 82

已删除删除了弃用软件工具的链接....................................................................................................................................... 83

3

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

5 Device Comparison Table

Table 1. Device Configuration Information

PLL2

REF-

OSCout (BUFFERED

OSCin Clock) LVDS/

LVPECL/ LVCMOS

PROGRAMMABLE

LVDS/LVPECL

OUTPUTS

ERENCE

PART NUMBER

VCO0 FREQUENCY

VCO1 FREQUENCY

(1)

INPUTS⁽¹⁾

LMK04228

Up to 3

Up to 1

14

2370 to 2630 MHz

2920 to 3080 MHz

(1) OSCout may also be third clock input, CLKin2.

6 Pin Configuration and Functions

NKD Package

64-Pin WQFN

Top View

Clock Group 0

Clock Group 3

Status_LD2

Vcc10_PLL2

CPout2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DCLKout0

DCLKout0*

SDCLKout1

SDCLKout1*

RESET/GPO

SYNC/SYSREF_REQ

NC

1

2

3

Vcc9_CP2

OSCin*

4

5

OSCin

6

Vcc8_OSCin

7

NC

OSCout*/CLKin2*

OSCout/CLKin2

Vcc7_OSCout

8

LLP-64

Top down view

NC

9

Vcc1_VCO

LDObyp1

10

11

12

13

14

15

16

CLKin0*

LDObyp2

CLKin0

SDCLKout3

SDCLKout3*

DCLKout2

DCLKout2*

Vcc6_PLL1

CLKin1*/Fin*/FBCLKin*

DAP

CLKin1/Fin/FBCLKin

Vcc5_DIG

Clock Group 2

Clock Group 1

Pin Functions⁽¹⁾

I/O

TYPE

DESCRIPTION

NO.

1

NAME

DCLKout0

DCLKout0*

SDCLKout1

SDCLKout1*

O

Programmable

Device clock output 0.

2

3

SYSREF / Device clock output 1

4

(1) See Pin Connection Recommendations section for recommended connections.

4

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

Pin Functions⁽¹⁾(continued)

I/O

TYPE

DESCRIPTION

NO.

5

NAME

RESET/GPO

I

CMOS

—

Device reset input or GPO

6

SYNC/SYSREF_REQ

NC

I

Synchronization input or SYSREF_REQ for requesting continuous SYSREF.

Do not connect. These pins must be left floating.

Power supply for VCO LDO.

7, 8, 9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

—

Vcc1_VCO

LDObyp1

PWR

ANLG

LDO Bypass, bypassed to ground with 10-µF capacitor.

LDO Bypass, bypassed to ground with a 0.1-µF capacitor.

LDObyp2

SDCLKout3

SDCLKout3*

DCLKout2

DCLKout2*

Vcc2_CG1

CS*

O

Programmable

SYSREF / Device Clock output 3.

Device clock output 2.

—

I

PWR

CMOS

PWR

Power supply for clock outputs 2 and 3.

Chip Select

SCK

I

SPI Clock

SDIO

I/O

—

SPI Data

Vcc3_SYSREF

SDCLKout5

SDCKLout5*

DCLKout4

DCLKout4*

Vcc4_CG2

DCLKout6

DCLKout6*

SDCLKout7

SDCLKout7*

Status_LD1

CPout1

Power supply for SYSREF divider and SYNC.

O

Programmable

SYSREF / Device clock output 5.

O

—

O

Programmable

PWR

Device clock output 4.

Power supply for clock outputs 4, 5, 6 and 7.

Device clock output 6.

Programmable

O

Programmable

SYSREF / Device clock output 7.

I/O

O

Programmable

ANLG

Programmable status pin.

Charge pump 1 output.

Vcc5_DIG

CLKin1

—

PWR

Power supply for the digital circuitry.

I

ANLG

PWR

Reference Clock Input Port 1 for PLL1.

CLKin1*

Vcc6_PLL1

CLKin0

—

I

Power supply for PLL1, charge pump 1, holdover DAC

Reference Clock Input Port 0 for PLL1.

ANLG

CLKin0*

Vcc7_OSCout

OSCout/CLKin2

OSCout*/CLKin2*

Vcc8_OSCin

OSCin

—

O

—

I

PWR

Power supply for OSCout port.

Buffered output of OSCin port.

Reference Clock Input Port 2 for PLL1.

Power supply for OSCin

Programmable

PWR

ANLG

Feedback to PLL1, Reference input to PLL2. AC-coupled.

OSCin*

Vcc9_CP2

CPout2

—

O

PWR

ANLG

Power supply for PLL2 Charge Pump.

Charge pump 2 output.

Vcc10_PLL2

Status_LD2

SDCLKout9

SDCLKout9*

DCLKout8

DCLKout8*

Vcc11_CG3

DCLKout10

DCLKout10*

SDCLKout11

SDCLKout11*

CLKin_SEL0

CLKin_SEL1

SDCLKout13

SDCLKout13*

—

I/O

PWR

Power supply for PLL2.

Programmable

Programmable status pin.

O

Programmable

SYSREF / Device clock 9

O

—

O

Programmable

PWR

Device clock output 8.

Power supply for clock outputs 8, 9, 10, and 11.

Device clock output 10.

Programmable

O

Programmable

SYSREF / Device clock output 11.

I/O

Programmable

Programmable status pin.

O

Programmable

SYSREF / Device clock output 13.

5

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

I/O

TYPE

DESCRIPTION

NO.

62

63

64

—

NAME

DCLKout12

DCLKout12*

Vcc12_CG0

DAP

O

Programmable

Device clock output 12.

—

PWR

GND

Power supply for clock outputs 0, 1, 12, and 13.

DIE ATTACH PAD, connect to GND.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)(3)

MIN

–0.3

MAX

3.6

UNIT

V

(4)

V_CC

V_IN

T_L

Supply voltage

Input voltage

(V_CC+ 0.3)

+260

V

Lead temperature (solder 4 seconds)

Junction temperature

°C

T_J

150

Differential input current (CLKinX/X*,

OSCin/OSCin*)

I_IN

±5

mA

MSL

T_stg

Moisture sensitivity level

Storage temperature

3

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This device is a high performance RF integrated circuit with an ESD rating up to 2-kV Human Body Model, up to 150-V Machine Model,

and up to 250-V Charged Device Model and is ESD-sensitive. Handling and assembly of this device should only be done at ESD-free

workstations.

(3) Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress

ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation

sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

(4) Never to exceed 3.6 V.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

V_(ESD)

Electrostatic discharge

±250

±150

V

Machine model (MM)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX UNIT

T_J

Junction temperature

Ambient temperature

Supply voltage

125

85

°C

V

T_A

–40

25

V_CC

3.15

3.3

3.45

6

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

7.4 Thermal Information

LMK04228

THERMAL METRIC⁽¹⁾

NKD (WQFN)

UNIT

64 PINS

24.3

6.1

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

R_θJC(top)

R_θJB

3.5

ψ_JT

0.1

ψ_JB

3.5

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, Ψ_JBestimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

CURRENT CONSUMPTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{CC_PD}

Power-down supply current

Supply current⁽¹⁾

1

3

mA

14 LVDS clocks enabled

PLL1 and PLL2 locked.

I_{CC_CLKS}

485

CLKin0/0*, CLKin1/1*, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS

f_CLKin

Clock input frequency

Clock input slew rate⁽²⁾

0.001

0.15

400

MHz

V/ns

|V|

SLEW_CLKin

V_IDCLKin

20% to 80%

AC-coupled

0.5

Clock input

0.125

1.55

3.1

differential input voltage⁽³⁾

Figure 2

V_SSCLKin

0.25

Vpp

AC-coupled to CLKinX;

CLKinX* AC-coupled to Ground

CLKinX_TYPE = 0 (Bipolar)

0.25

2.4

Clock input

single-ended input voltage

V_CLKin

Vpp

AC-coupled to CLKinX;

CLKinX* AC-coupled to Ground

CLKinX_TYPE = 1 (MOS)

0.35

(1) See applications section Power Supply Recommendations for specific part configuration and how to calculate the I_CCfor a specific

design.

(2) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input

clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew

rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks,

differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their

common-mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve

optimal phase noise performance at the device outputs.

(3) See Differential Voltage Measurement Terminology for definition of V_IDand V_ODvoltages.

7

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Each pin AC-coupled, CLKin0/1/2

CLKinX_TYPE = 0 (Bipolar)

0

DC offset voltage between

CLKinX/CLKinX* (CLKinX* –

CLKinX)

Each pin AC-coupled, CLKin0/1

CLKinX_TYPE = 1 (MOS)

55

20

V_{CLKinX-offset}

|

|mV|

DC offset voltage between

CLKin2/CLKin2* (CLKin2* –

CLKin2)

Each pin AC-coupled

CLKinX_TYPE = 1 (MOS)

V_CLKin-V_IH

V_CLKin-V_IL

High input voltage

Low input voltage

DC-coupled to CLKinX;

CLKinX* AC-coupled to Ground

CLKinX_TYPE = 1 (MOS)

2

0

V_CC

0.4

V

PLL1 SPECIFICATIONS

f_PD1

PLL1 phase detector frequency

40

MHz

µA

V_CPout1= V_CC/2, PLL1_CP_GAIN = 0

V_CPout1= V_CC/2, PLL1_CP_GAIN = 1

V_CPout1= V_CC/2, PLL1_CP_GAIN = 2

…

50

150

250

PLL1 charge

I_CPout1SOURCE

pump source current⁽⁴⁾

…

V_CPout1= V_CC/2, PLL1_CP_GAIN = 14

V_CPout1= V_CC/2, PLL1_CP_GAIN = 15

V_CPout1=V_CC/2, PLL1_CP_GAIN = 0

V_CPout1=V_CC/2, PLL1_CP_GAIN = 1

V_CPout1=V_CC/2, PLL1_CP_GAIN = 2

…

1450

1550

–50

–150

–250

…

PLL1 charge

I_CPout1SINK

µA

pump sink current⁽⁴⁾

V_CPout1=V_CC/2, PLL1_CP_GAIN = 14

V_CPout1=V_CC/2, PLL1_CP_GAIN = 15

–1450

–1550

Charge pump

sink / source mismatch

I_CPout1%MIS

V_CPout1= V_CC/2, T = 25 °C

1%

4%

10%

Magnitude of charge pump

current variation vs. charge

pump voltage

0.5 V < V_CPout1< V_CC– 0.5 V

T_A= 25°C

I_CPout1V_TUNE

Charge pump current vs.

temperature variation

I_CPout1%TEMP

I_CPout1TRI

Charge pump TRI-STATE

leakage current

0.5 V < V_CPout< V_CC– 0.5 V

5

nA

PLL 1/f noise at 10-kHz offset.

Normalized to 1-GHz output

frequency

PLL1_CP_GAIN = 350 µA

PLL1_CP_GAIN = 1550 µA

–117

–118

PN10kHz

PN1Hz

dBc/Hz

PLL1_CP_GAIN = 350 µA

PLL1_CP_GAIN = 1550 µA

–221.5

–223

Normalized phase noise

contribution

dBc/Hz

PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS

f_OSCin

PLL2 reference input⁽⁵⁾

500

2.4

MHz

V/ns

PLL2 reference clock minimum

SLEW_OSCin

20% to 80%

0.15

0.2

0.5

(2)

slew rate on OSCin

Input voltage for OSCin or

OSCin*

AC-coupled; single-ended

(Unused pin AC-coupled to GND)

V_OSCin

Vpp

V_IDOSCin

V_SSOSCin

0.2

0.4

1.55

3.1

|V|

Differential voltage swing

See Figure 2

AC-coupled

Vpp

DC offset voltage between

OSCin/OSCin* (OSCinX* -

OSCinX)

|V_OSCin-offset

|

Each pin AC-coupled

20

|mV|

(4) This parameter is programmable

(5) F_OSCinmaximum frequency assured by characterization. Production tested at 122.88 MHz.

8

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

EN_PLL2_REF_2X = 1⁽⁷⁾

OSCin duty cycle 40% to 60%

MIN

TYP

MAX

UNIT

;

(6)

f_{doubler_max}

Doubler input frequency

155

MHz

CRYSTAL OSCILLATOR MODE SPECIFICATIONS

Fundamental mode crystal

ESR = 200 Ω (10 to 30 MHz)

ESR = 125 Ω (30 to 40 MHz)

F_XTAL

C_IN

Crystal frequency range

10

40

MHz

pF

Input capacitance of OSCin port –40°C to +85°C

1

PLL2 PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS

(6)

f_PD2

Phase detector frequency

155

MHz

µA

V_CPout2=V_CC/2, PLL2_CP_GAIN = 0

V_CPout2=V_CC/2, PLL2_CP_GAIN = 1

V_CPout2=V_CC/2, PLL2_CP_GAIN = 2

V_CPout2=V_CC/2, PLL2_CP_GAIN = 0

V_CPout2=V_CC/2, PLL2_CP_GAIN = 1

V_CPout2=V_CC/2, PLL2_CP_GAIN = 2

100

400

PLL2 charge pump source

I_CPoutSOURCE

(4)

current

1600

–100

–400

–1600

PLL2 charge pump sink current

I_CPoutSINK

µA

(4)

Charge pump sink/source

mismatch

I_CPout2%MIS

V_CPout2=V_CC/2, T_A= 25°C

1%

4%

10%

Magnitude of charge pump

current vs. charge pump

voltage variation

0.5 V < V_CPout2< V_CC– 0.5 V

T_A= 25°C

I_CPout2V_TUNE

Charge pump current vs.

temperature variation

I_CPout2%TEMP

I_CPout2TRI

Charge pump leakage

0.5 V < V_CPout2< V_CC– 0.5 V

PLL2_CP_GAIN = 1600 µA

10

nA

PLL 1/f noise at 10-kHz

offset⁽⁸⁾. Normalized to

1-GHz output frequency

PN10kHz

PN1Hz

–120

dBc/Hz

PLL2_CP_GAIN = 400 µA

PLL2_CP_GAIN = 1600 µA

–222.5

–224

Normalized phase noise

contribution⁽⁹⁾

dBc/Hz

MHz

INTERNAL VCO SPECIFICATIONS

VCO0

2370

2920

2630

3080

f_VCO

LMK04228 VCO tuning range

VCO1

LMK04228 VCO0 at 2370 MHz⁽¹⁰⁾

LMK04228 VCO0 at 2630 MHz⁽¹⁰⁾

LMK04228 VCO1 at 2920 MHz⁽¹⁰⁾

LMK04228 VCO1 at 3080 MHz⁽¹⁰⁾

17

27

17

23

LMK04228 fine tuning

sensitivity

K_VCO

MHz/V

(6) Assured by characterization. ATE tested at 122.88 MHz.

(7) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

(8) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker

noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10

kHz) – 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single-side band phase noise of only the flicker noise's contribution to total noise,

L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean

crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference

oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f)

and L_{PLL_flat}(f).

(9) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as:

PN1HZ=L_{PLL_flat}(f) – 20log(N) – 10log(f_PDX). L_{PLL_flat}(f) is the single-side band phase noise measured at an offset frequency, f, in a 1-Hz

bandwidth and f_PDXis the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(10) For frequencies in between, linearly interpolate to compute the typical Kvco

9

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ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

After programming for lock, no changes

to output configuration are permitted to

assure continuous lock

Allowable temperature drift for

continuous lock⁽¹¹⁾

|ΔT_CL

|

125

°C

NOISE FLOOR

LVDS

–156.3

–161.6

–162.5

–155.7

–160.3

–161.1

LMK04228, VCO0, noise floor

20-MHz offset⁽¹²⁾

L(f)_CLKout

245.76 MHz

LVPECL16 with 240 Ω

LVPECL20 with 240 Ω

LVDS

dBc/Hz

LMK04228, VCO1, noise floor

20-MHz offset⁽¹²⁾

L(f)_CLKout

LVPECL16 with 240 Ω

LVPECL20 with 240 Ω

CLKout CLOSED-LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹³⁾

Offset = 1 kHz

–115.2

–126.5

–128.3

–150.0

–157.9

–163.1

–115.1

–126.3

–127.5

–154.4

–157.9

–162.3

Offset = 10 kHz

LMK04228

Offset = 100 kHz

VCO0

L(f)_CLKout

dBc/Hz

SSB phase noise⁽¹²⁾

245.76 MHz

Offset = 1 MHz

LVDS

Offset = 10

MHz

LVPECL20 with 240 Ω

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

LMK04228

VCO1

L(f)_CLKout

SSB phase noise⁽¹²⁾

245.76 MHz

LVDS

Offset = 10

MHz

LVPECL20 with 240 Ω

CLKout CLOSED-LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹³⁾

LVDS, BW = 100 Hz to 20 MHz

256

183

LVDS, BW = 12 kHz to 20 MHz

LMK04228, VCO0

LVPECL20 /w 240 Ω,

f_CLKout= 245.76 MHz

Integrated RMS jitter

254

176

(12)

BW = 100 Hz to 20 MHz

LVPECL20 /w 240 Ω,

BW = 12 kHz to 20 MHz

J_CLKout

fs rms

LVDS, BW = 100 Hz to 20 MHz

246

162

LVDS, BW = 12 kHz to 20 MHz

LMK04228, VCO1

LVPECL16 with 240 Ω,

f_CLKout= 245.76 MHz

Integrated RMS jitter

245

156

(12)

BW = 100 Hz to 20 MHz

LVPECL20 with 240 Ω,

BW = 12 kHz to 20 MHz

(11) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was

at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of

programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over

the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be

necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed

at, the temperature can never drift outside the frequency range of –40°C to 85°C without violating specifications.

(12) Data collected using MACOM H-183-4 balun. Loop filter is C1 = 82 pF, C2 = 2.2 nF, R2 = 1800 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF,

R4 = 200 Ω, PLL1_CP = 650 µA, PLL2_CP = 1600 µA. VCO0 loop filter bandwidth = 176 kHz, phase margin = 67 degrees. VCO1 Loop

filter loop bandwidth = 169 kHz, phase margin = 66 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

(13) VCXO used is a 30.72 MHz (TXC Bex05).

10

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY

Default output clock frequency

at device power on

f_{CLKout-startup}

LMK04228

See⁽⁶⁾

315

MHz

(14)(15)

f_OSCout

OSCout frequency

500

25

CLOCK SKEW AND DELAY

DCLKoutX to SDCLKoutY

F_CLK= 245.76 MHz, R_L= 100 Ω

AC-coupled⁽¹⁶⁾

(17)

Same pair, same format

SDCLKoutY_MUX = 0 (device clock)

Maximum DCLKoutX or

SDCLKoutY

to DCLKoutX or SDCLKoutY

F_CLK= 245.76 MHz, R_L= 100 Ω

AC-coupled

|T_SKEW

|

|ps|

(17)

Any pair, same format

50

SDCLKoutY_MUX = 0 (device clock)

SDCLKoutY_MUX = 1 (SYSREF)

SYSREF_DIV = 30

SYSREF to device clock setup SYSREF_DDLY = 8 (global)

time base reference.

See SYSREF to Device Clock

SDCLKoutY_DDLY = 1 (2 cycles, local)

DCLKoutX_MUX = 1 (Div+DCC+HS)

ts_JESD204B

–80

ps

Alignment to adjust SYSREF to DCLKoutX_DIV = 30

device clock setup time as

required.

DCLKoutX_DDLY_CNTH = 7

DCLKoutX_DDLY_CNTL = 6

DCLKoutX_HS = 0

SDCLKoutY_HS = 0

CLKin0_OUT_MUX = 0 (SYSREF Mux)

SYSREF_CLKin0_MUX = 1 (CLKin0)

SDCLKout1_PD = 0

SDCLKout1_DDLY = 0 (Bypass)

SDCLKout1_MUX = 1 (SR)

EN_SYNC = 1

t_PDCLKin0_

SDCLKout1

Propagation delay from CLKin0

to SDCLKout1

0.65

ns

LVPECL16 with 240 Ω

Maximum analog delay

frequency

f_ADLYmax

DCLKoutX_MUX = 4

1250

MHz

LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout)

V_OD

Differential output voltage

395

|mV|

mV

V

Change in magnitude of V_ODfor

complementary output states

ΔV_OD

V_OS

–60

60

1.375

35

T = 25°C, DC measurement

AC-coupled to receiver input

R_L= 100-Ω differential termination

Output offset voltage

1.125

1.25

Change in V_OSfor

complementary output states

ΔV_OS

|mV|

Output rise time

Output fall time

20% to 80%, R_L= 100 Ω, 245.76 MHz

80% to 20%, R_L= 100 Ω

T_R/ T_F

180

ps

I_SA

I_SB

Output short-circuit current -

single-ended

Single-ended output shorted to GND

T = 25°C

–24

–12

24

12

mA

Output short-circuit current -

differential

I_SAB

Complementary outputs tied together

LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)

20% to 80% output rise

R_L= 100 Ω, emitter resistors = 240 Ω to

GND

T_R/ T_F

150

ps

DCLKoutX_TYPE = 4 or 5

(1600 or 2000 mVpp)

80% to 20% output fall time

1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)

(14) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(15) Default outputs on DCLKout4, DCLKout6, DCLKout8, DCLKout10 and OSCout.

(16) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid

for delay mode.

(17) LVPECL uses 120-Ω emitter resistor, LVDS uses 560-Ω shunt.

11

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ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CC

1.04

–

V_OH

V_OL

V_OD

Output high voltage

V

DC Measurement

Termination = 50 Ω to

V_CC– 2 V

V_CC

1.80

–

Output low voltage

V

Output voltage

See Figure 3

760

|mV|

2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)

V_CC

1.09

–

V_OH

V_OL

V_OD

Output high voltage

Output low voltage

V

DC Measurement

Termination = 50 Ω to V_CC– 2.3 V

V_CC

2.05

–

Output voltage

See Figure 3

960

|mV|

LVCMOS CLOCK OUTPUTS (OSCout)

f_CLKout

V_OH

V_OL

I_OH

Maximum frequency⁽¹⁸⁾

5-pF Load

250

MHz

V

Output high voltage

1-mA Load

V_CC– 0.1

Output low voltage

1-mA Load

0.1

V

Output high current (source)

Output low current (sink)

V_CC= 3.3 V, V_O= 1.65 V

28

mA

I_OL

V_CC/2 to V_CC/2,

F_CLK= 100 MHz, T = 25°C

DUTY_CLK

Output duty cycle⁽¹⁹⁾

50%

T_R

T_F

Output rise time

Output fall time

20% to 80%, R_L= 50 Ω, C_L= 5 pF

80% to 20%, R_L= 50 Ω, C_L= 5 pF

400

ps

DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO)

I_OH= –500 µA

CLKin_SELX_TYPE = 3 or 4

Status_LDX_TYPE = 3 or 4

RESET_TYPE = 3 or 4

V_OH

High-level output voltage

Low-level output voltage

V_CC– 0.4

V

I_OL= 500 µA

CLKin_SELX_TYPE = 3, 4, or 6

Status_LDX_TYPE = 3, 4, or 6

RESET_TYPE = 3, 4, or 6

V_OL

0.4

DIGITAL OUTPUT (SDIO)

I_OH= –500 µA ; during SPI read.

SDIO_RDBK_TYPE = 0

V_OH

V_OL

High-level output voltage

Low-level output voltage

V_CC– 0.4

V

I_OL= 500 µA ; during SPI read.

SDIO_RDBK_TYPE = 0 or 1

DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*)

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.2

–5

V_CC

0.4

V

DIGITAL INPUTS (CLKinX_SEL)

CLKin_SELX_TYPE = 0,

(high impedance)

5

High-level input current

V_IH= V_CC

I_IH

µA

CLKin_SELX_TYPE = 1 (pullup)

CLKin_SELX_TYPE = 2 (pulldown)

–5

10

5

80

CLKin_SELX_TYPE = 0,

(High Impedance)

–5

5

Low-level input current

V_IL= 0 V

I_IL

CLKin_SELX_TYPE = 1 (pullup)

CLKin_SELX_TYPE = 2 (pulldown)

–40

–5

5

(18) Assured by characterization. ATE tested to 10 MHz.

(19) Assumes OSCin has 50% input duty cycle.

12

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40°C < T_A< 85°C. Typical values at V_CC= 3.3 V, T_A= 25°C, at the Recommended Operating

Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

DIGITAL INPUT (RESET/GPO)

High-level input current

V_IH= V_CC

RESET_TYPE = 2

(pulldown)

I_IH

10

80

RESET_TYPE = 0 (high impedance)

RESET_TYPE = 1 (pullup)

RESET_TYPE = 2 (pulldown)

–5

–40

–5

5

-5

5

Low-level input current

V_IL= 0 V

I_IL

µA

DIGITAL INPUTS (SYNC)

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CC

V_IL= 0 V

25

5

µA

–5

DIGITAL INPUTS (SCK, SDIO, CS*)

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CC

V_IL= 0

–5

5

µA

DIGITAL INPUT TIMING

t_HIGH

RESET pin held high for device reset

25

ns

7.6 SPI Interface Timing

TEST CONDITIONS

MIN

10

TYP

MAX

UNIT

ns

td_s

Setup time for SDI edge to SCLK rising edge

Hold time for SDI edge from SCLK rising edge

See Figure 1

td_H

10

50⁽¹⁾

ns

t_SCLK

t_HIGH

t_LOW

tc_s

Period of SCLK

ns

High width of SCLK

25

ns

Low width of SCLK

25

ns

Setup time for CS* falling edge to SCLK rising edge

10

ns

tc_H

Hold time for CS* rising edge from SCLK rising edge See Figure 1

SCLK falling edge to valid read back data See Figure 1

30

ns

td_v

20

ns

(1) 20 MHz

7.7 Timing Diagram

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK

signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed.

A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete, the CS* signal

should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is

sometimes the case when these lines are shared with other parts. The phase noise may be degraded during this

programming.

Four-wire mode read back has same timing as SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 will be written as 0.

13

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ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Timing Diagram (continued)

SDIO

(WRITE)

A12 to A0,

D7 to D2

R/W

W1

W0

D1

D0

td_S

td_H

SCLK

tc_H

tc_S

t_HIGH

t_LOW

t_SCLK

SDIO

(Read)

D7 to

D2

D1

D0

Data valid only

during read

td_V

CS*

Figure 1. SPI Timing Diagram

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LMK04228

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ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

8 Parameter Measurement Information

8.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= V_CC– ΔV

I2 = Charge Pump Sink Current at V_CPout= V_CC/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= V_CC– ΔV

I5 = Charge Pump Source Current at V_CPout= V_CC/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

8.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage

8.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch

8.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature

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www.ti.com.cn

8.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader will be able to understand and distinguish between the

two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if an

input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V_SSand is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V_SScan be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V_ODas described in the first description.

Figure 2 illustrates the two different definitions side-by-side for inputs and Figure 3 illustrates the two different

definitions side-by-side for outputs. The V_IDand V_ODdefinitions show V_Aand V_BDC levels that the noninverting

and inverting signals toggle between with respect to ground. V_SSinput and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

V_IDDefinition

V_SSDefinition for Input

Non-Inverting Clock

V_A

V_B

2·V_ID

V_ID

Inverting Clock

V_ID= | V_A- V_B|

V_SS= 2·V_ID

GND

Figure 2. Two Different Definitions for

Differential Input Signals

V_ODDefinition

V_SSDefinition for Output

Non-Inverting Clock

V_A

V_B

2·V_OD

V_OD

Inverting Clock

V_OD= | V_A- V_B|

V_SS= 2·V_OD

GND

Figure 3. Two Different Definitions for

Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

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ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

9 Detailed Description

9.1 Overview

The LMK04228 is a highly flexible dual-PLL jitter cleaner and integrated VCO clock generator, providing up to 15

configurable outputs. The typical use case for LMK04228 is as a cascaded dual-loop jitter cleaner for JESD204B

systems. However traditional (non-JESD204B) systems are possible with use of the large SYSREF divider to

produce a low frequency. Device Clock outputs (DCLKoutX) provide configurable LVDS and LVPECL options,

while the OSCout output may be used to provide a buffered copy of a VCXO/Crystal signal in LVDS, LVPECL, or

LVCMOS formats.

The LMK04228 may be configured for single-loop mode by powering down unused blocks in PLL1.

9.1.1 Jitter Cleaning

The dual-loop PLL architecture of the LMK04228 provides the lowest jitter performance over a wide range of

output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external

reference clock and uses an external VCXO or tunable crystal to provide a frequency-accurate, low phase noise

reference clock for the second stage frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow loop bandwidth (typically between 10 Hz to 200 Hz) to retain the frequency

accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency

phase noise that the reference clock may have accumulated along its path or from other circuits. This cleaned

reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically

between 50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high

offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the

reference VCXO or tunable crystal.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO or crystal to dominate the final

output phase noise at low offset frequencies, and the phase noise of the internal VCO to dominate the final

output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

9.1.2 JEDEC JESD204B Support

The LMK04228 provides support for JEDEC JESD204B. The LMK04228 will clock up to 7 JESD204B targets

using 7 device clocks (DCLKoutX) and 7 SYSREF clocks (SDCLKoutY). Each device clock is grouped with a

SYSREF clock.

It is also possible to reprogram SYSREF clocks to behave as extra device clocks for applications which have

non-JESD204B clock requirements.

9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)

The LMK04228 has up to three reference clock inputs for PLL1 (CLKin0, CLKin1, and CLKin2). The active clock

is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the inputs.

CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers.

CLKin2 is shared for use as OSCout. To use as CLKin2, OSCout must be powered down. See VCO_MUX,

OSCout_FMT for more details.

Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1.

9.1.4 VCXO- and Crystal-Buffered Output

The LMK04228 provides OSCout, which by default is a buffered copy of the PLL1 feedback/PLL2 reference

input. This reference input is typically a low noise VCXO or crystal. When using a VCXO, this output can be used

to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04228 is

programmed.

The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

Once PLL1 lock is established, the buffered output of VCXO/crystal has a deterministic phase relationship with

the CLKin input used as the PLL1 reference.

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Overview (continued)

9.1.5 Frequency Holdover

The LMK04228 supports holdover operation to keep the clock outputs on frequency with minimum drift when the

reference is lost until a valid reference clock signal is re-established.

9.1.6 PLL2 Integrated Loop Filter Poles

The LMK04228 features programmable 3rd- and 4th-order loop filter poles for PLL2. These internal resistors and

capacitor values may be selected from a fixed range of values to achieve either a 3rd- or 4th-order loop filter

response. The integrated programmable resistors and capacitors complement larger external components

mounted near the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

9.1.7 Internal VCOs

The LMK04228 has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed to the

Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and

N-divider.

9.1.8 Clock Distribution

The LMK04228 features a total of 14 PLL2 clock outputs driven from the internal VCO.

All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL or LVDS formats.

The total number of clock outputs the LMK04228 is able to distribute, including OSCout, is up to 15 differential

clocks.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

9.1.8.1 Device Clock Divider

Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32

(even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this divider may also

be directed to SDCLKoutY, where Y = X + 1.

9.1.8.2 SYSREF Clock Divider

The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191

(even and odd).

9.1.8.3 Device Clock Delay

The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.

The analog delay allows a nominal 25-ps step size and range from 0 to 575 ps of granular delay. Enabling the

device clock analog delay adds a nominal 500-ps delay in addition to the programmed value.

The digital delay allows an output to be delayed from 3.5 to 32 VCO cycles. The delay step can be as small as

half the period of the clock distribution path. For example, 2-GHz VCO frequency results in 250-ps tuning steps.

The digital delay value takes effect on the clock outputs after a SYNC event. Fixed digital delay allows all the

outputs to have a known phase relationship upon a SYNC event and is typically performed at start-up.

9.1.8.4 SYSREF Delay

The global SYSREF divider includes a digital delay block which allows a global phase shift with respect to the

other clocks.

Each local SYSREF clock output includes both an analog and additional local digital delay for unique phase

adjustment of each SYSREF clock.

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Overview (continued)

The local analog delay allows for 150-ps steps, ranging from 600 ps to 2700 ps of granular delay. Enabling the

analog delay path adds a nominal 700 ps of delay in addition to the programmed value, and the first delay value

adds 600 ps.

The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from 1.5 to

11 VCO cycles. The delay step can be as small as half the period of the clock distribution path by using the

DCLKoutX_HS bit. For example, 2-GHz VCO frequency results in 250-ps coarse tuning steps.

9.1.8.5 Programmable Output Formats

For increased flexibility LMK04228 device and SYSREF clock outputs, DCLKoutX and SDCLKoutY, can be

programmed to an LVDS or LVPECL output type. The OSCout can be programmed to an LVDS, LVPECL, or

LVCMOS output type.

Any LVPECL output type can be programmed to 1600- or 2000-mVpp amplitude levels. The 2000-mVpp

LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential

swing for compatibility with many data converters and is also known as 2VPECL.

9.1.8.6 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital

delay.

The SYNC event must occur for digital delay values to take effect.

9.1.9 Status Pins

The LMK04228 provides status pins which can be monitored for feedback or in some cases used for input

depending upon device programming. For example:

•

The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKin0.

The CLKin_SEL1 pin may be an input for selecting the active clock input.

The Status_LD1 pin may indicate if the device is locked.

The Status_LD2 pin may indicate if PLL2 is locked.

The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL

lock detect signals, PLL1 Vtune railing, readback, and other internal status signals. Refer to the Programming

section of this data sheet for more information.

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9.2 Functional Block Diagrams

Figure 4 illustrate the complete LMK04228 block diagram.

CLKin0 R

CLKin0*

Status_LD1

Status_LD2

RESET/GPO

SYNC

Divider

(1 to 1,023)

CLKin0

R Delay

N Delay

CLKin

MUX

Device

Control

Phase

Detector

PLL1

CLKin_SEL0

CLKin_SEL1

CLKin1*

CLKin1

CLKin1 R

Divider

(1 to 1,023)

N1 Divider

(1 to 16,383)

SCLK

CLKin2 R

Divider

(1 to 1,023)

Control

Registers

SPI

SDIO

CS*

Holdover

2X

Partially

Integrated

Loop Filter

2X

Mux

R2 Divider

(1 to 31)

Internal Dual

Core VCO

Phase

Detector

PLL2

OSCout/

CLKin2

N2 Prescaler

(2 to 8)

N2 Divider

(1 to 255)

OSCout*/

CLKin2*

SPI

Selectable

Clock Distribution Path

VCO

MUX

OSCin*

OSCin

Div (1-32)

Dig. Delay

DCLKout12*

DCLKout12

A. Delay

Divider

(8 to 8191)

System Reference

Control

SDCLKout13*

SDCLKout13

SYNC

Dig. Delay

Div (1-32)

DCLKout0

Div (1-32)

DCLKout10*

DCLKout10

DCLKout0*

A. Delay

SDCLKout1

SDCLKout1*

SDCLKout11*

SDCLKout11

A. Delay

Div (1-32)

DCLKout2

DCLKout2*

Div (1-32)

DCLKout8

DCLKout8*

A. Delay

SDCLKout3

SDCLKout3*

Dig. Delay

SDCLKout9

SDCLKout9*

Dig. Delay

Div (1-32)

DCLKout4

DCLKout4*

Div (1-32)

DCLKout6

DCLKout6*

SDCLKout5

SDCLKout5*

Dig. Delay

SDCLKout7

SDCLKout7*

Dig. Delay

Figure 4. Detailed LMK04228 Block Diagram

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Functional Block Diagrams (continued)

DCLKoutX_DDLY_PD

DCLKoutX_ADLY_PD

DCLKout0, 2, 4, 6, 8, 10, 12

VCO

DDLY Divider

(4 to 32) (1 to 32)

HS/

DCC

DCLKoutX

_MUX

DCLKoutX_

FMT

DCLKoutX

_ADLY

_MUX

Analog

DLY

CLKoutX_Y_ODL

SYNC_

1SHOT_EN

CLKoutX_Y_IDL

SYSREF_GBL_PD

SDCLKoutY_DIS_MODE

One

Shot

SDCLKoutY

_POL

SYNC_

DISX

SDCLKoutY_PD

SDCLKoutY

_MUX

SDCLKoutY_

FMT

SDCLKoutY

_ADLY_EN

SYSREF/SYNC

Digital

DLY

Half

Step

Analog

DLY

SDCLKout1, 3, 5, 7, 9, 11, 13

CLKoutX_Y_PD

Legend

SYSREF/SYNC Clock

SYSREF_CLR

SPI Register

VCO/Distribution Clock

Figure 5. Device and SYSREF Clock Output Block

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Functional Block Diagrams (continued)

SPI Register: SYNC_EN

Must be set to enable any

SYNC/SYSREF functionality

CLKin0

_OUT

_MUX

CLKin0

PLL1

SYNC_PLL1_DLD

PLL1_DLD

SYNC_PLL2_DLD

PLL2_DLD

SYSREF_REQ_EN

D

Dist. Path

SYNC

_MODE

SYSREF

_MUX

SYNC

_POL

PULSER MODE

Pulser

SYSREF_PULSE_CNT

VCO0

VCO

SYSREF_PLSR_PD

SYSREF

_CLKin0

_MUX

Dist. Path

SYSREF SYSREF

DDLY Divider

_MUX

VCO1

SYNC/SYSREF

SYSREF_PD

SYSREF_DDLY_PD

OSCout

Buffer

OSCin

SYNC_

DISSYSREF

OSCout

DCLKout0, 2, 4, 6, 8, 10, 12

VCO Frequency

SYSREF/SYNC

DDLY

3.5 to 32

Divider

1 to 32

Analog

DLY

Output

DCC

Buffer

SYNC_

DISX

Digital

DLY

Analog

DLY

Output

Buffer

Legend

SYSREF_CLR

SYSREF/SYNC Clock

VCO/Distribution Clock

SPI Register

SDCLKout1, 3, 5, 7, 9, 11, 13

Figure 6. SYNC/SYSREF Clocking Paths

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9.3 Feature Description

9.3.1 SYNC/SYSREF

The SYNC and SYSREF signals share the same clocking path. To properly use SYNC and SYSREF for

JESD204B, it is important to understand the SYNC/SYSREF system. Figure 5 illustrates the detailed diagram of

a clock output block with SYNC circuitry included. Figure 6 illustrates the interconnects and highlights some

important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.

2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF

signal.

–

If SYSREF block is being used, the SYSREF_PD bit must be clear.

If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.

3. For each SDCLKoutY being used for SYSREF, respective SDCLKoutY_PD bits must be cleared.

4. SYSREF_DDLY_PD and DCLKoutX_DDLY_PD bits must be clear to power up the digital delay circuitry

during SYNC as use requires.

5. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX

register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding

SYNC_DISX bit is clear.

6. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.

Table 2 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 2. Some Possible SYNC Configurations

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

No SYNC will occur.

SYNC Disabled

0

CLKin0_OUT_MUX ≠ 0

Basic SYNC functionality, SYNC pin polarity is

selected by SYNC_POL.

To achieve SYNC through SPI, toggle the

SYNC_POL bit.

Pin or SPI SYNC

1

0

CLKin0_OUT_MUX ≠ 0

Differential input

SYNC

0 or 1

2

0 or 1

2

CLKin0_OUT_MUX = 0

Differential CLKin0 now operates as SYNC input.

Produce SYSREF_PULSE_CNT programmed

number of pulses on pin transition. SYNC_POL can

be used to cause SYNC through SPI.

JESD204B Pulser

on pin transition.

SYSREF_PULSE_CNT

sets pulse count

JESD204B Pulser

on SPI

programming.

SYSREF_PULSE_CNT

sets pulse count

Programming SYSREF_PULSE_CNT register starts

sending the number of pulses.

3

1

2

1

SYSREF operational,

SYSREF Divider as

required for training frame for non-JESD converters such as LM97600.

size.

Allows precise SYNC for n-bit frame training patterns

Re-clocked SYNC

When SYNC pin is asserted, continuous SYSERF

External SYSREF

request

SYSREF_REQ_EN = 1

Pulser powered up

pulses occur. Turning on and off of the pulses is

synchronized to prevent runt pulses from occurring on

SYSREF.

0

2

3

SYSREF_PD = 0

SYSREF_DDLY_PD = 0

Continuous

SYSREF

X

Continuous SYSREF signal.

SYSREF_PLSR_PD = 1

(1)

(1) SDCLKoutY_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SDCLKoutY when

SDCLKoutY_MUX = 1 (SYSREF output)

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Feature Description (continued)

Table 2. Some Possible SYNC Configurations (continued)

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

CLKin0_OUT_MUX = 0

SDCLKoutY_DDLY = 0

(Local sysref DDLY

bypassed)

SYSREF_DDLY_PD = 1

SYSREF_PLSR_PD = 1

SYSREF_PD = 1.

Direct SYSREF

distribution

A direct fan-out of SYSREF with no reclocking to

clock distribution path.

0

9.3.2 JEDEC JESD204B

9.3.2.1 How to Enable SYSREF

Table 3 summarizes the bits needed to make SYSREF functionality operational.

Table 3. SYSREF Bits

REGIS

TER

FIELD

VALUE

DESCRIPTION

Must be clear, power-up SYSREF circuitry.

0x140

SYSREF_PD

0

1

SYSREF_DDLY_

PD

0x140

0x143

Must be clear to power-up digital delay circuitry during initial SYNC to ensure deterministic timing.

Must be set, enable SYNC.

SYNC_EN

Do not hold local SYSREF DDLY block in reset except at start.

Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set

SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared,

SYSREF_CLR must be cleared to allow SYSREF to operate.

0x143

SYSREF_CLR

1 → 0

Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divider, then

configuring the actual SYSREF functionality.

9.3.2.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system which is to operate with a 3000-MHz VCO

frequency. Use DCLKout0 and DCLKout2 to drive converters at 750 MHz. Use DCLKout4 to drive an FPGA at

150 MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x1fff as desired. Key to prepare for SYSREF operations:

a. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0

b. Setup output dividers as per example: DCLKout0_DIV and DCLKout2_DIV = 4 for frequency of 750 MHz.

DCLKout4_DIV = 20 for frequency of 150 MHz.

c. Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF

d. Setup SYSREF: SYSREF_PD

=

0, SYSREF_DDLY_PD

=

0, DCLKout0_DDLY_PD

=

0,

DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0,

SYSREF_PULSE_CNT = 1 (2 pulses). SDCLKout1_PD = 0, SDCLKout3_PD = 0”

e. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B:

a. Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL,

DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL,

SYSREF_DDLY.

b. Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS.

c. Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY,

SDCLKout3_DDLY, SDCLKout5_DDLY.

d. To allow SYNC to effect dividers: SYNC_DIS0

SYNC_DISSYSREF = 0

= 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0,

e. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0.

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3. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for

SYSREF to reset its own divider or the dividers of the output clocks.

a. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,

SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay.

a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 VCO clocks after SYSREF_PD = 0.

5. Set SYSREF operation.

a. Allow pin SYNC event to start pulser: SYNC_MODE = 2.

b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. Complete! Now asserting the SYNC pin, or toggling SYNC_POL will result in a series of 2 SYSREF pulses.

9.3.2.1.2 SYSREF_CLR

The local digital delay of the SDCLKout is implemented as a shift buffer. To ensure no unwanted pulses occur at

this SYSREF output at start-up, when using SYSREF, requires clearing the buffers by setting SYSREF_CLR = 1

for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF output is used.

9.3.2.2 SYSREF Modes

9.3.2.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming.

This implements the gapped periodic functionality of the JEDEC JESD204B specification.

When in SYSREF Pulser mode, programming the field SYSREF_PULSE_CNT in register 0x13E will result in the

pulser sending the programmed number of pulses.

9.3.2.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock.

JESD204B is designed to operate with a single burst of pulses to initialize the system at start-up, after which it is

theoretically not required to send another SYSREF because the system will continue to operate with

deterministic phases.

If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or

SYSREF from the OSCout pin to minimize crosstalk.

9.3.2.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses

using the SYNC/SYSREF_REQ pin.

Set up the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not

need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX will synchronously be set to continuous mode

providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is unasserted and the final

SYSREF pulse will complete sending synchronously.

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9.3.3 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 4 to 32 VCO cycles. The delay step can be as

small as half the period of the VCO cycle by using the DCLKoutX_HS bit. It is fixed digital delay.

The regular clock divider is substituted with an alternative divide value. The substitute divide value consists of

two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum _CNTH/_CNTL value is 2 and

the maximum _CNTH/_CNTL value is 16. This will result in a minimum alternative divide value of 4 and a

maximum of 32.

9.3.3.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW

for a while during the SYNC event.

9.3.3.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations, and the application should delay DCLKout2

by one VCO cycle compared to DCLKout0.

•

VCO frequency = 2949.12 MHz

DCLKout0 = 368.64 MHz (DCLKout0_DIV = 8)

DCLKout2 = 368.64 MHz (DCLKout2_DIV = 8)

The following steps should be followed

1. Set DCLKout0_DDLY_CNTH = 4 and DCLKout2_DDLY_CNTH = 4. First part of delay for each clock.

2. Set DCLKout0_DDLY_CNTL = 4 and DCLKout2_DDLY_CNTL = 5. Second part of delay for each clock.

3. Set DCLKout2_DDLY_PD = 0 and DCLKout2_DDLY_PD = 0. Power up the digital delay circuit.

4. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the output to be synchronized.

5. Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.

6. Power down DCLKout2_DDLY_PD = 0 and/or DCLKout2_DDLY_PD = 1 to save power now that the SYNC

is complete.

7. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1 to prevent the output from being synchronized; this step is very

important for steady-state operation when using JESD204B.

No CLKout during SYNC

DCLKout0

368.64 MHz

DCLKout2

368.64 MHz

SYNC event

1 VCO cycle delay

Figure 7. Fixed Digital Delay Example

Table 4 shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting

for delay by one VCO cycle. The clock will output high during the DCLKoutX_DDLY_CNTH time to permit a

continuous output clock. The clock output will be low during the DCLKoutX_DDLY_CNTL time.

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Table 4. Recommended DCLKoutX_DDLY_CNTH/_CNTL Values for Delay by One VCO Cycle

CLOCK DIVIDER

_CNTH

_CNTL

CLOCK DIVIDER

_CNTH

9

_CNTL

9

2

3

2

3

2

3

4

5

6

7

8

3

4

3

4

5

6

7

8

9

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

9

10

4

10

5

10

11

6

11

7

11

12

8

12

9

12

13

10

11

12

13

14

15

16

13

14

15

16⁽¹⁾

(1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.

9.3.4 SYSREF to Device Clock Alignment

To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must

be adjusted for optimum setup and hold time. The ts_JESD204Bdefines the time between SYSREF and Device

Clock for a specific condition of SYSREF divider and Device Clock digital delay. From this point, the

SYSREF_DDLY. SDCLKoutY_DDLY, DCLKoutX_DDLY_CNTH, DCLKoutDDLY_CNTL, and DCLKoutX_MUX,

SDCKLoutX_ADLY, and so forth, can be adjusted to provide the required setup and hold time between SYSREF

and Device Clock.

It is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF. So for example with a

2949.12-MHz VCO frequency, ts_JESD204B+ 20 × (1/VCO Frequency) = –80 ps + 20 × (1/2949.12 MHz) = 6.7 ns.

9.3.5 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the

CLKin_SEL_MODE register.

The following subsections have information about how the active input clock is selected and what causes a

switching event in the various clock input selection modes.

9.3.5.1 Input Clock Switching - Manual Mode

When CLKin_SEL_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2, respectively, is always selected as the

active input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate

even if CLKinX is disabled with EN_CLKinX = 0.

If holdover is entered in this mode, then the device will relock to the selected CLKin upon holdover exit.

9.3.5.2 Input Clock Switching - Pin Select Mode

When CLKin_SEL_MODE is 3, the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active.

9.3.5.2.1 Configuring Pin Select Mode

The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input

for pin select mode.

The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input

for pin select mode.

If the CLKin_SELX_TYPE is set as output, the pin input value is considered Low.

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The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit.

Table 5 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state.

Table 5. Active Clock Input - Pin Select Mode, CLKin_SEL_INV = 0

PIN CLKin_SEL1

PIN CLKin_SEL0

ACTIVE CLOCK

CLKin0

Low

High

Low

High

Low

High

CLKin1

CLKin2

Holdover

The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is

disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX =

1) that could be switched to.

9.3.5.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_MODE is 4, the active clock is selected in round-robin order of enabled clock inputs starting

upon an input clock switch event. The switching order of the clocks is CLKin0 → CLKin1 → CLKin2 → CLKin0,

and so forth.

For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.

9.3.5.3.1 Starting Active Clock

Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a

particular clock input is the active clock when starting this mode, program CLKin_SEL_MODE to the manual

mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select

this mode with CLKin_SEL_MODE = 4.

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9.3.6 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference

path (R) and the feedback path (N) of the PLL. When the time error (and therefore the phase error) between the

two signals is less than a window size (ε) specified by PLL1_WND_SIZE and PLL2_WND_SIZE, a lock detect

count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or

PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside

the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 8.

NO

PLLX

Lock Detected = False

Lock Count = 0

YES

Increment

PLLX Lock Count

PLLX

Lock Detected = True

PLLX Lock Count =

PLLX_DLD_CNT

START

Phase Error < g

YES

NO

Figure 8. Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for

only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial

phase lock.

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to

achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be

programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

NOTE

In cases where the period of the phase detector frequency approaches the value of the

default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with

the default value of PLL1_WND_SIZE. For phase detector frequencies at or above 25

MHz, TI recommends setting PLL1_WND_SIZE to 0x02 (19 ns) or a smaller value.

9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to

achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting

Holdover for more information.

9.3.7 Holdover

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock

reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed

tuning voltage is set on CPout1 to operate PLL1 in open-loop.

9.3.7.1 Enable Holdover

Program HOLDOVER_EN = 1 to enable holdover mode.

Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage

or a tracked voltage.

9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode

By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover.

The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value,

then reprogram MAN_DAC value to a user desired value based on information from previous DAC read backs.

This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.

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9.3.7.1.2 Tracked CPout1 Holdover Mode

By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 will be set on the

CPout1 pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is

set which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or

PLL2_LD_MUX respectively.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector

frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR).

The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy.

The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024-

kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the

device to look-back and set CPout1 at the previous good CPout1 tuning voltage values before the event which

caused holdover to occur.

The current voltage of DAC value can be read back using RB_DAC_VALUE, see RB_DAC_VALUE.

9.3.7.2 During Holdover

PLL1 is run in open-loop mode.

•

PLL1 charge pump is set to TRI-STATE.

PLL1 DLD will be unasserted.

The HOLDOVER status is asserted

During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD will continue to be asserted.

CPout1 voltage will be set to:

–

a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).

a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).

•

PLL1 will attempt to lock with the active clock input.

The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the

PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.

9.3.7.3 Exiting Holdover

Holdover mode can be exited in one of two ways.

•

Manually by programming the device from the host.

Automatically by a clock operating within a specified ppm of the current PLL1 frequency on the active clock

input.

9.3.7.4 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 will run in open-loop and the DAC will set the CPout1 voltage. If Fixed CPout1

mode is used, then the output of the DAC will be a voltage dependant upon the MAN_DAC register. If Tracked

CPout1 mode is used, then the output of the DAC will be the voltage at the CPout1 pin before holdover mode

was entered. When using Tracked mode and MAN_DAC_EN = 1, during holdover the DAC value is loaded with

the programmed value in MAN_DAC, not the tracked value.

When in Tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs once PLL1 tuning voltage

is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode

caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use.

Therefore, the accuracy of the system when in holdover mode in ppm is:

6.4 mV × Kv × 1e6

Holdover accuracy (ppm) =

VCXO Frequency

(1)

Example: consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The

accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

(2)

Take this frequency error into account when determining the allowable frequency error window to cause holdover

mode to exit.

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9.3.7.5 Holdover Mode - Automatic Exit of Holdover

The LMK048xx device can be programmed to automatically exit holdover mode when the accuracy of the

frequency on the active clock input achieves a specified accuracy. The programmable variables include

PLL1_WND_SIZE and DLD_HOLD_CNT.

See Digital Lock Detect Frequency Accuracy to calculate the register values to cause holdover to automatically

exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.

It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the

reference and feedback signals to have a time and phase error less than a programmable value. Because it is

possible for two clock signals to be very close in frequency but not close in phase, it may take a long time for the

phases of the clocks to align themselves within the allowable time and phase error before holdover exits.

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9.4 Programming

LMK04228 devices are programmed using 24-bit registers. Each register consists of a 1-bit command field

(R/W), a 2-bit multi-byte field (W1, W0), a 13-bit address field (A12 to A0) and a 8-bit data field (D7 to D0). The

contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS*

signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in,

the CS* signal goes high to latch the contents into the shift register. It is recommended to program registers in

numeric order -- for example, 0x000 to 0x1FFF -- to achieve proper device operation. Each register consists of

one or more fields which control the device functionality. See electrical characteristics and Figure 1 for timing

details.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 shall be written as 0.

9.4.1 Recommended Programming Sequence

Registers are programmed in numeric order with 0x000 being the first and 0x1FFF being the last register

programmed. TI recommends the following programming sequence:

1. Program register 0x000 with RESET = 1.

2. Program registers in ascending order from 0x000 to 0x165. Unused or unchanged registers can be skipped,

and will remain at default POR values.

3. Program register 0x171 to 0xAA and 0x172 to 0x02.

4. Program registers 0x17C and 0x17D.

5. Program registers 0x166 to 0x1FFF.

Program register 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in registers: 0x166,

0x167, and 0x168 to optimize VCO1 phase noise performance over temperature.

9.4.1.1 SPI LOCK

When writing to SPI_LOCK, registers 0x1FFD, 0x1FFE, and 0x1FFF should all always be written sequentially.

9.4.1.2 SYSREF_CLR

When using SYSREF output, SYSREF local digital delay block should be cleared using SYSREF_CLR bit. See

SYSREF_CLR for more information.

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9.5 Register Maps

9.5.1 Register Map for Device Programming

Table 6 provides the register map for device programming. Any register can be read from the same data address

it is written to.

Table 6. LMK04228 Register Map

ADDRESS

[20:8]

DATA

7

6

5

4

3

2

1

0

SPI_3WIRE

_DIS

0x000

0x002

RESET

0

POWER

DOWN

0

0x003

0x004

0x005

0x006

0x00C

0x00D

ID_DEVICE_TYPE

ID_PROD[15:8]

ID_PROD[7:0]

ID_MASKREV

ID_VNDR[15:8]

ID_VNDR[7:0]

CLKout0_1

_ODL

CLKout0_1

_IDL

0x100

0x101

0x103

0

DCLKout0_DIV

DCLKout0_DDLY_CNTH

DCLKout0_ADLY

SDCLKout1

DCLKout0_DDLY_CNTL

DCLKout0_

DCLKout0_MUX

ADLY_MUX

SDCLKout1_DDLY

SDCLKout1_ADLY

SDCLKout1_DIS_MODE

CLKout0_FMT

DCLKout0

_HS

SDCLKout1

_HS

0x104

0x105

0x106

0x107

0

_MUX

SDCLKout1_

ADLY_EN

0

CLKout0_1

_PD

SDCLKout1

_PD

DCLKout0

_ DDLY_PD

DCLKout0

_ADLY _PD

1

SDCLKout1

_POL

DCLKout0

_POL

CLKout1_FMT

CLKout2_3

_ODL

CLKout2_3

_IDL

0x108

0x109

0x10B

0

DCLKout2_DIV

DCLKout2_DDLY_CNTH

DCLKout2_ADLY

SDCLKout3

DCLKout2_DDLY_CNTL

DCLKout2_

DCLKout2_MUX

ADLY_MUX

SDCLKout3_DDLY

SDCLKout3_ADLY

SDCLKout3_DIS_MODE

CLKout2_FMT

DCLKout2

_HS

SDCLKout3

_HS

0x10C

0x10D

0x10E

0x10F

0

_MUX

SDCLKout3

_ ADLY_EN

0

DCLKout2

_ DDLY_PD

DCLKout2

_ADLY _PD

CLKout2_3

_PD

SDCLKout3

_PD

1

SDCLKout3

_POL

DCLKout2

_POL

CLKout3_FMT

CLKout4_5

_ODL

CLKout4_5

_IDL

0x110

0x111

0x113

0

DCLKout4_DIV

DCLKout4_DDLY_CNTH

DCLKout4_ADLY

SDCLKout5

DCLKout4_DDLY_CNTL

DCLKout4_

DCLKout4_MUX

ADLY_MUX

SDCLKout5_DDLY

SDCLKout5_ADLY

SDCLKout5_DIS_MODE

CLKout4_FMT

DCLKout4

_HS

SDCLKout5

_HS

0x114

0x115

0x116

0x117

0x118

0

_MUX

SDCLKout5

_ ADLY_EN

0

DCLKout4

_ DDLY_PD

DCLKout4

_ADLY _PD

CLKout4_5

_PD

SDCLKout5

_PD

1

SDCLKout5

_POL

DCLKout4

_POL

CLKout5_FMT

CLKout6_7

_ODL

CLKout6_7

_IDL

0

DCLKout6_DIV

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Register Maps (continued)

Table 6. LMK04228 Register Map (continued)

ADDRESS

[20:8]

DATA

7

6

5

4

3

2

1

0

0x119

DCLKout6_DDLY_CNTH

DCLKout6_ADLY

SDCLKout7

DCLKout6_DDLY_CNTL

DCLKout6_

0x11B

0x11C

0x11D

0x11E

0x11F

DCLKout6_MUX

ADLY_MUX

SDCLKout7_DDLY

SDCLKout7_ADLY

SDCLKout7_DIS_MODE

CLKout6_FMT

DCLKout6

_HS

SDCLKout7

_HS

0

_MUX

SDCLKout7

_ ADLY_EN

0

DCLKout6

_ DDLY_PD

DCLKout6

_ADLY _PD

CLKout6_7

_PD

SDCLKout7

_PD

1

SDCLKout7

_POL

CLKout7

_FMT

DCLKout6

_POL

CLKout8_9

_ODL

CLKout8_9

_IDL

0x120

0x121

0x123

0

DCLKout8_DIV

DCLKout8_DDLY_CNTH

DCLKout8_ADLY

SDCLKout9

DCLKout8_DDLY_CNTL

DCLKout8

DCLKout8_MUX

_ ADLY_MUX

SDCLKout9_DDLY

SDCLKout9_ADLY

SDCLKout9_DIS_MODE

CLKout8_FMT

DCLKout8

_HS

SDCLKout9

_HS

0x124

0x125

0x126

0x127

0

_MUX

SDCLKout9

_ ADLY_EN

0

DCLKout8

_ DDLY_PD

DCLKout8

_ADLY _PD

CLKout8_9

_PD

SDCLKout9

_PD

1

SDCLKout9

_POL

DCLKout8

_POL

CLKout9_FMT

CLKout10

_11 _ODL

CLKout10

_11_IDL

0x128

0x129

0x12B

0

DCLKout10_DIV

DCLKout10_DDLY_CNTH

DCLKout10_ADLY

SDCLKout11

DCLKout10_DDLY_CNTL

DCLKout10

DCLKout10_MUX

_ ADLY_MUX

SDCLKout11_DDLY

SDCLKout11_ADLY

SDCLKout11_DIS_MODE

CLKout10_FMT

DCLKout10

_HS

SDCLKout11

_HS

0x12C

0x12D

0x12E

0x12F

0

_MUX

SDCKLout11

_ ADLY_EN

0

DCLKout10

_ DDLY_PD

DCLKout10

_ ADLY_PD

CLKout10

_11_PD

SDCLKout11

_PD

1

SDCLKout11

_POL

DCLKout10

_POL

CLKout11_FMT

CLKout12

_13 _ODL

CLKout12

_13_IDL

0x130

0x131

0x133

0

DCLKout12_DIV

DCLKout12_DDLY_CNTH

DCLKout12_ADLY

SDCLKout13

DCLKout12_DDLY_CNTL

DCLKout12_

DCLKout12_MUX

ADLY_MUX

SDCLKout13_DDLY

SDCLKout13_ADLY

SDCLKout13_DIS_MODE

CLKout12_FMT

DCLKout12

_HS

SDCLKout13

_HS

0x134

0x135

0x136

0

_MUX

SDCLKout13

_ ADLY_EN

0

DCLKout12

_ DDLY_PD

DCLKout12

_ ADLY_PD

CLKout12

_13_PD

SDCLKout13

_PD

1

SDCLKout13

_POL

DCLKout12

_POL

0x137

0x138

0x139

CLKout13_FMT

0

VCO_MUX

0

OSCout_FMT

SYSREF_

0

SYSREF_MUX

CLKin0_MUX

0x13A

0x13B

0x13C

0x13D

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

0

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

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Register Maps (continued)

Table 6. LMK04228 Register Map (continued)

ADDRESS

DATA

[20:8]

7

6

5

4

3

2

1

0

0x13E

0

SYSREF_PULSE_CNT

SYSREF_GBL

_PD

SYSREF

_DDLY_PD

SYSREF

_PLSR_PD

0x140

0x143

0x144

PLL1_PD

VCO_LDO_PD

VCO_PD

SYNC_POL

SYNC_DIS10

OSCin_PD

SYNC_EN

SYNC_DIS8

SYSREF_PD

SYSREF_DDLY SYNC_1SHOT

SYNC_PLL2

_DLD

SYNC_PLL1

_DLD

SYNC_MODE

_CLR

_EN

SYNC

_DISSYSREF

SYNC_DIS12

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0x145

0x146

0

1

0

CLKin2_EN

CLKin1_EN

CLKin0_EN

CLKin2_TYPE

CLKin1_TYPE

CLKin0_TYPE

CLKin_SEL

_POL

0x147

0x148

0x149

0x14A

0x14B

CLKin_SEL_MODE

CLKin1_OUT_MUX

CLKin0_OUT_MUX

0

CLKin_SEL0_MUX

CLKin_SEL1_MUX

RESET_MUX

CLKin_SEL0_TYPE

CLKin_SEL1_TYPE

RESET_TYPE

SDIO_RDBK

_TYPE

0

HOLDOVER

_ FORCE

MAN_DAC

_EN

LOS_TIMEOUT

LOS_EN

TRACK_EN

MAN_DAC[9:8]

0x14C

0x14D

0x14E

0x14F

MAN_DAC[7:0]

0

DAC_TRIP_LOW

DAC_TRIP_HIGH

DAC_CLK_MULT

DAC_CLK_CNTR

HOLDOVER

_HITLESS

_SWITCH

CLKin

_OVERRIDE

HOLDOVER

_ PLL1_DET

HOLDOVER

_LOS _DET

HOLDOVER

_VTUNE_DET

HOLDOVER

_EN

0x150

0

0x151

0x152

0x153

0x154

0x155

0x156

0x157

0x158

0x159

0x15A

0

HOLDOVER_DLD_CNT[13:8]

HOLDOVER_DLD_CNT[7:0]

0

CLKin0_R[9:8]

CLKin0_R[7:0]

CLKin1_R[7:0]

CLKin2_R[7:0]

PLL1_N[7:0]

CLKin1_R[9:8]

CLKin2_R[9:8]

PLL1_N[11:8]

PLL1

_CP_TRI

PLL1

_CP_POL

0x15B

PLL1_WND_SIZE

PLL1_CP_GAIN

0x15C

0x15D

0x15F

0x161

0

PLL1_DLD_CNT[13:8]

PLL1_DLD_CNT[7:0]

PLL1_LD_MUX

0

PLL1_LD_TYPE

0

PLL2_R[4:0]

PLL2

_XTAL_EN

PLL2

_REF_2X_EN

0x162

PLL2_P

OSCin_FREQ

PLL2_FCAL

_DIS

0x166

0x168

0x169

0

PLL2_N[7:0]

PLL2_CP_GAIN

PLL2

_CP_POL

PLL

2_CP_TRI

0

PLL2_WND_SIZE

1

SYSREF_REQ_

EN

0x16A

PLL2_DLD_CNT[15:8]

0x16B

0x16C

0x16D

0x16E

PLL2_DLD_CNT[7:0]

PLL2_LF_R4

0

PLL2_LF_R3

PLL2_LF_C4

PLL2_LD_MUX

PLL2_LF_C3

PLL2_LD_TYPE

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Register Maps (continued)

Table 6. LMK04228 Register Map (continued)

ADDRESS

[20:8]

DATA

7

1

0

6

5

4

0

3

1

0

2

0

1

0

0x171

0

1

0

0x172

0

0x173

PLL2_PRE_PD

PLL2_PD

0x17C

0x17D

OPT_REG_1

OPT_REG_2

RB_PLL1_

LD_LOST

CLR_PLL1_

LD_LOST

0x182

0x183

0

RB_PLL1_LD

RB_PLL2_LD

RB_PLL2_

LD_LOST

CLR_PLL2_

LD_LOST

RB_CLKin2_

SEL

RB_CLKin1_

SEL

RB_CLKin0_

SEL

RB_CLKin1_

LOS

RB_CLKin0_

LOS

0x184

0x185

0x188

RB_DAC_VALUE[9:8]

X

RB_DAC_VALUE[7:0]

RB_

HOLDOVER

0

X

0x1FFD

0x1FFE

0x1FFF

SPI_LOCK[23:16]

SPI_LOCK[15:8]

SPI_LOCK[7:0]

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9.5.2 Device Register Descriptions

The following section details the fields of each register, the poweron-reset (POR) defaults, and specific

descriptions of each bit.

In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as

X or Y. In these cases the X will represent even numbers from 0 to 12 and the Y will represent odd numbers

from 1 to 13. In the case where X and Y are both used in a bit name, then Y = X + 1.

9.5.2.1 System Functions

9.5.2.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function.

Table 7. Register 0x000

POR

DEFAULT

BIT

NAME

DESCRIPTION

0: Normal Operation

1: Reset (automatically cleared)

7

RESET

NA

0

6:5

Reserved

Disable 3 wire SPI mode. 4 Wire SPI mode is enabled by selecting SPI Read back in one

of the output MUX settings. For example CLKin0_SEL_MUX.

0: 3 Wire Mode enabled

4

SPI_3WIRE_DIS

NA

0

1: 3 Wire Mode disabled

3:0

NA

Reserved

9.5.2.1.2 POWERDOWN

This register contains the POWERDOWN function.

Table 8. Register 0x002

POR

DEFAULT

BIT

7:1

0

NAME

NA

DESCRIPTION

0

Reserved

0: Normal Operation

1: Powerdown

POWERDOWN

0

9.5.2.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

Table 9. Register 0x003

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

ID_DEVICE_TYPE

6

PLL product device type.

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9.5.2.1.4 ID_PROD[15:8], ID_PROD

These registers contain the product identifier. This is read only register.

Table 10. ID_PROD Register Configuration, ID_PROD[15:0]

MSB

LSB

0x004[7:0]

0x005[7:0]

Table 11. Registers 0x004, 0x005

POR

BIT REGISTERS

FIELD NAME

DESCRIPTION

DEFAULT

208

91

7:0

0x004

0x005

ID_PROD[15:8]

ID_PROD

MSB of the product identifier.

LSB of the product identifier.

9.5.2.1.5 ID_MASKREV

This register contains the IC version identifier. This is read only register.

Table 12. Register 0x006

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

ID_MASKREV

32

IC version identifier for LMK04228

9.5.2.1.6 ID_VNDR[15:8], ID_VNDR

These registers contain the vendor identifier. This is read only register.

Table 13. ID_VNDR Register Configuration, ID_VNDR[15:0]

MSB

LSB

0x00C[7:0]

0x00D[7:0]

Table 14. Registers 0x00C, 0x00D

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:0

0x00C

0x00D

ID_VNDR[15:8]

ID_VNDR

81

MSB of the vendor identifier.

LSB of the vendor identifier.

4

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9.5.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV

These registers control the input and output drive level as well as the device clock out divider values.

Table 15. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

6

5

NA

0

Reserved

CLKoutX_Y_ODL

CLKoutX_Y_IDL

Output drive level.

Input drive level.

DCLKoutX_DIV sets the divide value for the clock output, the divide may be even or odd.

Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is

selected.

Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.

X = 0 → 2

X = 2 → 4

X = 4 → 8

X = 6 → 8

X = 8 → 8

X = 10 → 8

X = 12 → 2

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divider Value

32

4:0

DCLKoutX_DIV

(1)

1

2

...

30 (0x1E)

31 (0x1F)

30

31

(1) Not valid if DCLKoutX_MUX = 0, Divider only. Not valid if DCLKoutX_MUX = 3 (Analog Delay + Divider) and DCLKoutX_ADLY_MUX =

0 (without duty cycle correction/halfstep).

9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL

This register controls the digital delay high and low count values for the device clock outputs.

Table 16. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

POR

DEFAULT

BIT

NAME

DESCRIPTION

Number of clock cycles the output will be high when digital delay is engaged.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Values

16

DCLKoutX

_DDLY_CNTH

7:4

5

Reserved

2

...

15 (0x0F)

15

Number of clock cycles the output will be low when digital delay is engaged.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Values

16

DCLKoutX

_DDLY_CNTL

3:0

5

Reserved

2

...

15 (0x0F)

15

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9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX

These registers control the analog delay properties for the device clocks.

Table 17. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

POR

DEFAULT

BIT

NAME

DESCRIPTION

Device clock analog delay value. Setting this value results in a 500 ps timing delay in

additional to the delay of each 25 ps step. Effective range is 500 ps to 1075 ps.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Value

0 ps

7:3

DCLKoutX_ALDY

0

25 ps

50 ps

...

23 (0x17)

575 ps

This register selects the input to the analog delay for the device clock. Used when

DCLKoutX_MUX = 3.

0: Divided without duty cycle correction or half step.

DCLKoutX_ADLY

_MUX

2

0

(1)

1: Divided with duty cycle correction and half step.

This selects the input to the device clock buffer.

Field Value

Mux Output

(1)

0 (0x0)

Divider only

1:0

DCLKoutX_MUX

Divider with Duty Cycle Correction

and Half Step

1 (0x1)

2 (0x2)

3 (0x3)

Reserved

Analog Delay + Divider

(1) DCLKoutX_DIV = 1 is not valid.

9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay,

and half step.

Table 18. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

Sets the device clock half step value. Half step must be zero (0) for a divide of 1.

6

5

DCLKoutX_HS

0

0: 0 cycles

1: -0.5 cycles

Sets the input the the SDCLKoutY outputs.

0: Device clock output

SDCLKoutY_MUX

1: SYSREF output

Sets the number of VCO cycles to delay the SDCLKout by.

Field Value

0 (0x00)

Delay Cycles

Bypass

1 (0x01)

2

4:1

SDCLKoutY_DDLY

SDCLKoutY_HS

0

2 (0x02)

3

...

10 (0x0A)

11

11 to 15 (0x0B to 0x0F)

Reserved

Sets the SYSREF clock half step value.

0: 0 cycles

0

1: -0.5 cycles

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9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

Table 19. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:5

NA

0

Reserved

Enables analog delay for the SYSREF output.

0: Disabled

1: Enabled

SDCLKoutY

_ADLY_EN

4

Sets the analog delay value for the SYSREF output. Selecting analog delay adds an

additional 700 ps in propagation delay. Effective range is 700 ps to 2950 ps.

Field Value

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

...

Delay Value

0 ps

600 ps

SDCLKoutY

_ADLY

3:0

0

750 ps (+150 ps from 0x1)

900 ps (+150 ps from 0x2)

...

14 (0xE)

15 (0xF)

2550 ps (+150 ps from 0xD)

2700 ps (+150 ps from 0xE)

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9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD

This register controls the power down functions for the digital delay, analog delay, outputs, and SYSREF disable

modes.

Table 20. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT

7

NAME

POR DEFAULT

DESCRIPTION

Powerdown the device clock digital delay circuitry.

DCLKoutX

_DDLY_PD

0

3

1

0: Enabled

1: Powerdown

6:5

4

NA

These bits should always be programmed to 1 (Bit 6 = 1, Bit 5 = 1).

Powerdown the device clock analog delay feature.

DCLKoutX

_ADLY_PD

0: Enabled

1: Powerdown

X_Y = 0_1 → 1

X_Y = 2_3 → 1

X_Y = 4_5 → 0

X_Y = 6_7 → 0

X_Y = 8_9 → 0

X_Y = 10_11 → 0

X_Y = 12_13 → 1

Powerdown the clock group defined by X and Y.

0: Enabled

1: Powerdown

3

CLKoutX_Y_PD

Configures the output state of the SYSREF

Field Value

0 (0x00)

Disable Mode

Active in normal operation

1 (0x01)

If SYSREF_GBL_PD = 1, the output is a

logic low, otherwise it is active.

SDCLKoutY

_DIS_MODE

2:1

0

2 (0x02)

3 (0x03)

If SYSREF_GBL_PD = 1, the output is a

nominal Vcm voltage⁽¹⁾, otherwise it is

active.

Output is a nominal Vcm voltage⁽¹⁾

0

SDCLKoutY_PD

1

Powerdown SDCLKoutY and set to the state defined by SDCLKoutY_DIS_MODE

(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm will be ~0 V, each pin will be ~0 V.

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9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT

These registers configure the output polarity, and format.

Table 21. Registers 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137

POR

DEFAULT

BIT

NAME

DESCRIPTION

Sets the polarity of clock on SDCLKoutY when device clock output is selected with

SDCLKoutY_MUX.

0: Normal

7

SDCLKoutY_POL

0

1: Inverted

Sets the output format of the SYSREF clocks

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Output Format

Powerdown

LVDS

Reserved

6:4

SDCLKoutY_FMT

DCLKoutX_POL

DCLKoutX_FMT

0

Reserved

LVPECL 1600 mV

LVPECL 2000 mV

Reserved

Sets the polarity of the device clocks from the DCLKoutX outputs

3

0

0: Normal

1: Inverted

Sets the output format of the device clocks.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Output Format

Powerdown

LVDS

LMK04228:

X = 0 → 0

X = 2 → 0

X = 4 → 1

X = 6 → 1

X = 8 → 1

X = 10 → 1

X = 12 → 0

Reserved

2:0

Reserved

LVPECL 1600 mV

LVPECL 2000 mV

Reserved

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9.5.2.3 SYSREF, SYNC, and Device Config

9.5.2.3.1 VCO_MUX, OSCout_FMT

This register selects the clock distribution source, and OSCout parameters.

Table 22. Register 0x138

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

Selects clock distribution path source from VCO0, VCO1

Field Value

0 (0x00)

VCO Selected

VCO 0

6:5

4

VCO_MUX

NA

0

1 (0x01)

VCO 1

2 (0x02)

Reserved

3 (0x03)

Reserved

Selects the output format of OSCout. When powered down, these pins may be used as

CLKin2.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

OSCout Format

Powerdown (CLKin2)

LVDS

Reserved

LVPECL 1600 mVpp

LVPECL 2000 mVpp

LVCMOS (Norm / Inv)

LVCMOS (Inv / Norm)

LVCMOS (Norm / Norm)

LVCMOS (Inv / Inv)

LVCMOS (Off / Norm)

LVCMOS (Off / Inv)

LVCMOS (Norm / Off)

LVCMOS (Inv / Off)

LVCMOS (Off / Off)

3:0

OSCout_FMT

4

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9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX

This register sets the source for the SYSREF outputs. Refer to Figure 6 and SYNC/SYSREF.

Table 23. Register 0x139

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:3

NA

0

Reserved

Selects the SYSREF output from SYSREF_MUX or CLKin0 direct

Field Value

SYSREF Source

SYSREF_

CLKin0_MUX

2

0

SYSREF Mux

1

Selects the SYSREF source.

Field Value

CLKin0 Direct (from CLKin0_OUT_MUX)

SYSREF Source

Normal SYNC

0 (0x00)

1:0

SYSREF_MUX

1 (0x01)

Re-clocked

2 (0x02)

SYSREF Pulser

SYSREF Continuous

3 (0x03)

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9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]

These registers set the value of the SYSREF output divider.

Table 24. SYSREF_DIV Register Configuration, SYSREF_DIV[12:0]

MSB

LSB

0x13A[4:0]

0x13B[7:0]

Table 25. Registers 0x13A, 0x13B

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:5

0x13A

NA

0

Reserved

Divide value for the SYSREF outputs.

Field Value

0x00 to 0x07

8 (0x08)

Divide Value

4:0

0x13A

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

12

0

Reserved

8

9

9 (0x09)

...

7:0

0x13B

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]

These registers set the delay of the SYSREF digital delay value.

Table 26. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0]

MSB

LSB

0x13C[4:0]

0x13D[7:0]

Table 27. Registers 0x13C, 0x13D

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:5

0x13C

NA

0

Reserved

Sets the value of the SYSREF digital delay.

Field Value

0x00 to 0x07

8 (0x08)

Delay Value

4:0

0x13C

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

Reserved

8

9

9 (0x09)

...

7:0

0x13D

8

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

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9.5.2.3.5 SYSREF_PULSE_CNT

This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See

SYSREF_CLKin0_MUX, SYSREF_MUX for further description of SYSREF's outputs.

Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by

SYSREF_MUX and SYSREF functionality is powered up.

Table 28. Register 0x13E

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:2

NA

0

Reserved

Sets the number of SYSREF pulses generated when not in continuous mode.

See SYSREF_CLKin0_MUX, SYSREF_MUX for more information on SYSREF modes.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Number of Pulses

1 pulse

1:0

SYSREF_PULSE_CNT

3

2 pulses

4 pulses

8 pulses

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9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD,

SYSREF_PLSR_PD

This register contains powerdown controls for OSCin and SYSREF functions.

Table 29. Register 0x140

POR

DEFAULT

BIT

NAME

DESCRIPTION

Powerdown PLL1

0: Normal operation

1: Powerdown

7

PLL1_PD

0

Powerdown VCO_LDO

0: Normal operation

1: Powerdown

6

5

4

VCO_LDO_PD

VCO_PD

0

Powerdown VCO

0: Normal operation

1: Powerdown

Powerdown the OSCin port.

0: Normal operation

1: Powerdown

OSCin_PD

Powerdown individual SYSREF outputs depending on the setting of

SDCLKoutY_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many

SYSREF outputs to be controlled through a single bit.

0: Normal operation

3

2

SYSREF_GBL_PD

SYSREF_PD

0

1

1: Activate Powerdown Mode

Powerdown the SYSREF circuitry and divider. If powered down, SYSREF output mode

cannot be used. SYNC cannot be provided either.

0: SYSREF can be used as programmed by individual SYSREF output registers.

1: Powerdown

Powerdown the SYSREF digital delay circuitry.

0: Normal operation, SYSREF digital delay may be used. Must be powered up during

SYNC for deterministic phase relationship with other clocks.

1: Powerdown

1

0

SYSREF_DDLY_PD

SYSREF_PLSR_PD

1

Powerdown the SYSREF pulse generator.

0: Normal operation

1: Powerdown

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9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD,

SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to Figure 6 for block diagram.

Refer to Table 2 for using SYNC_MODE for specific SYNC use cases.

Table 30. Register 0x143

POR

DEFAULT

BIT

NAME

DESCRIPTION

Except during SYSREF Setup Procedure (see SYNC/SYSREF), this bit should always be

programmed to 0. While this bit is set, extra current is used. Refer to Table 82.

7

SYSREF_CLR

1

SYNC one shot enables edge sensitive SYNC.

0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC is asserted.

1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC. This results in

the clock being held in SYNC for a minimum amount of time.

6

SYNC_1SHOT_EN

0

Sets the polarity of the SYNC pin.

0: Normal

1: Inverted

5

4

SYNC_POL

SYNC_EN

0

1

Enables the SYNC functionality.

0: Disabled

1: Enabled

0: Off

3

2

SYNC_PLL2_DLD

SYNC_PLL1_DLD

0

1: Assert SYNC until PLL2 DLD = 1

0: Off

1: Assert SYNC until PLL1 DLD = 1

Sets the method of generating a SYNC event.

Field Value

SYNC Generation

Prevent SYNC Pin, SYNC_PLL1_DLD flag, or SYNC_PLL2_DLD

flag from generating a SYNC event.

0 (0x00)

SYNC event generated from SYNC pin or if enabled the

SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag.

1 (0x01)

2 (0x02)

1:0

SYNC_MODE

1

For use with pulser - SYNC/SYSREF pulses are generated by

pulser block via SYNC Pin or if enabled SYNC_PLL1_DLD flag

or SYNC_PLL2_DLD flag.

For use with pulser - SYNC/SYSREF pulses are generated by

pulser block when programming register 0x13E

(SYSREF_PULSE_CNT) is written to (see

SYSREF_PULSE_CNT).

3 (0x03)

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9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX

SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when

outputting SYSREF.

Table 31. Register 0x144

POR

DEFAULT

BIT

NAME

DESCRIPTION

Prevent the SYSREF clocks from becoming synchronized during a SYNC event. If

SYNC_DISSYSREF is enabled it will continue to operate normally during a SYNC event.

7

SYNC_DISSYSREF

0

6

5

4

3

2

1

0

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0

Prevent the device clock output from becoming synchronized during a SYNC event or

SYSREF clock. If SYNC_DIS bit for a particular output is enabled then it will continue to

operate normally during a SYNC event or SYSREF clock.

9.5.2.3.9 Fixed Register

Always program this register to value 127.

Table 32. Register 0x145

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

Fixed Register

0

Always program to 127

9.5.2.4 (0x146 - 0x149) CLKin Control

9.5.2.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE

This register has CLKin enable and type controls.

Table 33. Register 0x146

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Enable CLKin2 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

1: Enabled for auto mode

5

4

3

CLKin2_EN

CLKin1_EN

CLKin0_EN

0

1

Enable CLKin1 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

1: Enabled for auto mode

Enable CLKin0 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

1: Enabled for auto mode

2

1

CLKin2_TYPE

CLKin1_TYPE

0

There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS.

Bipolar is recommended for differential inputs like LVDS or LVPECL.

CMOS is recommended for DC coupled single ended inputs.

When using bipolar, CLKinX and CLKinX* must be AC coupled.

When using CMOS, CLKinX and CLKinX* may be AC or DC coupled

if the input signal is differential. If the input signal is single-ended the

used input may be either AC or DC coupled and the unused input

must AC grounded.

0: Bipolar

1: MOS

0

CLKin0_TYPE

0

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9.5.2.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX

Table 34. Register 0x147

POR

DEFAULT

BIT

NAME

DESCRIPTION

Inverts the CLKin polarity for use in pin select mode.

7

CLKin_SEL_POL

0

0: Active High

1: Active Low

Sets the mode used in determining the reference for PLL1.

Field Value

CLKin Mode

CLKin0 Manual

CLKin1 Manual

CLKin2 Manual

Pin Select Mode

Auto Mode

0 (0x00)

1 (0x01)

2 (0x02)

6:4

CLKin_SEL_MODE

3

3 (0x03)

4 (0x04)

5 (0x05)

Reserved

6 (0x06)

Reserved

7 (0x07)

Reserved

Selects where the output of the CLKin1 buffer is directed.

Field Value

CLKin1 Destination

Reserved

PLL1

0 (0x00)

3:2

1:0

CLKin1_OUT_MUX

CLKin0_OUT_MUX

2

1 (0x01)

2 (0x02)

3 (0x03)

Off

Selects where the output of the CLKin0 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin0 Destination

SYSREF Mux

Reserved

PLL1

Off

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9.5.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE

This register has CLKin_SEL0 controls.

Table 35. Register 0x148

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

This set the output value of the CLKin_SEL0 pin. This register only applies if

CLKin_SEL0_TYPE is set to an output mode

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin0 LOS

CLKin0 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL0_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL0 pin.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Configuration

Function

Input

Input mode, see Input

Clock Switching - Pin

Select Mode for

Input /w pull-up resistor

Input /w pull-down resistor

Output (push-pull)

2:0

CLKin_SEL0_TYPE

2

description of input mode.

Output modes; the

CLKin_SEL0_MUX

register for description of

outputs.

Output inverted (push-pull)

Reserved

Output (open drain)

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9.5.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE

This register has CLKin_SEL1 controls and register readback SDIO pin type.

Table 36. Register 0x149

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.

6

SDIO_RDBK_TYPE

1

0: Output, push-pull

1: Output, open drain.

This set the output value of the CLKin_SEL1 pin. This register only applies if

CLKin_SEL1_TYPE is set to an output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin1 LOS

CLKin1 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL1_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL1 pin.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Configuration

Input

Function

Input mode, see Input Clock

Switching - Pin Select Mode for

description of input mode.

Input /w pull-up resistor

Input /w pull-down resistor

Output (push-pull)

Output inverted (push-pull)

Reserved

2:0

CLKin_SEL1_TYPE

2

Output modes; see the

CLKin_SEL1_MUX register for

description of outputs.

Output (open drain)

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9.5.2.5 RESET_MUX, RESET_TYPE

This register contains control of the RESET pin.

Table 37. Register 0x14A

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an

output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

Reserved

5:3

RESET_MUX

0

2 (0x02)

CLKin2 Selected

DAC Locked

DAC Low

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

This sets the IO type of the RESET pin.

Field Value

SPI Readback

Configuration

Function

0 (0x00)

Input

Reset Mode

Reset pin high = Reset

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Input /w pull-up resistor

Input /w pull-down resistor

Output (push-pull)

2:0 RESET_TYPE

2

Output modes; see the

RESET_MUX register for

description of outputs.

Output inverted (push-pull)

Reserved

Output (open drain)

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9.5.2.6 (0x14B - 0x152) Holdover

9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]

This register contains the holdover functions.

Table 38. Register 0x14B

POR

DEFAULT

BIT

NAME

DESCRIPTION

This controls the amount of time in which no activity on a CLKin forces a clock switch

event.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Timeout

370 kHz

2.1 MHz

8.8 MHz

22 MHz

7:6

LOS_TIMEOUT

0

Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs.

5

4

LOS_EN

0

1

0: Disabled

1: Enabled

Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After

device reset, tracking starts at DAC code = 512.

Tracking can be used to monitor PLL1 voltage in any mode.

0: Disabled

TRACK_EN

1: Enabled, will only track when PLL1 is locked.

This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then

the DAC will set the programmed MAN_DAC value. Otherwise the tracked DAC value will

set the DAC voltage.

0: Disabled

HOLDOVER

_FORCE

3

0

1: Enabled.

This bit enables the manual DAC mode.

2

MAN_DAC_EN

MAN_DAC[9:8]

1

2

0: Automatic

1: Manual

1:0

See MAN_DAC[9:8], MAN_DAC[7:0] for more information on the MAN_DAC settings.

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9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]

These registers set the value of the DAC in holdover mode when used manually.

Table 39. MAN_DAC Register Configuration, MAN_DAC[9:0]

MSB

LSB

0x14B[1:0]

0x14C[7:0]

Table 40. Registers 0x14B, 0x14C

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

See LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE,

MAN_DAC_EN, MAN_DAC[9:8] for information on these bits.

7:2

0x14B

Sets the value of the manual DAC when in manual DAC mode.

Field Value

0 (0x00)

DAC Value

1:0

0x14B

MAN_DAC[9:8]

MAN_DAC[7:0]

2

0

1

1 (0x01)

2 (0x02)

2

...

7:0

0x14C

1022 (0x3FE)

1023 (0x3FF)

1022

1023

9.5.2.6.3 DAC_TRIP_LOW

This register contains the high value at which holdover mode is entered.

Table 41. Register 0x14D

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_LOW

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

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9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is

entered.

Table 42. Register 0x14E

POR

DEFAULT

BIT

NAME

DESCRIPTION

This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is

tracked.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

DAC Multiplier Value

4

7:6

DAC_CLK_MULT

0

64

1024

16384

Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_HIGH

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

9.5.2.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

Table 43. Register 0x14F

POR

DEFAULT

BIT

NAME

DESCRIPTION

This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate is =

DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Value

0

1

2

7:0

DAC_CLK_CNTR

127

3

...

253 (0xFD)

254 (0xFE)

255 (0xFF)

253

254

255

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9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET,

HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN

This register has controls for enabling clock in switch events.

Table 44. Register 0x150

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1

will force that clock input. Used with clock distribution mode for best performance.

0: Normal, no override.

CLKin

_OVERRIDE

6

0

1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MODE in manual mode.

5

4

NA

0

Reserved

This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low.

0: PLL1 DLD does not cause a clock switch event

1: PLL1 DLD causes a clock switch event

HOLDOVER

_PLL1_DET

This enables HOLDOVER when PLL1 LOS signal is detected.

0: Disabled

1: Enabled

HOLDOVER

_LOS_DET

3

2

0

Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this

bit is enabled, the current clock input is considered invalid and an input clock switch event

is generated.

0: Disabled

1: Enabled

HOLDOVER

_VTUNE_DET

HOLDOVER

_HITLESS

_SWITCH

Determines whether a clock switch event will enter holdover use hitless switching.

0: Hard Switch

1: Hitless switching (has an undefined switch time)

1

0

1

Sets whether holdover mode is active or not.

0: Disabled

1: Enabled

HOLDOVER_EN

9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]

Table 45. HOLDOVER_DLD_CNT Register Configuration, HOLDOVER_DLD_CNT[13:0]

MSB

LSB

0x151[5:0]

0x152[7:0]

This register has the number of valid clocks of PLL1 PDF before holdover is exited.

Table 46. Registers 0x151 and 0x152

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

0x151

NA

0

Reserved

The number of valid clocks of PLL1 PDF before holdover mode is exited.

Field Value

0 (0x00)

Count Value

HOLDOVER

_DLD_CNT[13:8]

5:0

0x151

2

0

1

1 (0x01)

2 (0x02)

2

...

HOLDOVER

_DLD_CNT[7:0]

7:0

0x152

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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9.5.2.7 (0x153 - 0x15F) PLL1 Configuration

9.5.2.7.1 CLKin0_R[9:8], CLKin0_R[7:0]

Table 47. CLKin0_R Register Configuration, CLKin0_R[9:0]

MSB

LSB

0x153[1:0]

0x154[7:0]

These registers contain the value of the CLKin0 divider.

Table 48. Registers 0x153, 0x154

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:2

0x153

NA

0

Reserved

The value of PLL1 N counter when CLKin0 is selected.

Field Value

0 (0x00)

Divide Value

1:0

0x153

CLKin0_R[9:8]

CLKin0_R[7:0]

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x154

120

1022 (0x3FE)

1023 (0x3FF)

1022

1023

9.5.2.7.2 CLKin1_R[9:8], CLKin1_R[7:0]

Table 49. CLKin1_R Register Configuration, CLKin1_R[9:0]

MSB

LSB

0x155[1:0]

0x156[7:0]

These registers contain the value of the CLKin1 R divider.

Table 50. Registers 0x155 and 0x156

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:2

0x155

NA

0

Reserved

The value of PLL1 N counter when CLKin1 is selected.

Field Value

0 (0x00)

Divide Value

1:0

0x155

CLKin1_R[9:8]

CLKin1_R[7:0]

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x156

150

1022 (0x3FE)

1023 (0x3FF)

1022

1023

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9.5.2.7.3 CLKin2_R[9:8], CLKin2_R[7:0]

Table 51. CLKin2_R Register Configuration, CLKin2_R[9:0]

MSB

LSB

0x157[1:0]

0x158[7:0]

Table 52. Registers 0x157 and 0x158

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:2

0x157

NA

0

Reserved

The value of PLL1 N counter when CLKin2 is selected.

Field Value

0 (0x00)

Divide Value

1:0

0x157

CLKin2_R[9:8]

CLKin2_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x158

150

1022 (0x3FE)

1023 (0x3FF)

1022

1023

9.5.2.7.4 PLL1_N

Table 53. PLL1_N Register Configuration, PLL1_N[13:0]

MSB

0x159[5:0]

LSB

0x15A[7:0]

These registers contain the N divider value for PLL1.

Table 54. Registers 0x159 and 0x15A

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:4

3:0

0x159

NA

0

Reserved

The value of PLL1 N counter.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

PLL1_N[11:8]

PLL1_N[7:0]

Not Valid

1

2

7:0

0x15A

120

...

4,095 (0xFFF)

4,095

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9.5.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN

This register controls the PLL1 phase detector.

Table 55. Register 0x15B

POR

DEFAULT

BIT

NAME

DESCRIPTION

PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase

error between the reference and feedback of PLL1 is less than specified time, then the

PLL1 lock counter increments.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

4 ns

7:6

PLL1_WND_SIZE

3

9 ns

19 ns

43 ns

This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE.

0: PLL1 CPout1 is active

1: PLL1 CPout1 is at TRI-STATE

5

4

PLL1_CP_TRI

PLL1_CP_POL

0

1

PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope.

A positive slope VCXO increases output frequency with increasing voltage. A negative

slope VCXO decreases output frequency with increasing voltage.

0: Negative Slope VCO/VCXO

1: Positive Slope VCO/VCXO

This bit programs the PLL1 charge pump output current level.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

...

Gain

50 µA

150 µA

250 µA

350 µA

450 µA

...

3:0

PLL1_CP_GAIN

4

14 (0x0E)

15 (0x0F)

1450 µA

1550 µA

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9.5.2.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]

Table 56. PLL1_DLD_CNT Register Configuration, PLL1_DLD_CNT[13:0]

MSB

LSB

0x15C[5:0]

0x15D[7:0]

This register contains the value of the PLL1 DLD counter.

Table 57. Registers 0x15C and 0x15D

BIT REGISTERS

NAME

POR DEFAULT

DESCRIPTION

7:6

0x15C

NA

0

Reserved

The reference and feedback of PLL1 must be within the window of phase

error as specified by PLL1_WND_SIZE for this many phase detector

cycles before PLL1 digital lock detect is asserted.

PLL1_DLD

_CNT[13:8]

5:0

0x15C

32

Field Value

0 (0x00)

Delay Value

Reserved

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL1_DLD

_CNT[7:0]

7:0

0x15D

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

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9.5.2.7.7 PLL1_LD_MUX, PLL1_LD_TYPE

This register configures the PLL1 LD pin.

Table 58. Register 0x15F

POR

DEFAULT

BIT

NAME

DESCRIPTION

This sets the output value of the Status_LD1 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

PLL1 DLD

PLL2 DLD

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL1_LD_MUX

1

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

DAC High

PLL1_N

PLL1_N/2

PLL2_N

PLL2_N/2

PLL1_R

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the IO type of the Status_LD1 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL1_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

Output inverted (push-pull)

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

Output (open drain)

(1) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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9.5.2.8 (0x160 - 0x16E) PLL2 Configuration

9.5.2.8.1 PLL2_R[4:0]

This register contains the value of the PLL2 R divider.

Table 59. Register 0x161

BIT REGISTERS

NAME

POR DEFAULT

DESCRIPTION

7:5

4:0

0x161

NA

0

Reserved

Valid values for the PLL2 R divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

Divide Value

Not Valid

1

2

PLL2_R[4:0]

2

3

...

30

31

30 (0x1E)

31 (0x1F)

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9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN

This register sets other PLL2 functions.

Table 60. Register 0x162

POR

DEFAULT

BIT

NAME

DESCRIPTION

The PLL2 N Prescaler divides the output of the VCO as selected by Mode_MUX1 and is

connected to the PLL2 N divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Value

8

2

3

4

5

6

7

7:5

PLL2_P

2

The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin*

port) must be programmed in order to support proper operation of the frequency calibration

routine which locks the internal VCO to the target frequency.

Field Value

0 (0x00)

OSCin Frequency

0 to 63 MHz

4:2

OSCin_FREQ

7

1 (0x01)

>63 MHz to 127 MHz

>127 MHz to 255 MHz

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

>255 MHz to 500 MHz

Reserved

5 (0x05) to 7(0x07)

If an external crystal is being used to implement a discrete VCXO, the internal feedback

amplifier must be enabled with this bit in order to complete the oscillator circuit.

0: Oscillator Amplifier Disabled

1

0

PLL2_XTAL_EN

0

1

1: Oscillator Amplifier Enabled

Enabling the PLL2 reference frequency doubler allows for higher phase detector

frequencies on PLL2 than would normally be allowed with the given VCXO or Crystal

frequency.

PLL2_REF_2X_EN

Higher phase detector frequencies reduces the PLL N values which makes the design of

wider loop bandwidth filters possible.

0: Doubler Disabled

1: Doubler Enabled

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9.5.2.8.3 PLL2_FCAL_DIS

This register disables frequency calibration.

Table 61. Register 0x166

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:3

NA

0

Reserved

This disables the PLL2 frequency calibration on programming register 0x168.

0: Frequency calibration enabled

1: Frequency calibration disabled

2

PLL2_FCAL_DIS

NA

0

1:0

Reserved

9.5.2.8.4 PLL2_N

This register sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if

PLL2_FCAL_DIS = 0.

Table 62. Register 0x168

BIT

NAME

POR DEFAULT

DESCRIPTION

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

Not Valid

1

2

7:0

PLL2_N[7:0]

12

...

255 (0xFF)

255

9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

Table 63. Register 0x169

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase

error between the reference and feedback of PLL2 is less than specified time, then the

PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns).

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Reserved

3.7 ns

6:5

PLL2_WND_SIZE

2

Reserved

This bit programs the PLL2 charge pump output current level. The table below also

illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

100 µA

4:3

PLL2_CP_GAIN

3

400 µA

1600 µA

Reserved

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Table 63. Register 0x169 (continued)

POR

DEFAULT

BIT

NAME

DESCRIPTION

PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the

negative charge pump polarity to be selected. Many VCOs use positive slope.

A positive slope VCO increases output frequency with increasing voltage. A negative slope

VCO decreases output frequency with increasing voltage.

2

PLL2_CP_POL

0

Field Value

Description

0

1

Negative Slope VCO/VCXO

Positive Slope VCO/VCXO

PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.

1

0

PLL2_CP_TRI

Fixed Value

0

1

0: Disabled

1: TRI-STATE

When programming register 0x169, this field must be set to 1.

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9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT

Table 64. PLL2_DLD_CNT Register Configuration, PLL2_DLD_CNT[15:0]

MSB

LSB

0x16A[5:0]

0x16B[7:0]

This register has the value of the PLL2 DLD counter.

Table 65. Registers 0x16A and 0x16B

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7

6

0x16A

NA

0

Reserved

Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for

continuous pulses. When using this feature enable pulser and set

SYSREF_MUX = 2 (Pulser).

SYSREF_REQ_EN

0

The reference and feedback of PLL2 must be within the window of phase error

as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital

lock detect is asserted.

PLL2_DLD

_CNT[13:8]

5:0

7:0

0x16A

0x16B

32

Field Value

0 (0x00)

Divide Value

Not Valid

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL2_DLD_CNT

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

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9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3

This register controls the integrated loop filter resistors.

Table 66. Register 0x16C

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop

filters without requiring external components.

Internal loop filter resistor R4 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Resistance

200 Ω

1 kΩ

5:3

PLL2_LF_R4

0

2 kΩ

4 kΩ

16 kΩ

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop

filters without requiring external components.

Internal loop filter resistor R3 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Resistance

200 Ω

1 kΩ

2:0

PLL2_LF_R3

0

2 kΩ

4 kΩ

16 kΩ

Reserved

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9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3

This register controls the integrated loop filter capacitors.

Table 67. Register 0x16D

POR

DEFAULT

BIT

NAME

DESCRIPTION

Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop

filters without requiring external components.

Internal loop filter capacitor C4 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Capacitance

10 pF

15 pF

29 pF

34 pF

47 pF

52 pF

7:4

PLL2_LF_C4

0

66 pF

71 pF

103 pF

108 pF

122 pF

126 pF

141 pF

146 pF

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop

filters without requiring external components.

Internal loop filter capacitor C3 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Capacitance

10 pF

11 pF

15 pF

16 pF

19 pF

20 pF

3:0

PLL2_LF_C3

0

24 pF

25 pF

29 pF

30 pF

33 pF

34 pF

38 pF

39 pF

Reserved

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9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE

This register sets the output value of the Status_LD2 pin.

Table 68. Register 0x16E

POR

DEFAULT

BIT

NAME

DESCRIPTION

This sets the output value of the Status_LD2 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

PLL1 DLD

PLL2 DLD

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL2_LD_MUX

2

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

DAC High

PLL1_N

PLL1_N/2

PLL2_N

PLL2_N/2

PLL1_R

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the IO type of the Status_LD2 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL2_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

Output inverted (push-pull)

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

Output (open drain)

(1) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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9.5.2.9 (0x16F - 0x1FFF) Misc Registers

9.5.2.9.1 Fixed Register

Always program this register to 0xAA.

Table 69. Register 0x171

POR

DEFAULT

BIT

NAME

DESCRIPTION

Always program to 170 (0xAA)

7:0

Fixed Register

10 (0x0A)

9.5.2.9.2 Fixed Register

Always program this register to 0x02.

Table 70. Register 0x172

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

Fixed Register

0

Always program to 2 (0x02)

9.5.2.9.3 PLL2_PRE_PD, PLL2_PD

Table 71. Register 0x173

BIT

NAME

DESCRIPTION

7

N/A

Reserved

Powerdown PLL2 prescaler

0: Normal Operation

1: Powerdown

6

PLL2_PRE_PD

Powerdown PLL2

0: Normal Operation

1: Powerdown

5

PLL2_PD

N/A

4:0

Reserved

9.5.2.9.4 OPT_REG_1

This register must be written with the following value depending on which LMK04228 is used to optimize VCO1

phase noise performance over temperature. This register must be written before writing register 0x168 when

using VCO1.

Table 72. Register 0x17C

BIT

NAME

DESCRIPTION

7:0

OPT_REG_1

21: LMK04228

9.5.2.9.5 OPT_REG_2

This register must be written with the following value depending on which LMK04228 is used to optimize VCO1

phase noise performance over temperature. This register must be written before writing register 0x168 when

using VCO1.

Table 73. Register 0x17D

BIT

NAME

DESCRIPTION

7:0

OPT_REG_2

51: LMK04228

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9.5.2.9.6 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST

Table 74. Register 0x182

BIT

7:3

2

NAME

N/A

DESCRIPTION

Reserved

RB_PLL1_LD_LOST

This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low.

Read back 0: PLL1 DLD is low.

Read back 1: PLL1 DLD is high.

1

RB_PLL1_LD

To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.

0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge.

1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to

become set again.

0

CLR_PLL1_LD_LOST

9.5.2.9.7 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST

Table 75. Register 0x0x183

BIT

7:3

2

NAME

N/A

DESCRIPTION

Reserved

RB_PLL2_LD_LOST

This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low.

Read back 0: PLL2 DLD is low.

Read back 1: PLL2 DLD is high.

1

RB_PLL2_LD

To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.

0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge.

1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to

become set again.

0

CLR_PLL2_LD_LOST

9.5.2.9.8 RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS

This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs

are shared with the RB_DAC_VALUE. See RB_DAC_VALUE section.

Table 76. Register 0x184

BIT

NAME

DESCRIPTION

7:6

RB_DAC_VALUE[9:8] See RB_DAC_VALUE section.

Read back 0: CLKin2 is not selected for input to PLL1.

Read back 1: CLKin2 is selected for input to PLL1.

5

4

RB_CLKin2_SEL

RB_CLKin1_SEL

Read back 0: CLKin1 is not selected for input to PLL1.

Read back 1: CLKin1 is selected for input to PLL1.

Read back 0: CLKin0 is not selected for input to PLL1.

Read back 1: CLKin0 is selected for input to PLL1.

3

2

1

RB_CLKin0_SEL

N/A

Read back 1: CLKin1 LOS is active.

Read back 0: CLKin1 LOS is not active.

RB_CLKin1_LOS

Read back 1: CLKin0 LOS is active.

Read back 0: CLKin0 LOS is not active.

0

RB_CLKin0_LOS

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9.5.2.9.9 RB_DAC_VALUE

Contains the value of the DAC for user readback.

Table 77. RB_DAC_VALUE Register Configuration, RB_DAC_VALUE[7:0]

Field Name

MSB

LSB

RB_DAC_VALUE

0x184 [7:6]

0x185 [7:0]

Table 78. Registers 0x184 and 0x185

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

RB_DAC_

VALUE[9:8]

DAC value is 512 on power on reset, if PLL1 locks upon power-up the DAC

value will change.

7:6

7:0

0x184

0x185

2

RB_DAC_

VALUE[7:0]

0

9.5.2.9.10 RB_HOLDOVER

Table 79. Register 0x188

BIT

NAME

DESCRIPTION

7:5

N/A

Reserved

Read back 0: Not in HOLDOVER.

Read back 1: In HOLDOVER.

4

RB_HOLDOVER

N/A

3:0

Reserved

9.5.2.9.11 SPI_LOCK

Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, 0x1FFF. These registers must be

written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF.

These registers cannot be read back.

Table 80. SPI_LOCK Register Configuration, SPI_LOCK[7:0]

MSB

—

LSB

0x1FFD [7:0]

0x1FFE [7:0]

0x1FFF [7:0]

Table 81. Registers 0x1FFD, 0x1FFE, and 0x1FFF

POR

BIT REGISTERS

NAME

DESCRIPTION

DEFAULT

0: Registers unlocked.

1 to 255: Registers locked

7:0

0x1FFD

0x1FFE

SPI_LOCK[23:16]

SPI_LOCK[15:8]

0

0: Registers unlocked.

1 to 255: Registers locked

0 to 82: Registers locked

83: Registers unlocked

84 to 256: Registers locked

7:0

0x1FFF

SPI_LOCK[7:0]

83

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

To assist customers in frequency planning and design of loop filters, Texas Instrument's provides the Clock

Design Tool (www.ti.com/tool/clockdesigntool) and Clock Architect (www.ti.com/clockarchitect).

10.1.1 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window

size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals

of the PLL for each event to occur. When a PLL digital lock event occurs, the corresponding PLL digital lock

detect is asserted true. When the holdover exit event occurs, the device will exit holdover mode.

EVENT

PLL

PLL1

PLL2

PLL1

WINDOW SIZE

PLL1_WND_SIZE

PLL2_WND_SIZE

PLL1_WND_SIZE

LOCK COUNT

PLL1_DLD_CNT

PLL1 Locked

PLL2 Locked

Holdover Exit

PLL2_DLD_CNT

HOLDOVER_DLD_CNT

For a digital lock detect event to occur there must be a lock count number of phase detector cycles of PLLX

during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the

user programmable window size. Because there must be at least lock count phase detector events before a lock

event occurs, a minimum digital lock event time can be calculated as lock count / f_PDXwhere X = 1 for PLL1 or 2

for PLL2.

By using Equation 3, values for a lock count and window size can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × f_PDX

ppm =

PLLX_DLD_CNT

(3)

The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by

lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window

size, then the lock count value is reset to 0.

NOTE

In cases where the period of the phase detector frequency approaches the value of the

default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with

the default value of PLL1_WND_SIZE. For phase detector frequencies at or above 25

MHz, TI recommends setting PLL1_WND_SIZE to 0x02 (19 ns) or a smaller value.

10.1.1.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000. Then the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs.

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10.1.2 Driving CLKin AND OSCin Inputs

10.1.2.1 Driving CLKin PINS With a Differential Source

Both CLKin ports can be driven by differential signals. TI recommends setting the input mode to bipolar

(CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04228 internally biases the input

pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with

either LVDS or LVPECL are shown in Figure 9 and Figure 10.

CLKinX

0.1 mF

100-W Trace

(Differential)

LMK048XX

Input

LVDS

0.1 mF

CLKinX*

Figure 9. CLKinX/X* Termination for an LVDS Reference Clock Source

CLKinX

0.1 mF

100-W Trace

(Differential)

LVPECL

Ref Clk

LMK048XX

Input

CLKinX*

Figure 10. CLKinX/X* Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the

following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in Electrical

Characteristics.

CLKinX

0.1 mF

100-W Trace

(Differential)

LMK048XX

Input

Differential

Sinewave

Clock Source

CLKinX*

Figure 11. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source

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10.1.2.2 Driving CLKin Pins With a Single-Ended Source

The CLKin pins of the LMK04228 can be driven using a single-ended reference clock source, for example, either

a sine wave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case

of the sine wave source that is expecting a 50-Ω load, TI recommends that AC coupling be used as shown in the

circuit below with a 50-Ω termination.

NOTE

The signal level must conform to the requirements for the CLKin pins listed in Electrical

Characteristics. CLKinX_BUF_TYPE is recommended to be set to bipolar mode

(CLKinX_BUF_TYPE = 0).

0.1 mF

50-W Trace

CLKinX

50 W

LMK048XX

Clock Source

CLKinX*

0.1 mF

Figure 12. CLKinX/X* Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC

coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode

(CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC-coupled,

MOS-mode clock inputs given in Electrical Characteristics. If AC coupling is used, the CLKinX_BUF_TYPE

should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must

meet the specifications for AC-coupled, bipolar mode clock inputs given in Electrical Characteristics. In this case,

some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC-

coupling capacitor is sufficient.

Figure 13. DC-Coupled LVCMOS/LVTTL Reference Clock

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10.2 Typical Application

This design example highlights using the available tools to design loop filters and create programming map for

LMK04228.

Multiple —clean“

clocks at

different

frequencies

VCXO

Recovered

—dirty“ clock or

clean clock

CLKin0

Backup

Reference

CLKin1

CLKout10

CLKout11

FPGA

LMK04228

Clock

CLKout6,

CLKout7,

CLKout8,

CLKout9

CLKout4,

CLKout5

DAC

ADC

CLKout0,

CLKout1,

CLKout2,

CLKout3

ADC

Serializer/

Deserializer

Figure 14. Typical Application

10.2.1 Design Requirements

Clocks outputs:

•

1× 245.76-MHz clock for JESD204B ADC, LVPECL.

This clock requires the best performance in this example.

2× 983.04-MHz clock for JESD204B DAC, LVPECL.

1× 122.88-MHz clock for JESD204B FPGA block, LVDS

3× 10.24-MHz SYSREF for ADC (LVPECL), DAC (LVPECL), FPGA (LVDS).

2× 122.88-MHz clock for FPGA, LVDS

–

•

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used.

10.2.2 Detailed Design Procedure

10.2.2.1 Device Programming

TICS Pro register programming tool exposes the registers for the LMK04228 (and many other TI products) using

block diagrams to demonstrate the purpose and location of register settings. By connecting a USB2ANY

programmer to the SPI inputs of the device, TICS Pro can update register configurations in real time for rapidly

validating desired configurations.

Frequency planning for assignment of outputs:

•

To minimize crosstalk perform frequency planning / CLKout assignments to keep common frequencies on

outputs close together.

•

It is best to place common device clock output frequencies on outputs sharing the same V_CCgroup, for

example, these outputs share Vcc4_CG2. Refer to Pin Configuration and Functions to see the V_CCgroupings

the clock outputs.

In this example, the 245.76-MHz ADC output needs the best performance. DCLKout2 on the LMK04228 provides

the best noise floor / performance. The 245.76 MHz will be placed on DCLKout2 with 10.24-MHz SYSREF on

SDCLKout3.

•

For best performance the input and output drive level bits may be set. Best noise floor performance is

achieved with DCLKout2_IDL = 1 and DCLKout2_ODL = 1.

In this example, the 983.04-MHz DAC output is placed on DCLKout4 and DCLKout6 with 10.24-MHz SYSREF

on paired SDCLKout5 and SDCLKout7 outputs.

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Typical Application (continued)

•

These outputs share Vcc4_CG2.

In this example, the 122.88-MHz FPGA JESD204B output is placed on DCLKout10 with 10.24-MHz SYSREF on

paired SDCLKout11 output.

Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on DCLKout8 and SDCLKout9.

•

When frequency planning, consider PLL2 as a clock output at the phase detector frequency. As such, these

122.88-MHz outputs have been placed on the outputs close to the PLL2 and Charge Pump power supplies.

Once the device programming is completed as desired in TICS Pro, the register settings can be exported for use

with other programming controllers.

10.3 Do's and Don'ts

10.3.1 Pin Connection Recommendations

•

V_CCPins and Decoupling: all V_CCpins must always be connected, including for unused clock output groups.

Unused Clock Outputs: leave unused clock outputs floating and powered down. Use the appropriate

registers to power down unused clock outputs.

•

Unused Clock Inputs: unused clock inputs can be left floating.

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11 Power Supply Recommendations

11.1 Current Consumption / Power Dissipation Calculations

From Table 82 the current consumption can be calculated for any configuration. Data below is typical and not

assured.

Table 82. Typical Current Consumption for Selected Functional Blocks

(T_A= 25°C, V_CC= 3.3 V)

POWER

TYPICAL I_CC

(mA)

DISSIPATED

IN DEVICE

(mW)

BLOCK

TEST CONDITION

CORE and FUNCTIONAL BLOCKS

Core

Dual-loop, internal VCO0

PLL1 and PLL2 locked

131.5

13.5

3

433.95

44.55

9.9

VCO

VCO1 is selected

Doubler is enabled

LMK04228

OSCin Doubler

CLKin

EN_PLL2_REF_2X = 1

Any one of the CLKinX is enabled

4.9

16.17

4.29

Holdover is enabled

Hitless switch is enabled

Track mode

HOLDOVER_EN = 1

1.3

HOLDOVER_HITLESS_SWI

TCH = 1

Holdover

0.9

2.97

TRACK_EN = 1

2.5

7.6

27.2

4.1

3

8.25

25.08

89.76

13.53

9.9

SYNC_EN = 1

Required for SYNC and SYSREF functionality

Enabled

SYSREF_PD = 0

Pulser is enabled

SYSREF pulses mode

SYSREF continuous mode

SYSREF_PLSR_PD = 0

SYSREF_MUX = 2

SYSREF_MUX = 3

SYSREF

3

9.9

CLOCK GROUP

Enabled

IDL

Any one of the CLKoutX_Y_PD = 0

Any one of the CLKoutX_Y_IDL = 1

Andy one of the CLKoutX_Y_ODL = 1

20.1

2.2

66.33

7.26

ODL

3.2

10.56

44.88

58.41

44.88

Divider only

DCLKoutX_MUX = 0

13.6

17.7

13.6

Clock Divider

Divider + DCC + HS

Analog Delay + Divider

DCLKoutX_MUX = 1

DCLKoutX_MUX = 3

CLOCK OUTPUT BUFFERS

LVDS

100-Ω differential termination

6

19.8

OSCout BUFFERS

LVDS

100-Ω differential termination

LVCMOS pair

18.5

42.6

27

61.05

140.58

89.1

150 MHz

LVCMOS

LVCMOS single

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12 Layout

12.1 Layout Guidelines

12.1.1 Thermal Management

Power consumption of the LMK04228 of devices can be high enough to require attention to thermal

management. For reliability and performance reasons the die temperature should be limited to a maximum of

125°C. That is, as an estimate, T_A(ambient temperature) plus device power consumption times R_θJAshould not

exceed 125°C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to a printed-circuit board. To maximize the removal of heat from the package, a thermal land

pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

7.2 mm

0.2 mm

1.46 mm

1.15 mm

Figure 15. Recommended Land and Via Pattern

81

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

12.2 Layout Example

Figure 16. LMK04228 Layout Example

82

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

13 器件和文档支持

13.1 器件支持

13.1.1 TICS Pro

免费 EVM 编程软件。还可用于生成寄存器映射，以便为特定的应用进行编程。

要下载 TICS Pro，请转到 www.ti.com.cn/tool/cn/ticspro-sw。

13.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 商标

PLLatinum, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

83

GENERIC PACKAGE VIEW

NKD 64

9 x 9, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4229637/A

www.ti.com

PACKAGE OUTLINE

NKD0064A

WQFN - 0.8 mm max height

S

C

A

L

E

1

.

6

0

WQFN

9.1

8.9

A

B

PIN 1 INDEX AREA

0.5

0.3

9.1

8.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

C

SEATING PLANE

(0.1)

TYP

7.2 0.1

SEE TERMINAL

DETAIL

17

32

60X 0.5

33

16

4X

7.5

1

48

0.3

64X

PIN 1 ID

64

49

0.2

(OPTIONAL)

0.1

C A

C

B

0.5

0.3

64X

0.05

4214996/A 08/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

NKD0064A

WQFN - 0.8 mm max height

WQFN

(

7.2)

SYMM

64X (0.6)

64X (0.25)

SEE DETAILS

49

64

1

48

60X (0.5)

SYMM

(8.8)

(1.36)

TYP

8X (1.31)

33

(

0.2) VIA

TYP

16

17

32

(1.36) TYP

8X (1.31)

(8.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214996/A 08/2013

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

NKD0064A

WQFN - 0.8 mm max height

WQFN

SYMM

(1.36) TYP

49

64X (0.6)

64X (0.25)

64

1

48

(1.36)

TYP

60X (0.5)

SYMM

(8.8)

METAL

TYP

16

33

17

32

25X (1.16)

(8.8)

SOLDERPASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

EXPOSED PAD

65% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4214996/A 08/2013

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMK04228NKDR
厂家：	TEXAS INSTRUMENTS
描述：	具有双环 PLL 的超低噪声时钟抖动消除器 \| NKD \| 64 \| -40 to 85 时钟
文件：	总90页 (文件大小：2006K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK04228NKDR [TI]

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