LMK04616ZCRT [TI]
符合 JESD204B 标准的超低噪声和低功耗时钟抖动消除器 | ZCR | 144 | -40 to 85;型号: | LMK04616ZCRT |
厂家: | TEXAS INSTRUMENTS |
描述: | 符合 JESD204B 标准的超低噪声和低功耗时钟抖动消除器 | ZCR | 144 | -40 to 85 时钟 |
文件: | 总138页 (文件大小:2724K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LMK04616
ZHCSG70B –MARCH 2017–REVISED JULY 2019
具有双环路 PLL 且符合 JESD204B 标准的 LMK04616 超低噪声和低功耗
时钟抖动消除器
1 特性
•
•
•
–40ºC 至 +85ºC 工业环境温度
支持 105ºC PCB 温度(在散热焊盘上测量)
1
•
•
双环路 PLL 架构
超低噪声(10kHz 至 20MHz):
LMK04616:10mm × 10mm NFBGA-144 封装,
间距为 0.8mm
–
–
–
1966.08MHz 频率下 48fs RMS 抖动
983.04MHz 频率下 50fs RMS 抖动
122.88MHz 频率下 61fs RMS 抖动
2 应用
•
LTE-BTS、小型蜂窝、远程射频单元 (RRU) 等无
线基础设施
•
•
122.88MHz 时具有 –165dBc/Hz 本底噪声
JESD204B 支持
•
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数据转换器和集成收发器时钟
网络、SONET/SDH、DSLAM
测试和测量
–
一次性、脉冲和连续 SYSREF
•
16 个差动输出时钟(处于 8 个频率组中)
–
介于 700mVpp 和 1600mVpp 之间的可编程输
出摆幅
3 说明
–
–
–
–
–
每个输出对可配置为 SYSREF 时钟输出
16 位通道分频器
LMK0461x 器件系列具有业界性能最高且功耗最低的
抖动清除器,支持 JESD204B 接口。可以配置 16 个
时钟输出以驱动 8 个 JESD204B 转换器或其他逻辑器
件(使用器件和 SYSREF 时钟)。可以配置第 17 个
输出,以提供来自 PLL2 的信号或来自外部 VCXO 的
副本。
最小 SYSREF 频率为 25kHz
最大输出频率为 2GHz
精密数字延迟,动态可调
–
数字延迟 (DDLY) ½ × 时钟分配路径频率
(最大 2GHz)
完全 集成的 PLL1 和 PLL2 环路滤波器、大量的集成
LDO、数字和模拟延迟、提供 3.3V、2.5V 和 1.8V 输
出的灵活性以及同时生成多个 SYSREF 域的灵活性等
特性使得该器件易于使用。
–
–
60ps 步长模拟延迟
50% 占空比输出分配,1 至 65535
(偶数和奇数)
•
4 个基准输入
–
–
–
输入丢失时采用保持模式
可以为传统计时 系统 配置 17 个输出中的每一个,不
限于 JESD204B 应用。
自动和手动切换模式
信号损失 (LOS) 检测
器件信息(1)
•
•
在 16 个有源输出下的典型功耗为 1.05W
器件型号
LMK04616
VCO 频率
通常由 1.8V(输出、输入)和 3.3V 电源(数字、
PLL1、PLL2_OSC、PLL2 内核)供电
5870MHz 至 6175MHz
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
•
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完全集成的可编程环路滤波器
PLL2
简化原理图
–
–
–
PLL2 相位检测器频率高达 250MHz
OSCin 倍频器
Multiple —clean“
clocks at different
frequencies
集成式低噪声 VCO
OSCout
VCXO
LMX2582
Recovered
—dirty“ clock or
clean clock
PLL+VCO
•
•
内部功率调节:优于 –80dBc PSRR(在 VDDO
上)(对于 122.88MHz 差动输出)
CLKin0
Backup
Reference
Clock
CLKout9
FPGA
3 线制或 4 线制 SPI 接口(4 线制为默认设置)
CLKout10
LMK0461x
CLKin1
CLKout5 &
CLKout6
CLKout1 &
CLKout2
DAC
ADC
CLKout7 &
CLKout8
CLKout3 &
CLKout4
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS663
LMK04616
ZHCSG70B –MARCH 2017–REVISED JULY 2019
www.ti.com.cn
目录
7.20 Typical Characteristics.......................................... 19
Parameter Measurement Information ................ 21
8.1 Differential Voltage Measurement Terminology ..... 21
8.2 Output Termination Scheme ................................... 21
Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
9.2 Functional Block Diagram ....................................... 25
9.3 Feature Description................................................. 26
9.4 Device Functional Modes........................................ 55
9.5 Programming........................................................... 57
9.6 Register Maps......................................................... 59
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 5
Pin Configuration and Functions......................... 5
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 9
8
9
10 Application and Implementation...................... 122
10.1 Application Information........................................ 122
10.2 Typical Application .............................................. 123
10.3 Do's and Don'ts................................................... 125
11 Power Supply Recommendations ................... 126
11.1 Recommended Power Supply Connection ......... 126
7.5 Digital Input and Output Characteristics (CLKin_SEL,
STATUSx, SYNC, RESETN) ................................... 10
7.6 Clock Input Characteristics (CLKinX)...................... 10
7.7 Clock Input Characteristics (OSCin) ....................... 11
7.8 PLL1 Specification Characteristics ......................... 12
7.9 PLL2 Specification Characteristics ......................... 12
7.10 Clock Output Type Characteristics (CLKoutX)...... 13
7.11 Oscillator Output Characteristics (OSCout) .......... 14
11.2 Current Consumption / Power Dissipation
Calculations............................................................ 126
12 Layout................................................................. 127
12.1 Layout Guidelines ............................................... 127
12.2 Layout Example .................................................. 128
13 器件和文档支持 ................................................... 129
13.1 器件支持 ............................................................. 129
13.2 接收文档更新通知 ............................................... 129
13.3 社区资源.............................................................. 129
13.4 商标..................................................................... 129
13.5 静电放电警告....................................................... 129
13.6 Glossary.............................................................. 129
14 机械、封装和可订购信息..................................... 129
7.12 Jitter and Phase Noise Characteristics for CLKoutX
and OSCout ............................................................. 15
7.13 Clock Output Skew and Isolation Characteristics . 16
7.14 Clock Output Delay Characteristics ...................... 16
7.15 DEFAULT POWER on RESET CLOCK OUTPUT
Characteristics ......................................................... 16
7.16 Power Supply Characteristics ............................... 17
7.17 Typical Power Supply Noise Rejection
Characteristics ......................................................... 17
7.18 SPI Interface Timing ............................................. 18
7.19 Timing Diagram..................................................... 18
4 修订历史记录
Changes from Revision A (May 2017) to Revision B
Page
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删除了双环路 PLL 架构 特性要点下的项目列表 ..................................................................................................................... 1
添加了超低噪声 特性要点 ....................................................................................................................................................... 1
将 VCO 频率单位从“5.8GHz 至 6.175GHz”更改为“5870MHz 至 6175MHz”.......................................................................... 1
Changed VCO frequency from: 5800 MHz to: 5870 MHz...................................................................................................... 5
Added PACKAGE column to device configuration information table ..................................................................................... 5
Added Footnote and link to LMK04610 datasheet ................................................................................................................ 5
Added OSCout polarity information to the OSCout/OSCout* pin description ........................................................................ 6
Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz ..................................................................... 12
Changed VCO tuning range minimum from: 5800 to: 5870................................................................................................. 12
Changed VOD symbol to VOD,pp to match mVpp units. .......................................................................................................... 13
Changed VOD symbol to VOD,pp to match mVpp units. ......................................................................................................... 14
Added content to the HSDS 4/6/8mA section ..................................................................................................................... 21
Added content to the HCSL section .................................................................................................................................... 22
Changed the VCXO Buffered Output section ...................................................................................................................... 23
Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz ........................... 24
Added content to the Programmable Output Formats section ............................................................................................ 24
2
版权 © 2017–2019, Texas Instruments Incorporated
LMK04616
www.ti.com.cn
ZHCSG70B –MARCH 2017–REVISED JULY 2019
修订历史记录 (接下页)
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Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 33
Changed HCSL to LVPECL graphic..................................................................................................................................... 33
Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 34
Changed HSDS to LVPECL graphic .................................................................................................................................... 34
Added content to the OSCout section ................................................................................................................................. 37
Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. .................................................... 37
Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values..................................................................... 40
Changed PLL1_PROP max from 255 to 127. ..................................................................................................................... 40
Added PLL1_PROP_FL to table. ......................................................................................................................................... 40
Changed PLL1_INTG and PLL1_INTG_FL settings for specific case examples. ............................................................... 40
Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse mode......................................................................... 41
Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode ....................................................................... 41
Deleted higher order poles information ................................................................................................................................ 41
Added C3 maximum capacitance recommendation ............................................................................................................ 41
Deleted Examples of PLL1 Setting....................................................................................................................................... 41
Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHz ......................................................................... 43
Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic .............................................. 44
Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value ................................ 47
Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value .............................................................................. 47
Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) ................................................................................ 52
Changed CLKout7 to CLKout6 and CLKout8 to CLKout9 for zero delay feedback clocks. ................................................ 52
Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchart......................................... 54
Deleted references to tunable crystal .................................................................................................................................. 55
Deleted use of external VCO for PLL2................................................................................................................................. 55
Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequence ............................. 58
Changed PLL1_PROP from 8 bit to 7 bit field in register map ............................................................................................ 61
Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map ..................................................................................... 61
Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67,
0x68, 0x69 to RSRVD in register map ................................................................................................................................ 61
•
•
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•
Changed PLL2_PROP from 8 bit to 6 bit field in register map ............................................................................................ 62
Changed PLL2_INTG from 8 bit to 5 bit field in register map ............................................................................................. 62
Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register map................................................................... 63
Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register
map....................................................................................................................................................................................... 63
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Added register 0xF6 for PLL2_DLD_EN in register map ..................................................................................................... 63
Changed channel 7 and 8 to channel 6 and 9 for feedback enable FBBUF_CHx_EN in register map............................... 64
Deleted unused DEVID values............................................................................................................................................. 66
Changed reset value for CHIPID from 0x1 to 0x3................................................................................................................ 66
Changed reset value for CHIPVER from 0x1 to 0x15 ......................................................................................................... 66
Changed PLL1_PROP from 8 bit to 7 bit field in register definition .................................................................................... 88
Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition .............................................................................. 88
Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit description .............................. 89
Changed PLL2_PROP field size from 8 bits to 6 bits in register definition ......................................................................... 93
Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definition ...................................................................... 95
Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition ............................... 96
Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definition.................. 96
版权 © 2017–2019, Texas Instruments Incorporated
3
LMK04616
ZHCSG70B –MARCH 2017–REVISED JULY 2019
www.ti.com.cn
修订历史记录 (接下页)
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Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 .............................................................................. 100
Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 .............................................................................. 100
Added note for using PLL1/2 REF/FB(SYS) status output for SYNC ............................................................................... 103
Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN.................................................. 104
Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and
PD_VCO_LDO.................................................................................................................................................................... 104
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Added register 0xF6 to register description. New field PLL2_DLD_EN............................................................................. 105
Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN .............................................................. 106
Changed Channel 6 and 9 FBClock Buffers from: Low Skew to: Zero Delay Mode.......................................................... 118
Changed OUTCH8 and OUTCH7 to OUTCH9 and OUTCH6............................................................................................ 118
Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW
SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text ........ 122
•
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Updated minimum lock time calculation example to reflect updated register names and count frequency ...................... 122
Simplified HSDS format description .................................................................................................................................. 127
Changes from Original (March 2017) to Revision A
Page
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将文本从“–70dBc PSRR”更改为“–80dBc PSRR(在 VDDO 上).......................................................................................... 1
将 SPI 接口默认设置从 3 线制更改为 4 线制.......................................................................................................................... 1
将 VCO 频率从“5.8GHz 至 6.2GHz”更改为“5.8GHz 至 6.175GHz”........................................................................................ 1
Changed VCO frequency from: 6200 MHz to: 6175 MHz...................................................................................................... 5
Removed tablenote from the doubler input frequency parameter........................................................................................ 12
Changed VCO tuning range maximum from: 6200 to: 6175................................................................................................ 12
Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258-MHz Phase detector frequency............ 12
Removed tablenote from the output frequency parameter................................................................................................... 14
Changed output frequency maximum from: 800 MHz to: 1000 MHz .................................................................................. 14
Added content to the Driving CLKin and OSCin Pins With a Differential Source section.................................................... 30
Updated Figure 36 ............................................................................................................................................................... 40
Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHz ......................................................................... 43
Updated Figure 48 ............................................................................................................................................................... 53
4
Copyright © 2017–2019, Texas Instruments Incorporated
LMK04616
www.ti.com.cn
ZHCSG70B –MARCH 2017–REVISED JULY 2019
5 Device Comparison Table
Table 1. Device Configuration Information
OSCout (BUFFERED
PLL2
REFEREN
CE
INPUTS
OSCin CLOCK) AC-
LVPECL/ AC-LVDS/
LVCMOS
PROGRAMMABLE
HCSL/HSDS
OUTPUTS
PART NUMBER
VCO FREQUENCY
PACKAGE
LMK04610
LMK04616
2
4
1
1
10
16
5870 to 6175 MHz
5870 to 6175 MHz
VQFN-56(1)
NFBGA-144
(1) Refer to LMK04610 datasheet.
6 Pin Configuration and Functions
ZCR Package
144-Pin NFBGA
Top View
1
2
3
4
5
6
7
8
9
10 11
12
CLKout
14N
CLKout CLKout
13N 12N
CLKout CLKout
11N 10N
CLKout CLKout
9P 8P
OSC
INP
A
B
C
D
E
CLKout
14P
CLKout CLKout
13P
CLKout CLKout
11P 10P
CLKout CLKout
9N
OSC
INN
12P
8N
CLKout VDDO
14-15
VDDO
12-13
VDDO
10-11
VDDO
8_9
15N
CLKout
15P
CTRL
VCXO
OSC
OUTP
NC
NC
NC
VDD_ PLL2_V
PLL2_ COLDO
STATUS
0
PLL1_C
AP
VDD
OSC
OSC
OUTN
OSC
_CAP
PLL2_L
DO_CA
P
STATUS
1
VDD
PLL1
F
VDD_
SDIO PLL2_C
ORE
CLKin CLKin0
N
G
H
J
SCL
CLKin0P
CLKin1P
CLKin2P
SEL
VDD
CORE
VDD CLKin1
SYNC
SCS
_IO
N
CLKout
0P
RESETN
CLKout VDDO
VDDO
2-3
VDDO
4-5
VDDO
6-7
CLKin2
N
K
L
0N
0-1
CLKout
1P
CLKout CLKout
CLKout CLKout
4P 5P
CLKout CLKout
6N 7P
CLKin3P
2P
3P
CLKout
1N
CLKout CLKout
2N 3N
CLKout CLKout
CLKout CLKout
6P 7N
CLKin3
N
M
4N
5N
OUTPUT
CAPS
GND
OTHER
VDD
INPUT
STATUS/Control
OSCin/out
A. LMK04616
Copyright © 2017–2019, Texas Instruments Incorporated
5
LMK04616
ZHCSG70B –MARCH 2017–REVISED JULY 2019
www.ti.com.cn
Pin Functions: LMK04616(1)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
POWER
VDD_CORE
VDD_IO
H4
H10
E11
F9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
P
P
P
P
P
P
P
P
P
P
P
P
P
3.3-V power supply for core
1.8-V to 3.3-V power supply for input block
VDD_OSC
VDD_PLL1
VDD_PLL2CORE
VDD_PLL2OSC
VDDO_0/1
VDDO_2/3
VDDO_4/5
VDDO_6/7
VDDO_8/9
VDDO_10/11
VDDO_12/13
VDDO_14/15
1.8-V to 3.3-V power supply for OSCout
3.3-V power supply for PLL 1
G3
E3
3.3-V power supply for PLL 2
3.3-V power supply for PLL2 VCO
K2
1.8-V to 3.3-V power supply for CLKout0 and CLKout1
1.8-V to 3.3-V power supply for CLKout2 and CLKout3
1.8-V to 3.3-V power supply for CLKout4 and CLKout5
1.8-V to 3.3-V power supply for CLKout6 and CLKout7
1.8-V to 3.3-V power supply for CLKout8 and CLKout9
1.8-V to 3.3-V power supply for CLKout10 and CLKout11
1.8-V to 3.3-V power supply for CLKout12 and CLKout13
1.8-V to 3.3-V power supply for CLKout14 and CLKout15
K5
K8
K10
C10
C8
C5
C2
A2, A5, A8, A11,
B2, B5, B8, B11,
C3, C4, C6, C7,
C9, C11, C12, D2,
D6, D7, D8, D9,
D11, E2, E5, E6,
E7, E8, E10, F2,
F3, F5, F6, F7,
F8, F10, F11, F12,
G4, G5, G6, G7,
G8, G9, H3, H5,
H6, H7, H8, H9,
J3, J4, J5, J6, J7,
J8, J9, J10, J11,
K3, K4, K6, K7,
K9, K11, L2, L5,
L8, L11, M2, M5,
M8, M11
Die attach pad.
The DAP is an electrical connection and provides a thermal dissipation path. For proper
electrical and thermal performance of the device, the DAP must be connected to the PCB
ground plane.
VSS
—
GND
PLL
CTRL_VCXO
PLL1_CAP
PLL2_LDO_CAP
D10
E9
—
—
—
Analog
Analog
Analog
VCXO control output
PLL1 LDO capacitance – 10-µF external
PLL2 LDO capacitance – 10-µF external
F4
PLL2_VCO_LDO_
CAP
E4
—
Analog
PLL2 LDO capacitance – 10-µF external
INPUT BLOCK
OSCin
A12
B12
G10
G12
G11
H12
H11
J12
Feedback to PLL1, reference input to PLL2.
Accepts both differential or single-ended (VCXO)
I
I/O
I
Analog
CMOS
Analog
OSCin*
CLKin_SEL
CLKin0
Manual reference input selection for PLL1 weak pullup resistor.
Reference clock input port 0 for PLL1.
CLKin0*
CLKin1
I
I
I
Analog
Analog
Analog
Reference clock input port 1 for PLL1.
Reference clock input port 2 for PLL1.
Reference clock input port 3 for PLL1.
CLKin1*
CLKin2
CLKin2*
K12
L12
M12
CLKin3
CLKin3*
OUTPUT BLOCK
OSCout
D12
E12
J1
Buffered output of OSCin port. When using differential output mode, OSCout polarity is
reversed from OSCin polarity.
O
O
Programmable
Programmable
OSCout*
CLKout0
CLKout0*
Differential clock output pair 0.
K1
(1) See Pin Connection Recommendations section for recommended connections.
6
Copyright © 2017–2019, Texas Instruments Incorporated
LMK04616
www.ti.com.cn
ZHCSG70B –MARCH 2017–REVISED JULY 2019
Pin Functions: LMK04616(1) (continued)
PIN
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TYPE
DESCRIPTION
NAME
NO.
L1
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
CLKout4
CLKout4*
CLKout5
CLKout5*
CLKout6
CLKout6*
CLKout7
CLKout7*
CLKout8
CLKout8*
CLKout9
CLKout9*
CLKout10
CLKout10*
CLKout11
CLKout11*
CLKout12
CLKout12*
CLKout13
CLKout13*
CLKout14
CLKout14*
CLKout15
CLKout15*
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Differential clock output pair 1.
Differential clock output pair 2.
Differential clock output pair 3.
Differential clock output pair 4.
Differential clock output pair 5.
Differential clock output pair 6.
Differential clock output pair 7.
Differential clock output pair 8.
Differential clock output pair 9.
Differential clock output pair 10.
Differential clock output pair 11.
Differential clock output pair 12.
Differential clock output pair 13.
Differential clock output pair 14.
Differential clock output pair 15.
M1
L3
M3
L4
M4
L6
M6
L7
M7
M9
L9
L10
M10
A10
B10
A9
B9
B7
A7
B6
A6
B4
A4
B3
A3
B1
A1
D1
C1
DIGITAL CONTROL / INTERFACES
NC
D3, D4, D5
—
I
Analog
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Do not connect.
RESETN
SCL
J2
G1
H2
G2
E1
F1
Device reset input
I
SPI serial clock.
SCS*
I
SPI serial chip select (active low).
SPI serial data input and output
SDIO
I/O
I/O
I/O
STATUS0
STATUS1
Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details.
Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details.
Synchronization of output divider, definition of OSCout divider or programmable status
pin. See STATUS0/1 and SYNC Pin Functions for more details.
SYNC
H1
I/O
CMOS
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
VDD_IO
Supply voltage for input(3)
Supply voltage for digital(3)
Supply voltage for PLL1(3)
3.6
VDD_CORE
VDD_PLL1
3.6
V
3.6
V
VDD_PLL2CORE Supply voltage for PLL2 core
3.6
V
VDD_PLL2OSC
VDD_OSC
VDDO_x
Supply voltage for PLL2 OSC(3)
Supply voltage for OSCout(3)
Supply voltage for CLKoutX
3.6
3.6
V
V
3.6
V
VIN_clk
Input voltage for CLKinX and OSCin(3)
(VDD_IO + 0.3)
V
Input voltage for digital and status pins (CLKin_SEL, SCK, SDIO,
SCS*, STATUSx, SYNC, RESETN)
VIN_gpio
–0.3
2.1
V
TL
Lead temperature (solder 4 s)
Junction temperature
Input current
+260
125
20
°C
°C
TJ
IIN
mA
MSL
Tstg
Moisture sensitivity level
Storage temperature
3
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress
ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation
sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
(3) Never to exceed 3.6 V.
7.2 ESD Ratings
VALUE
±2000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101(3)
Machine model
Electrostatic
discharge(1)
V(ESD)
V
±150
(1) This device is a high performance RF integrated circuit with an ESD rating up to 2-kV human-body model, up to 150-V machine model,
and up to 250-V charged-device model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free
workstations.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
TJ
Junction temperature
125
85
°C
°C
°C
V
TA
Ambient temperature
–40
25
TPCB
PCB temperature (measured at thermal pad)
Supply voltage for input
105
VDD_IO
1.7
3.135
3.135
3.135
3.135
1.7
1.8 3.465
3.3 3.465
3.3 3.465
3.3 3.465
3.3 3.465
1.8 3.465
1.8 3.465
VDD_CORE
VDD_PLL1
VDD_PLL2CORE
VDD_PLL2OSC
VDD_OSC
VDDO_x
Supply voltage for digital
V
Supply voltage for PLL1
V
Supply voltage for PLL2 Core
Supply voltage for PLL2 OSC
Supply voltage for OSCout
Supply voltage for CLKoutX
V
V
V
1.7
V
8
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LMK04616
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ZHCSG70B –MARCH 2017–REVISED JULY 2019
7.4 Thermal Information
LMK04616
THERMAL METRIC(1)
ZCR (NFBGA)
176 PINS
45.0
UNIT
RθJA
Junction-to-ambient thermal resistance(2)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
14-layer, 200-mm × 150-mm board, 144
thermal vias, airflow = 0 LFM
23.3
12.5
0.1
RθJC(top)
Junction-to-case (top) thermal resistance(3)
14-layer, 200-mm × 150-mm board, 144
thermal vias, airflow = 0 LFM
25.2
18.3
0.2
RθJB
Junction-to-board thermal resistance(4)
14-layer, 200-mm × 150-mm board, 144
thermal vias, airflow = 0 LFM
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
8-layer, 200-mm × 150-mm board, 21
thermal vias, airflow = 0 LFM
27.7
24.9
0.1
ψJB
8-layer, 200-mm × 150-mm board, 21
thermal vias, airflow = 0 LFM
n/a
RθJC(bot)
8-layer, 200-mm × 150-mm board, 21
thermal vias, airflow = 0 LFM
21.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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7.5 Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level output voltage
(STATUSX, SYNC)
IOH = –500 µA
1.8-V mode
VOH
VOL
VOH
VOL
1.2
1.9
0.6
1.9
0.6
V
V
V
V
Low-level output voltage
(STATUSX, SYNC)
IOL = 500 µA
1.8-V mode
0
1.2
0
High-level output voltage
(SDIO)
IOH = –500 µA during SPI read
1.8-V mode
Low-level output voltage
(SDIO)
IOL = 500 µA during SPI read
1.8-V mode
High-level input voltage
VIH
1.3
0
1.9
V
(CLKin_SEL, STATUSX, SYNC,
RESETN, SCK, SDIO, SCS*)
Low-level input voltage
(CLKin_SEL, STATUSX, SYNC,
RESETN, SCK, SDIO, SCS*)
VIL
0.45
V
V
Mid-level input voltage
(CLKin_SEL, SYNC)
VMID
0.8
–10
10
1.0
10
High-level input current
VIH = 1.8 V
(CLKin_SEL, RESETN)
Internal pullup
IIH
µA
Internal pulldown
Internal pullup
60
Low-level input current
VIL = 0 V
(CLKin_SEL, RESETN)
–60
–10
–10
10
IIL
µA
µA
Internal pulldown
High-level input current (SCK, SDIO,
SCS*, SYNC)
IIH
VIH = 1.8 V
–10
10
10
Low-level input current (SCK, SDIO,
SCS*, SYNC)
IIL
VIL = 0
–10
25
µA
ns
tLOW
RESETN pin held low for device reset
7.6 Clock Input Characteristics (CLKinX)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
Clock input frequency
Differential input slew rate
TEST CONDITIONS
MIN
5
TYP
MAX UNIT
(1)
Single-ended, DC-coupled
Single-ended, AC-coupled
500
(1)
fCLKin
5
500
600
MHz
(2)
Differential, AC-coupled
5
(3)
SLEWDIFF
SLEWSE
20% to 80%
0.2
0.1
6
3
V/ns
V/ns
(3)
Single-ended input slew rate
20% to 80%
DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
0.5
0.5
3.3
3.3
VCLKin
Single-ended input voltage
Vpp
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
(1) See Driving CLKin and OSCin Pins With a Single-Ended Source.
(2) See Driving CLKin and OSCin Pins With a Differential Source.
(3) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended differential slew rate for
all input clocks is 3 V/ns; this is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
10
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Clock Input Characteristics (CLKinX) (continued)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(4)
Peak-to-peak differential input voltage
See Figure 9
VID,pp
IDC
AC-coupled
0.4
3.3
Vpp
Input duty cycle
45%
50%
55%
No LOS state change with single-
ended, peak-to-peak input voltage
noise injects to either CLKinX or
CLKinX* or to both in phase.
Measured with 1-MHz sinusoidal
signal
Rejected input voltage noise during LOS
condition
VNoise
40
mV
(4) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
7.7 Clock Input Characteristics (OSCin)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX UNIT
(2)
Single-ended, AC-coupled
300
MHz
600
(1)
fOSCin
PLL2 reference input
(3)
Differential, AC-coupled
10
SLEWDIFF
SLEWSE
Differential input slew rate(4)
Single-ended input slew rate(4)
20% to 80%
20% to 80%
0.2
0.1
6
3
V/ns
V/ns
AC-coupled to OSCin;
OSCin* AC-coupled to Ground
VOSCin
Single-ended input voltage
0.5
3.3
Vpp
Vpp
Peak-to-peak differential input voltage(5)
See Figure 9
VID,pp
IDC
AC-coupled
0.4
3.3
Input duty cycle
45%
50%
55%
(1) FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
(2) See Driving CLKin and OSCin Pins With a Single-Ended Source.
(3) See Driving CLKin and OSCin Pins With a Differential Source.
(4) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended differential slew rate for
all input clocks is 3 V/ns; this is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
(5) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
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7.8 PLL1 Specification Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fPD1
PLL1 phase detector frequency
CTRL_VCXO tune voltage
4
MHz
V
VTUNE
0
3.3
PLL 1/f noise at 10-kHz offset.
Normalized to 1 GHz output
frequency.
10-Hz loop bandwidth
–130
–131
PN10kHz
dBc/Hz
(1)
300-Hz loop bandwidth
BWmin
BWmax
Minimum PLL1 bandwidth
Maximum PLL1 bandwidth
3
Hz
Hz
300
Measured with PLL1 only. PLL1
Bandwidth set to 50 Hz. PLL1 PFD
update frequency 1 MHz.
PFDspur
PLL1 PFD update spur
–150
–100 dBc/Hz
(1) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
7.9 PLL2 Specification Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EN_PLL2_REF_2X = 1(1)
OSCin duty cycle 40% to 60%
;
fdoubler_max
fPD2
Doubler input frequency
125
250
MHz
MHz
(2)
Phase detector frequency
PLL 1/f noise at 10-kHz offset.(3)
Normalized to
1-GHz output frequency
PN10kHz
fVCO
400-kHz loop bandwidth
–120
dBc/Hz
MHz
°C
VCO tuning range
5870
6175
145
After programming for lock, no changes
to output configuration are permitted to
assure continuous lock
Allowable temperature drift for
continuous lock(4)
|ΔTCL
|
BWmin
BWmax
Minimum PLL2 bandwidth
Maximum PLL2 bandwidth
90
kHz
kHz
1000
(1) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
(2) Assured by characterization. ATE tested at 258-MHz Phase detector frequency.
(3) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(4) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value and still
have the part stay in lock; this implies the part will work over the entire frequency range. However, if the temperature drifts more than
the maximum allowable drift for continuous lock, it will be necessary to reload the appropriate register to ensure it stays in lock.
Regardless of what temperature the part was initially programmed at, the temperature must never drift outside the frequency range of
–40°C to 105°C without violating specifications.
12
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7.10 Clock Output Type Characteristics (CLKoutX)(1)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
4-mA HSDS
MIN
TYP
MAX UNIT
1000
6-mA HSDS
1500
MHz
2000
fCLKout
Output frequency
8-mA HSDS
16-mA HCSL
4-mA HSDS
1500
55%
55%
55%
60%
55%
45%
45%
45%
40%
45%
50%
50%
50%
6-mA HSDS
ODC
Output duty cycle
8-mA HSDS
8-mA HSDS, >1.5 GHz
16-mA HCSL
50%
148
164
148
73
4-mA HSDS
245.76 MHz, 20%
to 80%,
RL = 100 Ω
6-mA HSDS
8-mA HSDS
16-mA HCSL
4-mA HSDS
6-mA HSDS
8-mA HSDS
16-mA HCSL
TR
Output rise time
ps
149
163
146
74
245.76 MHz, 80%
to 20%,
RL = 100 Ω
T F
Output fall time
ps
4-mA HSDS
6-mA HSDS
8-mA HSDS
16-mA HSCL
4-mA HSDS
6-mA HSDS
8-mA HSDS
16-mA HSCL
4-mA HSDS
6-mA HSDS
8-mA HSDS
16-mA HSCL
4-mA HSDS
6-mA HSDS
8-mA HSDS
16-mA HCSL
0.5
0.72
0.75
0.75
0.1
0.75
1.06
V
VOH
Output high voltage
Output low voltage
Differential output voltage
1.3
1.04
0.18
0.15
0.17
0.0
0.26
V
VOL
0.31
0.05
mVpp
15
958
1380
1544
1807
VOD,pp
–15
–20
–90
–15
20
Change in VOD for complementary
output states
ΔVOD
mVpp
115
15
(1) See test load description in Output Termination Scheme.
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7.11 Oscillator Output Characteristics (OSCout)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
2-pF load, 1.8-V LVCMOS(2)
4-mA HSDS(2)
MIN
TYP
MAX UNIT
200
1000
MHz
1000
(1)
fCLKout
Output frequency
8-mA HSDS(2)
16-mA HCSL(2)
400
55%
55%
55%
55%
2-pF load, 1.8-V LVCMOS
4-mA HSDS
45%
45%
45%
45%
50%
50%
50%
50%
156
ODC
Output duty cycle
8-mA HSDS
16-mA HCSL
20% to 80%, CL = 2 pF, 1.8 V LVCMOS
80% to 20%, CL = 2 pF, 1.8 V LVCMOS
273
< 300 MHz, 20 % to 80 %, RL = 100 Ω,
4-mA HSDS
176
152
183
300
> 300 MHz, 20 % to 80 %, RL = 100
Ω, 4-mA HSDS
TR / T F
Output rise/fall time
ps
< 300 MHz, 20% to 80%, RL = 100 Ω, 8-
mA HSDS
300
> 300 MHz, 20 % to 80 %, RL = 100 Ω,
8-mA HSDS
138
135
20 % to 80 %, RL = 100 Ω, 16-mA HCSL
1-mA load, 1.8-V LVCMOS
4-mA HSDS
1.44
0.46
0.82
0.61
0.7
V
VOH
Output high voltage
8-mA HSDS
1.19
16-mA HCSL
0.89
0.36
1-mA load, 1.8-V LVCMOS
4-mA HSDS
0.1
0.22
V
VOL
Output low voltage
8-mA HSDS
0.11
0.24
16-mA HCSL
0.02
775
1548
1360
–25
26
0.06
950
4-mA HSDS
600
1240
1000
VOD,pp
Differential output voltage
8-mA HSDS
mVpp
16-mA HCSL
IOH
IOL
Output high current (source)
Output low current (sink)
VOUT = 2 pF to GND, 1.8-V LVCMOS
VOUT = 2 pF to GND, 1.8-V LVCMOS
DC-Coupled, 4-mA HSDS
DC-Coupled, 8-mA HSDS
DC-Coupled, 16-mA HCSL
IOUT at VOUT = 0.9 V
mA
mA
0.1
0.3
0.34
0.55
0.34
67
0.45
VOX
Output common mode
Output impedance
0.7
V
ROUT
Ω
(1) OSCout Divider maximum input frequency is 1.5 GHz.
(2) See test load description in Output Termination Scheme.
14
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7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
HSDS 4 mA
MIN
TYP
–166
–166
–166
–165
MAX UNIT
HSDS 6 mA
HSDS 8 mA
Noise floor
20-MHz offset
HCSL 16 mA
L(f)CLKout/OSCoutNF
122.88 MHz
dBc/Hz
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for
PLL2(1)
OSCout, HSDS 4
mA
–161
–161
OSCout, HSDS 8
mA
OSCout, LVCMOS
HSDS 4 mA
–156
–151
–151
–151
Noise floor with analog delay
enabled
20-MHz offset
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for
PLL2(1)
HSDS 6 mA
122.88 MHz,
maximum analog
delay setting
L(f)CLKoutNF,ADLY
dBc/Hz
HSDS 8 mA
HCSL 16 mA
–151
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 800 kHz
Offset = 1 MHz
–97
–126
–139
–147
–158
–159
–166
–165
–97
SSB phase noise(2)
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
L(f)CLKoutPN
dBc/Hz
400-kHz loop bandwidth for PLL2
(1) (3)
HSDS 8 mA
HCSL 16 mA
Offset = 10 MHz
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
Offset = 10 MHz
SSB phase noise
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
–136
–148
–157
–160
–160
160
L(f)OSCoutPN
dBc/Hz
fs rms
400-kHz loop bandwidth for PLL2
(1) (3)
HSDS 4 mA
HSDS 8 mA
fCLKout = 122.88 MHz
Integrated RMS jitter
≤ 100-Hz loop bandwidth for PLL1
HSDS 8 mA, BW = 100 Hz to 20 MHz
HSDS 8 mA, BW = 10 kHz to 20 MHz
HCSL 16 mA, BW = 100 Hz to 20 MHz
HCSL 16 mA, BW = 10 kHz to 20 MHz
75
JCLKout
160
400-kHz loop bandwidth for PLL2
(1) (4)
75
(1) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
(2) Phase noise is defined in dual-loop mode and in single PLL mode if OSCin is used as the ref input.
(3) The input is configured to either a full swing AC-coupled, single-ended signal or a LVDS like AC-coupled differential signal. The input
frequency is 122.88 MHz. VDD_IN is at 1.8 V.
(4) PLL1 and PLL2 settings optimized to meet multicarrier GSM phase-noise specifications. For RMS jitter optimized settings, see PLL1 and
PLL2.
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7.13 Clock Output Skew and Isolation Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Same format, after SYNC
FCLK = 245.76 MHz, RL= 100 Ω, AC-coupled
Maximum CLKoutX to
CLKoutY
|TSKEW
|
60
95
|ps|
Buffer mode
fin=fout=122.88 MHz
CLKout0_TYPE = HSDS 8 mA
tPDCLKin0_
CLKoutX
Absolute propagation delay
from CLKin0 to CLKout0
3
ns
CLKout2 = 7.68 MHz (SYSref, HSDS 8 mA,
aggressor)
CLKout3 = 122.88 MHz (DeviceClk, HSDS 8
mA, victim)
isolationSYSref-
DeviceCLKtyp
Isolation between a SYSref
signal to a DeviceClk signal(1)
–94
dBc
CLKoutX = 153.6 MHz (HSDS 8 mA,
aggressor)
CLKoutY = 122.88 MHz (HSDS 8 mA, victim)
Isolation between 2 adjacent
CLKout channels(1)
isolationCLKoutXtyp
–70
–99
–80
–80
dBc
dBc
dBc
dBc
OSCout = 30.72 MHz (HSDS 8 mA,
aggressor)
CLKoutY = 122.88 MHz (HSDS 8 mA, victim)
isolationOSCout-
CLKouttyp
Isolation between OSCout and
CLKoutX channels(1)
PLL2 PFD update frequency = 122.88 MHz
(aggressor)
CLKoutX = 491.52 MHz (HSDS 8 mA, victim)
Isolation between PLL2 PFD
update and CLKoutX
channels(1)
isolationPLL2PFD-
DeviceCLKtyp
PLL2 PFD update frequency = 122.88 MHz
(aggressor)
CLKoutX = 1228.8 MHz (HSDS 8 mA, victim)
(1) Isolation in the victim channel is measured at aggressor frequency in power spectrum relative to the carrier (victim). Measured with
< 100-Hz resolution bandwidth. Internal LDO must be enabled.
7.14 Clock Output Delay Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fADLYmax
Maximum analog delay frequency
1st Analog delay step size
Analog delay step size variation
200
MHz
ps
tstepADLY1st
300
66
tstepADLYvariation
tstepDDLY1.47456GHz
tstepDDLYvariation
Variation over all steps
ps
Digital delay step size at 1.47456 GHz Half-step enabled
Digital delay step size variation
339
0
ps
ps
7.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40 °C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SYNC pin pulled Low at start up
VCXO used is a 122.88-MHz
Crystek CVHD-950-122.880
Default OSCout clock frequency at device
power on after RESETN = 1
fCLKout-startup
122.88
MHz
(1) (2)
(1) Assured by characterization. ATE tested at 122.88 MHz.
(2) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port. All other outputs are disabled.
16
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7.16 Power Supply Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_PD
Power-down supply current
12
20
mA
16 HSDS 8-mA clocks enabled at 122.88
MHz
OSCout disabled, LOS disabled, Delays
disabled
PLL1 and PLL2 locked.
122.88 MHz at CLKin0 and 122.88-MHz
VCXO
1050
970
1200
mW
Total power consumption for
LMK04616(1)
PTotal
16 HSDS 4-mA clocks enabled at 122.88
MHz
OSCout disabled, LOS disabled, analog
and digital delay used on SYSREF
PLL1 and PLL2 locked.
1100
mW
122.88 MHz at CLKin0 and 122.88-MHz
VCXO
IDDO_X
CLKoutX supply current
IO supply current
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
See PTotal Test Condition (HSDS 8-mA)
39.2
5.3
42.8
8.4
mA
mA
mA
mA
mA
mA
mA
IDDIO
IDD_PLL1
IDD_PLL2CORE
IDD_PLL2OSC
IDD_CORE
IDD_OSC
PLL1 supply current
PLL2 core supply current
PLL2 OSC supply current
Core supply current
OSC supply current
14.8
45.5
60.7
22.5
3.2
16.1
52.0
64.9
28.6
4.1
(1) See applications section Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a specific
design.
7.17 Typical Power Supply Noise Rejection Characteristics
Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC,
VDDOx = 1.8 V, TA = 25°C, at the Recommended Operating Conditions and are not assured. Sinusoidal noise injected in
either of the following supply nodes: VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE, VDD_IO, VDD_OSC, or
VDDOx
TEST
CONDITION
VDD_PLL2 VDD_PLL2
VDD_OSC/
VDD_IO
PARAMETER
VDD_PLL1
VDD_CORE
–104
n/a
VDDOx
UNIT
OSC
CORE
PSNR10kHz
10-kHz spur on 122.88-
MHz output
dBc
–59
–94
n/a
–108
n/a
n/a
25-mV ripple on
supply.
Single HSDS 8-
mA
PSNR100kHz 100-kHz spur on 122.88-
MHz output
dBc
dBc
dBc
dBc
dBc
dBc
dBc
–71
–87
–81
–80
–88
–81
–75
–74
–101
–90
–83
–109
–98
–84
–77
–101
–93
PSNR500kHz 500-kHz spur on 122.88-
MHz output
–87
n/a
n/a
output enabled.
PSNR1MHz
1-MHz spur on 122.88-
MHz output
–100
–53
n/a
n/a
–88
PSNR10kHz
10-kHz spur on 122.88-
MHz output
–100
n/a
–104
n/a
–107
–98
50-mV ripple on
supply.
Single HSDS 8-
mA output
PSNR100kHz 100-kHz spur on 122.88-
MHz output
–65
PSNR500kHz 500-kHz spur on 122.88-
MHz output
–81
–108
–104
n/a
–87
enabled.
PSNR1MHz
1-MHz spur on 122.88-
MHz output
–94
n/a
–82
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7.18 SPI Interface Timing
TEST CONDITIONS
See 图 1
MIN
10
10
50
25
25
10
30
TYP
MAX
UNIT
ns
tds
Setup time for SDI edge to SCLK rising edge
tdH
Hold time for SDI edge from SCLK rising edge
Period of SCLK
See 图 1
See 图 1
See 图 1
See 图 1
See 图 1
ns
tSCLK
tHIGH
tLOW
tcs
ns
High width of SCLK
ns
Low width of SCLK
ns
Setup time for CS* falling edge to SCLK rising edge
ns
tcH
Hold time for CS* rising edge from SCLK rising edge See 图 1
SCLK falling edge to valid read back data See 图 1
ns
tdv
20
ns
7.19 Timing Diagram
Each serial interface access cycle is exactly (2 + N) bytes long, where N is the number of data bytes. A frame is
initiated by asserting SCS* low. The frame ends when SCS* is de-asserted high. The first bit transferred is the
R/W bit. The next 15 bits are the register address and the remaining bits are data. For all writes, data is
committed in bytes as the 8th data bit of a data field is clocked in on the rising edge of SCL. If the write access is
not an even multiple of 8 clocks, the trailing data bits are not committed. On read access, data is clocked out on
the falling edge of SCL on the SDO pin.
Four-wire mode read back has the same timing as the SDIO pin.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
See Programming for more details.
SDIO
(WRITE)
D7 to D2
R/W
A14 to A0
D1
D0
tdS
tdH
SCL
tcH
tcS
tHIGH
tLOW
tSCLK
SDIO
(Read)
D7 to
D2
D1
D0
Data valid only
during read
tdV
SCS*
图 1. SPI Timing Diagram
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7.20 Typical Characteristics
7.20.1 Clock Output AC Characteristics
NOTE
These plots show performance at frequencies beyond what the part is ensured to operate
at to give the user an idea of the capabilities of the part, but they do not imply any sort of
ensured specification.
Figure 3. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
Figure 2. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 122.88 MHz
HSDS 8 mA
CLKout2 Frequency = 122.88 MHz
HSDS 8 mA
With PLL2 3rd Order Pole
Figure 4. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
Figure 5. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 983.04 MHz
HSDS 8 mA
CLKout2 Frequency = 245.76 MHz
HSDS 8 mA
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Clock Output AC Characteristics (continued)
Figure 7. LMK0461x CLKout2 Phase Noise
Figure 6. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 1474.56 MHz
HSDS 8 mA
VCO Frequency = 6144 MHz
CLKout2 Frequency = 1228.8 MHz
HSDS 8 mA
Figure 8. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 1966.08 MHz
HSDS 8 mA
20
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8 Parameter Measurement Information
8.1 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions, causing confusion
when reading data sheets or communicating with other engineers. This section addresses the measurement and
description of a differential signal so the reader is able to understand and distinguish between the two different
definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD, depending on if
an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal
with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter; this signal does not exist in the IC with respect to ground, it only exists in reference to its differential
pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be
calculated as twice the value of VOD as described in the first description.
Figure 9 illustrates the two different definitions side-by-side for inputs and Figure 10 illustrates the two different
definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now
increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
V
ID
Definition
V
Definition for Input
ID
Non-Inverting Clock
V
V
A
B
V
IDpp
V
ID
Inverting Clock
V
= | V - V
A
|
V
= 2·V
IDpp ID
ID
B
GND
Figure 9. Two Different Definitions for
Differential Input Signals
V
Definition
V
Definition for Output
OD
OD
Non-Inverting Clock
V
V
A
B
V
ODpp
V
OD
Inverting Clock
= | V - V
V
|
V
= 2·V
ODpp OD
OD
A
B
GND
Figure 10. Two Different Definitions for
Differential Output Signals
Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for
more information.
8.2 Output Termination Scheme
This section describes the test loads setup during device characterization.
8.2.1 HSDS 4/6/8mA
Available on CLKoutX/CLKoutX* and OSCout/OSCout*. When OSCout is programmed for differential output from
OSCin, the OSCout signal will be inverted from input.
CPARA≤ 3 pF
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Output Termination Scheme (continued)
The differential transmission line impedance is 100 Ω.
Receiver
CPARA
50 Ohm
50 Ohm
VTERM
Diff Microstrip
HSDS
CPARA
Figure 11. HSDS Test and Simulation Circuit
8.2.2 HCSL
Available on CLKoutX/CLKoutX* and OSCout/OSCout*. When OSCout is programmed for differential output from
OSCin, the OSCout signal will be inverted from input..
CPARA ≤ 3 pF
The differential transmission line impedance is 100 Ω.
Receiver
CPARA
Rs (opt.)
50 Ohm
50 Ohm
VTERM
Diff Microstrip ~10cm
HSCL
50 Ohm
CPARA
Figure 12. HCSL Test and Simulation Circuit
8.2.3 LVCMOS
Available at STATUS0/1 and OSCout/OSCout*.
CLoad = 10 pF
RS is optional to adjust LVCMOS driver impedance to transmission line.
The transmission line impedance is 50 Ω.
High Impedance Probe
Rs (opt.)
Oscilloscope
LVCMOS
Microstrip ~10cm
CLoad
Figure 13. LVCMOS Test and Simulation Circuit
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9 Detailed Description
9.1 Overview
The LMK04616 device is very flexible in meeting many application requirements. The typical use case for
LMK04616 is a cascaded Dual Loop Jitter Cleaner with optional support for JESD204B.
NOTE
While the Clock outputs (CLKoutX) do not provide LVCMOS outputs, the OSCout may be
used to provide LVCMOS outputs.
In addition to dual-loop operation, by powering down various blocks, the LMK04616 may be configured for single-
loop or clock distribution modes also.
9.1.1 Jitter Cleaning
The dual-loop PLL architecture of LMK04616 provides the lowest jitter performance over a wide range of output
frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external
reference clock and uses an external VCXO to provide a frequency accurate, low phase noise reference clock for
the second stage frequency multiplication PLL (PLL2).
PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the
reference clock input signal while simultaneously suppressing the higher offset frequency phase noise that the
reference clock may have accumulated along its path or from other circuits. This cleaned reference clock
provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 90
kHz to 500 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency
phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO.
Ultra-low jitter is achieved by allowing the external VCXO phase noise to dominate the final output phase noise
at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at high
offset frequencies. This results in best overall phase noise and jitter performance.
9.1.2 Four Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and
CLKin3/CLKin3*)
The LMK04616 has four reference clock inputs for PLL1. They are CLKin0, CLKin1, CLKin2, and CLKin3. The
active clock is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the
inputs.
Fast manual switching between CLKin0 and CLKin1 reference clocks is possible with external pin CLKin_SEL.
9.1.3 VCXO Buffered Output
The LMK04616 provides OSCout, which by default is a buffered copy of the PLL1 feedback or PLL2 reference
input. This reference input is typically a low noise VCXO. This output can be used to clock external devices such
as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04616 is programmed.
The OSCout buffer output types are LVCMOS, HSDS, and HCSL. When using HSDS and HCSL output from
OSCin, the output will be inverted from OSCin input.
OSCout has the option to fan out a copy of PLL2 output.
9.1.4 Frequency Holdover
LMK04616 supports holdover operation for PLL1 to keep the clock outputs on frequency with minimum drift when
the reference is lost until a valid reference clock signal is re-established.
9.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
LMK04616 features programmable loop filter for PLL1 and PLL2. See PLL1 and PLL2.
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Overview (continued)
9.1.6 Internal VCOs
LMK04616 has an internal VCO in PLL2 with 5870 MHz to 6175 MHz tuning range. The output of the VCO is
routed through a mandatory divider (by 3, by 4, by 5, or by 6) to the Clock Distribution Path. This limits the Clock
Distribution Path frequency to 2058 MHz. This same clock is also fed back to the PLL2 phase detector through
the N-divider (feedback divider).
9.1.7 Clock Distribution
The LMK04616 features a total of 16 PLL2 clock outputs driven from one of the internal VCOs.
All PLL2 clock outputs have programmable output types. They can be programmed to HSDS or HCSL.
If OSCout is included in the total number of clock outputs the LMK04616 is able to distribute up to 17 differential
clocks.
The following sections discuss specific features of the clock distribution channels that allow the user to control
various aspects of the output clocks.
9.1.7.1 Output Clock Divider
The output divider supports a divide range of 1 to 65535 (even and odd) with 50% output duty cycle.
9.1.7.2 Output Clock Delay
The clocks include both a analog and digital delay for phase adjustment of the clock outputs.
The analog delay allows a nominal 60-ps step size and range from 0 to 1.2 ns of total delay per output. See
Analog Delay for further information.
The digital delay allows an output channel to be delayed from 1 to 255 VCO cycles. The delay step can be as
small as half the period of the clock distribution path. For example, 1.5-GHz clock distribution path frequency
results in 333-ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a
SYNC event. See Digital Delay for further information.
1. Fixed Digital Delay (per output channel) – Allows all the output channels to have a known phase relationship
upon a SYNC event. Typically performed at start-up.
2. Dynamic Digital Delay (per output) – Allows additional coarse adjustment per output.
9.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
The device clocks include a features to ensure glitchless operation of the Half-Step and analog delay operations
when enabled.
9.1.7.4 Programmable Output Formats
All LMK0461x clock outputs (CLKoutX) can be programmed to an HSDS or HCSL output type. The OSCout can
be programmed to an HSDS, HCSL, or LVCMOS output type.
Any HSDS output type can be programmed to typical 800-, 1200-, or 1600-mVpp differential amplitude levels.
When OSCout is programmed for differential output from OSCin, the OSCout signal will be inverted from input.
9.1.7.5 Clock Output SYNChronization
Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital
delay.
The SYNC event must occur for digital delay values to take effect.
9.1.8 Status Pins
The LMK0461x provides status pins that can be monitored for feedback or in some cases used for input,
depending upon device programming. For example:
•
•
Indication of the loss-of signal (LOS) for CLKinX.
Indication of the selected active clock input.
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Overview (continued)
•
•
PLL1 and PLL2 lock signal.
Holdover Status.
The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL
lock detect signals, readback, and so forth. See Programming for more information.
A full list of functions can be found in STATUS0/1 and SYNC Pin Functions.
9.2 Functional Block Diagram
Figure 14 illustrates the complete block diagram.
VCXO
VDD_OSC
(1.8 - 3.3 V)
VDD_PLL2CORE
(1.8 - 3.3 V)
VDD_PLL2OSC
(3.3 V)
VDD_PLL1
(3.3 V)
OSCin
CTRL_VCXO
PLL2_CAP0/1
PLL1_CAP
VDD_IO
(1.8 - 3.3 V)
P
CMOS & Diff
VDD_OSCout
OSCout
M
U
X
Input Stage
Int. Div
8 bit
DRV
M
U
X
LOS
CMOS
&
Diff
CLKin0
CLKin1
VDDO_0/1
(1.8 - 3.3 V)
SYNC & RST
P
LDO
DRV
2
CLKout0
CLKout1
DIGITAL FSM
CMOS
&
Diff
VDD1v8
VDD3v3
PLL1
LDO
1v8/1V2
LDO
3v3/2V5
DRV
M
U
X
Ref Clk
/R
0.5 V - 3.3 V
Analg
Prop-CP
CMOS
&
Diff
DIV
Ctrl_VCXO
CLKin2
CLKin3
ADC/
DAC
f
MUX
OSCin
/N
Digital
Strg-CP
DIV
CMOS
&
Diff
VDD3v3
VDD1v8
SD-PLL2
LC-VCO
LDO
3v3/2v5
LDO
1v8/1V2
VDDO_6/7
(1.8 - 3.3 V)
DRV
DRV
INIT &
RESET
Clock
Control
SYNC & RST
BIASING
P
LDO
DRV
CLKin_SEL
controls CLKin0/1 only
x2
M
U
X
CLKout6
CLKout7
REF
PRE
SCALER
DIVIDER
Prop
(Digital Control)
/R
DIV
REF
f
(Digital
Control)
DRV
Storage
S
/ N
DIV
Intgrl
DRV
VDDO_8/9
(1.8 - 3.3 V)
REF
VDD_CORE
(3.3 V)
Control Voltage
Supplies / BGAP / POR
SYNC & RST
P
LDO
DRV
CLKout8
CLKout9
DRV
SYNC & SYSREF_REQ
Generation
Async SYSREF_REQ
Async SYNC
Input Stage
Clock
Control
Syncd SYNC
SDIO
Boot-Up
Holdover
SCL
SS
Device
Configuration
Registers
(PLL1/PLL2 Status & Test)
VDDO_14/15
(1.8 - 3.3 V)
Output
Channels
JESD204B
SYNC
SYNC & RST
P
LDO
DRV
(Digital Status & Debug)
RESET
SYNC
CLKout14
CLKout15
Digital
Device Control
and Status
DRV
STATUS1
(LVCMOS)
STATUS0
(LVCMOS)
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Detailed LMK04616 Block Diagram
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9.3 Feature Description
9.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and CLKin3/CLKin3*)
External VCXO
VDD_IO
Divider implemented in
PLL1
LOS
R div
8 bit
CLKin0
R div
8 bit
CLKin1
PLL1
R div
8 bit
CLKin2
R div
8 bit
CLKin3
PLL2
Digital Logic
- Input Priority Switching
- Pin Select
- LOS detection
CLKin_SEL
STATUS_0
Holdover Counter
0 to 200 ms
External VCXO
Figure 15. LMk04616 Clock Input Block
9.3.1.1 Input Clock Switching
Manual, pin select, and priority or automatic are three different kinds clock input switching modes can be set with
the CLKIN_SEL_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the
various clock input selection modes.
9.3.1.1.1 Input Clock Switching – Register Select Mode
When CLKIN_SEL_MODE = 2 then CLKin0, CLKin1, CLKin2, or CLKin3 is selected through register control
(SW_REFINSEL[3:0]).
If holdover is entered in this mode, then the device will relock to the selected CLKinX upon holdover exit.
Table 2. Active Clock Input – Register Select Mode (SW_REFINSEL[3:0])
SW_REFINSEL[3:0]
0001b
ACTIVE CLOCK (LMK04616)
CLKin0
CLKin1
CLKin2
CLKin3
0010b
0100b
1000b
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9.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL, STATUS0)
When CLKIN_SEL_MODE = 1, the CLKin_SEL pin selects which clock input is active. In LMK04616,
CLKIN_SEL_MODE = 1 forces STATUS0 to be CLKIN_SEL0.
9.3.1.1.2.1 Configuring Pin Select Mode
The CLKinSEL1_INV bit inverts the polarity of CLKin_SEL and STATUS0 input pins.
Table 3 lists which input clock is active depending on CLKin_SEL state.
Table 3. Active Clock Input – Pin Select Mode (CLKin_SEL, STATUS0), CLKinSEL_INV = 0
PIN CLKin_SEL
PIN STATUS0
Low
ACTIVE CLOCK
CLKin0
Low
Low
High
High
High
CLKin1
Low
CLKin2
High
CLKin3
9.3.1.1.3 Input Clock Switching – Automatic Mode
When CLKINSEL1_MODE = 0, the input clock switching is in Automatic mode. The priority of each input clock
can be individually set by programming CLKINx_PRIO[3:0] as shown in Table 4:
Table 4. Clock Input Priority Selection
CLKINx_PRIO[3:0]
0000b
CLKINx
Disabled
0001b
Priority 1 (Highest)
Priority 2 (High)
Priority 3 (Low)
Priority 4 (Lowest)
0010b
0100b
1000b
SPACER
NOTE
Equal priority setting for two CLKINx inputs are not allowed.
The clock inputs in this mode are monitored by on-chip LOS detection circuits. The device reads the priority bits
at start-up and locks to the input clock with highest priority. In the event of input clock loss, the internal PLL
switches to the next available clock. TI recommends using Holdover Mode while using the Automatic Reference
Clock Switching. See Holdover for programming the Holdover mode.
In this case, the outputs clocks will see minimum disturbance while switching from one clock to the other. In the
event of reference clock loss, the PLL1 enters the holdover mode. After the internal logic switches the PLL1 input
clock to the next available clock as per priority setting, PLL1 holdover exit is initiated and PLL1 relocks to the
new clock with minimum disturbance. Flowchart below describes the sequence of operations in the Automatic
Reference Clock Switching mode while holdover is enabled and programmed.
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Lock State
(CLKinX)
CLKinX Priority Loop
NO
IN
Switch to next
highest priority
CLKinZ
LOSz = 0?
YES
NO
Holdover LOS
enabled?
(PLL1_HOLDOVER_
LOS_MASK=0)
Configure CLKinX
PLL1 R divider
OUT
YES
Keep PLL1 R/N divider in Reset
Assert PLL1 reset
Release holdover status
Release PLL1 R/N divider
LOSX = 1?
YES
CLKinY disabled (optional)
LOSY disabled (optional)
Lock State
(CLKinX)
Figure 16. Input Clock Switching – Priority Loop
9.3.1.2 Loss of Signal Detection – LOS
The loss of signal detection circuit is available for all clock inputs. It has programmable assertion and de-
assertion cycles. LOS detection circuit reliable operation is ensured with >200-mVpp differential or >200-mV
single-ended CLKin amplitude and input frequencies between 10 MHz to 500 MHz. Maximum input frequency for
the doubler in the LOS block is 250 MHz. The ratio between VCXO frequency and input frequency must be
between 0.25 and 4.
9.3.1.2.1 LOS – Assertion
LOS assertion time is programmable between 1 to 8 VCXO clock cycles. The LOS assertion time is programmed
through
CLKINx_LOS_LAT_SEL[7:0].
LOS_LAT_SEL
is
an
8-Bit
code.
Additionally,
CLKINx_LOS_FRQ_DBL_EN bit controls the frequency doubler for the LOS block. This is especially important
for VCXO frequencies equal or smaller than CLKinX frequency.
For correct operation of LOS, the reference clock must be switched to logic low level (differential or single-
ended).
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Example 1:
LOS_LAT_SEL = 0010 0000
LOS_LAT_SEL
LOS_FRQ_DBL_EN = 0
VCXO = 122.88 MHz
CLKinX = 30.72 MHz
LOS_FRQ_DBL_EN
LOS_LAT_SEL
CNT reset
CNT reset
LOS (internal)
LOS detection 0.5 RefCLK Cycles
LOS_LAT_SEL
Example 2:
LOS_LAT_SEL = 0000 1000
LOS_FRQ_DBL_EN = 1
LOS
(internal)
VCXO
VCXO = 122.88 MHz
CLKinX = 122.88 MHz
x2
CNT reset
CNT reset
LOS (internal)
LOS detection 1 RefCLK Cycles
CLKinX
Example 3:
LOS_LAT_SEL = 0000 0010
LOS_FRQ_DBL_EN = 1
LOS_LAT_SEL
STATUSx
VCXO = 30.72 MHz
CLKinX = 122.88 MHz
CNT reset
LOS (internal)
LOS detection 3 RefCLK Cycles
Figure 17. LOS Detection
Table 5. Recommended LOS Register Configurations
CLKin TO OSCin FREQUENCY
RATIO
MAX LOS DETECTION
LATENCY IN CLKin CYCLES
LOS_LAT_SEL
LOS_FRQ_DBL_EN
0.25
0010 0000b
0000 1000b
0000 1000b
0000 0100b
0000 0100b
0000 0010b
0
0
1
0
1
1
0.5
1
0.5
1
1
1 (OSCin ≥ 250MHz)
2
2
4
2
3
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9.3.1.2.2 LOS – Reference Clock Recovery
LOS de-assertion can be programmed to 15 to 4095 reference clock cycles (CLKINx_LOS_REC_CNT[7:0]).
Number of Cycles
programmable
CLKinX
LOS (internal)
LOS (STATUSx pin)
Figure 18. LOS Deassertion
9.3.1.3 Driving CLKin and OSCin Inputs
9.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
The CLKin ports and OSCin can be driven by differential signals. TI recommends setting the input mode to
differential (CLKINX_SE_MODE = 0) when using differential reference clocks. The LMK0461x internally AC
couples the inputs with on-chip capacitors. An optional AC-coupling cap can be connected as shown in input
termination sachems. The recommended circuits for driving the CLKin or OSCin pins with either LVDS or
LVPECL are shown in Figure 19 and Figure 20.
CLKinX/
OSCin
0.1 mF
100W Trace
(Differential)
LMK046XX
LVDS
0.1 mF
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Termination for an LVDS Reference Clock Source
CLKinX/
OSCin
0.1 mF
0.1 mF
0.1 mF
0.1 mF
100W Trace
(Differential)
LVPECL
Ref Clk
LMK046XX
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Termination for an LVPECL Reference Clock Source
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Also, a reference clock source can produce a differential sine wave output can drive the CLKin pins using
Figure 21.
NOTE
The signal level must conform to the requirements for the CLKin pins listed in Clock Input
Characteristics (CLKinX). CLKINX_SE_MODE is recommended to be set to differential
mode (CLKINX_SE_MODE = 0).
CLKinX/
OSCin
0.1 mF
100W Trace
(Differential)
LMK046XX
SINE
0.1 mF
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 21. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source
9.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
The CLKin pins of the LMK0461x family can be driven using a single-ended reference clock source, like a sine
wave source or an LVCMOS or LVTTL source. Either AC coupling or DC coupling may be used. In the case of
the sine wave source that is expecting a 50-Ω load, TI recommends using AC coupling as shown in Figure 22
with a 50-Ω termination.
NOTE
The signal level must conform to the requirements for the CLKin pins listed in Clock Input
Characteristics (CLKinX). CLKINX_SE_MODE is recommended to be set to single-ended
mode (CLKINX_SE_MODE = 1).
CLKinX/
OSCin
0.1 mF
50W Trace
50W
LMK046XX
Clock Source
CLKinX*/
OSCin*
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
Figure 22. CLKinX/X* and OSCin AC-Coupled Single-Ended Termination
If the CLKin pins are being driven with a single-ended LVCMOS or LVTTL source, either DC coupling or AC
coupling may be used. If DC coupling is used, the CLKINX_SE_MODE should be set to single-ended buffer
mode (CLKINX_SE_MODE = 1) and the voltage swing of the source must meet the specifications for
DC-coupled, single-ended mode clock inputs given in Clock Input Characteristics (CLKinX). If AC coupling is
used, the CLKINX_SE_MODE should be set to the differential buffer mode (CLKINX_SE_MODE = 0). The
voltage swing at the input pins must meet the specifications for AC-coupled, differential mode clock inputs given
in Clock Input Characteristics (CLKinX). In this case, some attenuation of the clock input level may be required. A
simple resistive divider circuit before the AC-coupling capacitor is sufficient.
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CLKinX
50W Trace
LMK046XX
LVCMOS/LVTTL
Clock Source
CLKinX*
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
Figure 23. DC-Coupled LVCMOS or LVTTL Reference Clock
9.3.2 Clock Outputs (CLKoutX)
This section describes all related features of the clock outputs.
DUAL-CLK OUTPUT CHANNEL
Channel Specific
CLKoutX Specific
HS_EN_CH_xy
PLL_WRAPPER
SD-PLL2
OUTCHxy_DIV
½
CYC
DEL
DDLY
CLKoutX
Clock
Distribution Path
ADLY
PRE
SCAL
ER
INV
PF
D
CLK
CLK
CMOS
DIVID
ER
C
P
OUTCHxy_
16-bit Divider
CHx_ADLY
DIV_INV
RSTB
DYN_DDLY_CHx
FB
DIV
CHx_ADLY_EN
DYN_DDLY_EN_CHx
OUTCHx_DRIV_MODE
CLKROOT
CHxy_DDLY
LDO
VDDOxy
SYNCronize
SYNCronize
SYNC TO ALL
CHANNELS
CLKoutY Specific
SYNC | RESET
SYSREF_REQ
Static Digital Delay
SYNC_EN_CHxy
RSTB
SYSREF_EN_CHxy
Re-
sampling
SYNC
DDLY
CLKoutY
ADLY
INV
CHx_SYNC
CLK
OUTCH_SYSREF_PLSCNT
OUTCHxy_
CHy_ADLY
DYN_DDLY_CHy
DIV_INV
Re-
sampling
SYSREF Pulse
Counter
CHy_ADLY_EN
DYN_DDLY_EN_CHy
OUTCHy_DRIV_MODE
CHx_SYSREF_REQ
Figure 24. Clock Output Block and SYNC Clocking Path
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9.3.2.1 HCSL
Figure 25 shows a typical implementation for the HCSL output driver mode. HCSL requires external 50-Ω
termination resistors. Optionally, source resistors in the range from 22 Ω to 33 Ω are employed to eliminate
ringing.
For HSCL outputs, set OUTCHxx_DRIV_MODE to 0x3F.
Receiver
CPARA
Rs (opt.)
50 Ohm
VTERM
Diff Microstrip ~10cm
HSCL
50 Ohm
50 Ohm
CPARA
Figure 25. HCSL Output Termination
Figure 26 and Figure 27 show different connection methods to a LVPECL receiver.
Rs (opt.)
HSCL
LVPECL
50 Ohm
50 Ohm
Vb
Figure 26. HCSL to LVPECL With Bias Voltage Vb (Voltage as Required for Receiver Bias)
3.3V
82 Ohm
Rs (opt.)
HSCL
LVPECL
50 Ohm
130 Ohm
Figure 27. HCSL to LVPECL
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9.3.2.2 HSDS
HSDS does not need external output termination (see Figure 28).
For HSDS: 8-mA outputs set OUTCHxx_DRIV_MODE to 0x18.
For HSDS: 6-mA outputs set OUTCHxx_DRIV_MODE to 0x14.
For HSDS: 4-mA outputs set OUTCHxx_DRIV_MODE to 0x10.
Receiver
CPARA
50 Ohm
VTERM
Diff Microstrip
HSDS
50 Ohm
CPARA
Figure 28. HSDS Output Termination
Figure 29 to Figure 31 show different connection methods to a LVPECL and LVDS receiver. In case of LVDS
receivers, use HSDS 4-mA or HSDS 6-mA and for LVPECL use HSDS 8-mA setting.
HSDS
LVPECL
50 Ohm
Vb
Figure 29. HSDS to LVPECL With Bias Voltage Vb (Voltage as Required for Receiver Bias)
3.3V
82 Ohm
HSDS
LVPECL
130 Ohm
Figure 30. HSDS to LVPECL
HSDS
100 Ohm
LVDS
Figure 31. HSDS to LVDS
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9.3.2.3 SYNC
See additional information about the SYNC pin in STATUS0/1 and SYNC Pin Functions.
SYNC aligns all clock outputs to start at a common rising clock distribution path clock edge. Clocks divided by 1
or divider bypass are not gated during the SYNC event.
SYNC is not available in buffer mode.
Clock Distribution
Path (internal)
CLKoutA
(div by 1)
tskew1
CLKoutB
(div by 2)
No CLKout during SYNC
CLKoutC
(div by 5)
CLKoutD
(div by 5 + HS)
Latency 1
SYNC
Latency 2
SYNC asserted
SYNC released
Figure 32. SYNC Example
9.3.2.4 Digital Delay
Digital (coarse) delay allows an output to be delayed by 1 to 255 periods of the clock distribution path frequency.
The delay step can be as small as half the period of the clock distribution path frequency by using the
HS_EN_CHx bit.
The digital delay step size calculates with: 1 / VCO frequency / prescaler
1. Fixed digital delay (per output channel)
2. Dynamic digital delay (per output)
9.3.2.4.1 Fixed Digital Delay
Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs are LOW for
a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay
should use dynamic digital delay.
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Clock Distribution
Path
No CLKout during SYNC
CLKoutX
2 Cycles DDLY
CLKoutY
3 Cycles DDLY
1 Clock Distribution Path cycle delay
Fixed Delay
SYNC
SYNC event
Figure 33. Fixed Digital Delay Example
Table 6. Digital Delay Register Controls
REGISTER NAME
DESCRIPTION
HS_EN_CHx
Enables a Half-Step for Channel X: 0.5 / VCO frequency / Prescaler
Sets number of Digital Delay steps for Channel X. The channel delays 0 to 255 Clock
Distribution Path periods compared to other channels.
CHx_DDLY
9.3.2.4.2 Dynamic Digital Delay
Additionally, for the fixed digital delay per output channel, each output can be individually delayed using dynamic
digital delay. Up to 5 periods of the clock distribution path frequency can be shifted.
The setting applies without SYNC to the output.
Table 7. Dynamic Digital Delay Register Controls
REGISTER NAME
DESCRIPTION
DYN_DDLY_CHx_EN
Enable CHx Dynamic Digital Delay.
Sets number of Dynamic Digital Delay steps for Output X. The Output delays 0 to 5 Clock
Distribution Path periods compared to other channels.
DYN_DDLY_CHx
9.3.2.5 Analog Delay
Analog delay is available for all outputs. The typical step size is 60 ps and covers a total range of 1.3 ns.
Table 8. Analog Delay Register Controls
REGISTER NAME
CHx_ADLY_EN
CHx_ADLY
DESCRIPTION
Enables Analog Delay for Channel X.
Analog Steps can be programmed from 0 to 15. The resulting delay is shown in Figure 34.
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330
300
270
240
210
180
150
120
90
306
124
95
87
60
72
71
70
64
59
59
59
57
53
50
49
45
30
0
Figure 34. Analog Delay
9.3.3 OSCout
The default function for OSCout is providing two buffered LVCMOS copies (in phase or complementary) of the
external VCXO. Additionally, an 8-bit divider is integrated. The multiplexer selects the VCXO input or high-speed
clock distribution tree. The output type can be programmed to HSDS, HCSL, and LVCMOS. See Output
Termination Scheme for test load descriptions. When OSCout is programmed for differential output from OSCin,
the OSCout signal will be inverted from input.
NOTE
External VCXO
VCXO_CTRL
OSCin
Reference
PLL1
M
U
X
CMOS
DIFF
Integer Div
8-bit
OSCout
PLL2
Figure 35. OSCout Block
9.3.3.1 Pin-Controlled OSCout Divider
During power up (see Power-Up Sequence) after RESET = 1, the state of the SYNC pin is sampled. The input
level determines the OSCout divider setting.
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NOTE
This function is only available after power up and RESET transition from LOW to HIGH.
Table 9. Pin-Controlled OSCout Divider Settings
SYNC PIN INPUT LEVEL AT POWER UP
OSCout DIVIDER SETTING
OR RESET TRANSITION FROM LOW TO HIGH
LOW
OPEN
HIGH
1
2
4
9.3.4 STATUS0/1 and SYNC Pin Functions
Status and SYNC Pins supports 1.8-V logic and it can be configured as:
•
•
Input
Output
Common STATUS0/1 and SYNC Pin Functions describes the common input and output pin functions.
SYNC and STATUS0 have additional features that are restricted to the pins. See Additional SYNC Pin Functions
and Additional STATUS0 Pin Functions.
9.3.4.1 Common STATUS0/1 and SYNC Pin Functions
Two status pins are available (STATUS0, STATUS1). STATUSx/SYNC_OUTPUT_HIZ = 1 configures the pins as
input, while STATUSx/SYNC_OUTPUT_HIZ = 0 configures the pins as output. STATUSx/SYNC_INT_MUX
register configures the pin functions in Table 10.
Table 10. Common STATUS0/1 and SYNC Pin Functions
FUNCTION
SDO
INPUT/OUTPUT
Output
Output
Output
Output
Output
Output
Output
Output
Input
DESCRIPTION
Serial Data Output for 4-wire SPI
LD1 and LD2
LD1
Digital Lock Detect for PLL1 and PLL2
Digital Lock Detect for PLL1
LD2
Digital Lock Detect for PLL2
LD1 and LD2 and not Holdover
LD1 and not Holdover
LOS
PLL1 Lock Detect and PLL2 Lock Detect and not PLL1 Holdover
PLL1 Lock Detect and not PLL1 Holdover
Output of LOS Block
Holdover status
Holdover Control
Copy SYNC pin
Copy CLKIN_SEL pin
PLL2 Reference Clock
PLL1_R
Output of Holdover Status. High = Holdover. Low = Normal operation
Manual Holdover entry through pin. See Holdover.
Outputs a copy of SYNC pin
Output
Output
Output
Output
Output
Output
Output
Output
Output
Outputs a copy of CLKIN_SEL pin
PLL2 Reference Clock (Copy of OSCin divided by PLL2 R)
Output PLL1_R Clock Frequency
PLL2_R
Output PLL2_R Clock Frequency
PLL1_N
Output PLL1_N Clock Frequency
PLL2_N
Output PLL2_N Clock Frequency
Logic High
Logic Low
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9.3.4.2 Additional STATUS0 Pin Functions
This chapter describes the additional functions that are available on STATUS0 pin only.
Table 11. Additional STATUS0 Pin Functions
FUNCTION
INPUT/OUTPUT
DESCRIPTION
In LMK04616, the STATUS0 pin in combination with CLKIN_SEL selects the inputs
in pin mode.
CLKIN_SEL0
Input
9.3.4.3 Additional SYNC Pin Functions
This chapter describes the additional functions that are available on SYNC pin only.
Table 12. Additional SYNC Pin Functions
FUNCTION
INPUT/OUTPUT
DESCRIPTION
Sampled Pin Logic state at power up configures default OSCout divider setting.
Low level = divide by 1
Mid level = divide by 2
High level = divide by 4
OSCout Div Control
Input
SYNC_PIN_FUNC=0 → SYNC output channels. See SYNC
SYNC_PIN_FUNC=1 → Sysref Request
SYNC
Input
SYNC_PIN_FUNC=2 → Reset PLL1 N-/R-Dividers
SYNC_PIN_FUNC=3 → Reserved
9.3.5 PLL1 and PLL2
LMK0461x has two programmable PLLs. PLL1 is a very low bandwidth PLL with an external VCXO. The
bandwidth of the PLL1 can be programmed from 3 Hz to 300 Hz. PLL2 is a high bandwidth PLL using an on-
chip, very low phase noise LC VCO. PLL2 bandwidth can be programmed from 90 kHz to 1 MHz. The detailed
description about the individual PLLs is provided in the following sections.
9.3.5.1 PLL1
PLL1 in LMK0461x is a very low bandwidth PLL. The PLL is a fully programmable, ultra-flexible design and is
intended to be used for jitter cleaning of the noisy input clock. The PLL uses a semi-digital architecture and there
is no need for external loop filter. The loop-filter has separated integral and proportional paths, which can be
programmed individually to define the PLL transfer. There is a possibility to add higher order poles by connecting
a capacitor outside the chip with a fixed on-chip resistor RCTRL. The block diagram of the PLL1 is shown in
Figure 36. The PLL uses an external VCXO as a voltage controlled oscillator. Both positive and negative gain
VCXOs are supported by LMK046xx.
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V
CTRL
PLL1_PROP
PROP
RCTRL
PLL_RDIV
PFD
INT
PLL1_INTG
PLL_NDIV
PLL1_NDIV PROP_MODE
Figure 36. PLL1 Block Diagram
To reduce lock time, PLL1 supports two locking modes which can be individually configured by the user. When
configured, PLL1 starts with Fastlock (with very high integral gain) and after lock, it switches to desired integral
gain.
PLL1 Bandwidth depends on the VCXO gain and loop parameters. LMK0461x PLLs are designed with active
damping technique. For a given VCXO gain and divider settings, the bandwidth can be programmed by using the
PLL1_PROP settings. The higher the value, the higher the bandwidth.
Table 13 shows the internal PLL1 parameter, register and programming ranges. Use the TICS Pro EVM tool to
calculate PLL1_PROP, PLL1_PROP_LF, PLL1_INTG, and PLL1_INTG_LF values.
Table 13. PLL1 Parameter and Register
PARAMETER
REGISTER
DESCRIPTION
MIN
TYP
MAX
UNIT
0x1B,0x1C,0X1D,0x1E,
0x1F,0x20,0x21,0x22
CLKINx_PLL1_RDIV
Input clock divider for PLL1
1
32771
PLL1_NDIV
PLL1_PROP
0x61,0x62
0x5A
Feedback clock divider for PLL1
Proportional gain setting
1
0
0
32771
127
PLL1_PROP_FL
0x5B
Proportional gain setting for Fast Lock
127
Integral gain setting, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP < 7
PLL1_INTG
PLL1_INTG_FL
PLL1_INTG
0x59
0x59
0x59
0x59
0x59
0x59
0x59
0
0
0
0
0
0
0
0
1
0
3
0
2
0
1
Integral gain setting for Fast lock, C3 = 2.2
µF
1
1.92 MHz PDF, PLL1_PROP < 7
Integral gain setting, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP ≥ 7
3
Integral gain setting for Fast lock, C3 = 2.2
PLL1_INTG_FL
PLL1_INTG
µF
3
1.92 MHz PDF, PLL1_PROP ≥ 7
Integral gain setting, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP < 31
2
Integral gain setting for Fast lock, C3 = 2.2
µF
PLL1_INTG_FL
PLL1_INTG
2
0.12 MHz PDF, PLL1_PROP < 31
Integral gain setting, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP ≥ 31
15
40
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Table 13. PLL1 Parameter and Register (continued)
PARAMETER
REGISTER
DESCRIPTION
MIN
TYP
15
MAX
UNIT
Integral gain setting for Fast lock, C3 = 2.2
µF
PLL1_INTG_FL
RCTRL
0x59
0
15
0.12 MHz PDF, PLL1_PROP ≥ 31
500
Ω
9.3.5.1.1 PLL1 Proportional Modes
PLL1 bandwidth can be increased or decreased even further by using the different PROP modes (see Table 14).
Table 14. PLL1 Proportional Modes
PROP MODE
REGISTER SETTINGS
DUTY CYCLE OF CLOCK
PLL1_RDIV_4CY = 0
PLL1_NDIV_4CY = 0
Default
50%
PLL1_RDIV_4CY = 1
PLL1_NDIV_4CY = 1
PLL1_FBCLK_INV = 1
CLKINx_PLL1_INV = 1
Low Pulse mode
High Pulse mode
(4/DIV) * 100
PLL1_RDIV_4CY = 1
PLL1_NDIV_4CY = 1
PLL1_FBCLK_INV = 0
CLKINx_PLL1_INV = 0
(1-4/DIV) * 100
In the default input mode, the proportional is effective for 50% of the PFD clock period. Using low pulse mode,
the effect of the proportional is reduced which results in a reduced PLL bandwidth. Similarly, using the high pulse
mode, the proportional is effective for more than half of the PFD cycle, which results in higher bandwidth.
PLL1_INTG settings affect the integral gain in the loop. TI recommends using setting 0 in normal mode and
higher settings only for Fast lock using PLL1_INTG_FL.
9.3.5.1.2 PLL1 Higher Order Poles
There are no external resistors and capacitors required for the low bandwidth PLL1. However, to introduce 3rd
order pole in the loop, external capacitor C3 can be attached to the control voltage, which in combination with the
on-chip resistor, creates a pole at the desired frequency. Recommended maximum value of C3 for PLL1 lock is
2.2 µF.
PLL1
R1
C3
Figure 37. 3rd Order Loop Filter
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9.3.5.2 PLL2
The second PLL in LMK046xx is a high bandwidth PLL requiring no external components. The PLL contains a
very low phase noise on chip LC-based Voltage controlled oscillator (VCO). The VCO is very flexible and full
programmable. Similar to PLL1, PLL2 is also a semi-digital PLL designed with an active damping concept. The
bandwidth of the PLL can be programmed between 90 kHz to 1 MHz. PLL2 also has separated integral and
proportional paths to control the VCO. The 3rd order pole can also be introduced by selecting the integrated
resistors and capacitors.
The input clock frequency to the PLL2 can be doubled by using an integrated frequency doubler. Apart from that
there are additional input modes possible to have more flexibility for bandwidth programming.
LC VCO
x2
PRE
SCALER
DIVIDER
Prop
R DIV
f
/N
DIV
Intgrl
Figure 38. PLL2 Block Diagram
9.3.5.2.1 PLL2 Divider
PLL2 contains three dividers. Input clock can be divided down by using reference divider (PLL2_RDIV). Second
divider is the high-frequency prescalar at the output of the VCO. Third divider is in the PLL feedback path which
defines the PLL frequency multiplication ratio in combination with prescalar. Each of the three dividers is
programmable with the registers as described in Table 15.
Table 15. PLL2 Divider
PARAMETER
REGISTER
DESCRIPTION
MIN
TYP
MAX
UNIT
PLL2_RDIV
0x76
Input clock divider for PLL2
1
31
Feedback clock divider for
PLL2
PLL2_NDIV
0x73, 0x74
0x146
1
3
65535
6
The prescaler defines the
Clock Distribution Frequency.
PLL2_PRESCALER
9.3.5.2.2 PLL2 Input Modes
PLL2 has four input modes which can be selected by the user. These modes give more flexibility to adjust the
PLL2 bandwidth. See Table 16.
Table 16. PLL2 Input Modes
INPUT MODE
DESCRIPTION
Doubler Mode
The Input clock gets multiplied by 2. The duty cycle of the clock is <50%.
This mode is same like the doubler mode, where the input clock gets multiplied by 2, but the
duty cycle of the output clock is >50%.
Doubler invert mode
Pulse mode
RDIV mode
The duty cycle of the input clock is adjusted to a fixed value and is >50%.
The input divider is used to divide down the frequency with the range as shown in Table 15.
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9.3.5.2.3 PLL2 Loop Filter
PLL2 design is based on semi-digital PLL architecture where the proportional and integral parts are separated
from each other. Proportional gain and integral gain can be individually programmed by the user to define the
bandwidth and noise transfer characteristics of the PLL2 in combination with the input modes.
Table 17. PLL2 Parameter and Register
PARAMETER
PLL2_PROP_SET
PLL2_CPROP
PLL2_INTG
REGISTER
0x72
DESCRIPTION
Proportional gain setting
Proportional cap setting
Integral gain setting
MIN
0
TYP
MAX
63
UNIT
0x151
0x80
3
5.4
31
pF
0
PLL2_RFILT
0x151
0x153
3rd order filter resistor selection
3rd order filter capacitor selection
4.7
0
9.2
124
kΩ
PLL2_CFILT
15
pF
The proportional gain can be changed using PLL2_PROP and PLL2_CPROP. The difference between the two
modes is, PLL2_PROP controls the proportional charge pump current to define the gain and PLL2_CPROP
controls the on-chip capacitor used in active damping to define the proportional gain. Higher values of
PLL2_PROP result in higher proportional gain and Higher PLL2_CPROP values result in lower proportional gain.
9.3.5.2.4 PLL2 3rd Order Loop Filter
PLL2 also has programmable on-chip 3rd order loop filter in the proportional path to create additional pole for
better noise cutting, as shown in Figure 38. The resistor and capacitor value can be programmed as shown in
Table 18.
Table 18. 3rd Order Loop Filter
PARAMETER
DESCRIPTION
PLL2_EN_FILTER=1 → Enables resistor
PLL2_RFILT=0 → 9.2 kΩ
R3
PLL2_RFILT=1 → 4.7 kΩ
00000 → 0 pF
00001 → 4 pF
..
C3
PLL2_CFILT<5:0>
11111 →124 pF
9.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
PLL contains on chip very low phase noise LC oscillator. The tuning range of the oscillator is 5870 MHz to 6175
MHz. The VCO is tuned to the target frequency using the semi-digital control by the PLL loop. Due to the semi-
digital control, the PLL loops tracks the temperature and input frequency change with its loop bandwidth.
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9.3.5.2.6 Examples of PLL2 Setting
This section shows PLL2 setting examples to generate given loop bandwidth.
Table 19. PLL2 Settings
PLL2_
CPROP
FIN_PLL2
FVCO
PLL2_RDIV
PLL2_NDIV PRESCALER INPUT MODE PLL2_PROP PLL2_INTG
R3, C3(1)
122.88 MHz
122.88 MHz
30.72 MHz
30.72 MHz
5898.24 MHz
5898.24 MHz
5898.24 MHz
5898.24 MHz
1
1
1
1
4
4
6
6
6
6
Doubler Invert
Doubler Invert
Doubler Invert
Doubler Invert
20
21
20
7
0
0
0
0
5.4 pF
5.4 pF
5.4 pF
5.4 pF
disabled, 0 pF
4.7 kΩ, 96 pF
disabled, 0 pF
4.7 kΩ, 96 pF
16
16
(1) See Table 18 for reference.
9.3.5.3 Digital Lock Detect
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference
path (R) and the feedback path (N) of the PLL. When the time error (phase error) between the two signals is less
than a specified window size (ε), a lock detect count increments.
When the PLL1 lock detect count reaches a user specified value, PLL1_LOCKDET_CYC_CNT, lock detect is
asserted true. Once digital lock detect is true, a single phase comparison outside the specified window causes
the digital lock detect to be asserted false (see Figure 39).
NO
NO
PLL1
YES
YES
Increment
PLL1 Lock Count
PLL1
PLL1 Lock Count =
PLL1_LOCKDET_CYC_CNT
START
Lock Detected = False
Lock Count = 0
Phase Error < x
Phase Error < x
Lock Detected = True
YES
NO
Figure 39. PLL1 Digital Lock Detect Flowchart
PLL2 DLD requires register 0xF6 = 0x02, 0x85 = 0x00, and 0x86 = 0x00 set. Then to program register 0xAD for
valid digital lock detect. See Recommended Programming Sequence. When the PLL2 lock detect count reaches
a user specified value, PLL2_LOCKDET_CYC_CNT, lock detect is asserted true. Once digital lock detect is true,
a single phase comparison outside the specified window causes the digital lock detect to be asserted false (see
Figure 40).
START
Set Register 0xAD = 0x30
Wait 20 ms
Set Register 0xAD = 0x00
NO
NO
PLL2
YES
YES
Increment
PLL2 Lock Count
PLL2
PLL2 Lock Count =
PLL2_LOCKDET_CYC_CNT
Lock Detected = False
Lock Count = 0
Phase Error < x
Phase Error < x
Lock Detected = True
YES
NO
Figure 40. PLL2 Digital Lock Detect Flowchart
This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for
only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial
phase lock.
The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be
programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
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PLL (Analog Domain)
Digital-Block (Digital Domain)
LOCK_CYC_CNT
Div2
bypass
WNDW
CMP
LOCK
REF
SYS
SYNC
CNT
VDD
Div2
bypass
WNDW
CMP
Figure 41. Digital Lock Detect Implementation
9.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to
achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting
Holdover for more info.
9.3.6 Holdover
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock
reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed
tuning voltage is set on CPout1 to operate PLL1 in open-loop.
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9.3.6.1 Holdover Flowchart
Lock State
(CLKinX)
- CLKinY disabled (optional)
- LOSY disabled (optional)
NO
NO
NO
NO
Manual
Holdover LOS
Holdover Rail detect
Holdover
Holdover PLL1 DLD
enabled?
(PLL1_HOLDOVER_
enabled?
(PLL1_HOLDOVER_
LOS_MASK=0)
enabled?
through Pin or
Register?
(PLL1_HOLDOVER_
LCKDET_MASK=0)
RAILDET_EN=1)
CLKinX Priority Loop
IN
YES
YES
YES
NO
Switch to next
highest Priority
CLKinZ
LOSz = 0?
YES
NO
RAILDET_UPP <
VCTRL <
RAILDET_LOW?
PLL1 LD = 0?
LOSX = 1?
NO
NO
- configure CLKinX
PLL1 R Divider
YES
YES
YES
OUT
YES
CLKINSEL1_MODE =
AUTO?
- enable Holdover
- enable Holdover status
- hold last Vctrl value
NO
- enable Holdover
- enable Holdover status
- hold last Vctrl value
YES
- enable Holdover
- enable Holdover status
- hold last Vctrl value
Start
Holdover
Counter
YES
Holdover
Counter enabled?
(PLL1_HOLDOVER_MAX
_CNT_EN=1)
Holdover Counter Loop
NO
NO
Wait for SPI command to exit
Holdover
(Rail detect: PLL1_HOLDOVER_DLD_SWRST
Deassert Pin or
register?
NO
Holdover
counter
elapsed?
NO
LOSX = 0?
LOSX = 0?
NO
or
PLL1 Loss of Lock:
CLKinX Priority
Loop
PLL1_HOLDOVER_LOCKDET_SWRST)
YES
YES
YES
YES
- configure CLKinX
PLL1 R Divider
CLKinX Priority
Loop
- keep PLL1 R/N Divider in Reset
- assert PLL1 reset
- release Holdover Status
- release PLL1 R/N Divider
- CLKinY disabled (optional)
- LOSY disabled (optional)
Register Setting
Lock State
(CLKinX)
Figure 42. Holdover Flowchart Using LOS
9.3.6.2 Enable Holdover
Program HOLDOVER_EN = 1 to enable holdover mode for PLL1.
9.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
In holdover mode, PLL1 retains the last used control voltage.
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9.3.6.3 Enter Holdover
Holdover can be entered through different events.
•
•
•
•
•
•
LOS_x detects reference loss.
PLL1 DLD detects PLL1 unlock.
CTRL_VCXO rail detect.
Manual through register control
Manual through pin
Start-up into holdover
9.3.6.3.1 LOS_x Detect
Enter holdover if reference is lost.
9.3.6.3.2 PLL1 DLD Detect
Enter holdover if PLL1 is unlocked.
9.3.6.3.3 CTRL_VCXO Rail Detect
Rail detection allows to set upper and lower boundaries for the tuning voltage.
Once the boundaries are touched, the device enters holdover mode if this feature is enabled. The boundaries get
compared against the current 6-bit value of the PLL1 storage cells array, PLL1_STORAGE_CELL. It can be
determined whether the boundaries are absolute or relative boundaries.
Enter holdover if CTRL_VCXO represented as PLL1_STORAGE_CELL crosses a programmable high or low limit
of CTRL_VCXO.
•
•
If PLL1_STORAGE_CELL ≤ RAILDET_LOW, then go to holdover or into normal operation.
If PLL1_STORAGE_CELL ≥ RAILDET_UPP, then go to holdover or into normal operation.
CTRL_VCXO_HIGH/LOW_RAIL granularity is 82.5 mV.
9.3.6.3.3.1 Absolute Limits
RAILDET_LOW and RAILDET_UPP values are considered as absolute numbers, being compared against
current storage value.
9.3.6.3.3.2 Relative Limits
RAILDET_LOW and RAILDET_UPP values are considered as relative numbers. After PLL1 has locked the
current storage value is added to the relative numbers to form the absolute boundary.
9.3.6.3.4 Manual Holdover Enable – Register Control
When PLL1_HOLDOVER_FORCE is 1 PLL1 enters holdover mode regardless of other conditions.
9.3.6.3.5 Manual Holdover Enable – Pin Control
The SYNC control pin can be programmed to control the entry and exit of holdover.
9.3.6.3.6 Start-Up into Holdover
During the initial programming, the LMK0461x can be configured to start-up into holdover. It presets the VCXO
Control voltage to approximately 1.2 V. This allows PLL2 to lock to the VCXO reference. PLL1 locks as soon a
valid reference input clock is detected. The holdover status can be optionally displayed at the status pins.
9.3.6.4 During Holdover
PLL1 is run in open-loop mode:
•
•
•
•
PLL1 charge pump is set to TRI-STATE.
PLL1 DLD is unasserted.
The HOLDOVER status is asserted.
During holdover, if the PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.
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•
•
LOS engine searches for active input clock.
PLL1 attempts to lock with the active clock input.
The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the
PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.
9.3.6.5 Exiting Holdover
Holdover mode can be exited in one of four ways.
•
•
•
Manually by programming the device from the host.
Manual through pin.
Automatically by a clock operating within a specified ppm of the current PLL1 frequency on the active clock
input.
•
•
Automatically by LOS deassertion.
Automatically by switching to next clock input after holdover counter overflow. The order of switching is set in
a priority list.
9.3.6.6 Holdover Frequency Accuracy
The holdover frequency accuracy depends on the PLL1 loop bandwidth. A low loop bandwidth of ≤10 Hz results
in less then 0.6-ppm accuracy typical.
9.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
As soon as the reference clock is valid again and the LOS signal is deasserted, the PLL1_N and PLL1_R divider
reset and PLL1 exits holdover.
9.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
A programmable holdover counter can be set between 0 and 17 seconds count time. The counter starts counting
as soon the device is in holdover.
If the reference clock is valid again within the specified time, the device exits holdover.
If the counter overflows, the device switches to the next clock input. The order of clock inputs is set in a priority
list.
•
•
Minimum Holdover counter configuration step size: 4.069 ns
Holdover counter range: 0 – 17 s
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9.3.7 JEDEC JESD204B
Table 20 illustrates the some possible SYNC and SYSREF modes.
Table 20. Possible SYNC/SYSREF_REQ Configurations
NAME
DESCRIPTION
SYNC Disabled
No SYNC occurs.
Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL.
To achieve SYNC through SPI, toggle the SYNC_POL bit.
Pin or SPI SYNC
Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be
used to cause SYNC through SPI.
JESD204B Pulser on pin transition.
JESD204B Pulser on SPI
programming.
Programming SYSREF_PULSE_CNT register starts sending the number of pulses.
When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is
SYNChronized to prevent runt pulses from occurring on SYSREF.
External SYSREF request
Continuous SYSREF
Continuous SYSREF signal.
LMK0461x family provides support for JEDEC JESD204B. High-frequency device clock and low frequency
SYSREF clocks can be generated with programmable analog and digital delays and SYNC functionality. The
device provides possibility to control the SYNC and SYSREF functions by SYNC pin (pin mode) or SPI
programming. Each clock output can be used either as a device clock or SYSREF clock. Steps to use the SYNC
and SYSREF modes are described in Figure 43.
SYNC output divider
Setup SYSREF mode (and pulser)
Program SYNC mode
(Pin/SPI)
&
Enable the SYNC for the
channels to be synced
Program SYSREF mode
(Pulser /Continuous) &
Enable SYSREF channels
Issue a SYNC request
(PIN/SPI)
Program SYSREF
Pin/SPI mode
Issue a SYSREF request
(PIN/SPI)
Figure 43. Manual SYSREF Setup
The programming of the SYNC and SYSREF modes can be already done at the device setup. One time SYNC
for the output channels is issued automatically at the device start-up irrespective of the SYNC programming.
Detail description on setting up the SYNC and SYSREF modes are described in the following sections.
9.3.7.1 SYNC Pins
The SYNC pin in LMK0461x family has multiple functions which can be configured by the user using SPI
interface. Following table lists the possible function:
Table 21. SYNC Pins
BIT NAME
EN_SYNC_PIN_FUNC
SYNC_INV
FUNCTION
Enables the different functions at the SYNC pin when 1
Inverts SYNC Input when 1
00
01
10
11
SYNC output channels
SYSREF Request
SYNC_PIN_FUNC[1:0]
Reset PLL1 N-divider and R-divider
Reserved
SYNC_ANALOGDLY_EN
SYNC_ANALOGDLY[4:0]
Enables the Analog delay at the SYNC input pin
Analog delay can be programed from 0-15. See Analog Delay for details
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9.3.7.2 SYNC modes
SYNC can be requested by either PIN or using the SPI interface. Following table lists the register values that
must be programmed to use the SYNC functionality:
Table 22. Additional SYNC Bits
BIT NAME
FUNCTION
GLOBAL_SYNC
Global SW SYNC. Writing 1 puts the Device into SYNC mode. Writing 0 exits SYNC mode.
SYNC_EN_CH1
SYNC_EN_CH2
SYNC_EN_CH3_4
SYNC_EN_CH5
SYNC_EN_CH6
SYNC_EN_CH7_8
SYNC_EN_CH9
SYNC_EN_CH10
Enables the corresponding channel for SYNC functionality
Steps to configure each mode are described below.
•
SYNC pin mode:
1. EN_SYNC_PIN_FUNC should be set to 1. This enables the different functions supported by the SYNC
pin.
2. SYNC_PIN_FUNC[1:0] should be programmed to 00b (default). This sets the SYNC pin for SYNC
function.
3. SYNC_INV, when 0, SYNC is rising edge triggered. When set to 1, the SYNC pin is internaly inverted and
is falling edge triggered.
4. SYNC_EN_CHx should be set 1 for the channels which needs to SYNCed.
5. Depending on the SYNC_INV value, the output channels are SYNChronized by either rising edge or the
falling edge on the SYNC pin.
•
SYNC SPI mode:
1. EN_SYNC_PIN_FUNC should be set to 0. This disables the pin mode for SYNC function.
2. SYNC_EN_CHx should be set 1 for the channels which must SYNCed.
3. Writing 1 to the GLOBAL_SYNC puts the device into SYNC mode.
9.3.7.3 SYSREF Modes
Any channel can be programmed to generate SYSREF clock. There are different SYSREF modes supported by
LMK0461x. SYSREF can be either fixed number of pulses or a continuous clock. There is a 5-bit register
provided to program the number of pulses to be generated at each SYSREF request. Also, there is a possibility
to control the number of pulses with the SYNC pin. Each SYSREF clock can be individually delayed. There are
different options to introduce the delay in the SYSREF path. See Digital Delay and Analog Delay for
programming the delays. Following bits needs to be programed to use the SYSREF feature:
Table 23. SYSREF Registers
BIT NAME
FUNCTION
Enable SYNC_SYSREF features at SYNC pin
Enable continuous SYSREF
EN_SYNC_PIN_FUNC
GLOBAL_CONT_SYSREF
GLOBAL_SYSREF
Trigger SYSREF, Self-clearing
OUTCH_SYSREF_PLSCNT
Set number of desired SYSREF pulses from 1 to 32. 0 Enables continuous SYSREF
SYSREF_EN_CH10
SYSREF_EN_CH9
SYSREF_EN_CH7_8
SYSREF_EN_CH6
SYSREF_EN_CH5
SYSREF_EN_CH3_4
SYSREF_EN_CH2
SYSREF_EN_CH1
Enable SYSREF feature at channel CHx
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9.3.7.3.1 SYSREF Pulser
This mode allows for the output of 1 to 32 SYSREF pulses for every SYNC pin event or SPI programming. This
implements the gapped periodic functionality of the JEDEC JESD204B specification.
programmable
SYSREF_PULSE_CNT
SYSREF Output
SPI Programming
Or
SYNC pin
Figure 44. SYSREF Pulser
9.3.7.3.1.1 SPI Pulser Mode
OUTCH_SYSREF_PLSCNT is a 5-bit register that can be programmed to the required number of pulses.
When GLOBAL_SYSREF is programmed to 1, fixed number of pulses are defined by
OUTCH_SYSREF_PLSCNT are generated at the output channels which are enabled for SYSREF. The
GLOBAL_SYSREF bit is cleared automatically after fulfilling the SYSREF request.
9.3.7.3.1.2 Pin Pulser Mode
By programming EN_SYNC_PIN_FUNC= 1, SYNC_PIN_FUNC=01 and OUTCH_SYSREF_PLSCNT to the
desired number of pulses, The SYSREF output is in pin control Pulser mode. The SYSREF clock can be initiated
by a pulse at the SYNC pin. Fixed number of pulses as per the OUTCH_SYSREF_PLSCNT value are generated
after a fixed latency.
9.3.7.3.1.3 Multiple SYSREF Frequencies
In case of multiple SYSREF frequencies the latencies until SYSREF pulses start are different. As shown in
Figure 45, the different SYSREF signals are rising edge aligned with the device clock. The different SYSREF
signals might not be rising edge aligned if different SYSREF frequencies are used.
DeviceCLK
SYSREF_A
SYSREF_B
Latency A
Latency B
SYSREF Request
asserted
released
Figure 45. SYSREF Timing in Pulsor Mode With Different SYSREF Frequencies
9.3.7.3.2 Continuous SYSREF
This mode allows for continuous output of the SYSREF clock.
Setting GLOBAL_CONT_SYSREF to 1 allows for continuous output of the SYSREF clock.
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Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock.
JESD204B is designed to operate with a single burst of pulses to initialize the system at start-up, after which it is
theoretically not required to send another SYSREF because the system continues to operate with deterministic
phases.
If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or
SYSREF from the OSCout pin to minimize crosstalk.
SYSREF Output
Figure 46. Continuous SYSREF
9.3.7.3.3 SYSREF Request
This mode allows an external source to SYNChronously turn on or off a continuous stream of SYSREF pulses
using the SYNC pin.
When programming EN_SYNC_PIN_FUNC= 1, SYNC_PIN_FUNC=01 and OUTCH_SYSREF_PLSCNT=0, the
SYSREF output is in pin mode. The SYSREF pulses can be controlled by the pulse width at the SYNC pin.
When the SYNC pin is asserted, the channel is SYNChronously set to continuous mode providing continuous
pulses at the SYSREF frequency until the SYNC pin is unasserted. SYSREF stops after completing the final
pulse SYNChronously.
SYSREF Output
SYSREF_REQ
Or
SPI
Figure 47. SYSREF Request
9.3.7.4 How to Enable SYSREF
Enabling JESD204B operation involves SYNChronizing all the clock dividers and programming of the delays,
then configuring the actual SYSREF functionality.
9.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
1. Program EN_SYNC_PIN_FUNC=1, SYNC pin is enabled for SYSREF requests.
2. Program SYNC_PIN_FUNC=01, SYNC pin is programmed to accept the SYSREF requests.
3. Program OUTCH_SYSREF_PLSCNT= xx (max 32), programs the number of SYSREF pulses to be
generated.
4. Program SYSREF_EN_CHxx=1, enables corresponding output channels to generate SYSREF clock pulses.
5. Apply rising Edge at SYNC pin generates xx number of at the enabled at the enabled channel.
9.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
1. Program EN_SYNC_PIN_FUNC=0, the SYSREF function on the SYNC pin is not enabled.
2. Program OUTCH_SYSREF_PLSCNT= xx (max 32), programs the number of SYSREF pulses to be
generated.
3. Program SYSREF_EN_CHxx=1, enables corresponding output channels to generate SYSREF clock pulses.
4. Programming GLOBAL_SYSREF=1 generates the defined number of pulses on the SYSREF enabled
channels.
9.3.8 Zero Delay Mode (ZDM)
The LMK0461x zero delay mode (ZDM) is an internal feedback loop that minimizes the phase error between
output and reference input. The feedback can be selected from CLKout6 or CLKout9.
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CLKoutX*
CLKoutX
- Divider
- Digital Delay
- Analog Delay
PLL2
CLKoutY*
CLKoutY
R
N
Phase
Detector
PLL2
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
- Divider
- Digital Delay
- Analog Delay
CLKoutY*
CLKoutY
Figure 48. Zero Delay Mode
9.3.9 Power-Up Sequence
Figure 49 shows the steps to power up the device.
Power Supplies
all off
All Supplies
powered up
DEVICE IDLE
In
Power-Down
State
DEVICE IDLE
READY FOR SPI
PROGRAMMING
Release RESETn
Ramp-up Power Supplies
DEVICE
NOT READY
RESETn = X
(Power-down)
RESETn = 0
(Power-down)
RESETn = 1
Program device configuration settings
DEVICE IDLE
Trigger Startup
Sequence through SPI
STAT0/1
indicates
PLL Lock
DEVICE
BOOTING
UP
DEVICE
CONFIG
PROGRAMMING
DONE
DEVICE
RUNNING
DEV_STARTUP = 1
(self clearing bit)
RESETn = 1
RESETn = 1
RESETn = 1
Figure 49. Simplified Power-Up Sequence
The first step is to apply all the supplies needed for device to be functional. The RESETn should be kept at logic
0 when power supplies start ramping. LMK046xx devices do not need any specific power up sequencing for the
external power supplies. The on-chip POR logic makes sure that the device stays in power-down state until all
the supplies are available.
After all the device power supplies are stable, RESETn can be released to logic 1. The device enters idle state
and is now ready for the SPI programming.
After programming the device configuration, the DEV_start-up should be triggered using SPI, which initiates the
device bootup sequence. The loading of the configurations to the corresponding functional blocks and enable
sequencing is cared for by the on-chip state machines. One-time SYNC is also issued to the output channels
during device booting. The lock signals for the PLLs can be observed at the STAT0/1.
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Figure 50 shows the LMK0461x booting sequence of operations in details. Branch A, B, and C run in parallel.
RESETN = 0
Enable OSCout
SET OSCout
Low level
buffer:
divider = 1
LVCMOS
All Supplies
powered up
Sample SYNC pin
voltage level
SET OSCout
divider = 2
Mid level
Program
device and
boot up
SPI interface
ready
RESETN = 1
SET OSCout
divider = 4
High level
Branch A
(PLL1)
Branch B
(PLL2)
Branch C
(Outputs)
PLL2 in power down
mode.
PLL2 REF clock
available.
Internal LDO
settling time
Internal LDO
settling time
PLL1 Enabled?
YES
PLL2 Enabled?
NO
YES
Assert internal
SYNC signal
Set Prop/
Store-CP to
^(ꢀ•š o}ꢁl_
value
^(ꢀ•š o}ꢁl_
enabled?
YES
Internal LDO
settling time
PLL2
Amplitude
Calibration
NO
MUTE enabled?
YES
NO
Force Holdover
Mode with
CRTL_VCXO =
VDD/2
PLL1_STARTUP_I
N_HOLDOVER
Set?
YES
Waiting for
PLL2 lock
Release reset
of channels
Release reset
of channels
NO
NO
PLL1_N,
PLL1_R divider
reset is
CLKinX
available?
Wait for PLL2
lock
released
Release
internal SYNC
signal
Release
internal SYNC
signal
Wait for PLL1
Lock
Set Prop/
Store-CP to
^v}v-(ꢀ•š o}ꢁl_
^(ꢀ•š o}ꢁl_
enabled?
YES
PLL2 locks
value
NO
STATUS0/1 will
indicate PLL lock
Switch digital-block
clock to PLL2 Ref
clock source
Figure 50. Detailed Power-Up Sequence
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9.4 Device Functional Modes
The following section describes the settings to enable various modes of operation for the LMK0461x device
family.
The LMK0461x device is a flexible device that can be configured for many different use cases. The following
simplified block diagrams help show the user the different use cases of the device.
9.4.1 Dual PLL
illustrates the typical use case of the LMK0461x device family in dual-loop mode. In dual-loop mode the
reference to PLL1 from CLKin0, CLKin1, CLKin2, or CLKin3. An external VCXO is used to provide feedback for
the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow
loop bandwidth. The VCXO output may be buffered through the OSCout port. The VCXO is used as the
reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to 8 divide or
delay blocks which drive up to 16 clock outputs.
Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the
tuning voltage of PLL1 to the VCXO.
PLL1
PLL2
External
VCXO
CLKinX
CLKinX*
OSCout
R
N
Divider
Phase
Detector
PLL1
OSCout*
Integrated
Loop Filter
4 inputs
Internal VCO
R
N
16 Device/Sysref
Clocks
Phase
Detector
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
8 blocks
LMK04616
Copyright © 2017, Texas Instruments Incorporated
Figure 51. Simplified Functional Block Diagram for Dual-Loop Mode
9.4.2 Single PLL
No LOS detection and automatic reference switching available in this mode.
PLL1
PLL2
External
VCXO
CLKinX
CLKinX*
OSCout
R
N
Divider
Phase
Detector
PLL1
OSCout*
Integrated
Loop Filter
4 inputs
Internal VCO
R
N
16 Device/Sysref
Clocks
Phase
Detector
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
8 blocks
LMK04616
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Simplified Functional Block Diagram for PLL2 Only or Clock Generator Mode
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Device Functional Modes (continued)
9.4.3 PLL2 Bypass
PLL1
PLL2
External
VCXO
CLKinX
OSCout
R
Divider
CLKinX*
Phase
4 inputs
OSCout*
Integrated
Loop Filter
Detector
PLL1
Internal VCO
R
N
16 Device/Sysref
Clocks
N
Phase
Detector
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
8 blocks
LMK04616
Copyright © 2017, Texas Instruments Incorporated
Figure 53. Simplified Functional Block Diagram for PLL1 Only or PLL2 Bypass Mode
9.4.4 Clock Distribution
No LOS detection and automatic Reference Switching available in this mode.
PLL1
PLL2
External
VCXO
CLKinX
CLKinX*
OSCout
R
N
Divider
OSCout*
Phase
Detector
PLL1
Integrated
Loop Filter
4 inputs
Internal VCO
R
N
16 Device/Sysref
Clocks
Phase
Detector
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
8 blocks
LMK04616
Copyright © 2017, Texas Instruments Incorporated
Figure 54. Simplified Functional Block Diagram for Clock Distribution Mode
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9.5 Programming
LMK0461x device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a
15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB
first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in
on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents
into the shift register. TI recommends programming registers in numeric order -- for example, 0x000 to 0x1FFF --
to achieve proper device operation. Each register consists of one or more fields that control the device
functionality. See the electrical characteristics and 图 1 for timing details.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
SCS*
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24
SCL
SDIO
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2
D1 D0
SDO
(STATUS1)
Figure 55. SPI Write
SCS*
SCL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24
SDIO
SDIO
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2
D1 D0
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO
(STATUS1)
D7 D6 D5 D4 D3 D2
D1 D0
Figure 56. SPI Read
SCS*
1
2
3
14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32
SCL
Addr N
A2 A1 A0 D7 D6 D5 D4 D3 D2
Addr N+1 (ascending), Addr N-1 (descending)
D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDIO
R/W A14 A13
SDO
(STATUS1)
Figure 57. SPI Write – Streaming Mode
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Programming (continued)
SCS*
1
2
3
14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32
SCL
Addr N
A2 A1 A0 D7 D6 D5 D4 D3 D2
Addr N+1 (ascending), Addr N-1 (descending)
D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDIO
SDIO
R/W A14 A13
R/W A14 A13
A2 A1 A0
SDO
(STATUS1)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
D1 D0
Figure 58. SPI Read – Streaming Mode
9.5.1 Recommended Programming Sequence
The default programming sequence from POR involves:
1. Toggle RESETn pin High-Low-High
2. Program all registers with Register 0x0011 bit 0 = 0
–
–
–
Register 0x85 = 0x00
Register 0x86 = 0x00
Register 0xF6 = 0x02
3. Program Register 0x0011 bit 0 = 1 to start the device
4. Enable PLL2 digital lock detect
–
–
–
0xAD = 0x30
Delay 20 ms
0xAD = 0x00
Also refer to Power-Up Sequence.
9.5.1.1 Readback
Readback of the complete register content is possible.
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9.6 Register Maps
9.6.1 Register Map for Device Programming
Table 24 provides the register map for device programming. Any register can be read from the same data
address it is written to.
Table 24. Register Map
ADDRESS
[15:0]
DATA
D7
D6
D5
D4
D3
D2
D1
D0
ADDR_ASCEN
D
SDO_ACTIVE_C ADDR_ASCEND LSB_FIRST_C
0x00
SWRST
LSB_FIRST
SDO_ACTIVE
RSRVD
SWRST_CPY
RSRVD1
PY
_CPY
PY
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
RSRVD
RSRVD
RSRVD2[1:0]
DEVID[1:0]
CHIPTYPE[3:0]
CHIPID[15:8]
CHIPID[7:0]
CHIPVER[7:0]
RSRVD
RSRVD3
RSRVD4
RSRVD5
RSRVD6
RSRVD7
RSRVD
RSRVD
RSRVD
RSRVD
VENDORID[15:8]
VENDORID[7:0]
RSRVD
RSRVD
RSRVD8
RSRVD9
CLKINBLK_LOS
LDO_EN
0x10
0x11
RSRVD
OUTCH_MUTE
RSRVD
CH8TO15EN
CH0TO7EN
PLL2EN
PLL1EN
DEV_STARTU
P
RSRVD
PLL2_DIG_CL PORCLKAFTE
0x12
0x13
0x14
DIG_CLK_EN
K_EN
RLOCK
RSRVD
RSRVD
PLL2_REF_DIGCLK_DIV[4:0]
EN_SYNC_PIN_
GLOBAL_CON GLOBAL_SYSR INV_SYNC_INP
GLOBAL_SYN
C
SYNC_PIN_FUNC[1:0]
FUNC
T_SYSREF
EF
UT_SYNC_CLK
CLKIN_STAGGE
R_EN
CLKINSEL1_IN
V
0x15
0x16
0x17
0x18
0x19
0x1A
RSRVD
CLKIN_SWRST
RSRVD
RSRVD
CLKINBLK_ALL
_EN
CLKINBLK_EN_ CLKINBLK_EN_
CLKINSEL1_MODE[1:0]
RSRVD
RSRVD
BUF_CLK_PLL
BUF_BYP_PLL
CLKIN0_PLL1_ CLKIN0_LOS_
CLKIN0_SE_MO
DE
RSRVD
RSRVD
RSRVD
RSRVD
CLKIN0_EN
CLKIN0_PRIO[2:0]
CLKIN1_PRIO[2:0]
CLKIN2_PRIO[2:0]
CLKIN3_PRIO[2:0]
INV
FRQ_DBL_EN
CLKIN1_PLL1_ CLKIN1_LOS_
CLKIN1_SE_MO
DE
CLKIN1_EN
CLKIN2_EN
CLKIN3_EN
INV FRQ_DBL_EN
CLKIN2_PLL1_ CLKIN2_LOS_
INV FRQ_DBL_EN
CLKIN2_SE_MO
DE
CLKIN3_PLL1_ CLKIN3_LOS_
INV FRQ_DBL_EN
CLKIN3_SE_MO
DE
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
CLKIN0_PLL1_RDIV[15:8]
CLKIN0_PLL1_RDIV[7:0]
CLKIN1_PLL1_RDIV[15:8]
CLKIN1_PLL1_RDIV[7:0]
CLKIN2_PLL1_RDIV[15:8]
CLKIN2_PLL1_RDIV[7:0]
CLKIN3_PLL1_RDIV[15:8]
CLKIN3_PLL1_RDIV[7:0]
CLKIN0_LOS_REC_CNT[7:0]
CLKIN0_LOS_LAT_SEL[7:0]
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
0x25
DATA
CLKIN1_LOS_REC_CNT[7:0]
CLKIN1_LOS_LAT_SEL[7:0]
CLKIN2_LOS_REC_CNT[7:0]
CLKIN2_LOS_LAT_SEL[7:0]
CLKIN3_LOS_REC_CNT[7:0]
CLKIN3_LOS_LAT_SEL[7:0]
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
RSRVD
SW_REFINSEL[3:0]
RSRVD
SW_CLKLOS_TMR[4:0]
SW_LOS_CH_SEL[3:0]
SW_ALLREFSON_TMR[4:0]
OSCIN_PD_LD OSCIN_SE_MO OSCIN_BUF_TO OSCIN_OSCINS OSCIN_BUF_ OSCIN_BUF_L
0x2E
0x2F
RSRVD
O
DE _OSCOUT_EN TAGE_EN REF_EN OS_EN
OSCOUT_LVCM OSCOUT_DIV
OS_WEAK_DRI _REGCONTR
OSCOUT_SEL_ OSCOUT_DIV_ OSCOUT_SW OSCOUT_SEL
VBG CLKEN RST _SRC
OSCOUT_PINSEL_DIV[1:0]
VE
OL
0x30
0x31
OSCOUT_DIV[7:0]
OSCOUT_DRV_MODE[5:0]
OSCOUT_DRV_MUTE[1:0]
CH1415_SWRS CH1213_SWR CH1011_SWR
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
CH89_SWRST
CH67_SWRST
CH45_SWRST CH23_SWRST CH01_SWRST
T
ST ST
OUTCH01_LDO OUTCH01_LD
_BYP_MODE O_MASK
OUTCH0_DRIV_MODE[5:0]
OUTCH2_DRIV_MODE[5:0]
OUTCH4_DRIV_MODE[5:0]
OUTCH6_DRIV_MODE[5:0]
OUTCH8_DRIV_MODE[5:0]
OUTCH10_DRIV_MODE[5:0]
OUTCH12_DRIV_MODE[5:0]
OUTCH14_DRIV_MODE[5:0]
DIV_DCC_EN_ OUTCH01_DIV
CH0_1 _CLKEN
OUTCH1_DRIV_MODE[5:0]
OUTCH3_DRIV_MODE[5:0]
OUTCH5_DRIV_MODE[5:0]
OUTCH7_DRIV_MODE[5:0]
OUTCH9_DRIV_MODE[5:0]
OUTCH11_DRIV_MODE[5:0]
OUTCH13_DRIV_MODE[5:0]
OUTCH15_DRIV_MODE[5:0]
OUTCH23_LDO OUTCH23_LD
_BYP_MODE O_MASK
DIV_DCC_EN_ OUTCH23_DIV
CH2_3 _CLKEN
OUTCH45_LDO OUTCH45_LD
_BYP_MODE O_MASK
DIV_DCC_EN_ OUTCH45_DIV
CH4_5 _CLKEN
OUTCH67_LDO OUTCH67_LD
_BYP_MODE O_MASK
DIV_DCC_EN_ OUTCH67_DIV
CH6_7 _CLKEN
OUTCH89_LDO OUTCH89_LD
_BYP_MODE O_MASK
DIV_DCC_EN_ OUTCH89_DIV
CH8_9 _CLKEN
OUTCH1011_LD OUTCH1011_L
O_BYP_MODE DO_MASK
DIV_DCC_EN_ OUTCH1011_
CH10_11 DIV_CLKEN
OUTCH1213_LD OUTCH1213_L
O_BYP_MODE DO_MASK
DIV_DCC_EN_ OUTCH1213_
CH12_13 DIV_CLKEN
OUTCH1415_LD OUTCH1415_L
O_BYP_MODE DO_MASK
DIV_DCC_EN_ OUTCH1415_
CH14_15 DIV_CLKEN
0x43
0x44
0x45
0x46
0x47
0x48
0x49
OUTCH01_DIV[15:8]
OUTCH01_DIV[7:0]
OUTCH23_DIV[15:8]
OUTCH23_DIV[7:0]
OUTCH45_DIV[15:8]
OUTCH45_DIV[7:0]
OUTCH67_DIV[15:8]
60
Copyright © 2017–2019, Texas Instruments Incorporated
LMK04616
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
0x4A
DATA
OUTCH67_DIV[7:0]
OUTCH89_DIV[15:8]
OUTCH89_DIV[7:0]
OUTCH1011_DIV[15:8]
OUTCH1011_DIV[7:0]
OUTCH1213_DIV[15:8]
OUTCH1213_DIV[7:0]
OUTCH1415_DIV[15:8]
OUTCH1415_DIV[7:0]
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
OUTCH1415_DI OUTCH1213_
0x53
OUTCH1011_ OUTCH89_DIV_ OUTCH67_DIV_ OUTCH45_DIV_ OUTCH23_DIV OUTCH01_DIV
V_INV
DIV_INV
DIV_INV
INV
INV
INV
_INV
_INV
PLL1_EN_RE
GULATION
PLL1_DIR_POS
_GAIN
0x54
0x55
0x56
0x57
PLL1_F_30
PLL1_PD_LD
PLL1_LDO_WAIT_TMR[3:0]
PLL1_PFD_DO
WN_HOLDOV
ER
PLL1_LCKDET_ PLL1_FAST_L PLL1_LCKDET PLL1_FBCLK_IN
PLL1_PFD_UP
_HOLDOVER
RSRVD
PLL1_BYP_LOS
BY_32
OCK
_LOS_MASK
V
PLL1_LOL_NOR PLL1_RDIV_CL PLL1_RDIV_4C PLL1_NDIV_C PLL1_NDIV_4
RSRVD
ESET
KEN
Y
LKEN
CY
PLL1_HOLDO
VER_DLD_SW
RST
PLL1_HOLDO
PLL1_RDIV_SW PLL1_NDIV_SW PLL1_HOLDOV
RSRVD
VER_LOCKDE PLL1_SWRST
T_SWRST
RST
RST
ERCNT_SWRST
0x58
0x59
0x5A
0x5B
PLL1_LD_WNDW_SIZE[7:0]
PLL1_INTG_FL [3:0]
PLL1_INTG [3:0]
RSRVD
RSRVD
PLL1_PROP[6:0]
PLL1_PROP_FL[6:0]
PLL1_STARTU
P_HOLDOVER
_EN
PLL1_HOLDOV PLL1_HOLDOV
ER_RAIL_MOD ER_MAX_CNT_
PLL1_HOLDO PLL1_HOLDO
VER_LCKDET VER_RAILDET
PLL1_HOLDOV
ER_EN
PLL1_HOLDO
VER_FORCE
PLL1_HOLDOV
ER_LOS_MASK
0x5C
E
EN
_MASK
_EN
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
PLL1_HOLDOVER_MAX_CNT[31:24]
PLL1_HOLDOVER_MAX_CNT[23:16]
PLL1_HOLDOVER_MAX_CNT[15:8]
PLL1_HOLDOVER_MAX_CNT[7:0]
PLL1_NDIV[15:8]
PLL1_NDIV[7:0]
PLL1_LOCKDET_CYC_CNT[23:16]
PLL1_LOCKDET_CYC_CNT[15:8]
PLL1_LOCKDET_CYC_CNT[7:0]
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
PLL1_STORAGE_CELL[5:0]
RSRVD
PLL1_RC_CLK_
EN
0x6B
0x6C
0x6D
0x6E
RSRVD
RSRVD
PLL1_RC_CLK_DIV[2:0]
PLL2_BYP_BO PLL2_GLOBAL
PLL2_VCO_PRE
SC_LOW_POW PLL2_BYP_OSC PLL2_BYP_TOP
ER
T
_BYP
PLL2_EN_PULS PLL2_RDIV_B PLL2_DBL_EN PLL2_PD_VARB PLL2_SMART_T PLL2_LCKDET_ PLL2_RDIV_D
E_GEN YP _INV IAS RIM LOS_MASK BL_EN
PLL2_PD_LD
PLL2_EN_BUF
_CLK_BOTTO
M
PLL2_BYP_SYN PLL2_BYP_SY PLL2_EN_BYP PLL2_EN_BUF_ PLL2_EN_BUF_ PLL2_EN_BUF_ PLL2_EN_BUF
C_TOP
NC_BOTTOM
_BUF
SYNC_TOP
SYNC_BOTTOM
OSCOUT
_CLK_TOP
PLL2_RDIV_SW PLL2_NDIV_S
RST WRST
0x6F
0x70
RSRVD
PLL2_SWRST
PLL2_C4_LF_SEL[3:0]
PLL2_R4_LF_SEL[3:0]
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x7D
0x7E
PLL2_C3_LF_SEL[3:0]
PLL2_R3_LF_SEL[3:0]
PLL2_PROP[5:0]
RSRVD
PLL2_NDIV[15:8]
PLL2_NDIV[7:0]
PLL2_RDIV[15:8]
PLL2_RDIV[7:0]
PLL2_STRG_INITVAL[15:8]
PLL2_STRG_INITVAL[7:0]
RSRVD
RSRVD
RAILDET_UPP[5:0]
RAILDET_LOW[5:0]
PLL2_AC_CAL
_EN
PLL2_AC_RE PLL2_FAST_A
0x7F
RSRVD
PLL2_PD_AC
PLL2_IDACSET_RECAL[1:0]
Q
CAL
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
RSRVD
RSRVD
RSRVD
PLL2_INTG[4:0]
PLL2_AC_THRESHOLD[4:0]
PLL2_AC_STRT_THRESHOLD[4:0]
PLL2_AC_CMP_WAIT[3:0]
RSRVD
PLL2_AC_INIT_WAIT[3:0]
PLL2_AC_JUMP_STEP[3:0]
PLL2_LD_WNDW_SIZE[7:0]
PLL2_LD_WNDW_SIZE_INITIAL[7:0]
PLL2_LOCKDET_CYC_CNT[23:16]
PLL2_LOCKDET_CYC_CNT[15:8]
PLL2_LOCKDET_CYC_CNT[7:0]
PLL2_LOCKDET_CYC_CNT_INITIAL[23:16]
PLL2_LOCKDET_CYC_CNT_INITIAL[15:8]
PLL2_LOCKDET_CYC_CNT_INITIAL[7:0]
SPI_SDIO_OUT
PUT_WEAK_DR
IVE
SPI_EN_THREE
SPI_SDIO_OUT SPI_SDIO_OUT
PUT_MUTE PUT_INV
SPI_SDIO_EN SPI_SDIO_EN
0x8D
RSRVD
RSRVD
_WIRE_IF
_PULLUP
_PULLDOWN
SPI_SCL_EN_P SPI_SCL_EN_P SPI_SCS_EN_ SPI_SCS_EN_
0x8E
0x8F
0x90
0x91
ULLUP
ULLDOWN
PULLUP
PULLDOWN
SPI_SDIO_OU SPI_SDIO_EN SPI_SDIO_EN_
TPUT_HIZ B_INSTAGE ML_INSTAGE
SPI_SDIO_OUT SPI_SDIO_INP SPI_SDIO_INP
PUT_DATA
RSRVD
RSRVD
UT_Y12
UT_M12
SPI_SCL_ENB SPI_SCL_EN_M
_INSTAGE L_INSTAGE
SPI_SCL_INP
UT_Y12
SPI_SCL_INP
UT_M12
RSRVD
RSRVD
RSRVD
RSRVD
SPI_SCS_ENB SPI_SCS_EN_M
_INSTAGE L_INSTAGE
SPI_SCS_INP SPI_SCS_INP
UT_Y12 UT_M12
STATUS0_OUT
PUT_WEAK_DR
IVE
STATUS0_OUT STATUS0_OUT
PUT_MUTE PUT_INV
STATUS0_EN STATUS0_EN
_PULLUP _PULLDOWN
0x92
0x93
STATUS0_MUX_SEL[2:0]
STATUS1_MUX_SEL[2:0]
STATUS1_OUT
PUT_WEAK_DR
IVE
STATUS1_OUT STATUS1_OUT
PUT_MUTE PUT_INV
STATUS1_EN STATUS1_EN
_PULLUP _PULLDOWN
0x94
0x95
STATUS1_INT_MUX[7:0]
STATUS0_INT_MUX[7:0]
PLL2_REF_CLK
_EN
0x96
0x97
0x98
RSRVD
RSRVD
RSRVD
RSRVD
PLL2_REF_STATCLK_DIV[2:0]
STATUS0_OU STATUS0_EN STATUS0_EN_
TPUT_HIZ B_INSTAGE ML_INSTAGE
STATUS0_OUT STATUS0_INP STATUS0_INP
RSRVD
RSRVD
PUT_DATA
UT_Y12
UT_M12
STATUS1_OU STATUS1_EN STATUS1_EN_
STATUS1_OUT STATUS1_INP STATUS1_INP
PUT_DATA UT_Y12 UT_M12
TPUT_HIZ
B_INSTAGE
ML_INSTAGE
SYNC_OUTPUT SYNC_OUTPUT SYNC_OUTPUT SYNC_EN_PU SYNC_EN_PU
0x99
0x9A
0x9B
SYNC_MUX_SEL[2:0]
_MUTE
_INV
_WEAK_DRIVE
LLUP
LLDOWN
RSRVD
RSRVD
CLKINSEL1_E CLKINSEL1_E
N_PULLUP N_PULLDOWN
RSRVD
62
Copyright © 2017–2019, Texas Instruments Incorporated
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ZHCSG70B –MARCH 2017–REVISED JULY 2019
Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
CLKINSEL1_E CLKINSEL1_EN
CLKINSEL1_IN CLKINSEL1_IN
0x9C
0xAC
0xAD
0xAF
0xB0
0xBE
RSRVD
RSRVD
NB_INSTAGE
_ML_INSTAGE
PUT_Y12
PUT_M12
PLL1_TSTMOD
E_REF_FB_EN
RSRVD
RSRVD
RSRVD
RSRVD
PLL2_TSTMOD
E_REF_FB_EN
RSRVD
RESET_PLL2_DLD[1:0]
PD_VCO_LDO[1:0]
PLL2_RDIV_C
LKEN
RSRVD
RSRVD
RSRVD
RSRVD
PLL2_NDIV_C
LKEN
HOLDOVER_DL HOLDOVER_LO HOLDOVER_LO PLL2_LCK_DE PLL1_LCK_DE
RSRVD
LOS
D
L
S
T
T
0xF6
0xFD
RSRVD
PLL2_DLD_EN
RSRVD
OUTCH01_DDLY[7:0]
OUTCH23_DDLY[7:0]
OUTCH45_DDLY[7:0]
OUTCH67_DDLY[7:0]
OUTCH89_DDLY[7:0]
OUTCH1011_DDLY[7:0]
OUTCH1213_DDLY[7:0]
OUTCH1415_DDLY[7:0]
0xFF
0x101
0x103
0x105
0x107
0x109
0x10B
CH0_ADLY_E
N
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
CH0_ADLY[4:0]
CH1_ADLY[4:0]
CH2_ADLY[4:0]
CH3_ADLY[4:0]
CH4_ADLY[4:0]
CH5_ADLY[4:0]
CH6_ADLY[4:0]
CH7_ADLY[4:0]
CH8_ADLY[4:0]
CH9_ADLY[4:0]
CH10_ADLY[4:0]
CH11_ADLY[4:0]
CH12_ADLY[4:0]
CH13_ADLY[4:0]
CH14_ADLY[4:0]
CH15_ADLY[4:0]
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
CH1_ADLY_E
N
CH2_ADLY_E
N
CH3_ADLY_E
N
CH4_ADLY_E
N
CH5_ADLY_E
N
CH6_ADLY_E
N
CH7_ADLY_E
N
CH8_ADLY_E
N
CH9_ADLY_E
N
CH10_ADLY_E
N
CH11_ADLY_E
N
CH12_ADLY_E
N
CH13_ADLY_E
N
CH14_ADLY_E
N
CH15_ADLY_E
N
0x11B
0x124
RSRVD
SYSREF_BYP
_ANALOGDLY SYNC_EN_CH
_GATING_CH0
_1
CLKMUX[3:0]
SYSREF_BYP_
DYNDIGDLY_G
ATING_CH0_1
0x127
HS_EN_CH0_1
DRIV_1_SLEW[1:0]
DRIV_0_SLEW[1:0]
0_1
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
SYSREF_BYP
SYSREF_BYP_
_ANALOGDLY SYNC_EN_CH
0x128
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
DYNDIGDLY_G
ATING_CH2_3
HS_EN_CH2_3
HS_EN_CH4_5
HS_EN_CH6_7
HS_EN_CH8_9
DRIV_3_SLEW[1:0]
DRIV_5_SLEW[1:0]
DRIV_7_SLEW[1:0]
DRIV_9_SLEW[1:0]
DRIV_11_SLEW[1:0]
DRIV_13_SLEW[1:0]
DRIV_15_SLEW[1:0]
DRIV_2_SLEW[1:0]
_GATING_CH2
_3
2_3
SYSREF_BYP
_ANALOGDLY SYNC_EN_CH
SYSREF_BYP_
DYNDIGDLY_G
ATING_CH4_5
DRIV_4_SLEW[1:0]
DRIV_6_SLEW[1:0]
DRIV_8_SLEW[1:0]
DRIV_10_SLEW[1:0]
DRIV_12_SLEW[1:0]
DRIV_14_SLEW[1:0]
_GATING_CH4
_5
4_5
SYSREF_BYP
_ANALOGDLY SYNC_EN_CH
SYSREF_BYP_
DYNDIGDLY_G
ATING_CH6_7
_GATING_CH6
_7
6_7
SYSREF_BYP
_ANALOGDLY SYNC_EN_CH
SYSREF_BYP_
DYNDIGDLY_G
ATING_CH8_9
_GATING_CH8
_9
8_9
SYSREF_BYP_ SYSREF_BYP
DYNDIGDLY_G _ANALOGDLY SYNC_EN_CH HS_EN_CH10_1
ATING_CH10_1 _GATING_CH1 10_11
0_11
1
1
SYSREF_BYP_ SYSREF_BYP
DYNDIGDLY_G _ANALOGDLY SYNC_EN_CH HS_EN_CH12_1
ATING_CH12_1 _GATING_CH1 12_13
2_13
3
3
SYSREF_BYP_ SYSREF_BYP
DYNDIGDLY_G _ANALOGDLY SYNC_EN_CH HS_EN_CH14_1
ATING_CH14_1 _GATING_CH1
14_15
5
5
4_15
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x140
0x141
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
DYN_DDLY_CH0[2:0]
DYN_DDLY_CH1[2:0]
DYN_DDLY_CH2[2:0]
DYN_DDLY_CH3[2:0]
DYN_DDLY_CH4[2:0]
DYN_DDLY_CH5[2:0]
DYN_DDLY_CH6[2:0]
DYN_DDLY_CH7[2:0]
DYN_DDLY_CH8[2:0]
DYN_DDLY_CH9[2:0]
DYN_DDLY_CH10[2:0]
DYN_DDLY_CH11[2:0]
DYN_DDLY_CH12[2:0]
DYN_DDLY_CH13[2:0]
DYN_DDLY_CH14[2:0]
DYN_DDLY_CH15[2:0]
RSRVD
OUTCH_SYSREF_PLSCNT[5:0]
SYNC_INT_MUX[7:0]
SYNC_OUTPU SYNC_ENB_IN SYNC_EN_ML_I
SYNC_OUTPUT SYNC_INPUT_ SYNC_INPUT_
0x142
0x143
0x146
RSRVD
RSRVD
RSRVD
T_HIZ
STAGE
NSTAGE
_DATA
Y12
M12
FBBUF_CH6_E
N
FBBUF_CH9_
EN
RSRVD
RSRVD
PLL2_NBYPAS
S_DIV2_FB
PLL2_PRESCALER[3:0]
PLL1_CLKINSE
PLL2_FBDIV_MUXSEL[1:0]
PLL1_SYNC_H PLL1_STATUS PLL1_STATUS
0x149
RSRVD
L1_ML_HOLDO
VER
OLDOVER
1_HOLDOVER 0_HOLDOVER
SYNC_ANALO
SYNC_INV
GDLY_EN
0x14A
0x14B
RSRVD
SYNC_ANALOGDLY[4:0]
DYN_DDLY_CH DYN_DDLY_C DYN_DDLY_C DYN_DDLY_CH DYN_DDLY_CH DYN_DDLY_CH DYN_DDLY_C DYN_DDLY_C
15_EN H14_EN H13_EN 12_EN 11_EN 10_EN H9_EN H8_EN
64
Copyright © 2017–2019, Texas Instruments Incorporated
LMK04616
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ZHCSG70B –MARCH 2017–REVISED JULY 2019
Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
DYN_DDLY_CH DYN_DDLY_C DYN_DDLY_C DYN_DDLY_CH DYN_DDLY_CH DYN_DDLY_CH DYN_DDLY_C DYN_DDLY_C
7_EN H6_EN H5_EN 4_EN 3_EN 2_EN H1_EN H0_EN
0x14C
0x14E
0x150
0x151
SYSREF_EN_C SYSREF_EN_ SYSREF_EN_ SYSREF_EN_C SYSREF_EN_C SYSREF_EN_C SYSREF_EN_ SYSREF_EN_
H14_15
CH12_13
RSRVD
RSRVD
CH10_11
H8_9
H6_7
H4_5
PLL2_PROG_PFD_RESET[2:0]
PLL2_CP_EN_S
CH2_3
CH0_1
PLL2_PFD_DIS_
SAMPLE
RSRVD
RSRVD
PLL2_RFILT
RSRVD
PLL2_CPROP[1:0]
AMPLE_BYP
PLL2_EN_FILTE
R
0x152
0x153
PLL2_CSAMPLE[2:0]
PLL2_CFILT
9.6.2 Device Register Descriptions
The following section details the fields of each register, the Power On Reset Defaults, and specific descriptions of
each bit.
In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as
X or Y. In these cases the X will represent even numbers from 0 to 12 and the Y will represent odd numbers
from 1 to 13. In the case where X and Y are both used in a bit name, then Y = X + 1.
9.6.2.1 CONFIGA
The CONFIGA Register provides control of the SPI operation. The data written to this register must always be
symmetrical otherwise the write will not take place, that is, Bit0=Bit7, Bit1=Bit6, Bit2=Bit5, Bit3=Bit4. Back to
Register Map.
Table 25. Register - 0x00
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Software Reset. Writing a 1 to SWRST will reset the device
apart from the SPI programmable registers. SWRST is
automatically cleared to 0.
[7]
SWRST
RWSC
0
Least Significant Bit First. This feature is not support, register
data is always transmitted MSB first.
[6]
[5]
LSB_FIRST
RW
RW
0
0
Address Increment Ascending. When set to 1 the address in
streaming transactions is incremented by 1 after each data
byte. When set to 0 the address is decremented by 1 in
streaming transactions.
ADDR_ASCEND
[4]
[3]
SDO_ACTIVE
RW
RW
0
0
SDO Active. SDO is always active. This bit always reads 1.
SDO Active. Must be programmed equal to bit 4.
SDO_ACTIVE_CPY
Address Increment Ascending. Must be programmed equal
to bit 5.
[2]
ADDR_ASCEND_CPY
RW
0
Least Significant Bit First. Must be programmed equal to bit
6.
[1]
[0]
LSB_FIRST_CPY
SWRST_CPY
RW
0
0
RWSC
Software Reset. Must be programmed equal to bit 7.
9.6.2.2 RESERVED1
Reserved Register space. Back to Register Map.
Table 26. Register - 0x01
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD1
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
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9.6.2.3 RESERVED2
Reserved Register space. Back to Register Map.
Table 27. Register - 0x02
BIT NO.
[7:2]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[1:0]
RSRVD2[1:0]
R
0x0
Reserved for compatibility.
9.6.2.4 CHIP_TYPE
The CHIP_TYPE Register defines the nature of this device. Back to Register Map.
Table 28. Register - 0x03
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Device Identification. Indicates the device partname
DEVID - Device
0 - LMK04616
1 - LMK04610
[7:6]
DEVID[1:0]
R
0x0
[5:4]
[3:0]
RSRVD
-
-
Reserved.
CHIPTYPE[3:0]
R
0x6
Chip Type. Indicates that this is a PLL Device.
9.6.2.5 CHIP_ID_BY1
The CHIP_ID is a vendor specific field recorded in registers CHIP_ID_BY1 and CHIP_ID_BY0. Back to Register
Map.
Table 29. Register - 0x04
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPID[15:8]
R
0x38
CHIP Identification.
9.6.2.6 CHIP_ID_BY0
The CHIP_ID lower byte is recorded in CHIP_ID_BY1 Back to Register Map.
Table 30. Register - 0x05
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPID[7:0]
R
0x3
CHIP Identification.
9.6.2.7 CHIP_VER
The CHIP_VER Register records the mask set revision. Back to Register Map.
Table 31. Register - 0x06
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPVER[7:0]
R
0x15
CHIP Version.
9.6.2.8 RESERVED3
Reserved Register space. Back to Register Map.
Table 32. Register - 0x07
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD3
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
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9.6.2.9 RESERVED4
Reserved Register space. Back to Register Map.
Table 33. Register - 0x08
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD4
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.10 RESERVED5
Reserved Register space. Back to Register Map.
Table 34. Register - 0x09
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD5
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.11 RESERVED6
Reserved Register space. Back to Register Map.
Table 35. Register - 0x0A
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD6
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.12 RESERVED7
Reserved Register space. Back to Register Map.
Table 36. Register - 0x0B
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD7
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.13 VENDOR_ID_BY1
The VENDOR_ID field is recorded in registers VENDOR_ID_BY1 and VENDOR_ID_BY0. Back to Register Map.
Table 37. Register - 0x0C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
VENDORID[15:8]
R
0x51
Vendor Identification.
9.6.2.14 VENDOR_ID_BY0
VENDOR_ID Lower Byte. Back to Register Map.
Table 38. Register - 0x0D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
VENDORID[7:0]
R
0x8
Vendor Identification.
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9.6.2.15 RESERVED8
Reserved Register space. Back to Register Map.
Table 39. Register - 0x0E
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD8
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.16 RESERVED9
Reserved Register space. Back to Register Map.
Table 40. Register - 0x0F
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD9
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[0]
R
0
Reserved for compatibility.
9.6.2.17 STARTUP_CFG
The STARTUP_CFG Register provides control of the device operation at startup. Back to Register Map.
Table 41. Register - 0x10
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
Output Channel Mute. When OUTCH_MUTE is 1 the output
drivers are disabled until the PLL's have locked.
[5]
OUTCH_MUTE
RW
0
[4]
[3]
[2]
[1]
[0]
CLKINBLK_LOSLDO_EN
CH8TO15EN
CH0TO7EN
RW
RW
RW
RW
RW
1
1
1
1
1
Enable LOS LDO during the startup sequence.
Enable Channels 8 to 15 during the startup sequence.
Enable Channels 0 to 7 during the startup sequence.
Activate PLL2 during the startup sequence.
PLL2EN
PLL1EN
Activate PLL1 during the startup sequence.
9.6.2.18 STARTUP
The STARTUP Register allows device activation to be triggered. Back to Register Map.
Table 42. Register - 0x11
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:1]
RSRVD
-
-
Reserved.
Device Startup. When DEV_STARTUP is 1 the device
activation sequence is triggered. The device modules that
are automatically enabled during the sequence is determined
by the STARTUP_CFG register. If DEV_STARTUP is 1 on
exit from software reset then the startup sequence will also
be triggered.
[0]
DEV_STARTUP
RW
0
9.6.2.19 DIGCLKCTRL
The DIGCLKCTRL Register allows control of the digital system clock. Back to Register Map.
Table 43. Register - 0x12
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Digital Clock Enable. When DIG_CLK_EN is 1 the digital
system clock is active. When DIG_CLK_EN is 0 the digital
system clock is disabled.
[2]
DIG_CLK_EN
RW
1
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Table 43. Register - 0x12 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[1]
PLL2_DIG_CLK_EN
RW
1
Enable PLL2 Digital Clock Buffer.
POR Clock behaviour after Lock. If PORCLKAFTERLOCK is
0 then the system clock is switched from the POR Clock to
the PLL2 Digital Clock after lock and the POR Clock
oscillator is disabled. If PORCLKAFTERLOCK is 1 then the
POR Clock will remain as the digital system clock regardless
of the PLL Lock state.
[0]
PORCLKAFTERLOCK
RW
0
9.6.2.20 PLL2REFCLKDIV
The PLL2REFCLKDIV Register controls the PLL2 Reference Clock Divider value. Back to Register Map.
Table 44. Register - 0x13
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
PLL2 Ref Clock Divider for Digital Clock. Defines the divider
ratio for the PLL2 Reference Clock that can be used as the
digital system clock.
PLL2_REF_DIGCLK_DIV - Divider Value
b00000 - 32
PLL2_REF_DIGCLK_DIV[4:0
]
[4:0]
RW
0x0
b00001 - 16
b00010 - 8
b00100 - 4
b01000 - 2
b10000 - 1
9.6.2.21 GLBL_SYNC_SYSREF
The GLBL_SYNC_SYSREF Register provides software control of the SYSREF and SYNC features. Back to
Register Map.
Table 45. Register - 0x14
BIT NO.
[7]
FIELD
TYPE
RW
RESET
DESCRIPTION
Enable SYNC_SYSREF features at SYNC pin.
Reserved.
EN_SYNC_PIN_FUNC
RSRVD
0
-
[6]
-
[5]
GLOBAL_CONT_SYSREF
GLOBAL_SYSREF
RW
0
0
Enable continuous sysref.
Trigger sysref. Self-clearing.
[4]
RWSC
INV_SYNC_INPUT_SYNC_C
LK
Invert the internal syncronization clock for SYNC input sync
(For PLL1 N- and R-Divider Reset)
[3]
[2:1]
[0]
RW
RW
RW
0
0x0
0
SYNC input pin function.
SYNC_PIN_FUNC - Function
00 - SYNC output channels
01 - Sysref Request
10 - Reset PLL1 N- and R-Divider
11 - Reserved
SYNC_PIN_FUNC[1:0]
GLOBAL_SYNC
Global SW SYNC. Writing '1' puts the Device into SYNC
mode. Writing '0' exits SYNC mode.
9.6.2.22 CLKIN_CTRL0
The CLKIN_CTRL0 Register provides control of CLK Input features. Back to Register Map.
Table 46. Register - 0x15
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
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Table 46. Register - 0x15 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKINBLK Staggered Activation/De-Activation. When
CLKIN_STAGGER_EN is 1 the input clock stages are
activated and de-activated one at a time.
[3]
CLKIN_STAGGER_EN
RW
1
CLKINBLK Software Reset. Writing a 1 to CLKIN_SWRST
will reset reset the CLKIN Block. The CLKIN_SWRST is
cleared automatically to 0.
[2]
[1]
CLKIN_SWRST
RSRVD
RWSC
-
0
-
Reserved.
CLKIN_SEL Invert.
CLKINSEL1_INV - Polarity
0 - Non-Inverted
[0]
CLKINSEL1_INV
RW
0
1 - Inverted
9.6.2.23 CLKIN_CTRL1
The CLKIN_CTRL1 Register provides control of CLK Input features. Back to Register Map.
Table 47. Register - 0x16
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLK Inputs All Enabled after Clock Switch. If
CLKINBLK_ALL_EN is 1 then all clock input paths remain
enabled after a valid clock has been selected. If
CLKINBLK_ALL_EN is 0 then the clock paths are disabled
apart from the selected clock.
[7]
CLKINBLK_ALL_EN
RW
0
CLK Input Select Mode.
CLKINSEL1_MODE - CLOCK Selection Mode
[6:5]
CLKINSEL1_MODE[1:0]
RW
0x0
0 - Auto
1 - Pin
2 - Register
CLKINBLK_EN_BUF_CLK_P
LL
[4]
[3]
RW
RW
0
0
Clock Buffer for PLL1 Enable.
CLKINBLK_EN_BUF_BYP_P
LL
Clock Buffer for PLL2 Enable (PLL1 By-Passed).
[2]
[1]
[0]
RSRVD
RSRVD
RSRVD
RW
RW
RW
0
0
0
Reserved.
Reserved.
Reserved.
9.6.2.24 CLKIN0CTRL
The CLKIN0CTRL Register provides control of the CLK0 input path. Back to Register Map.
Table 48. Register - 0x17
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Inverts CLKIN0_PLL1_RDIV.
0=Non-Inverted
[6]
CLKIN0_PLL1_INV
RW
1
1=Inverted
[5]
[4]
CLKIN0_LOS_FRQ_DBL_EN
CLKIN0_EN
RW
RW
0
0
CLKIN0 Loss of Source Frequency Doubler Enable.
CLKIN0 Input Stage Enable (not clk buffer).
CLKIN0 Signal Mode.
CLKIN0_SE_MODE - Signal Mode Selection
0 - Differential
[3]
CLKIN0_SE_MODE
RW
1
1 - Single-ended
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ZHCSG70B –MARCH 2017–REVISED JULY 2019
Table 48. Register - 0x17 (continued)
FIELD
TYPE
RESET
DESCRIPTION
CLKIN0 Priority.
CLKIN0_PRIO - Clock Priority
0 - Clock Disabled
1 - Priority 1 - Highest
2 - Priority 2
[2:0]
CLKIN0_PRIO[2:0]
RW
0x1
3 - Priority 3
4 - Priority 4 - Lowest
9.6.2.25 CLKIN1CTRL
The CLKIN1CTRL Register provides control of the CLK1 input path. Back to Register Map.
Table 49. Register - 0x18
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Inverts CLKIN1_PLL1_RDIV.
0=Non-Inverted
[6]
CLKIN1_PLL1_INV
RW
1
1=Inverted
[5]
[4]
CLKIN1_LOS_FRQ_DBL_EN
CLKIN1_EN
RW
RW
0
0
CLKIN1 Loss of Source Frequency Doubler Enable.
CLKIN1 Input Stage Enable. (not clk buffer).
CLKIN1 Signal Mode.
CLKIN1_SE_MODE - Signal Mode Selection
0 - Differential
[3]
CLKIN1_SE_MODE
RW
1
1 - Single-ended
CLKIN1 Priority.
CLKIN1_PRIO - Clock Priority
0 - Clock Disabled
1 - Priority 1 - Highest
2 - Priority 2
[2:0]
CLKIN1_PRIO[2:0]
RW
0x2
3 - Priority 3
4 - Priority 4 - Lowest
9.6.2.26 CLKIN2CTRL
The CLKIN2CTRL Register provides control of the CLK2 input path. Back to Register Map.
Table 50. Register - 0x19
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Inverts CLKIN2_PLL1_RDIV.
0=Non-Inverted
[6]
CLKIN2_PLL1_INV
RW
0
1=Inverted
[5]
[4]
CLKIN2_LOS_FRQ_DBL_EN
CLKIN2_EN
RW
RW
0
0
CLKIN2 Loss of Source Frequency Doubler Enable.
CLKIN2 Input Stage Enable. (not clk buffer).
CLKIN2 Signal Mode.
CLKIN2_SE_MODE - Signal Mode Selection
0 - Differential
[3]
CLKIN2_SE_MODE
RW
1
1 - Single-ended
CLKIN2 Priority.
CLKIN2_PRIO - Clock Priority
0 - Clock Disabled
1 - Priority 1 - Highest
2 - Priority 2
[2:0]
CLKIN2_PRIO[2:0]
RW
0x3
3 - Priority 3
4 - Priority 4 - Lowest
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9.6.2.27 CLKIN3CTRL
The CLKIN3CTRL Register provides control of the CLK3 input path. Back to Register Map.
Table 51. Register - 0x1A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Inverts CLKIN3_PLL1_RDIV.
0=Non-Inverted
[6]
CLKIN3_PLL1_INV
RW
0
1=Inverted
[5]
[4]
CLKIN3_LOS_FRQ_DBL_EN
CLKIN3_EN
RW
RW
0
0
CLKIN3 Loss of Source Frequency Doubler Enable.
CLKIN3 Input Stage Enable. (not clk buffer).
CLKIN3 Signal Mode.
CLKIN3_SE_MODE - Signal Mode Selection
0 - Differential
[3]
CLKIN3_SE_MODE
RW
1
1 - Single-ended
CLKIN3 Priority.
CLKIN3_PRIO - Clock Priority
0 - Clock Disabled
1 - Priority 1 - Highest
2 - Priority 2
[2:0]
CLKIN3_PRIO[2:0]
RW
0x4
3 - Priority 3
4 - Priority 4 - Lowest
9.6.2.28 CLKIN0RDIV_BY1
The CLKIN0 RDIV Values is determined by CLKIN0RDIV_BY1 and CLKIN0RDIV_BY0. Back to Register Map.
Table 52. Register - 0x1B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN0 PLL1 Reference Divider Value.
CLKIN0_PLL1_RDIV - Reference Divider
0 - Reserved
1 - 1
[7:0]
CLKIN0_PLL1_RDIV[15:8]
RW
0x0
.. - ..
65535 - 65535
9.6.2.29 CLKIN0RDIV_BY0
The CLKIN0RDIV_BY0 Register controls the lower 8-bits of the CLKIN0 Reference Divider. Back to Register
Map.
Table 53. Register - 0x1C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN0_PLL1_RDIV[7:0]
RW
0x78
CLKIN0 PLL1 Reference Divider Value.
9.6.2.30 CLKIN1RDIV_BY1
The CLKIN1 RDIV Values is determined by CLKIN1RDIV_BY1 and CLKIN1RDIV_BY0. Back to Register Map.
Table 54. Register - 0x1D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN1 PLL1 Reference Divider Value.
CLKIN1_PLL1_RDIV - Reference Divider
0 - Reserved
1 - 1
[7:0]
CLKIN1_PLL1_RDIV[15:8]
RW
0x0
.. - ..
65535 - 65535
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9.6.2.31 CLKIN1RDIV_BY0
The CLKIN1RDIV_BY0 Register controls the lower 8-bits of the CLKIN1 Reference Divider. Back to Register
Map.
Table 55. Register - 0x1E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN1_PLL1_RDIV[7:0]
RW
0x78
CLKIN1 PLL1 Reference Divider Value.
9.6.2.32 CLKIN2RDIV_BY1
The CLKIN2 RDIV Values is determined by CLKIN2RDIV_BY1 and CLKIN2RDIV_BY0. Back to Register Map.
Table 56. Register - 0x1F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN2 PLL1 Reference Divider Value.
CLKIN2_PLL1_RDIV - Reference Divider
0 - Reserved
1 - 1
[7:0]
CLKIN2_PLL1_RDIV[15:8]
RW
0x0
.. - ..
65535 - 65535
9.6.2.33 CLKIN2RDIV_BY0
The CLKIN2RDIV_BY0 Register controls the lower 8-bits of the CLKIN2 Reference Divider. Back to Register
Map.
Table 57. Register - 0x20
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN2_PLL1_RDIV[7:0]
RW
0x78
CLKIN2 PLL1 Reference Divider Value.
9.6.2.34 CLKIN3RDIV_BY1
The CLKIN3 RDIV Values is determined by CLKIN3RDIV_BY1 and CLKIN3RDIV_BY0. Back to Register Map.
Table 58. Register - 0x21
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN3 PLL1 Reference Divider Value.
CLKIN3_PLL1_RDIV - Reference Divider
0 - Reserved
1 - 1
[7:0]
CLKIN3_PLL1_RDIV[15:8]
RW
0x0
.. - ..
65535 - 65535
9.6.2.35 CLKIN3RDIV_BY0
The CLKIN3RDIV_BY0 Register controls the lower 8-bits of the CLKIN3 Reference Divider. Back to Register
Map.
Table 59. Register - 0x22
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN3_PLL1_RDIV[7:0]
RW
0x78
CLKIN3 PLL1 Reference Divider Value.
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9.6.2.36 CLKIN0LOS_REC_CNT
The CLKIN0LOSCTRL Register sets the CLKIN0 Loss of Source recovery counter value. Back to Register Map.
Table 60. Register - 0x23
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN0 LOS Recovery Counter Value.
CLKIN0_LOS_REC_CNT - Counter Value
0 - 15+0*16
1 - 15+1*16
2 - 15+2*16
3 - 15+3*16
.. - ..
CLKIN0_LOS_REC_CNT[7:0
]
[7:0]
RW
0x14
255 - 15+255*16
9.6.2.37 CLKIN0LOS_LAT_SEL
The CLKIN0LOS_LAT_SEL Register sets the CLKIN0 Loss of Source latency. Back to Register Map.
Table 61. Register - 0x24
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN0_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN0 LOS Max Latency for LOS Detection.
9.6.2.38 CLKIN1LOS_REC_CNT
The CLKIN1LOS_REC_CNT Register sets the CLKIN1 Loss of Source recovery counter value. Back to Register
Map.
Table 62. Register - 0x25
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN1 LOS Recovery Counter Value.
CLKIN1_LOS_REC_CNT - Counter Value
0 - 15+0*16
1 - 15+1*16
2 - 15+2*16
3 - 15+3*16
.. - ..
CLKIN1_LOS_REC_CNT[7:0
]
[7:0]
RW
0x14
255 - 15+255*16
9.6.2.39 CLKIN1LOS_LAT_SEL
The CLKIN1LOS_LAT_SEL Register sets the CLKIN1 Loss of Source latency. Back to Register Map.
Table 63. Register - 0x26
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN1_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN1 LOS Max Latency for LOS Detection.
74
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9.6.2.40 CLKIN2LOS_REC_CNT
The CLKIN2LOS_REC_CNT Register sets the CLKIN2 Loss of Source recovery counter value. Back to Register
Map.
Table 64. Register - 0x27
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN2 LOS Recovery Counter Value.
CLKIN2_LOS_REC_CNT - Counter Value
0 - 15+0*16
1 - 15+1*16
2 - 15+2*16
3 - 15+3*16
.. - ..
CLKIN2_LOS_REC_CNT[7:0
]
[7:0]
RW
0x14
255 - 15+255*16
9.6.2.41 CLKIN2LOS_LAT_SEL
The CLKIN2LOS_LAT_SEL Register sets the CLKIN2 Loss of Source latency. Back to Register Map.
Table 65. Register - 0x28
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN2_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN2 LOS Max Latency for LOS Detection.
9.6.2.42 CLKIN3LOS_REC_CNT
The CLKIN3LOS_REC_CNT Register sets the CLKIN3 Loss of Source recovery counter value. Back to Register
Map.
Table 66. Register - 0x29
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN3 LOS Recovery Counter Value.
CLKIN3_LOS_REC_CNT - Counter Value
0 - 15+0*16
1 - 15+1*16
2 - 15+2*16
3 - 15+3*16
.. - ..
CLKIN3_LOS_REC_CNT[7:0
]
[7:0]
RW
0x14
255 - 15+255*16
9.6.2.43 CLKIN3LOS_LAT_SEL
The CLKIN3LOS_LAT_SEL Register sets the CLKIN3 Loss of Source latency. Back to Register Map.
Table 67. Register - 0x2A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN3_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN3 LOS Max Latency for LOS Detection.
9.6.2.44 CLKIN_SWCTRL0
The CLKIN_SWCTRL0 Register provides control of the input settling time after switching to another Ref channel
for Loss Of Signal Inspection. Back to Register Map.
Table 68. Register - 0x2B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
Wait Time for a Valid LOS Detection. Used during Priority
Switching in Auto CLKin selection mode.
[4:0]
SW_CLKLOS_TMR[4:0]
RW
0x0
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9.6.2.45 CLKIN_SWCTRL1
The CLKIN_SWCTRL1 Register provides control of the Loss Of Signal Channel select. Back to Register Map.
Table 69. Register - 0x2C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Software Mode Reference Input Select.
SW_REFINSEL - Input Selected
0001 - CLKIN0
[7:4]
SW_REFINSEL[3:0]
RW
0x0
0010 - CLKIN1
0100 - CLKIN2
1000 - CLKIN3
Loss of Source Channel Select.
SW_LOS_CH_SEL - Input Selected
0001 - CLKIN0
[3:0]
SW_LOS_CH_SEL[3:0]
RW
0x0
0010 - CLKIN1
0100 - CLKIN2
1000 - CLKIN3
9.6.2.46 CLKIN_SWCTRL2
The CLKIN_SWCTRL2 Register provides control of the input stage settling time when switching on all inputs in
case of Loss Of Signal. Back to Register Map.
Table 70. Register - 0x2D
BIT NO.
[7:5]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[4:0]
SW_ALLREFSON_TMR[4:0]
RW
0x0
Wait Time to allow Clock Inputs to Settle.
9.6.2.47 OSCIN_CTRL
The OSCIN_CTRL Register provides control of the OSCIN signal path. Back to Register Map.
Table 71. Register - 0x2E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
OSCIN LDO Powerdown.
OSCIN_PD_LDO - LDO State
0 - LDO On
[5]
OSCIN_PD_LDO
RW
0
1 - LDO Off
OSCin Signal Mode.
OSCIN_SE_MODE - Signal Mode Selection
0 - Differential
[4]
[3]
OSCIN_SE_MODE
RW
RW
1
1
1 - Single-ended
OSCIN_BUF_TO_OSCOUT_
EN
OSCin to OSCout Buffer Enable.
[2]
[1]
[0]
OSCIN_OSCINSTAGE_EN
OSCIN_BUF_REF_EN
OSCIN_BUF_LOS_EN
RW
RW
RW
1
0
0
OSCin Clock Input Stage Enable.
OSCin to PLL1 and PLL2 Ref Clock Buffer Enable.
OSCin to LOS Clock Buffer Enable.
9.6.2.48 OSCOUT_CTRL
The OSCOUT_CTRL Register controls the OSCOUT Function. Back to Register Map.
Table 72. Register - 0x2F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OSCOUT_LVCMOS_WEAK_
DRIVE
[7]
RW
0
Enable OSCOUT LVCMOS weak drive.
76
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Table 72. Register - 0x2F (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OSCOUT_DIV_REGCONTR
OL
Enable OSCOUT Divider setting through configuration
register rather than SYNC pin control.
[6]
RW
0
OSCOUT pin-selected Divider.
OSCOUT_PINSEL_DIV - Pin-Selected Oscout Divider ratio
00 - 1
01 - 2
10 - 2
11 - 4
[5:4]
OSCOUT_PINSEL_DIV[1:0]
R
0x0
OSCOUT Bandgap Source Select. When
OSCOUT_SEL_VBG is 0 the PLL1 Bandgap is used for
OSCOUT. If OSCOUT_SEL_VBG is 1 the Output Channel
Bandgap is used.
[3]
OSCOUT_SEL_VBG
RW
0
[2]
[1]
OSCOUT_DIV_CLKEN
OSCOUT_SWRST
RW
1
0
OSCout Divider Clock Enable. (RESERVED for PG1p0)
OSCOUT Software Reset. Writing a 1 to OSCOUT_SWRST
will reset the OSCOUT Block. The OSCOUT_SWRST is
cleared automatically to 0.
RWSC
OSCout Clock source select.
OSCOUT_SEL_SRC - Clock Source
0 - PLL2 Output
[0]
OSCOUT_SEL_SRC
RW
1
1 - OSCin
9.6.2.49 OSCOUT_DIV
The OSCOUT_DIV Register controls the OSCOUT Divider Back to Register Map.
Table 73. Register - 0x30
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OSCOUT_DIV[7:0]
RW
0x0
OSCOUT Divider. Set value of OSCOUT channel divider.
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9.6.2.50 OSCOUT_DRV
The OSCOUT_DRV Register controls the OSCOUT Driver. Back to Register Map.
Table 74. Register - 0x31
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OSCOUT Driver Mute Control. OSCOUT_DRV_MUTE sets
the OSCOUT driver mute input after the internal reset has
been de-asserted. During the reset sequence the mute input
is set to 11. It is configured together with
OSCOUT_DRV_MODE.
OSCOUT_DRV_MUTE,OSCOUT_DRV_MODE - Output
State
00,XXXXXX - OSCOUT Driver is Active
01,11XXXX - OSCOUT_P operating normal, OSCOUT_N
Low
01,01XXXX - OSCOUT_P operating normal, OSCOUT_N
Operating normal
01,10XX00 - OSCOUT_P High, OSCOUT_N High
01,10XX01 - OSCOUT_P operating normal, OSCOUT_N
operating normal
01,10XX10 - OSCOUT_P operating normal, OSCOUT_N
operating normal
[7:6]
OSCOUT_DRV_MUTE[1:0]
RW
0x0
01,10XX11 - OSCOUT_P operating normal, OSCOUT_N
operating normal
10,11XXXX - OSCOUT_P Low, OSCOUT_N operating
normal
10,01XXXX - OSCOUT_P Low, OSCOUT_N High
10,10XX00 - OSCOUT_P High, OSCOUT_N High
10,10XX01 - OSCOUT_P Low, OSCOUT_N High
10,10XX10 - OSCOUT_P Low, OSCOUT_N High
10,10XX11 - OSCOUT_P Low, OSCOUT_N High
11,11XXXX - OSCOUT_P Low, OSCOUT_N Low
11,01XXXX - OSCOUT_P Low, OSCOUT_N High
11,10XX00 - OSCOUT_P High, OSCOUT_N High
11,10XX01 - OSCOUT_P Low, OSCOUT_N High
11,10XX10 - OSCOUT_P Low, OSCOUT_N High
11,10XX11 - OSCOUT_P Low, OSCOUT_N High
OSCOUT Driver Mode.
OSCOUT_DRV_MODE - Output stage configuration
00XXXX - Power Down
01XXXX - HSDS Mode
10XXXX - HSCL Mode
11XXXX - LVCMOS Mode
XX00XX - HSDS, HSCL: ITail: 4mA, LVCMOS: OSCOUT_P
tristate
XX01XX - HSDS, HSCL: ITail: 6mA, LVCMOS: OSCOUT_P
Weak Drive
XX10XX - HSDS, HSCL: ITail: 8mA, LVCMOS: OSCOUT_P
Normal Drive Inverted
[5:0]
OSCOUT_DRV_MODE[5:0]
RW
0x3F
XX11XX - ITail HSDS: 8mA, HSCL: 16mA, LVCMOS:
OSCOUT_P Normal Drive Non-Inverted
XXXX00 - Rload HSDS: open, HSCL: open, LVCMOS:
OSCOUT_N tristate
XXXX01 - Rload HSDS: open, HSCL: 50Ohm, LVCMOS:
OSCOUT_N Weak Drive
XXXX10 - Rload HSDS: open, HSCL: 100Ohm for Itail=4mA,
6mA, 8mA, LVCMOS: OSCOUT_N Normal Drive Inverted
XXXX11 - Rload HSDS: open, HSCL: 200Ohm for Itail=4mA,
LVCMOS: OSCOUT_N Normal Drive Non-Inverted
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9.6.2.51 OUTCH_SWRST
The OUTCH_SWRST Register allows software reset to applied independently to each output channel. Back to
Register Map.
Table 75. Register - 0x32
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CH1415 Software Reset. Writing a 1 to CH1415_SWRST will
[7]
CH1415_SWRST
RWSC
0
reset CH1415. CH1415_SWRST is cleared automatically to
0.
CH1213 Software Reset. Writing a 1 to CH1213_SWRST will
[6]
[5]
CH1213_SWRST
CH1011_SWRST
RWSC
RWSC
0
0
reset CH1213. CH1213_SWRST is cleared automatically to
0.
CH1011 Software Reset. Writing a 1 to CH1011_SWRST will
reset CH1011. CH1011_SWRST is cleared automatically to
0.
CH89 Software Reset. Writing a 1 to CH89_SWRST will
reset CH89. CH89_SWRST is cleared automatically to 0.
[4]
[3]
[2]
[1]
[0]
CH89_SWRST
CH67_SWRST
CH45_SWRST
CH23_SWRST
CH01_SWRST
RWSC
RWSC
RWSC
RWSC
RWSC
0
0
0
0
0
CH67 Software Reset. Writing a 1 to CH67_SWRST will
reset CH67. CH67_SWRST is cleared automatically to 0.
CH45 Software Reset. Writing a 1 to CH45_SWRST will
reset CH45. CH45_SWRST is cleared automatically to 0.
CH23 Software Reset. Writing a 1 to CH23_SWRST will
reset CH23. CH23_SWRST is cleared automatically to 0.
CH01 Software Reset. Writing a 1 to CH01_SWRST will
reset CH01. CH01_SWRST is cleared automatically to 0.
9.6.2.52 OUTCH01CNTL0
The OUTCH01CNTRL0 Register controls Output CH0_1 Back to Register Map.
Table 76. Register - 0x33
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH01 LDO Bypass.
OUTCH01_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH01_LDO_BYP_MOD
E
[7]
RW
0
1 - Bypassed
OUTCH01 LDO Mask. If OUTCH01_LDO_MASK is 1 then
CH01 LDO is masked from the Power Up Sequence and
enabled directly.
[6]
OUTCH01_LDO_MASK
RW
RW
0
OUTCH0 Clock Driver Mode Setting.
OUTCH_DRIV_MODE - Function
00XXXX - Power Down
010000 - HSDS, Itail 4mA, RLoad 25 Ohm
010100 - HSDS, Itail 6mA, RLoad 25 Ohm
011000 - HSDS, Itail 8mA, RLoad 25 Ohm
111011 - HCSL, Itail 8mA, RLoad open
111111 - HCSL, Itail 16mA, RLoad open
111001 - HCSL, Itail 8mA, RLoad 50 Ohm
111101 - HCSL, Itail 16mA, RLoad 50 Ohm
[5:0]
OUTCH0_DRIV_MODE[5:0]
0x18
9.6.2.53 OUTCH01CNTL1
The OUTCH01CNTRL1 Register controls Output CH0_1 Back to Register Map.
Table 77. Register - 0x34
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
1
DESCRIPTION
OUTCH1_DRIV_MODE[5:0]
DIV_DCC_EN_CH0_1
OUTCH1 Clock Driver Mode Setting.
Output CH0_1 Divier Duty Cycle Correction Enable
[1]
RW
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Table 77. Register - 0x34 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH01 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH01_DIV_CLKEN
RW
1
9.6.2.54 OUTCH23CNTL0
The OUTCH23CNTL0 Register controls Output CH2_3 Back to Register Map.
Table 78. Register - 0x35
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH23 LDO Bypass.
OUTCH23_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH23_LDO_BYP_MOD
E
[7]
RW
0
1 - Bypassed
OUTCH23 LDO Mask. If OUTCH23_LDO_MASK is 1 then
CH23 LDO is masked from the Power Sequence.
[6]
OUTCH23_LDO_MASK
RW
RW
0
OUTCH2 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH2_DRIV_MODE[5:0]
0x18
9.6.2.55 OUTCH23CNTL1
The OUTCH23CNTRL1 Register controls Output CH2_3 Back to Register Map.
Table 79. Register - 0x36
BIT NO.
[7:2]
[1]
FIELD
TYPE
RESET
DESCRIPTION
OUTCH3 Clock Driver Mode Setting. See CHANNEL0 for
description.
OUTCH3_DRIV_MODE[5:0]
DIV_DCC_EN_CH2_3
OUTCH23_DIV_CLKEN
RW
0x18
RW
1
1
Output CH2_3 Divider Duty Cycle Correction Enable
OUTCH23 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
RW
9.6.2.56 OUTCH45CNTL0
The OUTCH45CNTRL0 Register controls Output CH4_5 Back to Register Map.
Table 80. Register - 0x37
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH45 LDO Bypass.
OUTCH45_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH45_LDO_BYP_MOD
E
[7]
RW
0
1 - Bypassed
OUTCH45 LDO Mask. If OUTCH45_LDO_MASK is 1 then
CH45 LDO is masked from the Power Sequence.
[6]
OUTCH45_LDO_MASK
RW
RW
0
OUTCH4 Clock Driver Mode Setting. See OUTCH0 for
description.
[5:0]
OUTCH4_DRIV_MODE[5:0]
0x18
9.6.2.57 OUTCH45CNTL1
The OUTCH45CNTRL1 Register controls Output CH4_5 Back to Register Map.
Table 81. Register - 0x38
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
1
DESCRIPTION
OUTCH5_DRIV_MODE[5:0]
DIV_DCC_EN_CH4_5
OUTCH5 Clock Driver Mode Setting.
[1]
RW
Output CH4_5 Divider Duty Cycle Correction Enable
OUTCH45 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH45_DIV_CLKEN
RW
1
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9.6.2.58 OUTCH67CNTL0
The OUTCH67CNTRL0 Register controls Output CH6_7 Back to Register Map.
Table 82. Register - 0x39
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH67 LDO Bypass.
OUTCH67_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH67_LDO_BYP_MOD
E
[7]
RW
0
1 - Bypassed
OUTCH67 LDO Mask. If OUTCH67_LDO_MASK is 1 then
CH67 LDO is masked from the Power Sequence.
[6]
OUTCH67_LDO_MASK
RW
RW
0
OUTCH6 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH6_DRIV_MODE[5:0]
0x18
9.6.2.59 OUTCH67CNTL1
The OUTCH67CNTRL1 Register controls Output CH6_7 Back to Register Map.
Table 83. Register - 0x3A
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
0
DESCRIPTION
OUTCH7_DRIV_MODE[5:0]
DIV_DCC_EN_CH6_7
OUTCH7 Clock Driver Mode Setting.
[1]
RW
Output CH6_7 Divider Duty Cycle Correction Enable
OUTCH67 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH67_DIV_CLKEN
RW
1
9.6.2.60 OUTCH89CNTL0
The OUTCH89CNTRL0 Register controls Output CH8_9 Back to Register Map.
Table 84. Register - 0x3B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH89 LDO Bypass.
OUTCH89_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH89_LDO_BYP_MOD
E
[7]
RW
0
1 - Bypassed
OUTCH89 LDO Mask. If OUTCH89_LDO_MASK is 1 then
CH89 LDO is masked from the Power Sequence.
[6]
OUTCH89_LDO_MASK
RW
RW
0
OUTCH8 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH8_DRIV_MODE[5:0]
0x18
9.6.2.61 OUTCH89CNTL1
The OUTCH89CNTRL1 Register controls Output CH8_9 Back to Register Map.
Table 85. Register - 0x3C
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
0
DESCRIPTION
OUTCH9_DRIV_MODE[5:0]
DIV_DCC_EN_CH8_9
OUTCH9 Clock Driver Mode Setting.
[1]
RW
Output CH8_9 Divider Duty Cycle Correction Enable
OUTCH89 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH89_DIV_CLKEN
RW
1
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9.6.2.62 OUTCH1011CNTL0
The OUTCH1011CNTRL0 Register controls Output CH10_11 Back to Register Map.
Table 86. Register - 0x3D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1011 LDO Bypass.
OUTCH1011_LDO_BYP_MODE - LDO State
OUTCH1011_LDO_BYP_MO
DE
[7]
RW
0
0 - Enabled
1 - Bypassed
OUTCH1011 LDO Mask. If OUTCH1011_LDO_MASK is 1
then CH1011 LDO is masked from the Power Sequence.
[6]
OUTCH1011_LDO_MASK
RW
RW
0
OUTCH10 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH10_DRIV_MODE[5:0]
0x18
9.6.2.63 OUTCH1011CNTL1
The OUTCH1011CNTRL1 Register controls Output CH10_11 Back to Register Map.
Table 87. Register - 0x3E
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
0
DESCRIPTION
OUTCH11_DRIV_MODE[5:0]
DIV_DCC_EN_CH10_11
OUTCH11 Clock Driver Mode Setting.
[1]
RW
Output CH10_11 Divider Duty Cycle Correction Enable
OUTCH1011 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH1011_DIV_CLKEN
RW
1
9.6.2.64 OUTCH1213CNTL0
The OUTCH1213CNTRL0 Register controls Output CH12_13 Back to Register Map.
Table 88. Register - 0x3F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1213 LDO Bypass.
OUTCH1213_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH1213_LDO_BYP_MO
DE
[7]
RW
0
1 - Bypassed
OUTCH1213 LDO Mask. If OUTCH1213_LDO_MASK is 1
then CH1213 LDO is masked from the Power Sequence.
[6]
OUTCH1213_LDO_MASK
RW
RW
0
OUTCH12 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH12_DRIV_MODE[5:0]
0x18
9.6.2.65 OUTCH1213CNTL1
The OUTCH1213CNTRL1 Register controls Output CH12_13 Back to Register Map.
Table 89. Register - 0x40
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
0
DESCRIPTION
OUTCH13_DRIV_MODE[5:0]
DIV_DCC_EN_CH12_13
OUTCH13 Clock Driver Mode Setting.
[1]
RW
Output CH12_13 Divider Duty Cycle Correction Enable
OUTCH1213 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH1213_DIV_CLKEN
RW
1
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9.6.2.66 OUTCH1415CNTL0
The OUTCH1415CNTRL0 Register controls Output CH14_15 Back to Register Map.
Table 90. Register - 0x41
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1415 LDO Bypass.
OUTCH1415_LDO_BYP_MODE - LDO State
0 - Enabled
OUTCH1415_LDO_BYP_MO
DE
[7]
RW
0
1 - Bypassed
OUTCH1415 LDO Mask. If OUTCH1415_LDO_MASK is 1
then CH1415 LDO is masked from the Power Sequence.
[6]
OUTCH1415_LDO_MASK
RW
RW
0
OUTCH14 Clock Driver Mode Setting. See CHANNEL0 for
description.
[5:0]
OUTCH14_DRIV_MODE[5:0]
0x18
9.6.2.67 OUTCH1415CNTL1
The OUTCH1415CNTRL1 Register controls Output CH14_15 Back to Register Map.
Table 91. Register - 0x42
BIT NO.
[7:2]
FIELD
TYPE
RW
RESET
0x18
0
DESCRIPTION
OUTCH15_DRIV_MODE[5:0]
DIV_DCC_EN_CH14_15
OUTCH15 Clock Driver Mode Setting.
[1]
RW
Output CH14_15 Divider Duty Cycle Correction Enable
OUTCH1415 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH1415_DIV_CLKEN
RW
1
9.6.2.68 OUTCH01DIV_BY1
The OUTCH01DIV_BY1,BY0 Registers set the OUTCH01 Divider Value. Back to Register Map.
Table 92. Register - 0x43
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH01 Divider Value. Sets the divider value for output
channels 0 and 1. An automatic reset is issued whenever the
divider value is changed.
[7:0]
OUTCH01_DIV[15:8]
RW
0x0
9.6.2.69 OUTCH01DIV_BY0
The OUTCH01DIV_BY0 Register sets the lower 7 bits of the OUTCH01 Divider Value. Back to Register Map.
Table 93. Register - 0x44
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH01_DIV[7:0]
RW
0x1
OUTCH01 Divider Value.
9.6.2.70 OUTCH23DIV_BY1
The OUTCH23DIV_BY1,BY0 Registers set the OUTCH23 Divider Value. Back to Register Map.
Table 94. Register - 0x45
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH23 Divider Value. Sets the divider value for output
channels 2 and 3. An automatic reset is issued whenever the
divider value is changed.
[7:0]
OUTCH23_DIV[15:8]
RW
0x0
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9.6.2.71 OUTCH23DIV_BY0
The OUTCH23DIV_BY0 Register sets the lower 7 bits of the OUTCH23 Divider Value. Back to Register Map.
Table 95. Register - 0x46
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH23_DIV[7:0]
RW
0x2
OUTCH23 Divider Value.
9.6.2.72 OUTCH45DIV_BY1
The OUTCH45DIV_BY1,BY0 Registers set the OUTCH45 Divider Value. Back to Register Map.
Table 96. Register - 0x47
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH45 Divider Value. Sets the divider value for output
channels 4 and 5. An automatic reset is issued whenever the
divider value is changed.
[7:0]
OUTCH45_DIV[15:8]
RW
0x0
9.6.2.73 OUTCH45DIV_BY0
The OUTCH45DIV_BY0 Register sets the lower 7 bits of the OUTCH45 Divider Value. Back to Register Map.
Table 97. Register - 0x48
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH45_DIV[7:0]
RW
0x8
OUTCH45 Divider Value.
9.6.2.74 OUTCH67DIV_BY1
The OUTCH67DIV_BY1,BY0 Registers set the OUTCH67 Divider Value. Back to Register Map.
Table 98. Register - 0x49
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH67 Divider Value. Sets the divider value for output
channels 6 and 7. An automatic reset is issued whenever the
divider value is changed.
[7:0]
OUTCH67_DIV[15:8]
RW
0x0
9.6.2.75 OUTCH67DIV_BY0
The OUTCH67DIV_BY0 Register sets the lower 7 bits of the OUTCH67 Divider Value. Back to Register Map.
Table 99. Register - 0x4A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH67_DIV[7:0]
RW
0x20
OUTCH67 Divider Value.
9.6.2.76 OUTCH89DIV_BY1
The OUTCH89DIV_BY1,BY0 Registers set the OUTCH89 Divider Value. Back to Register Map.
Table 100. Register - 0x4B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH89 Divider Value. Sets the divider value for output
channels 8 and 9. An automatic reset is issued whenever the
divider value is changed.
[7:0]
OUTCH89_DIV[15:8]
RW
0x0
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9.6.2.77 OUTCH89DIV_BY0
The OUTCH89DIV_BY0 Register sets the lower 7 bits of the OUTCH89 Divider Value. Back to Register Map.
Table 101. Register - 0x4C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH89_DIV[7:0]
RW
0x3
OUTCH89 Divider Value.
9.6.2.78 OUTCH1011DIV_BY1
The OUTCH1011DIV_BY1,BY0 Registers set the OUTCH1011 Divider Value. Back to Register Map.
Table 102. Register - 0x4D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1011 Divider Value. Sets the divider value for output
channels 10 and 11. An automatic reset is issued whenever
the divider value is changed.
[7:0]
OUTCH1011_DIV[15:8]
RW
0x0
9.6.2.79 OUTCH1011DIV_BY0
The OUTCH1011DIV_BY0 Register sets the lower 7 bits of the OUTCH1011 Divider Value. Back to Register
Map.
Table 103. Register - 0x4E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH1011_DIV[7:0]
RW
0x5
OUTCH1011 Divider Value.
9.6.2.80 OUTCH1213DIV_BY1
The OUTCH1213DIV_BY1,BY0 Registers set the OUTCH1213 Divider Value. Back to Register Map.
Table 104. Register - 0x4F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1213 Divider Value. Sets the divider value for output
channels 12 and 13. An automatic reset is issued whenever
the divider value is changed.
[7:0]
OUTCH1213_DIV[15:8]
RW
0x0
9.6.2.81 OUTCH1213DIV_BY0
The OUTCH1213DIV_BY0 Register sets the lower 7 bits of the OUTCH1213 Divider Value. Back to Register
Map.
Table 105. Register - 0x50
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH1213_DIV[7:0]
RW
0x9
OUTCH1213 Divider Value.
9.6.2.82 OUTCH1415DIV_BY1
The OUTCH1415DIV_BY1,BY0 Registers set the OUTCH1415 Divider Value. Back to Register Map.
Table 106. Register - 0x51
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1415 Divider Value. Sets the divider value for output
channels 14 and 15. An automatic reset is issued whenever
the divider value is changed.
[7:0]
OUTCH1415_DIV[15:8]
RW
0x0
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9.6.2.83 OUTCH1415DIV_BY0
The OUTCH1415DIV_BY0 Register sets the lower 7 bits of the OUTCH1415 Divider Value. Back to Register
Map.
Table 107. Register - 0x52
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH1415_DIV[7:0]
RW
0x1F
OUTCH1415 Divider Value.
9.6.2.84 OUTCH_DIV_INV
The OUTCH_DIV_INV Register controls inversion of the dividier output clock. Back to Register Map.
Table 108. Register - 0x53
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1415 Divider Output Invert. When
OUTCH1415_DIV_INV is 1 the divider output for channels
14 and 15 is inverted.
[7]
OUTCH1415_DIV_INV
RW
0
OUTCH1213 Divider Output Invert. When
OUTCH1213_DIV_INV is 1 the divider output for channels
12 and 13 is inverted.
[6]
[5]
OUTCH1213_DIV_INV
OUTCH1011_DIV_INV
RW
RW
0
0
OUTCH1011 Divider Output Invert. When
OUTCH1011_DIV_INV is 1 the divider output for channels
10 and 11 is inverted.
OUTCH89 Divider Output Invert. When OUTCH89_DIV_INV
is 1 the divider output for channels 8 and 9 is inverted.
[4]
[3]
[2]
[1]
[0]
OUTCH89_DIV_INV
OUTCH67_DIV_INV
OUTCH45_DIV_INV
OUTCH23_DIV_INV
OUTCH01_DIV_INV
RW
RW
RW
RW
RW
0
0
0
0
0
OUTCH67 Divider Output Invert. When OUTCH67_DIV_INV
is 1 the divider output for channels 6 and 7 is inverted.
OUTCH45 Divider Output Invert. When OUTCH45_DIV_INV
is 1 the divider output for channels 4 and 5 is inverted.
OUTCH23 Divider Output Invert. When OUTCH23_DIV_INV
is 1 the divider output for channels 2 and 3 is inverted.
OUTCH01 Divider Output Invert. When OUTCH01_DIV_INV
is 1 the divider output for channels 0 and 1 is inverted.
9.6.2.85 PLL1CTRL0
The PLL1CTRL0 Register provides control of the following PLL1 related features. Back to Register Map.
Table 109. Register - 0x54
BIT NO.
[7]
FIELD
PLL1_F_30
TYPE
RESET
DESCRIPTION
PLL1 RC Freq 0 = 122 MHz 1 = 32MHz.
PLL1_F_30 - PLL1 RC Frequency
0 - 122 MHz
RW
0
0
1
1 - 32 MHz
[6]
PLL1_EN_REGULATION
PLL1_PD_LD
RW
PLL1 Prop-CP Enable Regulation
PLL1 Window Comparator Powerdown.
PLL1_PD_LD - PLL1 Window Comparator
0 - Enabled
[5]
RW
1 - Off
PLL1 VCXO pos/neg Gain.
PLL1_DIR_POS_GAIN - Polarity
0 - Positive
[4]
PLL1_DIR_POS_GAIN
RW
RW
1
1 - Negative
PLL1 LDO Wait Timer. The PLL1 LDO Wait Timer counts a
number of clock cycles equal to
32*(PLL1_LDO_WAIT_TMR+31) before releasing the PLL1
NDIV and RDIV resets.
[3:0]
PLL1_LDO_WAIT_TMR[3:0]
0x0
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9.6.2.86 PLL1CTRL1
The PLL1CTRL1 Register provides control over PLL1 related features. Back to Register Map.
Table 110. Register - 0x55
BIT NO.
[7]
FIELD
TYPE
RW
RESET
DESCRIPTION
PLL1 Lock Detect counter multiply with 32.
PLL1 Fast Lock Enable.
PLL1_LCKDET_BY_32
PLL1_FAST_LOCK
0
1
[6]
RW
PLL1 Lock Detect LOS Mask. When
PLL1_LCKDET_LOS_MASK is 1 then Loss of Source has no
effect on the PLL1 Lock Detect circuit.
[5]
PLL1_LCKDET_LOS_MASK
RW
0
PLL1 Feedback Clock Inversion. When PLL1_FBCLK_INV is
1 then the Feedback Clock divider output is inverted.
[4]
[3]
PLL1_FBCLK_INV
RSRVD
RW
-
1
-
Reserved.
PLL1 Bypass Loss of Source indication. When
PLL1_BYP_LOS is 1 the PLL1 controller ignores the LOS
indicator.
[2]
PLL1_BYP_LOS
RW
0
[1]
[0]
PLL1_PFD_UP_HOLDOVER
RW
RW
0
0
PLL1 PFD UP-Input value during Holdover.
PLL1_PFD_DOWN_HOLDO
VER
PLL1 PFD DN-Input value during Holdover.
9.6.2.87 PLL1CTRL2
The PLL1CTRL2 Register provides control over PLL1 related features. Back to Register Map.
Table 111. Register - 0x56
BIT NO.
[7:5]
[4]
FIELD
TYPE
-
RESET
DESCRIPTION
Reserved.
RSRVD
-
PLL1_LOL_NORESET
PLL1_RDIV_CLKEN
RW
RW
0
1
If set to 1, PLL1 will not be reset on a Loss-of-Lock event.
PLL1 RDIV Clock Enable.
[3]
PLL1 RDIV Enable tied clock low phase to 4cycs.
Independent from divider setting.
[2]
[1]
[0]
PLL1_RDIV_4CY
PLL1_NDIV_CLKEN
PLL1_NDIV_4CY
RW
RW
RW
1
1
1
PLL1 NDIV Clock Enable
PLL1 NDIV Enable tied clock low phase to 4cycs.
Independent from divider setting.
9.6.2.88 PLL1_SWRST
The PLL1_SWRST Register provides control of the PLL1 software reset's Back to Register Map.
Table 112. Register - 0x57
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
PLL1 Holdover DLD Software Reset. Writing a 1 to
PLL1_HOLDOVER_DLD_SWRST will activate the reset.
PLL1_HOLDOVER_DLD_SWRST is cleared automatically to
0.
PLL1_HOLDOVER_DLD_SW
RST
[5]
RWSC
0
PLL1 R-Divider Software Reset. Writing a 1 to
PLL1_RDIV_SWRST will reset the R-Divider.
PLL1_RDIV_SWRST is cleared automatically to 0.
[4]
[3]
PLL1_RDIV_SWRST
PLL1_NDIV_SWRST
RWSC
RWSC
0
0
PLL1 N-Divider Software Reset. Writing a 1 to
PLL1_NDIV_SWRST will reset the N-Divider.
PLL1_NDIV_SWRST is cleared automatically to 0.
PLL1 Holdover Counter Software Reset. Writing a 1 to
PLL1_HOLDOVERCNT_SWRST will activate the reset.
PLL1_HOLDOVERCNT_SWRST is cleared automatically to
0.
PLL1_HOLDOVERCNT_SW
RST
[2]
RWSC
0
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Table 112. Register - 0x57 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1 Holdover Lock Detect Software Reset. Writing a 1 to
PLL1_HOLDOVER_LOCKDET_SWRST will activate the
reset. PLL1_HOLDOVER_LOCKDET_SWRST is cleared
automatically to 0.
PLL1_HOLDOVER_LOCKDE
T_SWRST
[1]
RWSC
0
PLL1 Software Reset. Writing a 1 to PLL1_SWRST will reset
PLL1 PLL1_SWRST is cleared automatically to 0.
[0]
PLL1_SWRST
RWSC
0
9.6.2.89 PLL1WNDWSIZE
The PLL1WNDWSIZE Register sets the PLL1 Window Comparator Size. Back to Register Map.
Table 113. Register - 0x58
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_LD_WNDW_SIZE[7:0]
RW
0x3F
PLL1 Window Comparator Size.
9.6.2.90 PLL1STRCELL
The PLL1STRCELL Register provides control of the Storage Cell settings. Back to Register Map.
Table 114. Register - 0x59
BIT NO.
[7:4]
FIELD
TYPE
RW
RESET
0x1
DESCRIPTION
PLL1_INTG_FL[3:0]
PLL1_INTG[3:0]
PLL1 Integral Gain setting during Fast Lock.
PLL1 Integral Gain setting.
[3:0]
RW
0x1
9.6.2.91 PLL1CPSETTING
The PLL1CPSETTING Register provides control of the Chargepump Current/Bandwidth Setting. Back to Register
Map.
Table 115. Register - 0x5A
BIT NO.
[7]
FIELD
RSRVD
TYPE
RW
RESET
0x0
DESCRIPTION
Reserved.
[6:0]
PLL1_PROP[6:0]
RW
0x8
Prop-CP Current/Bandwidth Setting.
9.6.2.92 PLL1CPSETTING_FL
The PLL1CPSETTING_FL Register provides control of the Chargepump Current/Bandwidth Setting during Fast
Lock. Back to Register Map.
Table 116. Register - 0x5B
BIT NO.
[7]
FIELD
RSRVD
TYPE
RW
RESET
0x1
DESCRIPTION
Reserved
[6:0]
PLL1_PROP_FL[6:0]
RW
0x7F
Prop-CP Current/Bandwidth Setting for Fast Lock.
9.6.2.93 PLL1_HOLDOVER_CTRL1
The PLL1_HOLDOVER_CTRL1 Register provides control of the PLL1 holdover operation. Back to Register Map.
Table 117. Register - 0x5C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Enable PLL1 Holdover function. When
PLL1_HOLDOVER_EN is 1 the holdover circuit is enabled.
When PLL1_HOLDOVER_EN is 0 the holdover circuit is
disabled.
[7]
PLL1_HOLDOVER_EN
RW
1
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Table 117. Register - 0x5C (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_STARTUP_HOLDOVE
R_EN
When PLL1_HOLDOVER_FORCE is 1, PLL1 enters
holdover mode immediately on startup.
[6]
RW
1
PLL1 Force Holdover Operation. When
PLL1_HOLDOVER_FORCE is 1 PLL1 enters holdover mode
regardless of other conditions.
[5]
[4]
PLL1_HOLDOVER_FORCE
RW
RW
0
0
PLL1 Rail Detection Level Relative or absolute.
PLL1_HOLDOVER_RAIL_MODE - Level Mode
0 - Absolute-Level
PLL1_HOLDOVER_RAIL_M
ODE
1 - Relative to Level set at Lock
PLL1 Holdover Max Counter enable. Wait for
PLL1_HOLDOVER_MAXCNT cycles before starting Auto-
CLKin-Switch procedure.
PLL1_HOLDOVER_MAX_CN
T_EN
[3]
[2]
[1]
RW
RW
RW
1
0
1
PLL1 Holdover LOS Mask. When
PLL1_HOLDOVER_LOS_MASK is 1 then Loss of Source
has no effect in the activation of holdover.
PLL1_HOLDOVER_LOS_MA
SK
PLL1 Holdover Lock Detect Mask. When
PLL1_HOLDOVER_LCKDET_MASK is 1 then Lock Detect
has no effect in the activation of holdover.
PLL1_HOLDOVER_LCKDET
_MASK
PLL1 Holdover Rail Detection Enable. When
PLL1_HOLDOVER_RAILDET_EN is 1 the rail detection
circuit is enabled. When PLL1_HOLDOVER_RAILDET EN is
0 the rail detection circuit is disabled.
PLL1_HOLDOVER_RAILDE
T_EN
[0]
RW
0
9.6.2.94 PLL1_HOLDOVER_MAXCNT_BY3
The PLL1_HOLDOVER_MAXCNT field is set by PLL1_HOLDOVER_MAXCNT_BY3,BY2,BY1 and BY0. Back to
Register Map.
Table 118. Register - 0x5D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1 Maximum Holdover Count. When the value specified
by PLL1_HOLDOVER_MAX_CNT is reached then the
device will attempt to switch to any available reference
clocks.
PLL1_HOLDOVER_MAX_CN
T[31:24]
[7:0]
RW
0x0
9.6.2.95 PLL1_HOLDOVER_MAXCNT_BY2
The PLL1_HOLDOVER_MAXCNT1 Register sets bits [23:16] Back to Register Map.
Table 119. Register - 0x5E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_HOLDOVER_MAX_CN
T[23:16]
[7:0]
RW
0x1
PLL1 Maximum Holdover Count.
9.6.2.96 PLL1_HOLDOVER_MAXCNT_BY1
The PLL1_HOLDOVER_MAXCNT0 Register sets bits [15:8] Back to Register Map.
Table 120. Register - 0x5F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_HOLDOVER_MAX_CN
T[15:8]
[7:0]
RW
0x84
PLL1 Maximum Holdover Count.
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9.6.2.97 PLL1_HOLDOVER_MAXCNT_BY0
The PLL1_HOLDOVER_MAXCNT0 Register sets bits [7:0] Back to Register Map.
Table 121. Register - 0x60
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_HOLDOVER_MAX_CN
T[7:0]
[7:0]
RW
0x80
PLL1 Maximum Holdover Count.
9.6.2.98 PLL1_NDIV_BY1
The PLL1_NDIV value is set by Register's PLL1_NDIV_BY1 and PLL1_NDIV_BY0 Back to Register Map.
Table 122. Register - 0x61
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1 N-Feedback Divider Value.
PLL1_NDIV - N-Feedback Divider
0 - Reserved
1 - 1
[7:0]
PLL1_NDIV[15:8]
RW
0x0
.. - ..
65535 - 65535
9.6.2.99 PLL1_NDIV_BY0
The PLL1_NDIV_BY0 Register sets bits [7:0] Back to Register Map.
Table 123. Register - 0x62
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_NDIV[7:0]
RW
0x78
PLL1 N-Feedback Divider Value.
9.6.2.100 PLL1_LOCKDET_CYC_CNT_BY2
The PLL1_LOCKDET_CYC_CNT is
set
by
registers
PLL1_LOCKDET_CYC_CNT_BY2,
PLL1_LOCKDET_CYC_CNT_BY1 and PLL1_LOCKDET_CYC_CNT_BY0 Back to Register Map.
Table 124. Register - 0x63
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_LOCKDET_CYC_CNT[
23:16]
[7:0]
RW
0x0
PLL1 Lock Detect Cycle Counter.
9.6.2.101 PLL1_LOCKDET_CYC_CNT_BY1
The PLL1_LOCKDET_CYC_CNT_BY1 Register sets bits [15:8] Back to Register Map.
Table 125. Register - 0x64
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_LOCKDET_CYC_CNT[
15:8]
[7:0]
RW
0x40
PLL1 Lock Detect Cycle Counter.
9.6.2.102 PLL1_LOCKDET_CYC_CNT_BY0
The PLL1_LOCKDET_CYC_CNT_BY0 Register sets bits [7:0] Back to Register Map.
Table 126. Register - 0x65
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_LOCKDET_CYC_CNT[
7:0]
[7:0]
RW
0x0
PLL1 Lock Detect Cycle Counter.
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9.6.2.103 RSRVD_0x66
Table 127. Register - 0x66
BIT NO.
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
[7:0]
R
0x0
Reserved.
9.6.2.104 RSRVD_0x67
Table 128. Register - 0x67
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_STORAGE_CELL[31:2
4]
[7:0]
R
0x0
PLL1 Storage Cell Value.
9.6.2.105 RSRVD_0x68
Table 129. Register - 0x68
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_STORAGE_CELL[23:1
6]
[7:0]
R
0x0
PLL1 Storage Cell Value.
9.6.2.106 RSRVD_0x69
Table 130. Register - 0x69
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL1_STORAGE_CELL[15:8
]
[7:0]
R
0x0
PLL1 Storage Cell Value.
9.6.2.107 PLL1_STRG
The PLL1_STRG reads current storage cell value of PLL1. Back to Register Map.
Table 131. Register - 0x6A
BIT NO.
[7:6]
FIELD
RSRVD
TYPE
RESET
0x0
DESCRIPTION
Reserved
R
R
[5:0]
PLL1_STORAGE_CELL[5:0]
0x0
PLL1 Storage Cell Value.
9.6.2.108 PLL1RCCLKDIV
The PLL1RCCLKDIV Register controls the PLL1 RC Clock Divider Back to Register Map.
Table 132. Register - 0x6B
BIT NO.
[7:5]
[4]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
RW
-
-
1
-
PLL1_RC_CLK_EN
RSRVD
PLL1 RC Clock Enable.
Reserved.
[3]
PLL1 RC Clk Divider value. Sets the divider value for the
PLL1 RC clock that is derived from the PLL2 VCO Clock.
PLL1_RC_CLK_DIV - Divider Value
0 - 1
1 - 2
.. - ..
7 - 8
[2:0]
PLL1_RC_CLK_DIV[2:0]
RW
0x7
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9.6.2.109 PLL2_CTRL0
The PLL2_CTRL0 Register provides control of PLL2 features. Back to Register Map.
Table 133. Register - 0x6C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
PLL2_VCO_PRESC_LOW_P
OWER
[4]
[3]
RW
RW
0
0
PLL2 Prescaler Low Power Mode.
Clock Source for Oscout Buffer.
PLL2_BYP_OSC - Oscout Clock Source
0 - PLL2 Output
PLL2_BYP_OSC
PLL2_BYP_TOP
PLL2_BYP_BOT
PLL2_GLOBAL_BYP
1 - PLL2 Input
Clock Source for Top Outputs.
PLL2_BYP_TOP - Top Outputs Clock Source
0 - PLL2 Output
[2]
[1]
[0]
RW
RW
RW
0
0
0
1 - PLL2 Input
Clock Source for Bottom Outputs.
PLL2_BYP_BOT - Bottom Outputs Clock Source
0 - PLL2 Output
1 - PLL2 Input
PLL2 Global Bypass Enable.
PLL2_GLOBAL_BYP - PLL2 Input Clock Source
0 - OSCin
1 - CLKIN0..3
9.6.2.110 PLL2_CTRL1
The PLL2_CTRL1 Register provides control of PLL2 features. Back to Register Map.
Table 134. Register - 0x6D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL2_EN_PULSE_GEN
RW
0
Enable Pulse Generator in PLL2 R input block.
PLL2 R-Divider Bypass. When PLL2_RDIV_BYP is 1 the R-
Divider is by-passed.
[6]
PLL2_RDIV_BYP
RW
0
PLL2 Doubler Enable Invert. When PLL2_DBL_EN_INV is 1
the output of the PLL2 Doubler is inverted.
[5]
[4]
PLL2_DBL_EN_INV
PLL2_PD_VARBIAS
RW
RW
0
0
VCO Varactor Biasing PD.
PLL2 Smart trim enable. If PLL2_SMART_TRIM is set to 1
then the initial calibration threshold is set by
[3]
PLL2_SMART_TRIM
RW
1
PLL2_AC_STRT_THRESHOLD and the final threshold is set
by PLL2_AC_THRESHOLD. If PLL2_SMART_TRIM is 0 the
threshold is set by PLL2_AC_THRESHOLD at all times.
PLL2 Lock Detect LOS Mask. When
PLL2_LCKDET_LOS_MASK is 1 then Loss of Source has no
effect on the PLL2 Lock Detect circuit.
[2]
PLL2_LCKDET_LOS_MASK
RW
1
[1]
[0]
PLL2_RDIV_DBL_EN
PLL2_PD_LD
RW
RW
0
1
PLL2 R-Divider Doubler Enable.
PLL2 Window Comparator Powerdown.
9.6.2.111 PLL2_CTRL2
The PLL2_CTRL2 Register provides control of PLL2 features. Back to Register Map.
Table 135. Register - 0x6E
BIT NO.
[7]
FIELD
TYPE
RW
RESET
DESCRIPTION
RESERVED
PLL2_BYP_SYNC_TOP
PLL2_BYP_SYNC_BOTTOM
PLL2_EN_BYP_BUF
0
0
0
[6]
RW
RESERVED
[5]
RW
PLL2 Enable Bypass Clock Buffer.
92
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Table 135. Register - 0x6E (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 Enable Clock Buffer for Re-clocked SYNC signal to
TOP Output-CHs.
[4]
PLL2_EN_BUF_SYNC_TOP
RW
1
PLL2_EN_BUF_SYNC_BOT
TOM
PLL2 Enable Clock Buffer for Re-clocked SYNC signal to
Bottom Output-CHs.
[3]
RW
1
[2]
[1]
PLL2_EN_BUF_OSCOUT
PLL2_EN_BUF_CLK_TOP
RW
RW
0
1
PLL2 Enable Clock Buffer for OSCOut.
PLL2 Enable Clock Buffer for Top Output-CHs.
PLL2_EN_BUF_CLK_BOTT
OM
[0]
RW
1
PLL2 Enable Clock Buffer for Bottom Output-CHs.
9.6.2.112 PLL2_SWRST
The PLL2_SWRST Register allows activation of the following PLL2 related software resets. Back to Register
Map.
Table 136. Register - 0x6F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
PLL2 R-Divider Software Reset. Writing a 1 to
PLL2_RDIV_SWRST will reset the R-Divider.
PLL2_RDIV_SWRST is cleared automatically to 0.
[2]
PLL2_RDIV_SWRST
RWSC
0
PLL2 N-Divider Software Reset. Writing a 1 to
PLL2_NDIV_SWRST will reset the N-Divider.
PLL2_NDIV_SWRST is cleared automatically to 0.
[1]
[0]
PLL2_NDIV_SWRST
PLL2_SWRST
RWSC
RWSC
0
0
PLL2 Software Reset. Writing a 1 to PLL2_SWRST will reset
PLL2 PLL2_SWRST is cleared automatically to 0.
9.6.2.113 PLL2_LF_C4R4
The PLL2_LF_C4R4 Register sets the values for C4 and R4 Back to Register Map.
Table 137. Register - 0x70
BIT NO.
[7:4]
FIELD
TYPE
RW
RESET
0x0
DESCRIPTION
PLL2_C4_LF_SEL[3:0]
PLL2_R4_LF_SEL[3:0]
PLL2 Loop Filter C4 Value.
PLL2 Loop Filter R4 Value.
[3:0]
RW
0x0
9.6.2.114 PLL2_LF_C3R3
The PLL2_LF_C3R3 Register sets the values for C3 and R3 Back to Register Map.
Table 138. Register - 0x71
BIT NO.
[7:4]
FIELD
TYPE
RW
RESET
0x0
DESCRIPTION
PLL2_C3_LF_SEL[3:0]
PLL2_R3_LF_SEL[3:0]
PLL2 Loop Filter C3 Value.
PLL2 Loop Filter R3 Value.
[3:0]
RW
0x0
9.6.2.115 PLL2_CP_SETTING
The PLL2_CP_SETTING Register provides control of the PLL2 Chargepump. Back to Register Map.
Table 139. Register - 0x72
BIT NO.
[7:6]
FIELD
RSRVD
TYPE
RW
RESET
0x0
DESCRIPTION
Reserved.
[5:0]
PLL2_PROP[5:0]
RW
0x3
PLL2 Charge pump Setting.
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9.6.2.116 PLL2_NDIV_BY1
The PLL2 N-Divider Value is set by Register's PLL2_NDIV_BY1 and PLL2_NDIV_BY0. Back to Register Map.
Table 140. Register - 0x73
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_NDIV[15:8]
RW
0x0
PLL2 N-Divider Value.
9.6.2.117 PLL2_NDIV_BY0
The PLL2_NDIV_BY0 Register sets bits [7:0] Back to Register Map.
Table 141. Register - 0x74
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_NDIV[7:0]
RW
0x20
PLL2 N-Divider Value.
9.6.2.118 PLL2_RDIV_BY1
RESERVED. Back to Register Map.
Table 142. Register - 0x75
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 R-Divider Value. PLL2 R-Divider configuration limited
to bits [5..0].
[7:0]
PLL2_RDIV[15:8]
RW
0x0
9.6.2.119 PLL2_RDIV_BY0
The PLL2_RDIV Register sets the PLL2 R-Divider bits [5:0]. Back to Register Map.
Table 143. Register - 0x76
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 R-Divider Value. PLL2 R-Divider configuration limited
to bits [5..0].
[7:0]
PLL2_RDIV[7:0]
RW
0x0
9.6.2.120 PLL2_STRG_INIT_BY1
The PLL2_STRG_INIT_BY1 Register Back to Register Map.
Table 144. Register - 0x77
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_STRG_INITVAL[15:8]
RW
0x0
PLL2 Storage-CP Init Value.
9.6.2.121 PLL2_STRG_INIT_BY0
The PLL2_STRG_INIT_BY0 Register Back to Register Map.
Table 145. Register - 0x78
BIT NO.
FIELD
TYPE
RW
RESET
0xFF
DESCRIPTION
[7:0]
PLL2_STRG_INITVAL[7:0]
PLL2 Storage-CP Init Value.
9.6.2.122 RAILDET_UP
The Rail Detect Upper Limit Back to Register Map.
Table 146. Register - 0x7D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
94
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Table 146. Register - 0x7D (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[5:0]
RAILDET_UPP[5:0]
RW
0x0
Upper Rail Detection Limit.
9.6.2.123 RAILDET_LOW
The Rail Detect Lower Limit Back to Register Map.
Table 147. Register - 0x7E
BIT NO.
[7:6]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[5:0]
RAILDET_LOW[5:0]
RW
0x0
Lower Rail Detection Limit.
9.6.2.124 PLL2_AC_CTRL
The PLL2_AC_CTRL Register provides control of PLL2 Amplitude Calibration features. Back to Register Map.
Table 148. Register - 0x7F
BIT NO.
[7:6]
[5]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
PLL2_AC_CAL_EN
PLL2_PD_AC
RW
RW
1
1
PLL2 Amplitude Calibration Enable.
VCO Peak detector Power down. 1=off, 0=enabled.
[4]
PLL2 IDAC Re-Calibration Setting. When the difference
between consecutive IDACSET values is greater than
PLL2_IDACSET_RECAL the amplitude calibration is
restarted.
[3:2]
PLL2_IDACSET_RECAL[1:0]
RW
0x1
[1]
[0]
PLL2_AC_REQ
RWSC
RW
0
0
PLL2 Amplitude Calibration Request.
PLL2 Fast Amplitude Calibration Enable.
PLL2_FAST_ACAL
9.6.2.125 PLL2_CURR_STOR_CELL
The PLL2_CURR_STOR_CELL Register is described below. Back to Register Map.
Table 149. Register - 0x80
BIT NO.
[7:5]
FIELD
RSRVD
TYPE
RW
RESET
0x0
DESCRIPTION
Reserved.
[4:0]
PLL2_INTG[4:0]
RW
0x3
PLL2 Integral gain setting.
9.6.2.126 PLL2_AC_THRESHOLD
The PLL2_AC_THRESHOLD Register sets the Amplitude Calibration Threshold Back to Register Map.
Table 150. Register - 0x81
BIT NO.
[7:5]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[4:0]
PLL2_AC_THRESHOLD[4:0]
RW
0x0
PLL2 VCO Amplitude Calibration Threshold.
9.6.2.127 PLL2_AC_STRT_THRESHOLD
The PLL2_AC_THRESHOLD Register sets the Amplitude Calibration Starting Threshold Back to Register Map.
Table 151. Register - 0x82
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
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Table 151. Register - 0x82 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_AC_STRT_THRESHO
LD[4:0]
[4:0]
RW
0x0
PLL2 VCO Amplitude Calibration Starting Threshold.
9.6.2.128 PLL2_AC_WAIT_CTRL
The PLL2_AC_WAIT_CTRL Register sets the Amplitude Calibration Wait Periods. Back to Register Map.
Table 152. Register - 0x83
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 VCO Amplitude Calibration Delay between IDAC Code
Changes. Delay is equal to PLL2_AC_CMP_WAIT*4*Clock
Period (Clock Period 100ns).
[7:4]
PLL2_AC_CMP_WAIT[3:0]
RW
0x0
PLL2 VCO Amplitude Calibration Initial Comparator Delay.
Delay is equal to PLL2_AC_INIT_WAIT*4*Clock Period.
[3:0]
PLL2_AC_INIT_WAIT[3:0]
RW
0x0
9.6.2.129 PLL2_AC_JUMPSTEP
The PLL2_AC_JUMPSTEP Register provides control of the PLL2 Amplitude Calibration step size. Back to
Register Map.
Table 153. Register - 0x84
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
PLL2 IDAC Code Jump Step. When PLL2_FAST_ACAL is 1
then the IDACSET step value is set by
PLL2_AC_JUMP_STEP.
[3:0]
PLL2_AC_JUMP_STEP[3:0]
RW
0xF
9.6.2.130 PLL2_LD_WNDW_SIZE
The PLL2_LD_WNDW_SIZE Register sets the PLL2 Window Comparator Setting. Back to Register Map.
Table 154. Register - 0x85
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 Window Comparator Size Setting. PLL2 Window
comparator size after PLL2 AC Calibration and initial lock.
[7:0]
PLL2_LD_WNDW_SIZE[7:0]
RW
0x1
Always set to 0.
0: 1 ns.
1 to 255: Reserved
9.6.2.131 PLL2_LD_WNDW_SIZE_INITIAL
The PLL2_LD_WNDW_SIZE_INITIAL Register sets the PLL2 Window Comparator Initial Setting. Back to
Register Map.
Table 155. Register - 0x86
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2 Window Comparator Size Initial Setting. Window
comparator size prior to PLL2 AC Calibration and initial lock.
PLL2_LD_WNDW_SIZE_INI
TIAL[7:0]
[7:0]
RW
0x7F
Always set to 0.
0: 1 ns.
1 to 255: Reserved
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9.6.2.132 PLL2_LOCKDET_CYC_CNT_BY2
The
PLL2
Lock
Detection
Cycle
Count
is
set
by
PLL2_LOCKDET_CYC_CNT_BY2,
PLL2_LOCKDET_CYC_CNT_BY1 and PLL2_LOCKDET_CYC_CNT_BY0. Back to Register Map.
Table 156. Register - 0x87
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT[
23:16]
[7:0]
RW
0x0
PLL2 Lock detection cycle counter.
9.6.2.133 PLL2_LOCKDET_CYC_CNT_BY1
The PLL2_LOCKDET_CYC_CNT_BY1 Register sets bits [15:8] Back to Register Map.
Table 157. Register - 0x88
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT[
15:8]
[7:0]
RW
0x40
PLL2 Lock detection cycle counter.
9.6.2.134 PLL2_LOCKDET_CYC_CNT_BY0
The PLL2_LOCKDET_CYC_CNT_BY0 Register sets bits [7:0] Back to Register Map.
Table 158. Register - 0x89
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT[
7:0]
[7:0]
RW
0x0
PLL2 Lock detection cycle counter.
9.6.2.135 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
The PLL2 Lock Detection Initial Cycle Count is set by PLL2_LOCKDET_CYC_CNT_INITIAL_BY2,
PLL2_LOCKDET_CYC_CNT_INITIAL_BY1 and PLL2_LOCKDET_CYC_CNT_INITIAL_BY0. This counter is
used for initial PLL2 Lock before final Amplitude Calibration has finished. Back to Register Map.
Table 159. Register - 0x8A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT
_INITIAL[23:16]
[7:0]
RW
0x0
PLL2 Lock detection initial cycle counter.
9.6.2.136 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
The PLL2_LOCKDET_CYC_CNT_INITIAL_BY1 Register sets bits [15:8] Back to Register Map.
Table 160. Register - 0x8B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT
_INITIAL[15:8]
[7:0]
RW
0x40
PLL2 Lock detection initial cycle counter.
9.6.2.137 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
The PLL2_LOCKDET_CYC_CNT_INITIAL_BY0 Register sets bits [7:0] Back to Register Map.
Table 161. Register - 0x8C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
PLL2_LOCKDET_CYC_CNT
_INITIAL[7:0]
[7:0]
RW
0x0
PLL2 Lock detection initial cycle counter.
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9.6.2.138 IOCTRL_SPI0
The IOCTRL_SPI0 Register provides control of the SDIO Input/Output Driver. Back to Register Map.
Table 162. Register - 0x8D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SPI 3-Wire Selection. 1=3-Wire, 0=4-Wire. When configured
for 4 wire operation the SDO output is connected to the
STATUS1 output pad.
[7]
SPI_EN_THREE_WIRE_IF
RW
0
[6:5]
[4]
RSRVD
-
-
Reserved.
SDIO Output Mute. When SPI_SDIO_OUTPUT_MUTE is 1
the SDIO output driver is forced to 0 if it is enabled.
SPI_SDIO_OUTPUT_MUTE
RW
0
SDIO Output Invert. When SPI_SDIO_OUTPUT_INV is 1 the
SDIO output is inverted.
[3]
[2]
[1]
[0]
SPI_SDIO_OUTPUT_INV
RW
RW
RW
RW
0
0
0
0
SDIO Output Weak Drive Strength. When
SPI_SDIO_OUTPUT_WEAK DRIVE is 1 the SDIO output is
configured with a low slew rate.
SPI_SDIO_OUTPUT_WEAK
_DRIVE
SPI SDIO Pull Up Enable. When SPI_SDIO_PULLUP_EN is
1 a pullup resistor is activated.
SPI_SDIO_EN_PULLUP
SPI SDIO Pull Down Enable. When
SPI_SDIO_PULLDWN_EN is 1 a pulldown resistor is
activated.
SPI_SDIO_EN_PULLDOWN
9.6.2.139 IOCTRL_SPI1
The IOCTRL_SPI1 Register provides control of the SCL and SCS input drivers. Back to Register Map.
Table 163. Register - 0x8E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
SPI SCL Pull Up Enable. When SPI_SCL_PULLUP_EN is 1
a pullup resistor is activated.
[3]
[2]
[1]
SPI_SCL_EN_PULLUP
SPI_SCL_EN_PULLDOWN
SPI_SCS_EN_PULLUP
RW
RW
RW
0
0
0
SPI SCL Pull Down Enable. When SPI_SCL_PULLDWN_EN
is 1 a pulldown resistor is activated.
SPI SCS Pull Up Enable. When SPI_SCS_PULLUP_EN is 1
a pullup resistor is activated.
SPI SCS Pull Down Enable. When
SPI_SCS_PULLDWNEN_EN is 1 a pulldown resistor is
activated.
[0]
SPI_SCS_EN_PULLDOWN
RW
0
9.6.2.140 IOTEST_SDIO
The IOTEST_SDIO Register provides control of the SDIO driver and test features. Back to Register Map.
Table 164. Register - 0x8F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
0
Reserved.
SPI SDIO Output Driver High Impedance. When
SPI_SDIO_OUTPUT_HIZ is set to 1 the SDIO output driver
stage is disabled. Only when SPI_SDIO_IOTESTEN is 1.
[6]
[5]
SPI_SDIO_OUTPUT_HIZ
SPI_SDIO_ENB_INSTAGE
RW
RW
1
0
SPI SDIO Input Stage Enable BAR. When
SPI_SDIO_INPUT_ENB is 0 the SDIO Input stage is
enabled. Whenever SPI_SDIO_INPUT_ENB is set to 1 the
SPI interface is rendered inoperable and can only be
recovered by a hardware reset.
SPI SDIO Input Stage Enable Multi-level. When
SPI_SDIO_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
SPI_SDIO_EN_ML_INSTAG
E
[4]
[3]
RW
-
0
0
RSRVD
Reserved.
98
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Table 164. Register - 0x8F (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SPI SDIO Output Data. Controls the SDIO output data value
when SPI_SDIO_IOTESTEN is set to 1.
[2]
SPI_SDIO_OUTPUT_DATA
RW
0
SPI SDIO Input Y12 Value. Indicates the logic level present
on the SDIO Y12 pin. This feature is currently not supported.
[1]
[0]
SPI_SDIO_INPUT_Y12
SPI_SDIO_INPUT_M12
R
R
0
0
SPI SDIO Input M12 Value. Indicates the logic level present
on the SDIO M12 pin. This feature is currently not supported.
9.6.2.141 IOTEST_SCL
The IOTEST_SCL Register provides control of the SCL driver and test features. Back to Register Map.
Table 165. Register - 0x90
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
SPI SCL Input Stage Enable BAR. When
SPI_SCL_INPUT_ENB is 0 the SCL Input stage is enabled.
Whenever SPI_SCL_INPUT_ENB is set to 1 the SPI
interface is rendered inoperable and can only be recovered
by a hardware reset.
[5]
SPI_SCL_ENB_INSTAGE
RW
RW
0
0
SPI SCL Input Stage Enable Multi-level. When
SPI_SCL_INPUT_ENML is 1 the input stage is configured for
multi-level mode.
[4]
SPI_SCL_EN_ML_INSTAGE
[3:2]
[1]
RSRVD
-
-
Reserved.
SPI SCL Input Y12 Value. Indicates the logic level present
on the SCL Y12 pin. This feature is currently not supported.
SPI_SCL_INPUT_Y12
R
0
SPI SCL Input M12 Value. Indicates the logic level present
on the SCL M12 pin. This feature is currently not supported.
[0]
SPI_SCL_INPUT_M12
R
0
9.6.2.142 IOTEST_SCS
The IOTEST_SCS Register provides control of the SCS driver and test features. Back to Register Map.
Table 166. Register - 0x91
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
SPI SCS Input Stage Enable BAR. When
SPI_SCS_INPUT_ENB is 0 the SCS Input stage is enabled.
Whenever SPI_SCS_INPUT_ENB is set to 1 the SPI
interface is rendered inoperable and can only be recovered
by a hardware reset.
[5]
SPI_SCS_ENB_INSTAGE
RW
RW
0
0
SPI SCS Input Stage Enable Multi-level. When
SPI_SCS_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[4]
SPI_SCS_EN_ML_INSTAGE
[3:2]
[1]
RSRVD
-
-
Reserved.
SPI SCS Input Y12 Value. Indicates the logic level present
on the SCS Y12 pin. This feature is currently not supported.
SPI_SCS_INPUT_Y12
R
0
SPI SCS Input M12 Value. Indicates the logic level present
on the SCS M12 pin. This feature is currently not supported.
[0]
SPI_SCS_INPUT_M12
R
0
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9.6.2.143 IOCTRL_STAT0
The IOCTRL_STAT0 Register provides control of the STATUS0 Input/Output Driver. Back to Register Map.
Table 167. Register - 0x92
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
STAT0 Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
STATUS0_MUX_SEL - STATUS0 Output
000 - PLL1 REF CLK
[7:5]
STATUS0_MUX_SEL[2:0]
RW
0x4
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by STATUS0_INT_MUX (digital)
STATUS0 Output Mute. When STATUS0_OUTPUT_MUTE
is 1 the STATUS0 output driver is forced to 0 if it is enabled.
[4]
[3]
STATUS0_OUTPUT_MUTE
STATUS0_OUTPUT_INV
RW
RW
0
0
STATUS0 Output Invert. When STATUS0_OUTPUT_INV is
1 the STATUS0 output is inverted.
STATUS0 Output Weak drivestrength. When
STATUS0_OUTPUT_WEAK DRIVE is 1 the STATUS0
output is configured with a lower slew rate.
STATUS0_OUTPUT_WEAK_
DRIVE
[2]
[1]
[0]
RW
RW
RW
0
0
0
STATUS0 Pull Up Enable. When STATUS0_PULLUPEN_EN
is 1 a pullup resistor is activated.
STATUS0_EN_PULLUP
STATUS0 Pull Down Enable. When
STATUS0_PULLDWN_EN is 1 a pulldown resistor is
activated.
STATUS0_EN_PULLDOWN
9.6.2.144 IOCTRL_STAT1
The IOCTRL_STAT1 Register provides control of the STATUS1 Input/Output Driver. Back to Register Map.
Table 168. Register - 0x93
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
STAT1 Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
STATUS1_MUX_SEL - STATUS1 Output
000 - PLL1 REF CLK
[7:5]
STATUS1_MUX_SEL[2:0]
RW
0x4
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by STATUS1_INT_MUX (digital)
STATUS1 Output Mute. When STATUS1_OUTPUT_MUTE
is 1 the STATUS1 output driver is forced to 0 if it is enabled.
[4]
[3]
STATUS1_OUTPUT_MUTE
STATUS1_OUTPUT_INV
RW
RW
0
0
STATUS1 Output Invert. When STATUS1_OUTPUT_INV is
1 the STATUS1 output is inverted.
STATUS1 Output weak drive. When
STATUS1_OUTPUT_WEAK_DRIVE is 1 the STATUS1
output is configured with a lower slew rate.
STATUS1_OUTPUT_WEAK_
DRIVE
[2]
[1]
[0]
RW
RW
RW
0
0
0
STATUS1 Pull Up Enable. When STATUS1_PULLUP_EN is
1 a pullup resistor is activated.
STATUS1_EN_PULLUP
STATUS1 Pull Down Enable. When
STATUS1_PULLDWN_EN is 1 a pulldown resistor is
activated.
STATUS1_EN_PULLDOWN
100
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9.6.2.145 STAT1MUX
The STAT1MUX Register controls the status signal that is routed to the STATUS0 output. Back to Register Map.
Table 169. Register - 0x94
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
STAT1 Integrated Mux Select.
STAT1_INT_MUX - STATUS1 Output
0 - PLL1 Lock Detect and PLL2 Lock Detect
1 - PLL1 Lock Detect
2 - PLL2 Lock Detect
3 - CLKINBLK LOS
4 - SPI Output Data
5 - Reserved
6 - Reserved
7 - Reserved
8 - HOLDOVER_EN
[7:0]
STATUS1_INT_MUX[7:0]
RW
0x4
9 - Mirror of SYNC_INPUT
10 - Mirror of CLKINSEL1 INPUT
11 - Reserved
12 - Reserved
13 - PLL2 Reference Clock
14 - Reserved
15 - PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16 - PLL1 Lock Detect and not PLL1 Holdover
17 - Logic 1
18 - Logic 0
9.6.2.146 STAT0MUX
The STAT0MUX Register controls the status signal that is routed to the STATUS1 output. Back to Register Map.
Table 170. Register - 0x95
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
STAT0 Integrated Mux Select.
STAT0_INT_MUX - STATUS0 Output
0 - PLL1 Lock Detect and PLL2 Lock Detect
1 - PLL1 Lock Detect
2 - PLL2 Lock Detect
3 - CLKINBLK LOS
4 - SPI Output Data
5 - Reserved
6 - Reserved
7 - Reserved
8 - HOLDOVER_EN
[7:0]
STATUS0_INT_MUX[7:0]
RW
0x0
9 - Mirror of SYNC_INPUT
10 - Mirror of CLKINSEL1 INPUT
11 - Reserved
12 - Reserved
13 - PLL2 Reference Clock
14 - Reserved
15 - PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16 - PLL1 Lock Detect and not PLL1 Holdover
17 - Logic 1
18 - Logic 0
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9.6.2.147 STATPLL2CLKDIV
The STATPLL2CLKDIV Register controls the PLL2 Status Output Clock Divider Back to Register Map.
Table 171. Register - 0x96
BIT NO.
[7:5]
[4]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
RW
-
-
1
-
PLL2_REF_CLK_EN
RSRVD
PLL2 Ref Clock Enable.
Reserved.
[3]
PLL2 Ref Clock Divider for Status Outputs. Sets the divider
value for the PLL2 VCO clock that can be routed to the
STAT0/1 outputs.
PLL2_REF_STATCLK_DIV - Divider Value
PLL2_REF_STATCLK_DIV[2
:0]
[2:0]
RW
0x0
0 - 1
1 - 2
.. - ..
7 - 8
9.6.2.148 IOTEST_STAT0
The IOTEST_STAT0 Register provides control of the STATUS0 driver and test features. Back to Register Map.
Table 172. Register - 0x97
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
STATUS0 Output Driver High Impedance. When
STATUS0_OUTPUT_HIZ is set to 1 the STATUS0 output
driver stage is disabled.
[6]
[5]
[4]
STATUS0_OUTPUT_HIZ
STATUS0_ENB_INSTAGE
RW
RW
RW
0
1
0
STATUS0 Input Stage Enable BAR. When
STATUS0_INPUT_ENB is 0 the STATUS0 Input stage is
enabled. When STATUS0_INPUT_ENB is set to 1 the
STATUS0 input stage is disabled.
STATUS0 Input Stage Enable Multi-level. When
STATUS0_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
STATUS0_EN_ML_INSTAG
E
[3]
[2]
RSRVD
-
-
Reserved.
STATUS0 Output Data. Set the STATUS0 output data value
when STATUS0_IOTESTEN is 1.
STATUS0_OUTPUT_DATA
RW
0
STATUS0 Input Y12 Value. Indicates the logic level present
on the STATUS0 Y12 pin.
[1]
[0]
STATUS0_INPUT_Y12
STATUS0_INPUT_M12
R
R
0
0
STATUS0 Input M12 Value. Indicates the logic level present
on the STATUS0 M12 pin.
9.6.2.149 IOTEST_STAT1
The IOTEST_STAT1 Register provides control of the STATUS1 driver and test features. Back to Register Map.
Table 173. Register - 0x98
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
STATUS1 Output Driver High Impedance. When
STATUS1_OUTPUT_HIZ is set to 1 the STATUS1 output
driver stage is disabled.
[6]
[5]
STATUS1_OUTPUT_HIZ
STATUS1_ENB_INSTAGE
RW
RW
0
1
STATUS1 Input Stage Enable BAR. When
STATUS1_INPUT_ENB is 0 the STATUS1 Input stage is
enabled. When STATUS1_INPUT_ENB is set to 1 the
STATUS1 input stage is disabled.
102
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Table 173. Register - 0x98 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
STATUS1 Input Stage Enable Multi-level. When
STATUS1_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
STATUS1_EN_ML_INSTAG
E
[4]
RW
0
[3]
[2]
RSRVD
-
-
Reserved.
STATUS1 Output Data. Set the STATUS1 output data value
when STATUS1_IOTESTEN is 1.
STATUS1_OUTPUT_DATA
RW
0
STATUS1 Input Y12 Value. Indicates the logic level present
on the STATUS1 Y12 (high-level) pin.
[1]
[0]
STATUS1_INPUT_Y12
STATUS1_INPUT_M12
R
R
0
0
STATUS1 Input M12 Value. Indicates the logic level present
on the STATUS1 M12 (mid-level) pin.
9.6.2.150 IOCTRL_SYNC
The IOCTRL_SYNC Register provides control of the SYNC Input. Back to Register Map.
Table 174. Register - 0x99
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYNC Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
SYNC_MUX_SEL - SYNC Output
000 - PLL1 REF CLK
[7:5]
SYNC_MUX_SEL[2:0]
RW
0x4
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by SYNC_INT_MUX (digital)
SYNC Output Mute. When SYNC_OUTPUT_MUTE is 1 the
SYNC output driver is forced to 0 if it is enabled.
[4]
[3]
SYNC_OUTPUT_MUTE
SYNC_OUTPUT_INV
RW
RW
0
0
SYNC Output Invert. When SYNC_OUTPUT_INV is 1 the
SYNC output is inverted.
SYNC Output weak drive. When
SYNC_OUTPUT_WEAK_DRIVE is 1 the SYNC output is
configured with a lower slew rate.
SYNC_OUTPUT_WEAK_DRI
VE
[2]
RW
0
SYNC Pull Up Enable. When SYNC_PULLUPEN_EN is 1 a
pullup resistor is activated.
[1]
[0]
SYNC_EN_PULLUP
RW
RW
0
0
SYNC Pull Down Enable. When SYNC_PULLDWN_EN is 1
a pulldown resistor is activated.
SYNC_EN_PULLDOWN
9.6.2.151 DUMMY_REGISTER_1
Placeholder 1. Back to Register Map.
Table 175. Register - 0x9A
BIT NO.
[7:1]
FIELD
RSRVD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
-
-
-
[0]
Reserved.
9.6.2.152 IOCTRL_CLKINSEL1
The IOCTRL_CLKINSEL1 Register provides control of the CLKINSEL1 Input. Back to Register Map.
Table 176. Register - 0x9B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RSRVD
-
-
Reserved.
CLKIN_SEL1 Pull Up Enable. When
CLKINSEL1_PULLUP_EN is 1 a pullup resistor is activated.
[1]
CLKINSEL1_EN_PULLUP
RW
0
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Table 176. Register - 0x9B (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
CLKIN_SEL1 Pull Down Enable. When
CLKINSEL1_PULLDWN_EN is 1 a pulldown resistor is
activated.
CLKINSEL1_EN_PULLDOW
N
[0]
RW
0
9.6.2.153 IOTEST_CLKINSEL1
The IOTEST_CLKINSEL1 Register provides control of the CLKINSEL1 driver test features. Back to Register
Map.
Table 177. Register - 0x9C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
CLKINSEL1 Input Stage Enable BAR. When
CLKINSEL1_INPUT_ENB is 0 the CLKINSEL1 Input stage is
enabled.
[5]
[4]
CLKINSEL1_ENB_INSTAGE
RW
RW
0
0
CLKINSEL1 Input Stage Enable Multi-level. When
CLKINSEL1_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
CLKINSEL1_EN_ML_INSTA
GE
[3:2]
[1]
RSRVD
-
-
Reserved.
CLKINSEL1 Input Y12 Value. Indicates the logic level
present on the CLKINSEL1 Y12 (high-level) pin.
CLKINSEL1_INPUT_Y12
R
0
CLKINSEL1 Input M12 Value. Indicates the logic level
present on the CLKINSEL1 M12 (mid-level) pin.
[0]
CLKINSEL1_INPUT_M12
R
0
9.6.2.154 PLL1_TSTMODE
The PLL1_TSTMODE Register supports PLL1 Test by enabling output of PLL1 phase detector inputs.Back to
Register Map.
Table 178. Register - 0xAC
BIT NO.
[7]
FIELD
TYPE
RESET
DESCRIPTION
Set this bit when STATUS0_MUX_SEL,
STATUS1_MUX_SEL, or SYNC_MUX_SEL selects a PLL1
REF clock or FB (SYS) clock output.
0: PLL1 REF or PLL1 FB (SYS) clock not selected by any
mux
PLL1_TSTMODE_REF_FB_
EN
RW
0
0
1: PLL1 REF or PLL1 FB (SYS) clock selected by at least
one mux
[6:0]
RSRVD
RW
Reserved.
9.6.2.155 PLL2_CTRL
The PLL2_CTRL Register supports other PLL2 features. Back to Register Map.
Table 179. Register - 0xAD
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
Before using PLL2 DLD signal, set this field to 0x3, wait 20
ms, set to 0x0. Refer to PLL2 DLD flow chart in Figure 40.
0x0: Clear reset state
0x1: Reserved
[5:4]
[3]
RESET_PLL2_DLD
RSRVD
RW
-
0
-
0x2: Reserved
0x3: Reset set
Reserved.
104
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BIT NO.
ZHCSG70B –MARCH 2017–REVISED JULY 2019
Table 179. Register - 0xAD (continued)
FIELD
TYPE
RESET
DESCRIPTION
Set this bit when STATUS0_MUX_SEL,
STATUS1_MUX_SEL, or SYNC_MUX_SEL selects a PLL1
REF clock or FB (SYS) clock output.
0: PLL1 REF or PLL1 FB (SYS) clock not selected by any
mux
PLL2_TSTMODE_REF_FB_
EN
[2]
RW
0
1: PLL1 REF or PLL1 FB (SYS) clock selected by at least
one mux
Set for modes not using PLL2 VCO.
0x0: VCO LDO active
0x1: Reserved
[1:0]
PD_VCO_LDO
RW
0
0x2: Reserved
0x3: VCO LDO disabled
9.6.2.156 PLL2_RDIV_CLKEN
The PLL2_RDIV_CLKEN Register supports PLL2 R-Divider enable. Back to Register Map.
Table 180. Register - 0xAF
BIT NO.
[7:1]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[0]
PLL2_RDIV_CLKEN
RW
0
PLL2 R-Divider Clock Enable.
9.6.2.157 PLL2_NDIV_CLKEN
The PLL2_NDIV_CLKEN Register supports PLL2 N-Divider enable. Back to Register Map.
Table 181. Register - 0xB0
BIT NO.
[7:1]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[0]
PLL2_NDIV_CLKEN
RW
1
PLL2 N-Divider Clock Enable.
9.6.2.158 STATUS
The STATUS Register provides access to the following status signals. Back to Register Map.
Table 182. Register - 0xBE
BIT NO.
[7:6]
[5]
FIELD
TYPE
RESET
DESCRIPTION
Reserved.
RSRVD
-
-
LOS
R
R
R
R
R
R
0
0
0
0
0
0
Loss of Source
[4]
HOLDOVER_DLD
HOLDOVER_LOL
HOLDOVER_LOS
PLL2_LCK_DET
PLL1_LCK_DET
Holdover - Digital Lock Detect
Holdover - Loss of Lock
Holdover - Loss of Source
PLL2 Lock Detect
[3]
[2]
[1]
[0]
PLL1 Lock Detect
9.6.2.159 PLL2_DLD_EN
The PLL2_DLD_EN Register supports PLL2 DLD EN Feature Back to Register Map.
Table 183. Register - 0xF6
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RSRVD
RW
0
Reserved
Enable for PLL2 DLD
0: Non PLL2 modes
1: PLL2 DLD enabled
[1]
PLL2_DLD_EN
RW
0
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Table 183. Register - 0xF6 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[0]
RSRVD
FW
0
Reserved
9.6.2.160 PLL2_DUAL_LOOP
The PLL2_DUAL_LOOP Register supports Dual Loop Feature Back to Register Map.
Table 184. Register - 0xF7
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
R
0
Reserved.
Dual Loop enable
0x0: Non-Dual Loop mode
0x1: Reserved
0x2: Reserved
0x3: Dual Loop mode
[6:5]
[4:0]
PLL2_DUAL_LOOP_EN
RSRVD
RW
RW
0
0
Reserved.
9.6.2.161 CH01_DDLY_BY0
Register CH01_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 185. Register - 0xFD
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH01_DDLY[7:0]
RW
0x0
9.6.2.162 CH23_DDLY_BY0
Register CH23_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 186. Register - 0xFF
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH23_DDLY[7:0]
RW
0x0
9.6.2.163 CH45_DDLY_BY0
Register CH45_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 187. Register - 0x101
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH45_DDLY[7:0]
RW
0x0
9.6.2.164 CH67_DDLY_BY0
Register CH67_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 188. Register - 0x103
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH67_DDLY[7:0]
RW
0x0
106
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9.6.2.165 CH89_DDLY_BY0
Register CH89_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 189. Register - 0x105
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH89_DDLY[7:0]
RW
0x0
9.6.2.166 CH1011_DDLY_BY0
Register CH1011_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 190. Register - 0x107
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH1011_DDLY[7:0]
RW
0x0
9.6.2.167 CH1213_DDLY_BY0
Register CH1213_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 191. Register - 0x109
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH1213_DDLY[7:0]
RW
0x0
9.6.2.168 CH1415_DDLY_BY0
Register CH1415_DDLY_BY0 provides control of the following JESD204B control signals Back to Register Map.
Table 192. Register - 0x10B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
[7:0]
CH1415_DDLY[7:0]
RW
0x0
9.6.2.169 OUTCH0_JESD_CTRL
Register OUTCH0_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 193. Register - 0x10C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH0_ADLY[4:0]
RW
0x0
[1]
[0]
CH0_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 0.
Reserved.
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9.6.2.170 OUTCH1_JESD_CTRL
Register OUTCH1_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 194. Register - 0x10D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH1_ADLY[4:0]
RW
0x0
[1]
[0]
CH1_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 1.
Reserved.
9.6.2.171 OUTCH2_JESD_CTRL
Register OUTCH2_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 195. Register - 0x10E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH2_ADLY[4:0]
RW
0x0
[1]
[0]
CH2_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 2.
Reserved.
9.6.2.172 OUTCH3_JESD_CTRL
Register OUTCH3_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 196. Register - 0x10F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH3_ADLY[4:0]
RW
0x0
[1]
[0]
CH3_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 3.
Reserved.
9.6.2.173 OUTCH4_JESD_CTRL
Register OUTCH4_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 197. Register - 0x110
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH4_ADLY[4:0]
RW
0x0
[1]
[0]
CH4_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 4.
Reserved.
108
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9.6.2.174 OUTCH5_JESD_CTRL
Register OUTCH5_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 198. Register - 0x111
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH5_ADLY[4:0]
RW
0x0
[1]
[0]
CH5_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 5.
Reserved.
9.6.2.175 OUTCH6_JESD_CTRL
Register OUTCH6_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 199. Register - 0x112
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH6_ADLY[4:0]
RW
0x0
[1]
[0]
CH6_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 6.
Reserved.
9.6.2.176 OUTCH7_JESD_CTRL
Register OUTCH7_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 200. Register - 0x113
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH7_ADLY[4:0]
RW
0x0
[1]
[0]
CH7_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 7.
Reserved.
9.6.2.177 OUTCH8_JESD_CTRL
Register OUTCH8_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 201. Register - 0x114
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH8_ADLY[4:0]
RW
0x0
[1]
[0]
CH8_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 8.
Reserved.
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9.6.2.178 OUTCH9_JESD_CTRL
Register OUTCH9_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 202. Register - 0x115
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH9_ADLY[4:0]
RW
0x0
[1]
[0]
CH9_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 9.
Reserved.
9.6.2.179 OUTCH10_JESD_CTRL
Register OUTCH10_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 203. Register - 0x116
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH10_ADLY[4:0]
RW
0x0
[1]
[0]
CH10_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 10.
Reserved.
9.6.2.180 OUTCH11_JESD_CTRL
Register OUTCH11_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 204. Register - 0x117
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH11_ADLY[4:0]
RW
0x0
[1]
[0]
CH11_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 11.
Reserved.
9.6.2.181 OUTCH12_JESD_CTRL
Register OUTCH12_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 205. Register - 0x118
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH12_ADLY[4:0]
RW
0x0
[1]
[0]
CH12_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 12.
Reserved.
110
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9.6.2.182 OUTCH13_JESD_CTRL
Register OUTCH13_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 206. Register - 0x119
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH13_ADLY[4:0]
RW
0x0
[1]
[0]
CH13_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 13.
Reserved.
9.6.2.183 OUTCH14_JESD_CTRL
Register OUTCH14_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 207. Register - 0x11A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH14_ADLY[4:0]
RW
0x0
[1]
[0]
CH14_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 14.
Reserved.
9.6.2.184 OUTCH15_JESD_CTRL
Register OUTCH15_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
Table 208. Register - 0x11B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[6:2]
CH15_ADLY[4:0]
RW
0x0
[1]
[0]
CH15_ADLY_EN
RSRVD
RW
-
0
-
Enables Analog Delay for Channel 15.
Reserved.
9.6.2.185 CLKMUXVECTOR
The CLKMUXVECTOR Register reflects the current status of the RefClk Mux Back to Register Map.
Table 209. Register - 0x124
BIT NO.
[7:4]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
-
[3:0]
CLKMUX[3:0]
R
0x0
CLKmux status.
9.6.2.186 OUTCH01CNTL2
The OUTCH01CNTRL2 Register controls Output CH0_1 Back to Register Map.
Table 210. Register - 0x127
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH0_1
[7]
RW
0
Bypass CH0_1 Dynamic Digital Delay Gating
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Table 210. Register - 0x127 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_ANALOGDLY
_GATING_CH0_1
[6]
RW
0
Bypass CH0_1 Analog Delay Gating
[5]
[4]
SYNC_EN_CH0_1
HS_EN_CH0_1
RW
RW
RW
RW
0
Output CH0_1 SYNC Enable
Output CH0_1 Enable Half-cycle delay
Slew Rate Setting OUTCH1.
0
[3:2]
[1:0]
DRIV_1_SLEW[1:0]
DRIV_0_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH0.
9.6.2.187 OUTCH23CNTL2
The OUTCH23CNTRL2 Register controls Output CH2_3 Back to Register Map.
Table 211. Register - 0x128
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH2_3
[7]
RW
0
Bypass CH2_3 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH2_3
[6]
RW
0
Bypass CH2_3 Analog Delay Gating
[5]
[4]
SYNC_EN_CH2_3
HS_EN_CH2_3
RW
RW
RW
RW
0
Output CH2_3 SYNC Enable
Output CH2_3 Enable Half-cycle delay
Slew Rate Setting OUTCH3.
0
[3:2]
[1:0]
DRIV_3_SLEW[1:0]
DRIV_2_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH2.
9.6.2.188 OUTCH45CNTL2
The OUTCH45CNTRL2 Register controls Output CH4_5 Back to Register Map.
Table 212. Register - 0x129
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH4_5
[7]
RW
0
Bypass CH4_5 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH4_5
[6]
RW
0
Bypass CH4_5 Analog Delay Gating
[5]
[4]
SYNC_EN_CH4_5
HS_EN_CH4_5
RW
RW
RW
RW
0
Output CH4_5 SYNC Enable
Output CH4_5 Enable Half-cycle delay
Slew Rate Setting OUTCH5.
0
[3:2]
[1:0]
DRIV_5_SLEW[1:0]
DRIV_4_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH4.
9.6.2.189 OUTCH67CNTL2
The OUTCH67CNTRL2 Register controls Output CH6_7 Back to Register Map.
Table 213. Register - 0x12A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH6_7
[7]
RW
0
Bypass CH6_7 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH6_7
[6]
RW
0
Bypass CH6_7 Analog Delay Gating
[5]
[4]
SYNC_EN_CH6_7
HS_EN_CH6_7
RW
RW
RW
RW
0
Output CH6_7 SYNC Enable
Output CH6_7 Enable Half-cycle delay
Slew Rate Setting OUTCH7.
0
[3:2]
[1:0]
DRIV_7_SLEW[1:0]
DRIV_6_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH6.
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9.6.2.190 OUTCH89CNTL2
The OUTCH89CNTRL2 Register controls Output CH8_9 Back to Register Map.
Table 214. Register - 0x12B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH8_9
[7]
RW
0
Bypass CH8_9 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH8_9
[6]
RW
0
Bypass CH8_9 Analog Delay Gating
[5]
[4]
SYNC_EN_CH8_9
HS_EN_CH8_9
RW
RW
RW
RW
0
Output CH8_9 SYNC Enable
Output CH8_9 Enable Half-cycle delay
Slew Rate Setting OUTCH9.
0
[3:2]
[1:0]
DRIV_9_SLEW[1:0]
DRIV_8_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH8.
9.6.2.191 OUTCH1011CNTL2
The OUTCH1011CNTRL2 Register controls Output CH10_11 Back to Register Map.
Table 215. Register - 0x12C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH10_11
[7]
RW
0
Bypass CH10_11 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH10_11
[6]
RW
0
Bypass CH10_11 Analog Delay Gating
[5]
[4]
SYNC_EN_CH10_11
HS_EN_CH10_11
RW
RW
RW
RW
0
Output CH10_11 SYNC Enable
Output CH10_11 Enable Half-cycle delay
Slew Rate Setting OUTCH11.
0
[3:2]
[1:0]
DRIV_11_SLEW[1:0]
DRIV_10_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH10.
9.6.2.192 OUTCH1213CNTL2
The OUTCH1213CNTRL2 Register controls Output CH12_13 Back to Register Map.
Table 216. Register - 0x12D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH12_13
[7]
RW
0
Bypass CH12_13 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH12_13
[6]
RW
0
Bypass CH12_13 Analog Delay Gating
[5]
[4]
SYNC_EN_CH12_13
HS_EN_CH12_13
RW
RW
RW
RW
0
Output CH12_13 SYNC Enable
Output CH12_13 Enable Half-cycle delay
Slew Rate Setting OUTCH13.
0
[3:2]
[1:0]
DRIV_13_SLEW[1:0]
DRIV_12_SLEW[1:0]
0x0
0x0
Slew Rate Setting OUTCH12.
9.6.2.193 OUTCH1415CNTL2
The OUTCH1415CNTRL2 Register controls Output CH14_15 Back to Register Map.
Table 217. Register - 0x12E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYSREF_BYP_DYNDIGDLY
_GATING_CH14_15
[7]
RW
0
Bypass CH14_15 Dynamic Digital Delay Gating
SYSREF_BYP_ANALOGDLY
_GATING_CH14_15
[6]
[5]
RW
RW
0
0
Bypass CH14_15 Analog Delay Gating
Output CH14_15 SYNC Enable
SYNC_EN_CH14_15
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Table 217. Register - 0x12E (continued)
BIT NO.
[4]
FIELD
TYPE
RW
RESET
0
DESCRIPTION
HS_EN_CH14_15
DRIV_15_SLEW[1:0]
DRIV_14_SLEW[1:0]
Output CH14_15 Enable Half-cycle delay
Slew Rate Setting OUTCH15.
[3:2]
RW
0x0
[1:0]
RW
0x0
Slew Rate Setting OUTCH14.
9.6.2.194 OUTCH0_JESD_CTRL1
The OUTCH0_JESD_CTRL1 Register controls Output CH0 Back to Register Map.
Table 218. Register - 0x12F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH0[2:0]
RW
0x0
9.6.2.195 OUTCH1_JESD_CTRL1
The OUTCH1_JESD_CTRL1 Register controls Output CH1 Back to Register Map.
Table 219. Register - 0x130
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH1[2:0]
RW
0x0
9.6.2.196 OUTCH2_JESD_CTRL1
The OUTCH2_JESD_CTRL1 Register controls Output CH2 Back to Register Map.
Table 220. Register - 0x131
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH2[2:0]
RW
0x0
9.6.2.197 OUTCH3_JESD_CTRL1
The OUTCH3_JESD_CTRL1 Register controls Output CH3 Back to Register Map.
Table 221. Register - 0x132
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH3[2:0]
RW
0x0
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9.6.2.198 OUTCH4_JESD_CTRL1
The OUTCH4_JESD_CTRL1 Register controls Output CH4 Back to Register Map.
Table 222. Register - 0x133
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH4[2:0]
RW
0x0
9.6.2.199 OUTCH5_JESD_CTRL1
The OUTCH5_JESD_CTRL1 Register controls Output CH5 Back to Register Map.
Table 223. Register - 0x134
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH5[2:0]
RW
0x0
9.6.2.200 OUTCH6_JESD_CTRL1
The OUTCH6_JESD_CTRL1 Register controls Output CH6 Back to Register Map.
Table 224. Register - 0x135
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH6[2:0]
RW
0x0
9.6.2.201 OUTCH7_JESD_CTRL1
The OUTCH7_JESD_CTRL1 Register controls Output CH7 Back to Register Map.
Table 225. Register - 0x136
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH7[2:0]
RW
0x0
9.6.2.202 OUTCH8_JESD_CTRL1
The OUTCH8_JESD_CTRL1 Register controls Output CH8 Back to Register Map.
Table 226. Register - 0x137
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH8[2:0]
RW
0x0
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9.6.2.203 OUTCH9_JESD_CTRL1
The OUTCH9_JESD_CTRL1 Register controls Output CH9 Back to Register Map.
Table 227. Register - 0x138
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH9[2:0]
RW
0x0
9.6.2.204 OUTCH10_JESD_CTRL1
The OUTCH10_JESD_CTRL1 Register controls Output CH10 Back to Register Map.
Table 228. Register - 0x139
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH10[2:0]
RW
0x0
9.6.2.205 OUTCH11_JESD_CTRL1
The OUTCH11_JESD_CTRL1 Register controls Output CH11 Back to Register Map.
Table 229. Register - 0x13A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH11[2:0]
RW
0x0
9.6.2.206 OUTCH12_JESD_CTRL1
The OUTCH12_JESD_CTRL1 Register controls Output CH12 Back to Register Map.
Table 230. Register - 0x13B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH12[2:0]
RW
0x0
9.6.2.207 OUTCH13_JESD_CTRL1
The OUTCH13_JESD_CTRL1 Register controls Output CH13 Back to Register Map.
Table 231. Register - 0x13C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH13[2:0]
RW
0x0
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9.6.2.208 OUTCH14_JESD_CTRL1
The OUTCH14_JESD_CTRL1 Register controls Output CH14 Back to Register Map.
Table 232. Register - 0x13D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH14[2:0]
RW
0x0
9.6.2.209 OUTCH15_JESD_CTRL1
The OUTCH15_JESD_CTRL1 Register controls Output CH15 Back to Register Map.
Table 233. Register - 0x13E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH15[2:0]
RW
0x0
9.6.2.210 SYSREF_PLS_CNT
Sysref Pulse Count Configuration Back to Register Map.
Table 234. Register - 0x140
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
OUTCH_SYSREF_PLSCNT[
5:0]
Set number of desired sysref pulses. 0 Enables continuous
sysref.
[5:0]
RW
0x0
9.6.2.211 SYNCMUX
The SYNCMUX Register controls the status signal that is routed to the SYNC output. Back to Register Map.
Table 235. Register - 0x141
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
SYNC Integrated Mux Select.
SYNC_INT_MUX - SYNC Output
0 - PLL1 Lock Detect and PLL2 Lock Detect
1 - PLL1 Lock Detect
2 - PLL2 Lock Detect
3 - CLKINBLK LOS
4 - SPI Output Data
5 - Reserved
6 - Reserved
7 - Reserved
8 - HOLDOVER_EN
[7:0]
SYNC_INT_MUX[7:0]
RW
0x4
9 - Mirror of SYNC_INPUT
10 - Mirror of CLKINSEL1 INPUT
11 - Reserved
12 - Reserved
13 - PLL2 Reference Clock
14 - Reserved
15 - PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16 - PLL1 Lock Detect and not PLL1 Holdover
17 - Logic 1
18 - Logic 0
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9.6.2.212 IOTEST_SYNC
The IOTEST_SYNC Register provides control of the SYNC driver and test features. Back to Register Map.
Table 236. Register - 0x142
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
SYNC Output Driver High Impedance. When
SYNC_OUTPUT_HIZ is set to 1 the SYNC output driver
stage is disabled.
[6]
[5]
[4]
SYNC_OUTPUT_HIZ
SYNC_ENB_INSTAGE
SYNC_EN_ML_INSTAGE
RW
RW
RW
1
1
1
SYNC Input Stage Enable BAR. When SYNC_INPUT_ENB
is 0 the SYNC Input stage is enabled. When
SYNC_INPUT_ENB is set to 1 the SYNC input stage is
disabled.
SYNC Input Stage Enable Multi-level. When
SYNC_INPUT_ENML is 1 the input stage is configured for
multi-level mode.
[3]
[2]
RSRVD
-
-
Reserved.
SYNC Output Data. Set the SYNC output data value when
SYNC_IOTESTEN is 1.
SYNC_OUTPUT_DATA
RW
0
SYNC Input Y12 Value. Indicates the logic level present on
the SYNC Y12 pin.
[1]
[0]
SYNC_INPUT_Y12
SYNC_INPUT_M12
R
R
0
0
SYNC Input M12 Value. Indicates the logic level present on
the SYNC M12 pin.
9.6.2.213 OUTCH_ZDM
Low Skew Feedback Buffer Settings Back to Register Map.
Table 237. Register - 0x143
BIT NO.
[7:5]
[4]
FIELD
RSRVD
TYPE
RESET
DESCRIPTION
Reserved.
-
-
0
-
FBBUF_CH6_EN
RSRVD
RW
-
Enable Channel 6 Zero Delay Mode FBClock Buffer
Reserved.
[3:1]
[0]
FBBUF_CH9_EN
RW
0
Enable Channel 9 Zero Delay Mode FBClock Buffer
9.6.2.214 PLL2_CTRL3
The PLL2_CTRL3 Register provides control of PLL2 features. Back to Register Map.
Table 238. Register - 0x146
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
Enable By-2 Divider in PLL2 Feedback.
nbypass_div2_fb - PLL2 Feedback by-2 Divider
0 - Divider Off
[6]
PLL2_NBYPASS_DIV2_FB
PLL2_PRESCALER[3:0]
RW
RW
0
1 - Divider On
PLL2 VCO Prescaler Configuration.
PLL2_PRESCALER - Effect
00XX - PLL2 VCO Prescaler DIV3
01XX - PLL2 VCO Prescaler DIV4
10XX - PLL2 VCO Prescaler DIV5
11XX - PLL2 VCO Prescaler DIV6
[5:2]
0x0
PLL2 Feedback MUX control.
PLL2_FBDIV_MUXSEL - Effect
[1:0]
PLL2_FBDIV_MUXSEL[1:0]
RW
0x0
00 - Feedback Prescaler Output
01 - Feedback OUTCH9 Output (Zero Delay Mode)
10 - Feedback OUTCH6 Output (Zero Delay Mode)
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9.6.2.215 PLL1_HOLDOVER_CTRL0
The PLL1_HOLDOVER_CTRL0 Register selects the GPIO pin to use to force Holdover mode. Back to Register
Map.
Table 239. Register - 0x149
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
PLL1_CLKINSEL1_ML_HOL
DOVER
[3]
[2]
[1]
RW
RW
RW
0
0
0
Force holdover by applying mid-level at CLKINSEL1.
Force holdover by applying high-level at SYNC.
Force holdover by applying high-level at STATUS1.
PLL1_SYNC_HOLDOVER
PLL1_STATUS1_HOLDOVE
R
PLL1_STATUS0_HOLDOVE
R
[0]
RW
0
Force holdover by applying high-level at STATUS0.
9.6.2.216 IOCTRL_SYNC_1
The IOCTRL_SYNC_1 Register provides control of SYNC Input features. Back to Register Map.
Table 240. Register - 0x14A
BIT NO.
[7]
FIELD
TYPE
-
RESET
DESCRIPTION
Reserved.
RSRVD
-
0x0
0
[6:2]
[1]
SYNC_ANALOGDLY[4:0]
SYNC_ANALOGDLY_EN
RW
RW
SYNC input Analog Delay.
Enable Analog Delay at SYNC input.
SYNC_IN Invert.
SYNC_INV - Polarity
0 - Not inverted
1 - Inverted
[0]
SYNC_INV
RW
0
9.6.2.217 OUTCH_TOP_JESD_CTRL
OUTCH_TOP_JESD_CTRL controls JESD functions for TOP output channels. Back to Register Map.
Table 241. Register - 0x14B
BIT NO.
[7]
FIELD
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
DESCRIPTION
DYN_DDLY_CH15_EN
DYN_DDLY_CH14_EN
DYN_DDLY_CH13_EN
DYN_DDLY_CH12_EN
DYN_DDLY_CH11_EN
DYN_DDLY_CH10_EN
DYN_DDLY_CH9_EN
DYN_DDLY_CH8_EN
0
0
0
0
0
0
0
0
Enable CH15 Dynamic Digital Delay.
Enable CH14 Dynamic Digital Delay.
Enable CH13 Dynamic Digital Delay.
Enable CH12 Dynamic Digital Delay.
Enable CH11 Dynamic Digital Delay.
Enable CH10 Dynamic Digital Delay.
Enable CH9 Dynamic Digital Delay.
Enable CH8 Dynamic Digital Delay.
[6]
[5]
[4]
[3]
[2]
[1]
[0]
9.6.2.218 OUTCH_BOT_JESD_CTRL
OUTCH_BOT_JESD_CTRL controls JESD functions for BOTTOM output channels. Back to Register Map.
Table 242. Register - 0x14C
BIT NO.
[7]
FIELD
TYPE
RW
RESET
DESCRIPTION
DYN_DDLY_CH7_EN
DYN_DDLY_CH6_EN
DYN_DDLY_CH5_EN
DYN_DDLY_CH4_EN
0
0
0
0
Enable CH7 Dynamic Digital Delay.
Enable CH6 Dynamic Digital Delay.
Enable CH5 Dynamic Digital Delay.
Enable CH4 Dynamic Digital Delay.
[6]
RW
[5]
RW
[4]
RW
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Table 242. Register - 0x14C (continued)
BIT NO.
[3]
FIELD
TYPE
RW
RESET
DESCRIPTION
DYN_DDLY_CH3_EN
DYN_DDLY_CH2_EN
DYN_DDLY_CH1_EN
DYN_DDLY_CH0_EN
0
0
0
0
Enable CH3 Dynamic Digital Delay.
Enable CH2 Dynamic Digital Delay.
Enable CH1 Dynamic Digital Delay.
Enable CH0 Dynamic Digital Delay.
[2]
RW
[1]
RW
[0]
RW
9.6.2.219 OUTCH_JESD_CTRL1
OUTCH_TOP_JESD_CTRL controls JESD functions for TOP output channels. Back to Register Map.
Table 243. Register - 0x14E
BIT NO.
[7]
FIELD
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
DESCRIPTION
SYSREF_EN_CH14_15
SYSREF_EN_CH12_13
SYSREF_EN_CH10_11
SYSREF_EN_CH8_9
SYSREF_EN_CH6_7
SYSREF_EN_CH4_5
SYSREF_EN_CH2_3
SYSREF_EN_CH0_1
0
0
0
0
0
0
0
0
Enable CH14_15 Sysref feature.
Enable CH12_13 Sysref feature.
Enable CH10_11 Sysref feature.
Enable CH8_9 Sysref feature.
Enable CH6_7 Sysref feature.
Enable CH4_5 Sysref feature.
Enable CH2_3 Sysref feature.
Enable CH0_1 Sysref feature.
[6]
[5]
[4]
[3]
[2]
[1]
[0]
9.6.2.220 PLL2_CTRL4
PLL2 CTRL4 Register sets PLL2 configuration. Back to Register Map.
Table 244. Register - 0x150
BIT NO.
[7:4]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[3]
PLL2_PFD_DIS_SAMPLE
RW
0
Disable PFD Sampling.
PLL2_PROG_PFD_RESET[2
:0]
[2:0]
RW
0x0
Programmable PFD reset.
9.6.2.221 PLL2_CTRL5
PLL2 CTRL5 Register sets PLL2 configuration. Back to Register Map.
Table 245. Register - 0x151
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
0-> 9.2kOhm
1->4.7kOhm
[4]
[3]
PLL2_RFILT
RSRVD
RW
-
0
-
Reserved.
PLL2_CP_EN_SAMPLE_BY
P
[2]
RW
RW
0
Bypass PLL2 Chargepump sampling.
Set Cap prior Sampling.
[1:0]
PLL2_CPROP[1:0]
0x0
9.6.2.222 PLL2_CTRL6
PLL2 CTRL6 Register sets PLL2 configuration. Back to Register Map.
Table 246. Register - 0x152
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
120
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Table 246. Register - 0x152 (continued)
BIT NO.
[3]
FIELD
TYPE
RW
RESET
0
DESCRIPTION
PLL2_EN_FILTER
PLL2_CSAMPLE[2:0]
Enable PLL2 Chargepump Filter.
PLL2 Set Cap After sampling.
[2:0]
RW
0x0
9.6.2.223 PLL2_CTRL7
PLL2 CTRL7 Register sets PLL2 configuration. Back to Register Map.
Table 247. Register - 0x153
BIT NO.
[7:5]
FIELD
RSRVD
TYPE
-
RESET
DESCRIPTION
Reserved.
-
[4:0]
PLL2_CFILT
RW
0
0 to 124pF in 4pF steps
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
To assist customers in frequency planning and design of loop filters Texas Instrument's provides the Clock
Design Tool and Clock Architect.
10.1.1 Digital Lock Detect Frequency Accuracy
The digital lock detect circuit is used to determine PLL1 locked and PLL2 locked. A window size and lock count
register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each
event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true.
EVENT
PLL
WINDOW SIZE
LOCK COUNT
PLL1 Lock
PLL1
PLL1_LD_WNDW_SIZE
PLL1_LOCKDET_CYC_CNT * (1 + (31 * PLL1_LCKDET_BY_32))
PLL2 Lock
(Initial)
PLL2_LD_WNDW_SIZE_INITIAL =
1 ns
PLL2
PLL2
PLL2_LOCKDET_CYC_CNT_INITIAL
PLL2_LOCKDET_CYC_CNT
PLL2 Lock
PLL2_LD_WNDW_SIZE = 1 ns
For a digital lock detect event to occur there must be a lock count number of a count frequency during which the
time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable
window size. Because there must be at least lock count number of count frequency cycles, a minimum digital
lock detect assert time can be calculated as lock count / count frequency where count frequency = PLL2 phase
detector frequency. PLL2 lock time is the sum of the PLL2 Lock (Initial) + PLL2 Lock time.
By using Equation 1, values for a lock count and window size can be chosen to set the frequency accuracy
required by the system in ppm before the digital lock detect event occurs:
1e6 × WINDOW SIZE × COUNT FREQUENCY
ppm =
LOCK COUNT
(1)
The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by
lock count.
If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window
size, then the lock count value is reset to 0.
10.1.1.1 Minimum Lock Time Calculation Example
To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 245.76 MHz,
PLL2_LOCK_DET_CYC_CNT_INITAL = 32768, and PLL2_LOCK_DET_CYC_CNT = 16384. Then the minimum
digital lock time assert time of PLL2 is PLL2 Lock time (Initial) + PLL2 Lock time = (32768 / 245.76 MHz) +
(16384 / 245.76 MHz) = 200 µs.
122
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10.2 Typical Application
Normal use case of the LMK04616 device is as a dual loop jitter cleaner. This section will discuss a design
example to illustrate the various functional aspects of the LMK04616 device.
PLL1
PLL2
External
VCXO
CLKinX
CLKinX*
OSCout
R
N
Divider
Phase
Detector
PLL1
OSCout*
Integrated
Loop Filter
4 inputs
Internal VCO
R
N
16 Device/Sysref
Clocks
Phase
Detector
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
Pre
Div
Integrated
Loop Filter
CLKoutX*
CLKoutX
8 blocks
LMK04616
Copyright © 2017, Texas Instruments Incorporated
Figure 59. Simplified Functional Block Diagram for Dual-Loop Mode
10.2.1 Design Requirements
Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES,
and an LO. The input clock is a recovered clock which needs jitter cleaning. The FPGA clock should have a
clock output on power up. A summary of clock input and output requirements are as follows:
Clock Input:
•
122.88-MHz recovered clock.
Clock Outputs:
•
•
•
•
1x 245.76-MHz clock for ADC
2x 983.04-MHz clock for DAC
2x 122.88-MHz clock for FPGA
1x 122.88-MHz clock for SERDES
It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The
following information reviews the steps to produce this design.
If JESD204B support is also required for the clock outputs, see JEDEC JESD204B for more details.
10.2.2 Detailed Design Procedure
Design of all aspects of the LMK04616 are quite involved and software has been written to assist in part
selection and part programming. Contact TI for optimized loop filter settings based on the system requirement.
This design procedure gives a quick outline of the process.
NOTE
This information is current as of the date of the release of this data sheet. Design tools
receive continuous improvements to add features and improve model accuracy. Refer to
software instructions or training for latest features.
1. Device Selection
–
–
–
The key to device selection is required VCO frequency given required output frequencies. The device
must be able to produce the VCO frequency that can be divided down to required output frequencies.
The software design tools take the VCO frequency range into account for specific devices based on the
application's required output frequencies.
To understand the process better, see the Detailed Description which provides more insight into the
functional blocks and programming options.
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Typical Application (continued)
2. Device Configuration
There are many possible permutations of dividers and other registers to get same input and output
frequencies from a device. However, consider that there are some optimizations and trade-offs. It is possible,
although not assured, that some crosstalk and mixing could be created when using some divides.
–
The optimum setting attempts to maximize phase detector frequency and uses the smallest dividers
settings.
–
–
For lowest possible in-band PLL noise, maximize phase detector frequency to minimize N divide value.
As rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop bandwidth
and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be
unstable and a phase detector frequency > 100 × loop bandwidth may experience increased lock time
due to cycle slipping. However, for clock generation and jitter cleaning applications, lock time is typically
not critical and large phase detector frequencies typically result in reduced PLL noise, so cycle-slipping
during lock is acceptable.
10.2.2.1 PLL Loop Filter Design
Contact TI with the application requirements to get the optimized loop filter settings.
10.2.2.2 Clock Output Assignment
It is best to consider proximity of each clock output to each other and other PLL circuitry when choosing final
clock output locations. Here are some guidelines to help achieve best performance when assigning outputs to
specific CLKout/OSCout pins.
•
•
Group common frequencies together.
Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output from
OSCout/OSCout* for such a clock target.
•
Some clock targets require excellent noise floor performance. Outputs driven by the internal LC-VCO have
the best noise floor performance. An example is an ADC or DAC.
Other device specific configuration. For LMK04616, consider the following:
•
Holdover Configuration
LMK04616 provides the option to have two clock inputs. The clock priority, clock loss detection, holdover, and
loss recovery can be programmed. See Holdover for more details.
•
JESD204B support
To generate JESD204B compliant clocks, see JEDEC JESD204B for more details.
Digital delay: phase alignment of the output clocks.
Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase noise
floor.
•
•
10.2.2.3 Calculation Using LCM
In this example, the LCM (245.76 MHz, 983.04 MHz, 122.88 MHz) = 983.04 MHz. A valid VCO frequency for
LMK04616 is 5898.24 MHz = 6 × 983.04 MHz. Therefore, the LMK04616 may be used to produce these output
frequencies.
10.2.2.4 Device Programming
The software tool TICS Pro for EVM programming can be used to set up the device in the desired configuration,
then export a hex register map suitable for use in applications.
10.2.2.5 Device Selection
Use the WEBENCH Clock Architect Tool and enter the required frequencies and formats into the tool. To use
this device, find a solution using the LMK04616.
124
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Typical Application (continued)
10.2.2.6 Clock Architect
When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter. Filtering
of a specific device can be done by selecting the device from the filter combo box. Also, regular expressions can
be typed into filter combo box. LMK04616 will only filter for the LMK04616 device.
10.2.3 Application Curves
Table 248 lists the application curves for this device.
Table 248. Table of Graphs
FIGURE
LMK04616 CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 122.88 MHz
Figure 2
HSDS 8 mA
LMK04616 CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 245.76 MHz
Figure 4
HSDS 8 mA
LMK04616 CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 983.04 MHz
Figure 5
HSDS 8 mA
10.3 Do's and Don'ts
10.3.1 Pin Connection Recommendations
•
•
•
VCC Pins and Decoupling: all VCC pins must always be connected.
Unused Clock Outputs: leave unused clock outputs floating and powered down.
Unused Clock Inputs: unused clock inputs can be left floating.
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11 Power Supply Recommendations
11.1 Recommended Power Supply Connection
Figure 60 shows the recommended power supply connection using a low-noise LDO and a DC-DC converter.
LMK0461x
Clean 3.3V
VDD_PLL2OSC
LDO
3.3V
VDD_PLL1
3.3V
VDD_CORE
3.3V
VDD_PLL2CORE
3.3V
1.8V
VDD_OSC
DC-DC
1.8V - 3.3V
VDD_IO
1.8V - 3.3V
VDDO_0..7
1.8V - 3.3V
Copyright © 2017, Texas Instruments Incorporated
Figure 60. Recommended Power Supply Connection
11.2 Current Consumption / Power Dissipation Calculations
From Table 249 the current consumption can be calculated for any configuration. Data below is typical and not
assured.
Table 249. Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V)
POWER
DISSIPATED
IN DEVICE
(mW)
POWER
DISSIPATED
EXTERNALLY
(mW)
TYPICAL ICC
(mA)
BLOCK
TEST CONDITIONS
CORE AND FUNCTIONAL BLOCKS
PLL1
PLL1 locked
14.5
44
60
1.8
0.1
1.5
1.2
1.5
0
47.85
145.2
198
3.24
0.33
3.24
2.16
2.7
-
-
PLL2
PLL2 locked
VCO
VCO (with VCO divider)
LOS
LOS enabled
PLL1 Regulation
OSCin Doubler
Doubler is enabled
EN_PLL2_REF_2X = 1
Single-Ended Mode
Differential Mode
-
-
Any one of the CLKinX
is enabled
CLKinX
Holdover
Holdover is enabled
HOLDOVER_EN = 1
0
-
-
SYNC_EN = 1
Required for SYNC and SYSREF functionality
0
0
126
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Current Consumption / Power Dissipation Calculations (continued)
Table 249. Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V) (continued)
POWER
POWER
DISSIPATED
EXTERNALLY
(mW)
TYPICAL ICC
(mA)
DISSIPATED
IN DEVICE
(mW)
BLOCK
TEST CONDITIONS
Enabled
SYSREF_PD = 0
0
0
-
Dynamic Digital Delay
enabled
SYSREF_DDLY_PD = 0
3.5
6.3
-
SYSREF
Pulser is enabled
SYSREF_PLSR_PD = 0
SYSREF_MUX = 2
0
0
0
0
SYSREF Pulses mode
SYSREF Continuous
mode
SYSREF_MUX = 3
0
0
Static Digital Delay
0
0
0
Static Digital Delay + Half step
Dynamic Digital Delay
Analog Delay
0
Output channel
3.5
2.5
0.2
6.3
4.8
0.36
Analog Delay per Step
CLOCK OUTPUT BUFFERS
HCSL
50 Ω to Ground termination
HSDS 4 mA
19
5
34.2
9
-
-
-
-
HSDS
HSDS 6 mA
7
12.6
16.2
HSDS 8 mA
9
OSCout BUFFERS
HCSL
50 Ω to Ground termination
19
9
34.2
16.2
9
-
HSDS
HSDS 8 mA
LVCMOS Pair
150 MHz
150 MHz
5
-
-
LVCMOS
LVCMOS Single
2.5
4.5
12 Layout
12.1 Layout Guidelines
Power consumption of the LMK0461x family of devices can be high enough to require attention to thermal
management. For reliability and performance reasons the die temperature should be limited to a maximum of
125°C.
12.1.1 CLKin and OSCin
If differential input (preferred) is used route traces tightly coupled. If single-ended, have at least 3 trace width (of
CLKin or OSCin trace) separation from other RF traces. Place terminations close to IC.
12.1.2 CLKout
Normally differential signals must be routed tightly coupled to minimize PCB crosstalk. Trace impedance and
terminations must be designed accord to output type being used. Unused outputs must be left open and
programmed to power-down state.
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12.2 Layout Example
Figure 61. Recommended PCB Layout
1. CLKin and OSCin path:
–
If differential input (preferred), route traces tightly coupled. If single ended, have at least 3 trace width (of
CLKin/OSCin trace) separation from other RF traces.
2. CLKouts/OSCout:
Normally differential signals should be routed tightly coupled to minimize PCB crosstalk. Trace impedance
–
must be designed according to 100-Ω differential. For optimal isolation place different clock group signals
on different layers.
3. VCXO connection
–
Shorter traces are better. Place a resistors and capacitors closer to IC except for a single capacitor and
associated resistor, if any, next to VCXO. If any, place loop filter components close to VCXO Vtune pin.
128
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13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
13.1.1.1 时钟设计工具
如需时钟设计工具,请访问 www.ti.com.cn/tool/cn/clockdesigntool。
13.1.1.2 时钟架构
部件选择、环路滤波器设计、仿真。
如需时钟架构,请访问 www.ti.com/clockarchitect。
13.1.1.3 TICS Pro
EVM 编程软件。还可用于生成寄存器映射,以便为特定的应用进行编程。
如需 TICS Pro,请访问 www.ti.com.cn/tool/cn/TICSPRO-SW。
13.2 接收文档更新通知
如需接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收
产品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
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129
PACKAGE OPTION ADDENDUM
www.ti.com
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK04616ZCRR
LMK04616ZCRT
ACTIVE
ACTIVE
NFBGA
NFBGA
ZCR
ZCR
144
144
1000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LMK04616
LMK04616
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK04616ZCRR
LMK04616ZCRT
NFBGA
NFBGA
ZCR
ZCR
144
144
1000
250
330.0
178.0
24.4
24.4
10.25 10.25 2.25
10.25 10.25 2.25
16.0
16.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK04616ZCRR
LMK04616ZCRT
NFBGA
NFBGA
ZCR
ZCR
144
144
1000
250
367.0
213.0
367.0
191.0
45.0
55.0
Pack Materials-Page 2
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Copyright © 2022,德州仪器 (TI) 公司
相关型号:
LMK04805BISQE/NOPB
Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO 64-WQFN -40 to 85
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