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LMK04821, LMK04826, LMK04828

SNAS605AS –MARCH 2013–REVISED MAY 2020

LMK0482x Ultra Low-Noise JESD204B Compliant

Clock Jitter Cleaner With Dual Loop PLLs

1 Features

2 Applications

1

•

JEDEC JESD204B Support

Ultra-Low RMS Jitter

•

Wireless Infrastructure

Data Converter Clocking

Networking, SONET/SDH, DSLAM

Medical / Video / Military / Aerospace

Test and Measurement

–

88 fs RMS Jitter (12 kHz to 20 MHz)

91 fs RMS Jitter (100 Hz to 20 MHz)

–162.5 dBc/Hz Noise Floor at 245.76 MHz

•

Up to 14 Differential Device Clocks from PLL2

3 Description

The LMK0482x family is the industry's highest

–

Up to 7 SYSREF Clocks

Maximum Clock Output Frequency 3.1 GHz

performance

clock

conditioner

with

JEDEC

LVPECL, LVDS, HSDS, LCPECL

Programmable Outputs from PLL2

JESD204B support.

The 14 clock outputs from PLL2 can be configured to

drive seven JESD204B converters or other logic

devices, using device and SYSREF clocks. SYSREF

can be provided using both DC and AC coupling. Not

limited to JESD204B applications, each of the 14

outputs can be individually configured as high-

performance outputs for traditional clocking systems.

•

Up to 1 Buffered VCXO/Crystal Output from PLL1

LVPECL, LVDS, 2xLVCMOS Programmable

–

•

Dual Loop PLLatinum™ PLL Architecture

PLL1

–

Up to 3 Redundant Input Clocks

–

Automatic and Manual Switch-Over Modes

Hitless Switching and LOS

The high performance, combined with features such

as the ability to trade off between power or

performance, dual VCOs, dynamic digital delay,

holdover, and glitchless analog delay, make the

LMK0482x family ideal for providing flexible high-

performance clocking trees.

–

Integrated Low-Noise Crystal Oscillator Circuit

Holdover Mode When Input Clocks are Lost

•

PLL2

–

Normalized [1 Hz] PLL Noise Floor of

–227 dBc/Hz

Device Information⁽¹⁾

PART

NUMBER

VCO0

FREQUENCY

VCO1 FREQUENCY

–

Phase Detector Rate up to 155 MHz

OSCin Frequency-Doubler

Two Integrated Low-Noise VCOs

2920 to 3080 MHz

LMK04821

1930 to 2075 MHz

VCO1 Div = ÷2 to ÷8

(÷2 = 1460 to 1540 MHz)

50% Duty Cycle Output Divides, 1 to 32

(even and odd)

LMK04826

LMK04828

1840 to 1970 MHz

2370 to 2630 MHz

2440 to 2505 MHz

2920 to 3080 MHz

•

Precision Digital Delay, Dynamically Adjustable

25-ps Step Analog Delay

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

Simplified Schematic

•

Industrial Temperature Range: –40 to 85°C

Supports 105°C PCB Temperature (Measured at

Thermal Pad)

•

3.15-V to 3.45-V Operation

Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8

mm)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK04821, LMK04826, LMK04828

SNAS605AS –MARCH 2013–REVISED MAY 2020

www.ti.com

Table of Contents

9.6 Register Maps ........................................................ 57

9.7 Device Register Descriptions.................................. 61

10 Applications and Implementation.................... 102

10.1 Application Information........................................ 102

10.2 Digital Lock Detect Frequency Accuracy ............ 102

10.3 Driving CLKin and OSCin Inputs......................... 103

10.4 Output Termination and Biasing ......................... 105

10.5 Typical Applications ............................................ 107

10.6 System Examples .............................................. 110

10.7 Do's and Don'ts................................................... 113

11 Power Supply Recommendations ................... 114

11.1 Pin Connection Recommendations..................... 114

1

2

3

4

5

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 7

5.1 Device Configuration Information.............................. 7

Pin Configuration and Functions......................... 8

Specifications....................................................... 11

7.1 Absolute Maximum Ratings .................................... 11

7.2 ESD Ratings............................................................ 11

7.3 Recommended Operating Conditions..................... 11

7.4 Thermal Information................................................ 11

7.5 Electrical Characteristics......................................... 12

7.6 SPI Interface Timing ............................................... 25

6

7

11.2 Current Consumption / Power Dissipation

Calculations............................................................ 116

12 Layout................................................................. 117

12.1 Layout Guidelines ............................................... 117

12.2 Layout Example .................................................. 118

13 Device and Documentation Support ............... 119

13.1 Device Support .................................................. 119

13.2 Related Links ...................................................... 119

13.3 Trademarks......................................................... 119

13.4 Electrostatic Discharge Caution.......................... 119

13.5 Glossary.............................................................. 119

7.7 Typical Characteristics – Clock Output AC

Characteristics ......................................................... 26

8

9

Parameter Measurement Information ................ 28

8.1 Charge Pump Current Specification Definitions...... 28

8.2 Differential Voltage Measurement Terminology ..... 29

Detailed Description ............................................ 30

9.1 Overview ................................................................. 30

9.2 Functional Block Diagram ....................................... 35

9.3 Feature Description................................................. 39

9.4 Device Functional Modes........................................ 50

9.5 Programming........................................................... 56

14 Mechanical, Packaging, and Orderable

Information ......................................................... 119

4 Revision History

Changes from Revision AR (December 2015) to Revision AS

Page

•

Deleted references to "LMK0482xB" and replaced with device names ................................................................................. 1

Updated Pin Configuration and Functions table with expanded descriptions ........................................................................ 8

Changed mVpp to |mV| for 10-mA HSDS V_ODin Electrical Characteristics......................................................................... 22

Added requirements for OSCout LVPECL emitter resistors to Detailed Description ........................................................... 30

Changed Overview to provide more detail. .......................................................................................................................... 30

Changed Three PLL1 Redundant Reference Inputs to provide more detail. ....................................................................... 31

Changed Frequency Holdover wording for added clarity. .................................................................................................... 31

Moved VCO1 Divider (LMK04821 only) to within Internal VCOs. ........................................................................................ 31

Changed all instances of '0-delay' to 'zero-delay' and added reference to Multi-Clock Synchronization app note. ............ 33

Changed Figure 10 and Figure 11 to show OSCout_MUX, SYNC/SYSREF detail, and color............................................ 35

Changed Figure 13 to show distribution path reclocking, other FB_MUX targets. .............................................................. 38

Added SYSREF_DDLY_PD and DCLKoutX_DDLY_PD conditions for added power savings in SYNC/SYSREF.............. 39

Added reference to Recommended Programming Sequence.............................................................................................. 40

Changed _CNTH/_CNTL register values to 0, representing delay value of 16, in Table 3. ............................................... 43

Added timing alignment figure, alignment equations to SYSREF to Device Clock Alignment ............................................ 45

Added LOS register requirements to Input Clock Switching - Automatic Mode................................................................... 47

Merged redundant paragraph into Digital Lock Detect. ....................................................................................................... 47

Added note clarifying PLL1 phase detector frequency effect on PLL1_WND_SIZE in Digital Lock Detect......................... 47

Added holdover entry conditions and clarifications in Holdover........................................................................................... 48

Added Single-Loop Mode, Single-Loop Mode With External VCO, Distribution Mode to Device Functional Modes. ......... 50

2

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Revision History (continued)

•

Added RESET Pin to Recommended Programming Sequence........................................................................................... 56

Changed CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV descriptions to add more detail........................................ 63

Changed DCLKoutX_ADLY description in DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX........................... 64

Changed SDCLKoutY_ADLY description in SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY. ................................................ 65

Added OSCout LVPECL format instructions in VCO_MUX, OSCout_MUX, OSCout_FMT. ............................................... 68

Changed SYSREF_CLR description in SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN,

SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE to add more detail.......................................................................... 74

•

Added time alongside frequency for LOS_TIMEOUT in Table 45 ....................................................................................... 80

Changed LOS_EN description to clarify requirements in Table 45...................................................................................... 80

Changed Table 53, Table 55, Table 56 register text from "N counter" to "R divider" .......................................................... 84

Changed Table 57 maximum field value to match register size........................................................................................... 85

Changed Table 75 headers from Resistance to Capacitance. .......................................................................................... 96

Changed Application Information to reference current TI tools.......................................................................................... 102

Changed all images in Driving CLKin and OSCin Inputs to include OSCin. ..................................................................... 103

Changed CLKinX_BUF_TYPE to CLKinX_TYPE in Driving CLKin and OSCin Pins With a Single-Ended Source. ......... 104

Added Output Termination and Biasing section................................................................................................................. 105

Changed Typical Applications to reference up-to-date tools.............................................................................................. 107

Added System Examples .................................................................................................................................................. 110

Added OSCout, LVDS/HSDS, and RESET pin recommendations to Do's and Don'ts...................................................... 113

Added Pin Connection Recommendations ........................................................................................................................ 114

Deleted empty column in Table 87 and redirected to TICS Pro current calculator............................................................ 116

Changed tools listed in Device Support . ........................................................................................................................... 119

Changes from Revision AQ (August 2014) to Revision AR

Page

•

Added Support for 105°C thermal pad temperature............................................................................................................... 1

Changed from I/O to I for pin 6 in Pin Functions table. ......................................................................................................... 8

Deleted programmable status pin in Description column for pin 6 in Pin Functions table..................................................... 8

Changed from No connection to Do not connect for pins 7, 8, 9 in Pin Functions table. ..................................................... 9

Changed to Reference Clock Input Port 1 for PLL 1 for Pins 34, 35 in Pin Functions. ........................................................ 9

Added Reference Clock Input Port 2 for PLL1 for pins 40, 41 in Pin Functions. ................................................................ 10

Added ESD Ratings.............................................................................................................................................................. 11

Added PCB temperature in Recommended Operating Conditions. ..................................................................................... 11

Added Digital Input Timing in Electrical Characteristics. ..................................................................................................... 24

Changed Detailed block diagrams for LMK04821 and LMK04826/8. ................................................................................. 35

Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 12................................................................... 37

Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 13................................................................... 38

Added For each SDCLKoutY being used in SYNC/SYSREF............................................................................................... 39

Deleted "SDCLKoutY_PD as required per output. " in Table 1............................................................................................ 39

Added footnote starting SDCLKoutY_PD = 0 as... in Table 1. ............................................................................................ 39

Added SDCLKout1_PD = 0, SDCLKout3_PD = 0 in Setup of SYSREF Example............................................................... 40

Changed DLD_HOLD_CNT to HOLDOVER_DLD_CNT in Holdover Mode - Automatic Exit of Holdover . ........................ 49

Changed Recommended Programming Sequence. ............................................................................................................ 56

Added 0x171/0x172 to Register Map. ................................................................................................................................. 60

Added LMK04821 register setting. ....................................................................................................................................... 62

Revised Register 0x143 table............................................................................................................................................... 74

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SNAS605AS –MARCH 2013–REVISED MAY 2020

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•

Added fixed register setting for 0x171.................................................................................................................................. 75

Added fixed register setting for 0x172 ................................................................................................................................. 75

Added LMK04821 register setting. ...................................................................................................................................... 98

Added LMK04821 register setting. ...................................................................................................................................... 99

Changed RB_PLL1_LD description. .................................................................................................................................... 99

Changed RB_PLL2_LD description. .................................................................................................................................... 99

Changes from Revision AP (June 2013) to Revision AQ

Page

•

Changed data sheet flow and layout to conform with new TI standards. Added, updated, or renamed the following

sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout;

Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................... 1

Added values for LMK04821 under "Features" section. ........................................................................................................ 1

Changed LMK04820 family to LMK0482x family. ................................................................................................................. 1

Added values for LMK04821 in Device Configuration Information......................................................................................... 7

Added holdover DAC to pin 36 description in Pin Functions. ............................................................................................... 9

Changed Thermal Information header from LMK0482xB to LMK0482x. ............................................................................ 11

Changed CLKinX_BUF_TYPE to CLKinX_TYPE in Electrical Characteristics. ................................................................... 12

Added values for LMK04821 under Internal VCO Specifications in Electrical Characteristics. ........................................... 15

Added values for LMK04821 under Noise Floor in Electrical Characteristics...................................................................... 16

•

Added values for LMK04821 under CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO

in Electrical Characteristics. ................................................................................................................................................. 17

•

Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)_CLKoutfor VCO0. .................................................. 18

Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)_CLKoutfor VCO1. .................................................. 18

Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)_CLKoutfor VCO0. .................................................. 18

Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)_CLKoutfor VCO1. .................................................. 18

Added values for LMK04821 under CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO. ................... 19

Added SDCLKoutY_HS = 0 for ts_JESD204Bin Electrical Characteristics. ............................................................................... 21

Added Propagation Delay from CLKin0 to SDCLKoutY in Electrical Characteristics........................................................... 21

Added footnote that LMK04821 has no DCLKoutX or SDCLKoutY outputs on at power up, only OSCout. ...................... 21

Changed V_OHTEST CONDITIONS to = 3 or 4 and V_OLTEST CONDITIONS to 3, 4, or 6 under DIGITAL OUTPUTS

(CLKin_SELX, Status_LDX, and RESET/GPO) subheading in Electrical Characteristics................................................... 23

•

Changed Digital Inputs (SCK, SDIO, CS*) I_IHV_IH= VCC min line from 5 µA to –5 µA........................................................ 24

Added 4 wire mode read back has same timing as SDIO pin, R/W bit = 0 is for SPI write, R/W bit = 1 is for SPI

read, W1 and W0 shall be written as 0. ............................................................................................................................... 25

•

Added LMK04821 phase noise graphs under Clock Output AC Characteristics. ................................................................ 26

Added link to AN-912 Application Report............................................................................................................................. 29

Changed from Glitchless Half Shift to Glitchless Half Step.................................................................................................. 33

Added LMK04821 detailed block diagram............................................................................................................................ 35

Changed block from SDCLKoutY_POL to DCLKoutX_POL in Figure 12. ........................................................................... 37

Added SYSREF_CLKin0_MUX block to Figure 13 image. .................................................................................................. 38

Changed Figure 13 to show that FB_MUX SYSREF input comes from SYSREF Divider, not SYSREF_MUX.................. 38

Changed term pulsor to pulser throughout........................................................................................................................... 39

Changed DCLKout0_1_DIV to DCLKout0_DIV; DCLKout2_3_DIV to DCLKout2_DIV; DCLKout4_5_DIV to

DCLKout4_DIV. .................................................................................................................................................................... 40

•

Added DCLKout4_DIV = 20. ................................................................................................................................................ 40

Added DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0.................................................. 40

Changed text to read, Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH,

DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH,

4

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SNAS605AS –MARCH 2013–REVISED MAY 2020

DCLKout4_DDLY_CNTL, SYSREF_DDLY. ........................................................................................................................ 40

Added = 1 in SYSREF Request. ......................................................................................................................................... 41

Changed step numbers in dynamic delay and references to steps to be correct, step 8 was duplicated. ......................... 44

Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 50

Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 51

Added R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. ......................................................................................... 56

Added If using LMK04821, program register 0x174 in Recommended Programming Sequence. ..................................... 56

Added SYSREF_CLKin0_MUX and VCO1_DIV to register map......................................................................................... 58

Added CLKin_OVERRIDE bit to register map. .................................................................................................................... 59

Changed from half shift to half step...................................................................................................................................... 64

Changed definition of SDCLKoutY_DDLY value of 0 from Reserved to Bypass. ................................................................ 64

•

Changed from Sets the polarity of SYSREF clocks to Sets the polarity of clock on SDCLKoutY when device clock

output is selected with SDCLKoutY_MUX............................................................................................................................ 67

•

Changed Sets the polarity of the device clocks to Sets the polarity of the device clocks from the DCLKoutX outputs. ..... 67

Added LMK04821 DCLKoutX_FMT power on reset values as powerdown......................................................................... 67

Changed from SYSREF to SYSREF Divider in Source column of Register 0x13F. ........................................................... 71

Changed reserved to Off for CLKin1_OUT_MUX. .............................................................................................................. 76

Changed reserved to Off for CLKin0_OUT_MUX. .............................................................................................................. 76

Added CLKin_OVERRIDE bit............................................................................................................................................... 83

Added LMK04821 register 0x174 for VCO1_DIV................................................................................................................. 98

Deleted LMK04828 from Core line. ................................................................................................................................... 116

Added VCO1 Icc including VCO1 Divider for LMK04821................................................................................................... 116

Changed VCO1 Icc and power dissipated for LMK04828B/26B from 6 mA to 13.5 mA and 19.8 mW to 44.55 mW. ...... 116

Changes from Revision AO (March 2013) to Revision AP

Page

•

Changed datasheet title from LMK04828 to LMK0482xB ...................................................................................................... 1

Changed LMK04828 family to LMK04820 family. .................................................................................................................. 1

Changed image from LMK04828B to LMK0482xB. ............................................................................................................... 1

Added LMK04826 to Device Configuration Information table. ............................................................................................... 7

Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz. ..................................................... 7

Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz..................... 7

Changed Thermal Information header from LMK04828B to LMK0482xB............................................................................ 11

Added LMK04826 VCO Range Specification....................................................................................................................... 15

Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz. ................................................... 15

Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz................... 15

Added LMK04826 K_VCOspecification. .................................................................................................................................. 15

Added clarification of LMK04828 specification vs LMK04826 specification for K_VCO........................................................... 15

Added LMK04826 noise floor data. ...................................................................................................................................... 16

Changed - clarified phase noise data section header. ......................................................................................................... 17

Added LMK04826 phase noise data. ................................................................................................................................... 18

Added LMK04826 jitter data................................................................................................................................................. 19

Added LMK04826 f_{CLKout-startup}spec. ..................................................................................................................................... 21

Added clarification of LMK04828 specification vs. LMK04826 specification for f_{CLKout-startup.}................................................ 21

Added LMK04826B Phase Noise Performance Graph for VCO0. ....................................................................................... 26

Added LMK04826B Phase Noise Performance Graph for VCO1. ....................................................................................... 26

Added Added PLL2 loop filter bandwidth and phase margin info to plot. ............................................................................ 27

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SNAS605AS –MARCH 2013–REVISED MAY 2020

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•

Changed LMK04828 to LMK0482xB in VCXO/Crystal Buffered Output. ............................................................................ 31

Changed LMK04828 to LMK0482xB in Status Pins. ........................................................................................................... 33

Changed image from LMK04828 to LMK0482xB................................................................................................................. 50

Changed - corrected value of PLL2_P selection to be 0 to correspond with register programming definition. ................... 50

Changed image from LMK04828 to LMK0482xB................................................................................................................. 51

Changed image from LMK04828 to LMK0482xB................................................................................................................. 52

Added LMK04826 register setting. ....................................................................................................................................... 62

Added LMK04826 register setting. ....................................................................................................................................... 98

Added LMK04826 register setting. ....................................................................................................................................... 99

6

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SNAS605AS –MARCH 2013–REVISED MAY 2020

5 Device Comparison Table

5.1 Device Configuration Information

PLL2

REF-

OSCout (BUFFERED

OSCin Clock) LVDS/

LVPECL/ LVCMOS

PROGRAMMABLE

LVDS/LVPECL/HSDS

OUTPUTS

ERENCE

PART NUMBER

VCO0 FREQUENCY

VCO1 FREQUENCY

(1)

INPUTS⁽¹⁾

VCO1_DIV = ÷2

1460 to 1540 MHz

VCO1_DIV = ÷3

974 to 1026 MHz

VCO1_DIV = ÷4

730 to 770 MHz

VCO1_DIV = ÷5

584 to 616 MHz

LMK04821

Up to 3

Up to 1

14

1930 to 2075 MHz

VCO1_DIV = ÷6

487 to 513 MHz

VCO1_DIV = ÷7

418 to 440 MHz

VCO1_DIV = ÷8

365 to 385 MHz

LMK04826

LMK04828

Up to 3

Up to 1

14

1840 to 1970 MHz

2370 to 2630 MHz

2440 to 2505 MHz

2920 to 3080 MHz

(1) OSCout may also be third clock input, CLKin2.

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SNAS605AS –MARCH 2013–REVISED MAY 2020

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6 Pin Configuration and Functions

NKD Package

64-Pin WQFN

Top View

Clock Group 0

Clock Group 3

Status_LD2

Vcc10_PLL2

CPout2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DCLKout0

DCLKout0*

SDCLKout1

SDCLKout1*

RESET/GPO

SYNC/SYSREF_REQ

NC

1

2

3

Vcc9_CP2

OSCin*

4

5

OSCin

6

Vcc8_OSCin

7

NC

OSCout*/CLKin2*

OSCout/CLKin2

Vcc7_OSCout

8

LLP-64

Top down view

NC

9

Vcc1_VCO

LDObyp1

10

11

12

13

14

15

16

CLKin0*

LDObyp2

CLKin0

SDCLKout3

SDCLKout3*

DCLKout2

DCLKout2*

Vcc6_PLL1

CLKin1*/Fin*/FBCLKin*

DAP

CLKin1/Fin/FBCLKin

Vcc5_DIG

Clock Group 2

Clock Group 1

Pin Functions

I/O⁽¹⁾

DESCRIPTION⁽²⁾

NO.

NAME

1

DCLKout0

DCLKout0*

SDCLKout1

Device clock output 0. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

2

3

4

SYSREF / Device clock output 1. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

O

SDCLKout1*

RESET/GPO

Device reset input or GPO. If used as a reset input, pin polarity and nominal 160-kΩ pull-up or pull-down are controlled

by register settings. If used as an output, can be set to push-pull or open-drain.

5

6

I/O

I

Synchronization input.. Can be used to reset dividers, trigger the SYSREF pulser, or request continuous SYSREF from

the SYSREF divider. Pin polarity is controlled by register settings. Nominal 160-kΩ pulldown.

SYNC/SYSREF_REQ

(1) The definitions below define the I/O type for each pin.

(a) I = Input

(b) O = Output

(c) I/O = Input / Output (Configurable)

(d) P = Power Supply

(e) BP = Bypass (LDO output)

(f) G = Ground

(g) NC = No Connect

(2) See Pin Connection Recommendations for recommended connections.

8

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION⁽²⁾

NO.

7,

NAME

-

NC

8

Do not connect. These pins must be left floating.

9

Power supply for VCO LDO. Decoupling capacitance requirements may change with system frequency. See Pin

Connection Recommendations for recommendations.

10

Vcc1_VCO

P

11

12

13,

LDObyp1

LDObyp2

SDCLKout3

BP

LDO bypass. This pin must be bypassed to ground with 10-µF capacitor placed close to the pin.

LDO bypass.This pin must be bypassed to ground with a 0.1-µF capacitor placed close to the pin.

SYSREF / Device clock output 3. Differential clock output. Part of clock group 1. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

O

14

15

16

SDCLKout3*

DCLKout2

Device clock output 2. Differential clock output. Part of clock group 1. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

P

DCLKout2*

Power supply for clock outputs 2 and 3. Decoupling capacitance requirements may change with system frequency. See

Pin Connection Recommendations for recommendations.

17

Vcc2_CG1

18

19

CS*

I

SPI Chip select. Active-low input. Must be pulled up externally or actively driven high when not in use.

SCK

SPI clock. Active-high input. Nominal 160-kΩ pulldown.

SPI data. This pin can implement bidirectional I/O. As an output, this pin can be configured for open-drain or push-pull.

Open-drain output requires external pull-up. Register settings can disable the output feature of this pin. Other GPIO pins

can also be configured as SPI MISO (master-in slave-out) for traditional 4-wire SPI.

20

21

SDIO

I/O

P

Power supply for SYSREF divider and SYNC. Decoupling capacitance requirements may change with system

frequency. See Pin Connection Recommendations for recommendations.

Vcc3_SYSREF

22

23

24

25

SDCLKout5

SDCLKout5*

DCLKout4

SYSREF / Device clock output 5. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

O

Device clock output 4. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

DCLKout4*

Power supply for clock outputs 4, 5, 6, and 7. Decoupling capacitance requirements may change with system frequency.

See Pin Connection Recommendations for recommendations.

26

Vcc4_CG2

27

28

29

30

DCLKout6

Device clock output 6. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

DCLKout6*

SDCLKout7

SDCLKout7*

SYSREF / Device clock output 7. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

Programmable status pin. By default, this pin is configured as an active-high output representing the state of PLL1 lock

detect. Other status conditions and output polarity are register-selectable. This pin can be configured for open-drain or

push-pull output.

31

Status_LD1

I/O

Charge pump 1 output. This pin is connected to the external loop filter components for PLL1, and to the VCXO control

voltage pin.

32

33

CPout1

O

P

Power supply for digital circuitry, such as SPI bus and GPIO pins. Decoupling capacitance requirements may change

with system frequency. See Pin Connection Recommendations for recommendations.

Vcc5_DIG

(Default) Reference clock input port 1 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or

differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if

both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information.

CLKin1

I

Feedback input for external clock feedback input (zero–delay mode). Can be configured for DC or AC coupling. Accepts

single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor.

Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information.

FBCLKin

34

External VCO input (external VCO mode) or Clock Distribution input (distribution mode). Can be configured for DC or

AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a

0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended

termination information.

Fin

I

(Default) Reference clock input port 1 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or

differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if

both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information.

CLKin1*

I

Feedback input for external clock feedback input (zero-delay mode). Can be configured for DC or AC coupling. Accepts

single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor.

Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information.

FBCLKin*

35

External VCO input (external VCO mode) or Clock Distribution input (distribution mode). Can be configured for DC or

AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a

0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended

termination information.

Fin*

I

P

I

Power supply for PLL1, charge pump 1, holdover DAC. Decoupling capacitance requirements may change with system

frequency. See Pin Connection Recommendations for recommendations.

36

37

Vcc6_PLL1

CLKin0

Reference clock input port 0 for PLL1. Can also be used as a synchronization input for SYNC/SYSREF. Can be

configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration,

connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for

single-ended termination information.

38

CLKin0*

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Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION⁽²⁾

NO.

NAME

Vcc7_OSCout

Power supply for OSCout port and CLKin2. Decoupling capacitance requirements may change with system frequency.

See Pin Connection Recommendations for recommendations.

39

P

(Default) Buffered output of OSCin port. Defaults to LVPECL. In LVPECL output format, this pin only supports 240-Ω

emitter resistors. If unused, set output format buffer to powerdown and leave pins floating.

OSCout

Reference clock input port 2 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential

clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are

unused. See Driving CLKin and OSCin Inputs for single-ended termination information. Registers must be configured to

set this pin as an input.

40

I/O

CLKin2

(Default) Buffered output of OSCin port. Defaults to LVPECL. In LVPECL output format, this pin only supports 240-Ω

emitter resistors. If unused, set output format buffer to powerdown and leave pins floating.

OSCout*

CLKin2*

Vcc8_OSCin

Reference clock input port 2 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential

clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are

unused. See Driving CLKin and OSCin Inputs for single-ended termination information. Registers must be configured to

set this pin as an input.

41

42

Power supply for OSCin. Decoupling capacitance requirements may change with system frequency. See Pin Connection

Recommendations for recommendations.

P

I

43

44

OSCin

Feedback to PLL1, reference input to PLL2. Inputs to this pin should be AC-coupled. Accepts single-ended or differential

clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are

unused. See Driving CLKin and OSCin Inputs for single-ended termination information.

OSCin*

Power supply for PLL2 charge pump. Decoupling capacitance requirements may change with system frequency. See

Pin Connection Recommendations for recommendations.

45

46

47

Vcc9_CP2

CPout2

P

O

P

Charge pump 2 output. This pin is connected to the external components of the PLL2 loop filter. If an external VCO is

used, this pin is also connected to the external VCO control voltage pin. Do not route this pin near noisy signals.

Power supply for PLL2. Decoupling capacitance requirements may change with system frequency. See Pin Connection

Recommendations for recommendations.

Vcc10_PLL2

Programmable status pin. By default, this pin is configured as an active-high output representing the state of PLL2 lock

detect. Other status conditions and output polarity are register-selectable. This pin can be configured for open-drain or

push-pull output.

48

Status_LD2

I/O

O

49

50

51

52

SDCLKout9

SDCLKout9*

DCLKout8

SYSREF / Device clock 9. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the

clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

Device clock output 8. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

P

DCLKout8*

Power supply for clock outputs 8, 9, 10, and 11. Decoupling capacitance requirements may change with system

frequency. See Pin Connection Recommendations for recommendations.

53

Vcc11_CG3

54

55

56

57

DCLKout10

Device clock output 10. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

O

DCLKout10*

SDCLKout11

SDCLKout11*

SYSREF / Device clock output 11. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

O

Programmable status pin. By default this pin is programmed as an active-high input with nominal 160-kΩ pulldown that

selects which CLKin is used as the reference to PLL1 in pin-select mode. If used as an input, pin polarity and nominal

160-kΩ pull-up or pull-down are controlled by register settings. If used as an output, can be set to push-pull or open-

drain.

58

59

CLKin_SEL0

CLKin_SEL1

I/O

Programmable status pin. By default this pin is programmed as an active-high input with nominal 160-kΩ pulldown that

selects which CLKin is used as the reference to PLL1 in pin-select mode. If used as an input, pin polarity and nominal

160-kΩ pull-up or pull-down are controlled by register settings. If used as an output, can be set to push-pull or open-

drain.

I/O

60

61

62

63

SDCLKout13

SDCLKout13*

DCLKout12

SYSREF / Device clock output 13. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in

the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format

buffer to powerdown and leave pins floating.

O

Device clock output 12. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock

group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to

powerdown and leave pins floating.

DCLKout12*

Power supply for clock outputs 0, 1, 12, and 13. Decoupling capacitance requirements may change with system

frequency. See Pin Connection Recommendations for recommendations.

64

-

Vcc12_CG0

DAP

P

Die attach pad. Connect directly to GND plane through multiple vias to minimize resistive and inductive effects and to

achieve good thermal performance. All power supply pins are referred to the DAP ground.

G

10

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

(2)

V_CC

V_IN

Supply voltage

Input voltage

–0.3

3.6

V

(V_CC

0.3)

+

–0.3

V

T_L

T_J

Lead temperature (solder 4 seconds)

Junction temperature

260

150

°C

Differential input current (CLKinX/X*,

OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)

I_IN

± 5

mA

MSL

T_stg

Moisture sensitivity level

Storage temperature

3

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Never to exceed 3.6 V.

7.2 ESD Ratings

VALUE

±2000

±150

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Machine Model (MM)

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

–40

TYP

25

MAX UNIT

T_J

Junction temperature

125

85

°C

V

T_A

Ambient temperature

T_PCB

V_CC

PCB temperature (measured at thermal pad)

Supply voltage

105

3.45

3.15

3.3

7.4 Thermal Information

LMK0482x

THERMAL METRIC⁽¹⁾

NKD (WQFN)

64 PINS

24.3

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

°C/W

R_θJC(top)

R_θJB

6.1

3.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

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Thermal Information (continued)

LMK0482x

NKD (WQFN)

64 PINS

0.1

THERMAL METRIC⁽¹⁾

UNIT

ψ_JT

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

ψ_JB

3.5

R_θJC(bot)

0.7

(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, Ψ_JBestimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT CONSUMPTION

I_{CC_PD}

Power down supply current

Supply current⁽¹⁾

1

3

mA

14 HSDS 8-mA clocks enabled

PLL1 and PLL2 locked.

I_{CC_CLKS}

565

665

CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS

f_CLKin

Clock input frequency

Clock input slew rate

Clock input

Differential input voltage

Figure 8

0.001

0.15

750

MHz

V/ns

|V|

(2)

SLEW_CLKin

V_IDCLKin

20% to 80%

AC coupled

0.5

0.125

1.55

3.1

(3)

V_SSCLKin

0.25

Vpp

AC coupled to CLKinX;

CLKinX* AC coupled to ground

CLKinX_TYPE = 0 (bipolar)

0.25

2.4

Vpp

Clock input

Single-ended input voltage

V_CLKin

AC coupled to CLKinX;

CLKinX* AC coupled to ground

CLKinX_TYPE = 1 (MOS)

0.35

Vpp

Each pin AC coupled, CLKin0/1/2

CLKinX_TYPE = 0 (bipolar)

0

55

20

|mV|

DC offset voltage between

CLKinX/CLKinX* (CLKinX* - CLKinX)

Each pin AC coupled, CLKin0/1

CLKinX_TYPE = 1 (MOS)

|V_{CLKinX-offset}

|

DC offset voltage between

CLKin2/CLKin2* (CLKin2* - CLKin2)

Each pin AC coupled

CLKinX_TYPE = 1 (MOS)

V_CLKin-V_IH

V_CLKin-V_IL

High input voltage

Low input voltage

DC coupled to CLKinX;

CLKinX* AC coupled to ground

CLKinX_TYPE = 1 (MOS)

2.0

0.0

V_CC

0.4

V

FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS

Clock input frequency for

zero-delay with external feedback.

AC coupled

CLKinX_TYPE = 0 (bipolar)

f_FBCLKin

f_Fin

0.001

750

MHz

(4)

Clock input frequency for

external VCO or distribution mode

AC coupled

CLKinX_TYPE = 0 (bipolar)

3100

(1) See the applications section of Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a

specific design.

(2) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input

clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase-noise performance begins to degrade as the clock input slew

rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks,

differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase-noise performance at lower slew rates, due to their

common-mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve

optimal phase-noise performance at the device outputs.

(3) See Differential Voltage Measurement Terminology for definition of V_IDand V_ODvoltages.

(4) Assured by characterization. ATE tested at 2949.12 MHz.

12

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

Single ended

Clock input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

AC coupled

CLKinX_TYPE = 0 (bipolar)

V_FBCLKin/Fin

0.25

2.0

Vpp

AC coupled; 20% to 80%;

(CLKinX_TYPE = 0)

(2)

SLEW_FBCLKin/FinSlew rate on CLKin

0.15

0.5

V/ns

PLL1 SPECIFICATIONS

f_PD1

PLL1 phase detector frequency

40

MHz

µA

V_CPout1= V_CC/2, PLL1_CP_GAIN = 0

V_CPout1= V_CC/2, PLL1_CP_GAIN = 1

V_CPout1= V_CC/2, PLL1_CP_GAIN = 2

…

50

150

250

PLL1 charge

I_CPout1SOURCE

(5)

Pump source current

…

V_CPout1= V_CC/2, PLL1_CP_GAIN = 14

V_CPout1= V_CC/2, PLL1_CP_GAIN = 15

V_CPout1=V_CC/2, PLL1_CP_GAIN = 0

V_CPout1=V_CC/2, PLL1_CP_GAIN = 1

V_CPout1=V_CC/2, PLL1_CP_GAIN = 2

…

1450

1550

–50

–150

–250

…

PLL1 charge

Pump sink current

I_CPout1SINK

µA

(5)

V_CPout1=V_CC/2, PLL1_CP_GAIN = 14

V_CPout1=V_CC/2, PLL1_CP_GAIN = 15

–1450

–1550

Charge pump

Sink / source mismatch

I_CPout1%MIS

I_CPout1V_TUNE

I_CPout1%TEMP

I_CPout1TRI

V_CPout1= V_CC/2, T = 25 °C

1%

4%

10%

Magnitude of charge pump current

variation vs. charge pump voltage

0.5 V < V_CPout1< V_CC- 0.5 V

T_A= 25 °C

Charge pump current vs. temperature

variation

Charge pump TRI-STATE leakage

current

0.5 V < V_CPout< V_CC- 0.5 V

5

nA

PLL 1/f noise at 10-kHz offset.

Normalized to 1-GHz output

frequency

PLL1_CP_GAIN = 350 µA

PLL1_CP_GAIN = 1550 µA

–117

–118

PN10kHz

PN1Hz

dBc/Hz

PLL1_CP_GAIN = 350 µA

PLL1_CP_GAIN = 1550 µA

–221.5

–223

Normalized phase noise contribution

dBc/Hz

PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS

(6)

f_OSCin

PLL2 reference input

500

2.4

MHz

V/ns

PLL2 reference clock minimum slew

SLEW_OSCin

20% to 80%

0.15

0.2

0.5

20

(2)

rate on OSCin

AC coupled; single-ended

(unused pin AC coupled to GND)

V_OSCin

Input voltage for OSCin or OSCin*

Vpp

V_IDOSCin

V_SSOSCin

0.2

0.4

1.55

3.1

|V|

Differential voltage swing

Figure 8

AC coupled

Vpp

DC offset voltage between

OSCin/OSCin* (OSCinX* - OSCinX)

|V_OSCin-offset

|

Each pin AC coupled

|mV|

MHz

EN_PLL2_REF_2X = 1⁽⁸⁾

OSCin duty cycle 40% to 60%

;

(7)

f_{doubler_max}

Doubler input frequency

155

(5) This parameter is programmable.

(6) F_OSCinmaximum frequency assured by characterization. Production tested at 122.88 MHz.

(7) Assured by characterization. ATE tested at 122.88 MHz.

(8) The EN_PLL2_REF_2X bit enables or disables a frequency doubler mode for the PLL2 OSCin path.

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CRYSTAL OSCILLATOR MODE SPECIFICATIONS

Fundamental mode crystal

ESR = 200 Ω (10 to 30 MHz)

ESR = 125 Ω (30 to 40 MHz)

F_XTAL

Crystal frequency range

10

40

MHz

pF

C_IN

Input capacitance of OSCin port

–40 to 85 °C

1

PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS

(7)

f_PD2

Phase detector frequency

155

MHz

µA

V_CPout2=V_CC/2, PLL2_CP_GAIN = 0

V_CPout2=V_CC/2, PLL2_CP_GAIN = 1

V_CPout2=V_CC/2, PLL2_CP_GAIN = 2

V_CPout2=V_CC/2, PLL2_CP_GAIN = 3

V_CPout2=V_CC/2, PLL2_CP_GAIN = 0

V_CPout2=V_CC/2, PLL2_CP_GAIN = 1

V_CPout2=V_CC/2, PLL2_CP_GAIN = 2

V_CPout2=V_CC/2, PLL2_CP_GAIN = 3

V_CPout2=V_CC/2, T_A= 25 °C

100

400

(5)

I_CPoutSOURCE

PLL2 charge pump source current

1600

3200

–100

–400

–1600

–3200

1%

(5)

I_CPoutSINK

PLL2 charge pump sink current

µA

I_CPout2%MIS

I_CPout2V_TUNE

Charge pump sink/source mismatch

10%

10

Magnitude of charge pump current vs. 0.5 V < V_CPout2< V_CC- 0.5 V

charge pump voltage variation

4%

T_A= 25 °C

Charge pump current vs. temperature

variation

I_CPout2%TEMP

I_CPout2TRI

Charge pump leakage

0.5 V < V_CPout2< V_CC- 0.5 V

PLL2_CP_GAIN = 400 µA

nA

(9)

PLL 1/f noise at 10-kHz offset

Normalized to

.

–118

–121

PN10kHz

PN1Hz

dBc/Hz

PLL2_CP_GAIN = 3200 µA

1-GHz output frequency

PLL2_CP_GAIN = 400 µA

PLL2_CP_GAIN = 3200 µA

–222.5

–227

Normalized phase noise contribution

dBc/Hz

(10)

(9) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker

noise has a 10-dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10

kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to total noise,

L(f). To measure L_{PLL_flicker}(f), it is important to be on the 10-dB/decade slope close to the carrier. A high compare frequency and a

clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference

oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f)

and L_{PLL_flat}(f).

(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as:

PN1HZ=L_{PLL_flat}(f) - 20log(N) - 10log(f_PDX). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1-Hz

bandwidth and f_PDXis the phase-detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

14

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

INTERNAL VCO SPECIFICATIONS

TEST CONDITIONS

MIN

TYP

MAX UNIT

VCO0

VCO1⁽¹¹⁾

VCO0

VCO1

VCO0

VCO1

1930

2920

1840

2440

2370

2920

2075

MHz

3080

LMK04821 VCO tuning range

LMK04826 VCO tuning range

LMK04828 VCO tuning range

LMK04821 fine tuning sensitivity

LMK04826 fine tuning sensitivity

1970

MHz

2505

f_VCO

2630

MHz

3080

LMK04821 VCO0

12 to 20

15 to 24

11 to 19

8 to 11

MHz/V

LMK04821 VCO1

LMK04826 VCO0

K_VCO

LMK04826 VCO1

LMK04828 VCO0 at 2457.6 MHz

LMK04828 VCO1 at 2949.12 MHz

17 to 27

17 to 23

LMK04828 fine tuning sensitivity

Allowable temperature drift for

After programming for lock, no changes

to output configuration are permitted to

assure continuous lock

|ΔT_CL

|

continuous lock

125

°C

(12)

(11) The VCO1 divider, VCO1_DIV in register 0x174, can be programmed to ÷2 to ÷8 resulting in a lower effective VCO frequency range, as

shown in Device Configuration Information.

(12) Maximum allowable temperature drift for continuous lock is how far the temperature can drift in either direction from the value it was at

the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of

programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over

the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary

to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the

temperature can never drift outside the frequency range of –40 °C to 85 °C without violating specifications.

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

NOISE FLOOR

LVDS

–158.2

–160

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

–161

–161.4

LMK04821, VCO0, noise floor

20-MHz offset⁽¹³⁾

L(f)_CLKout

245.76 MHz

dBc/Hz

LVPECL16 with 240

Ω

–161.6

–162

LVPECL20 with 240

Ω

LVPECL

161.7

–157.1

–158.3

–159

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

–159.2

LMK04821, VCO1, noise floor

20-MHz offset⁽¹³⁾

L(f)_CLKout

245.76 MHz

dBc/Hz

LVPECL16 with 240

Ω

–158.8

–158.9

LVPECL20 with 240

Ω

LVPECL

–158.8

–158.1

–159.7

–160.8

–161.3

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LMK04826, VCO0, noise floor

(14)

LVPECL16 with 240

Ω

20-MHz offset

–161.8

–162.0

LVPECL20 with 240

Ω

LCPECL

–161.7

–157.5

–158.9

–159.8

–160.3

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LMK04826, VCO1, noise floor

(14)

LVPECL16 with 240

Ω

20-MHz offset

–160.8

LVPECL20 with 240

Ω

–160.7

LCPECL

(13) Data collected using a Prodyn BIB-100G balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10

pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 PLL2 loop filter bandwidth = 288 kHz, phase margin = 72 degrees.

VCO1 Loop filter loop bandwidth = 221 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

(14) Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω,

C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees.

VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

16

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

NOISE FLOOR (continued)

LVDS

–156.3

–158.4

–159.3

–158.9

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LMK04828, VCO0, noise floor

20-MHz offset

L(f)_CLKout

245.76 MHz

dBc/Hz

(15)

LVPECL16 with 240

Ω

–161.6

–162.5

LVPECL20 with 240

Ω

LCPECL

–162.1

–155.7

–157.5

–158.1

–157.7

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LMK04828, VCO1, noise floor

20-MHz offset

L(f)_CLKout

245.76 MHz

dBc/Hz

(15)

LVPECL16 with 240

Ω

–160.3

LVPECL20 with 240

Ω

–161.1

–160.8

LCPECL

CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO⁽¹⁶⁾

Offset = 1 kHz

Offset = 10 kHz

–126.9

–133.5

–135.4

–149.8

–158.1

–161.1

Offset = 100 kHz

LMK04821

VCO0

SSB phase noise

245.76 MHz

Offset = 1 MHz

L(f)_CLKout

dBc/Hz

(13)

LVDS

HSDS 8 mA

Offset = 10 MHz

LVPECL16 with 240

Ω

–161.7

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

–126.8

–133.4

–135.4

–151.8

–157.2

–159.1

LMK04821

VCO1

SSB phase noise

245.76 MHz

L(f)_CLKout

dBc/Hz

(13)

LVDS

HSDS 8 mA

Offset = 10 MHz

LVPECL16 with 240

Ω

–158.9

(15) Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 =

200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter

loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

(16) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)

Offset = 10 kHz

Offset = 100 kHz

LVDS

–134.8

–135.4

–148.2

LMK04826

VCO0

SSB phase noise

245.76 MHz

HSDS 8 mA

LVPECL16 with 240

Ω

Offset = 1 MHz

–148.6

L(f)_CLKout

dBc/Hz

(14)

LVDS

–157.8

–160.4

HSDS 8 mA

Offset = 10 MHz

LVPECL16 with 240

Ω

–161.5

Offset = 10 kHz

Offset = 100 kHz

–134.3

–133.7

–152.5

LVDS

LMK04826

VCO1

SSB phase noise

245.76 MHz

HSDS 8 mA

LVPECL16 with 240

Ω

Offset = 1 MHz

Offset = 10 MHz

–153.6

L(f)_CLKout

dBc/Hz

(14)

LVDS

–157.3

–159.6

HSDS 8 mA

LVPECL16 with 240

Ω

–160.5

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

–124.3

–134.7

–136.5

–148.4

–156.4

–159.1

LMK04828

VCO0

SSB phase noise

245.76 MHz

L(f)_CLKout

dBc/Hz

(15)

LVDS

HSDS 8 mA

Offset = 10 MHz

LVPECL16 with 240

Ω

–160.8

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

–124.2

–134.4

–135.2

–151.5

–159.9

–155.8

LMK04828

VCO1

SSB phase noise

245.76 MHz

L(f)_CLKout

dBc/Hz

(15)

LVDS

HSDS 8 mA

Offset = 10 MHz

LVPECL16 with 240

Ω

–158.1

18

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO⁽¹⁶⁾

LVDS, BW = 12 kHz to 20 MHz

99

94

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 with 240 Ω,

BW = 12 kHz to 20 MHz

LMK04821, VCO0

f_CLKout= 245.76-MHz

integrated RMS jitter

96

94

93

fs rms

(13)

LVPECL20 with 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL with 240 Ω,

BW = 12 kHz to 20 MHz

J_CLKout

LVDS, BW = 12 kHz to 20 MHz

96

90

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 with 240 Ω,

BW = 12 kHz to 20 MHz

LMK04821, VCO1

f_CLKout= 245.76-MHz

integrated RMS jitter

92

91

fs rms

(13)

LVPECL20 with 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL with 240 Ω,

BW = 12 kHz to 20 MHz

CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)⁽¹⁶⁾

LVDS, BW = 100 Hz to 20 MHz

106

104

99

LVDS, BW = 12 kHz to 20 MHz

HSDS 8 mA, BW = 100 Hz to 20 MHz

HSDS 8 mA, BW = 12 kHz to 20 MHz

97

LVPECL16 /w 240 Ω,

BW = 100 Hz to 20 MHz

LMK04826, VCO0

f_CLKout= 245.76-MHz

integrated RMS jitter

99

96

fs rms

(14)

LVPECL16 /w 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL /w 240 Ω,

BW = 100 Hz to 20 MHz

100

97

LCPECL /w 240 Ω,

BW = 12 kHz to 20 MHz

J_CLKout

LVDS, BW = 100 Hz to 20 MHz

LVDS, BW = 12 kHz to 20 MHz

99

97

92

90

HSDS 8 mA, BW = 100 Hz to 20 MHz

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 /w 240 Ω,

BW = 100 Hz to 20 MHz

LMK04826, VCO1

f_CLKout= 245.76-MHz

integrated RMS jitter

91

89

92

89

fs rms

(14)

LVPECL20 /w 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL /w 240 Ω,

BW = 100 Hz to 20 MHz

LCPECL /w 240 Ω,

BW = 12 kHz to 20 MHz

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)⁽¹⁶⁾

LVDS, BW = 100 Hz to 20 MHz

112

109

102

99

LVDS, BW = 12 kHz to 20 MHz

HSDS 8 mA, BW = 100 Hz to 20 MHz

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 /w 240 Ω,

BW = 100 Hz to 20 MHz

LMK04828, VCO0

f_CLKout= 245.76-MHz

integrated RMS jitter

98

95

96

93

fs rms

(15)

LVPECL20 /w 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL /w 240 Ω,

BW = 100 Hz to 20 MHz

LCPECL /w 240 Ω,

BW = 12 kHz to 20 MHz

J_CLKout

LVDS, BW = 100 Hz to 20 MHz

LVDS, BW = 12 kHz to 20 MHz

108

105

98

HSDS 8 mA, BW = 100 Hz to 20 MHz

HSDS 8 mA, BW = 12 kHz to 20 MHz

94

LVPECL16 /w 240 Ω,

BW = 100 Hz to 20 MHz

LMK04828, VCO1

f_CLKout= 245.76-MHz

integrated RMS jitter

93

90

91

88

fs rms

(15)

LVPECL20 /w 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL /w 240 Ω,

BW = 100 Hz to 20 MHz

LCPECL /w 240 Ω,

BW = 12 kHz to 20 MHz

20

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY

LMK04826

235

315

Default output clock frequency at

device power on

f_{CLKout-startup}

f_OSCout

MHz

(17)(18)

LMK04828

(7)

OSCout frequency

500

25

MHz

|ps|

CLOCK SKEW and DELAY

DCLKoutX to SDCLKoutY

(20)

Same pair, same format

SDCLKoutY_MUX = 0 (device clock)

F_CLK= 245.76 MHz, R_L= 100 Ω

(19)

AC coupled

|T_SKEW

|

Maximum DCLKoutX or SDCLKoutY

to DCLKoutX or SDCLKoutY

F_CLK= 245.76 MHz, R_L= 100 Ω

AC coupled

(20)

Any pair, same format

SDCLKoutY_MUX = 0 (device clock)

50

SDCLKoutY_MUX = 1 (SYSREF)

SYSREF_DIV = 30

SYSREF_DDLY = 8 (global)

SDCLKoutY_DDLY = 1 (2 cycles, local)

DCLKoutX_MUX = 1 (Div+DCC+HS)

DCLKoutX_DIV = 30

DCLKoutX_DDLY_CNTH = 7

DCLKoutX_DDLY_CNTL = 6

DCLKoutX_HS = 0

SYSREF to device clock setup time

base reference.

See SYSREF to Device Clock

Alignment to adjust SYSREF to

device clock setup time as required.

ts_JESD204B

–80

ps

SDCLKoutY_HS = 0

CLKin0_OUT_MUX = 0 (SYSREF mux)

SYSREF_CLKin0_MUX = 1 (CLKin0)

SDCLKout1_PD = 0

SDCLKout1_DDLY = 0 (bypass)

SDCLKout1_MUX = 1 (SR)

EN_SYNC = 1

t_PDCLKin0_

SDCLKout1

Propagation delay from CLKin0 to

SDCLKout1

0.65

ns

LVPECL16 /w 240 Ω

f_ADLYmax

Maximum analog delay frequency

DCLKoutX_MUX = 4

1536

395

MHz

LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)

V_OD

Differential output voltage

|mV|

mV

V

Change in magnitude of V_ODfor

complementary output states

ΔV_OD

V_OS

–60

60

1.375

35

T = 25 °C, DC measurement

AC coupled to receiver input

R_L= 100-Ω differential termination

Output offset voltage

1.125

1.25

180

Change in V_OSfor complementary

output states

ΔV_OS

|mV|

Output rise time

Output fall time

20% to 80%, R_L= 100 Ω, 245.76 MHz

80% to 20%, R_L= 100 Ω

T_R/ T_F

ps

I_SA

I_SB

Output short circuit current - single

ended

Single-ended output shorted to GND

T = 25 °C

–24

–12

24

12

mA

Output short circuit current -

differential

I_SAB

Complimentary outputs tied together

(17) OSCout oscillates at start-up at the frequency of the VCXO attached to the OSCin port.

(18) LMK04821 has no DCLKoutX or SDCLKoutY outputs which oscillate at power on. Only OSCout oscillates at power on.

(19) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid

for delay mode.

(20) LVPECL uses a 120-Ω emitter resistor, LVDS and HSDS uses a 560-Ω shunt.

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

6-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

V_CC

1.05

-

V_OH

T = 25 °C, DC measurement

Termination = 50 Ω to

V_CC- 1.42 V

V_CC

1.64

-

V_OL

V_OD

ΔV_OD

Differential output voltage

590

|mV|

Change in V_ODfor complementary

output states

–80

80 mVpp

8-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

Output rise time

Output fall time

245.76 MHz, 20% to 80%, R_L= 100 Ω

T_R/ T _F

V_OH

170

ps

245.76 MHz, 80% to 20%, R_L= 100 Ω

V_CC

-

1.26

T = 25 °C, DC measurement

Termination = 50 Ω to

V_CC- 1.64 V

V_CC

–2.06

V_OL

V_OD

ΔV_OD

Differential output voltage

800

|mV|

Change in V_ODfor complementary

output states

–115

115 mVpp

10-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

V_CC

0.99

-

V_OH

T = 25 °C, DC measurement

Termination = 50 Ω to

V_CC- 1.43 V

V_CC

1.97

-

V_OL

V_OD

ΔV_OD

980

|mv|

Change in V_ODfor complementary

output states

–115

115 mVpp

LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

20% to 80% output rise

R_L= 100 Ω, emitter resistors = 240 Ω to

GND

T_R/ T_F

150

ps

DCLKoutX_TYPE = 4 or 5

(1600 or 2000 mVpp)

80% to 20% output fall time

1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

V_CC

1.04

-

V_OH

V_OL

V_OD

Output high voltage

Output low voltage

V

DC measurement

Termination = 50 Ω to

V_CC- 2.0 V

V_CC

1.80

-

Output voltage

Figure 9

760

|mV|

2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

V_CC

1.09

-

V_OH

V_OL

V_OD

Output high voltage

Output low voltage

V

DC measurement

Termination = 50 Ω to V_CC- 2.3 V

V_CC

2.05

-

Output voltage

Figure 9

960

|mV|

LCPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)

V_OH

V_OL

Output high voltage

Output low voltage

1.57

0.62

V

DC measurement

Termination = 50 Ω to 0.5 V

Output voltage

Figure 9

V_OD

950

|mV|

22

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SNAS605AS –MARCH 2013–REVISED MAY 2020

Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

LVCMOS CLOCK OUTPUTS (OSCout)

TEST CONDITIONS

MIN

TYP

MAX UNIT

Maximum frequency

f_CLKout

V_OH

5-pF load

250

MHz

V

(21)

V_CC

-

Output high voltage

1-mA load

0.1

V_OL

I_OH

I_OL

Output low voltage

0.1

V

Output high current (source)

Output low current (sink)

V_CC= 3.3 V, V_O= 1.65 V

28

mA

V_CC/2 to V_CC/2,

F_CLK= 100 MHz, T = 25 °C

DUTY_CLK

Output duty cycle⁽²²⁾

50%

T_R

T_F

Output rise time

Output fall time

20% to 80%, R_L= 50 Ω, C_L= 5 pF

80% to 20%, R_L= 50 Ω, C_L= 5 pF

400

ps

DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)

I_OH= –500 µA

CLKin_SELX_TYPE = 3 or 4

Status_LDX_TYPE = 3 or 4

RESET_TYPE = 3 or 4

V_CC

0.4

-

V_OH

High-level output voltage

Low-level output voltage

V

I_OL= 500 µA

CLKin_SELX_TYPE = 3, 4, or 6

Status_LDX_TYPE = 3, 4, or 6

RESET_TYPE = 3, 4, or 6

V_OL

0.4

DIGITAL OUTPUT (SDIO)

I_OH= –500 µA ; During SPI read.

SDIO_RDBK_TYPE = 0

V_CC

0.4

-

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

I_OL= 500 µA ; During SPI read.

SDIO_RDBK_TYPE = 0 or 1

DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.2

–5

V_CC

0.4

V

DIGITAL INPUTS (CLKinX_SEL)

CLKin_SELX_TYPE = 0,

(high impedance)

5

High-level input current

V_IH= V_CC

I_IH

µA

CLKin_SELX_TYPE = 1 (pull-up)

CLKin_SELX_TYPE = 2 (pull-down)

–5

10

5

80

CLKin_SELX_TYPE = 0,

(high impedance)

–5

5

Low-level input current

V_IL= 0 V

I_IL

CLKin_SELX_TYPE = 1 (pull-up)

CLKin_SELX_TYPE = 2 (pull-down)

–40

–5

5

DIGITAL INPUT (RESET/GPO)

High-level input current

RESET_TYPE = 2

(pull-down)

I_IH

10

80

µA

V_IH= V_CC

RESET_TYPE = 0 (high impedance)

RESET_TYPE = 1 (pull-up)

–5

–40

–5

5

–5

5

Low-level input current

V_IL= 0 V

I_IL

RESET_TYPE = 2 (pull-down)

DIGITAL INPUTS (SYNC)

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CC

V_IL= 0 V

25

5

µA

–5

DIGITAL INPUTS (SCK, SDIO, CS*)

(21) Assured by characterization. ATE tested to 10 MHz.

(22) Assumes OSCin has 50% input duty cycle.

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Electrical Characteristics (continued)

(3.15 V < V_CC< 3.45 V, –40 °C < T_A< 85 °C and T_PCB≤ 105 °C. Typical values at V_CC= 3.3 V, T_A= 25 °C, at the

Recommended Operating Conditions and are not assured.)

PARAMETER

High-level input current

Low-level input current

TEST CONDITIONS

MIN

–5

TYP

MAX UNIT

I_IH

I_IL

V_IH= V_CC

V_IL= 0

5

µA

–5

DIGITAL INPUT TIMING

t_HIGH

RESET pin held high for device reset

25

ns

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7.6 SPI Interface Timing

TEST CONDITIONS

See Figure 1

MIN

10

TYP

MAX

UNIT

ns

td_s

Setup time for SDI edge to SCLK rising edge

td_H

Hold time for SDI edge from SCLK rising edge

Period of SCLK

See Figure 1

10

50⁽¹⁾

ns

t_SCLK

t_HIGH

t_LOW

tc_s

ns

High width of SCLK

25

ns

Low width of SCLK

25

ns

Setup time for CS* falling edge to SCLK rising edge

10

ns

tc_H

Hold time for CS* rising edge from SCLK rising edge See Figure 1

SCLK falling edge to valid read back data See Figure 1

30

ns

td_v

20

ns

(1) 20 MHz

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK

signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed.

A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete, the CS* signal

should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is

sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this

programming.

4-wire mode read back has same timing as the SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 are written as 0.

SDIO

(WRITE)

A12 to A0,

D7 to D2

R/W

W1

W0

D1

D0

td_S

td_H

SCLK

tc_H

tc_S

t_HIGH

t_LOW

t_SCLK

SDIO

(Read)

D7 to

D2

D1

D0

Data valid only

during read

td_V

CS*

Figure 1. SPI Timing Diagram

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7.7 Typical Characteristics – Clock Output AC Characteristics

These plots show performance at frequencies beyond the point at which the part is ensured to operate, to give an idea of the

capabilities of the part. They do not imply any sort of ensured specification.

For Figure 2 through Figure 7, CLKout2_3_IDL=1; CLKout2_3_ODL=0; LVPECL20 with 240-Ω emitter resistors; DCLKout2

Frequency = 245.76 MHz; DCLKout2_MUX = 0 (Divider). For Figure 2 through Figure 5, Balun Prodyn BIB-100G. For

Figure 6 and Figure 7, Balun ADT2-1T+.

VCO_MUX = 0 (VCO0)

VCO0 = 1966.08 MHz

DCLKout2_DIV = 8

PLL2 Loop Filter Bandwidth = 288 kHz

PLL2 Phase Margin = 72°

VCO_MUX = 1 (VCO1)

VCO = 2949.12 MHz

DCLKout2_DIV = 6

VCO1_DIV = 0 (÷2)

PLL2 Loop Filter Bandwidth = 221 kHz

PLL2 Phase Margin = 70°

Figure 2. LMK04821 DCLKout2 Phase Noise

Figure 3. LMK04821 DCLKout2 Phase Noise

VCO_MUX = 0 (VCO0)

PLL2 Loop Filter Bandwidth = 303 kHz

PLL2 Phase Margin = 73°

VCO_MUX = 1 (VCO1)

PLL2 Loop Filter Bandwidth = 151 kHz

PLL2 Phase Margin = 64°

VCO0 = 1966.08 MHz

DCLKout2_DIV = 8

VCO = 2457.6 MHz

DCLKout2_DIV = 10

Figure 4. LMK04826 DCLKout2 Phase Noise

Figure 5. LMK04826 DCLKout2 Phase Noise

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Typical Characteristics – Clock Output AC Characteristics (continued)

These plots show performance at frequencies beyond the point at which the part is ensured to operate, to give an idea of the

capabilities of the part. They do not imply any sort of ensured specification.

For Figure 2 through Figure 7, CLKout2_3_IDL=1; CLKout2_3_ODL=0; LVPECL20 with 240-Ω emitter resistors; DCLKout2

Frequency = 245.76 MHz; DCLKout2_MUX = 0 (Divider). For Figure 2 through Figure 5, Balun Prodyn BIB-100G. For

Figure 6 and Figure 7, Balun ADT2-1T+.

VCO_MUX = 0 (VCO0)

VCO0 = 2457.6 MHz

DCLKout2_DIV = 10

PLL2 Loop Filter Bandwidth = 344 kHz

PLL2 Phase Margin = 73°

VCO_MUX = 1 (VCO1)

VCO = 2949.12 MHz

DCLKout2_DIV = 12

PLL2 Loop Filter Bandwidth = 233 kHz

PLL2 Phase Margin = 70°

Figure 6. LMK04828 DCLKout2 Phase Noise

Figure 7. LMK04828 DCLKout2 Phase Noise

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8 Parameter Measurement Information

8.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= V_CC- ΔV

I2 = Charge Pump Sink Current at V_CPout= V_CC/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= V_CC- ΔV

I5 = Charge Pump Source Current at V_CPout= V_CC/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

8.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage

8.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch

8.1.3 Charge Pump Output Current Magnitude Variation Vs. Ambient Temperature

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8.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions, which can cause

confusion when reading data sheets or communicating with other engineers. This section addresses the

measurement and description of a differential signal, so that the reader can understand and distinguish between

the two different definitions.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and non-inverting signal. The symbol for this first measurement is typically V_IDor V_OD, depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal

with respect to the inverting signal. The symbol for this second measurement is V_SS, and is a calculated

parameter. This signal does not exist in the IC with respect to ground; it only exists in reference to its differential

pair. V_SScan be measured directly by oscilloscopes with floating references; otherwise this value can be

calculated as twice the value of V_OD, as described in the first description.

Figure 8 illustrates the two different definitions side-by-side for inputs, and Figure 9 illustrates the two different

definitions side-by-side for outputs. The V_IDand V_ODdefinitions show V_Aand V_BDC levels that the non-inverting

and inverting signals toggle between with respect to ground. V_SSinput and output definitions show that if the

inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now

increasing and decreasing above and below the non-inverting reference. Thus, the peak-to-peak voltage of the

differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

V

ID

Definition

V

Definition for Input

SS

Non-Inverting Clock

V

A

B

2·V

V

ID

Inverting Clock

= | V - V

V

|

B

V

SS

= 2·V

ID

A

GND

Figure 8. Two Different Definitions for

Differential Input Signals

V

Definition

V

Definition for Output

SS

OD

Non-Inverting Clock

V

A

B

2·V

OD

V

OD

Inverting Clock

= | V - V

V

|

B

V

SS

= 2·V

OD

A

GND

Figure 9. Two Different Definitions for

Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

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9 Detailed Description

9.1 Overview

The LMK0482x family are multi-purpose, jitter cleaning dual-PLL circuits, with user-programmable settings to

support a flexible set of configurations for many different application requirements. PLL1 is optimized for use with

an external VCXO as the PLL oscillator, while PLL2 includes a dual-range integrated VCO and distributes the

VCO output to 7 integrated 10-bit channel dividers and a 13-bit SYSREF divider, yielding a total of 14 differential

clock outputs at up to 8 different frequencies.

The primary use case is as a dual-loop jitter cleaner (dual-loop mode), when using a reference clock with good

frequency accuracy but poor phase noise to generate ultra-low jitter output clocks. Dual-loop mode also helps to

maintain a high phase detector frequency and loop bandwidth in the clock generation PLL when the greatest

common divisor of the reference clock frequency and the output clock frequencies is small, avoiding a low phase

detector frequency that would elevate output clock phase noise.

Both PLLs can optionally be disabled. By disabling PLL1, the LMK0482x can be used as a standard single-PLL

clock generator with integrated VCO (single-loop mode). By disabling both PLLs, the LMK0482x can act as a

distribution buffer/divider, directly connecting an input reference to the clock dividers and the SYSREF divider.

The clock output dividers can also be bypassed or set to divide of 1 for distribution only mode.

In a typical dual-loop configuration, the external VCXO is connected to the PLL1 N-divider, and the integrated

VCO is connected to the N-divider directly. However, by routing the divided clock or SYSREF output of PLL2 to

the N-divider of PLL1, PLL2, or both PLLs in a family of configurations called zero-delay mode, the LMK0482x

can establish a deterministic phase relationship between reference input phase and clock output phase. Using

zero-delay mode, multiple LMK0482x can be cascaded to fan out exponentially more outputs, while maintaining

predictable input-to-output phase throughout the whole chain of devices. Zero-delay mode is supported in

singleloop and dual-loop mode, with two dual-loop configurations: nested dual-loop (feedback connected to PLL1

Ndivider) and cascaded dual-loop (feedback connected to PLL2 N-divider).

The LMK0482x may be used in JESD204B sytems by providing a device clock and SYSREF to up to 7 devices.

However, alternate (non-JESD204B) systems are also possible by programming pairs of outputs to share the

clock divider. Any mix of JESD204B and alternate systems can be supported.

9.1.1 Jitter Cleaning

The dual-loop PLL architecture of the LMK0482x family provides the lowest jitter performance over a wide range

of output frequencies and phase-noise integration bandwidths. The first-stage PLL (PLL1) is driven by an

external reference clock, and uses an external VCXO or tunable crystal to provide a frequency accurate, low

phase-noise reference clock for the second-stage frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow-loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference

clock input signal, while at the same time suppressing the higher offset frequency phase noise that the reference

clock may have accumulated along its path or from other circuits. This “cleaned” reference clock provides the

reference input to PLL2.

The low phase-noise reference provided to PLL2 allows PLL2 to operate with a wide-loop bandwidth (typically 50

kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high-offset frequency

phase-noise profile of the internal VCO, and the good low-offset frequency phase noise of the reference VCXO

or tunable crystal.

Ultra low jitter is achieved by allowing the external VCXO or crystal phase noise to dominate the final output

phase noise at low-offset frequencies, and the internal VCO phase noise to dominate the final output phase

noise at high-offset frequencies. This results in best overall phase noise and jitter performance.

9.1.2 JEDEC JESD204B Support

The LMK0482x family provides support for JEDEC JESD204B. The LMK0482x clocks up to 7 JESD204B targets

using 7 device clocks (DCLKoutX) and 7 SYSREF clocks (SDCLKoutY). Each device clock is grouped with a

SYSREF clock.

The user can reprogram SYSREF clocks to behave as extra device clocks for applications which have non-

JESD204B clock requirements.

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Overview (continued)

9.1.3 Three PLL1 Redundant Reference Inputs

The LMK0482x family has up to three reference clock inputs for PLL1. They are CLKin0, CLKin1, and CLKin2.

The active clock is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the

inputs.

CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers. CLKin0, CLKin1, and CLKin2 each support

differential or single-ended inputs, and support DC coupling or AC coupling. See Driving CLKin and OSCin

Inputs.

CLKin1 is shared for use as an external zero-delay feedback (FBCLKin), or for use with an external VCO (Fin).

CLKin2 is shared for use as OSCout. To use CLKin2 as an input, OSCout must be powered down. See

VCO_MUX, OSCout_MUX, OSCout_FMT.

Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1.

For clock distribution mode, a reference signal is applied to the Fin pins for clock distribution. CLKin0 can also be

used to distribute a SYSREF signal through the device. In this use case, CLKin0 may be re-clocked by Fin, or

can be routed directly to the SYSREF outputs.

9.1.4 VCXO/Crystal Buffered Output

CLKin2 may instead be configured as OSCout, which by default is a buffered copy of the PLL1 feedback/PLL2

reference input (OSCin). This reference input is typically a low-noise VCXO or crystal. When using a VCXO, this

output can be used to clock external devices such as microcontrollers, FPGAs, and CPLDs, before the

LMK0482x is programmed.

The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS. OSCout LVPECL mode only

supports 240-Ω emitter resistors.

The VCXO/crystal buffered output can be synchronized to the VCO clock distribution outputs by using cascaded

zero-delay mode. The buffered output of VCXO/crystal has a deterministic phase relationship with CLKin.

9.1.5 Frequency Holdover

When the reference inputs to PLL1 are lost, the LMK0482x family can enter holdover mode until a valid

reference clock signal is re-established. Holdover mode forces a constant DC voltage output to the control pin of

the PLL1 VCXO, ensuring minimal frequency drift while the reference inputs are absent.

9.1.6 PLL2 Integrated Loop Filter Poles

The LMK0482x family features programmable 3rd- and 4th-order loop filter poles for PLL2. These internal

resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd- or 4th-order

loop filter response. The integrated programmable resistors and capacitors compliment external components

mounted near the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

9.1.7 Internal VCOs

The LMK0482x family has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed

to the clock distribution path. This same selection is also fed back to the PLL2 phase detector through a

prescaler and N-divider.

9.1.7.1 VCO1 Divider (LMK04821 only)

The LMK04821 includes a VCO divider on the output of VCO1. The VCO1 divider can be programmed from 2 to

8.

When using a VCO1 frequency of 2949.12 MHz and a divide of 8, frequencies as low as 11.52 MHz can be

achieved. Using the VCO1_DIV limits the maximum output frequency from any output to the VCO1 frequency,

divided by VCO1_DIV value.

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Overview (continued)

When using VCO1, the output frequency from the VCO1_DIV defines the digital delay resolution.

The VCO1_DIV divider also impacts the total N divide value for PLL2 when VCO1 is selected; this should be

accounted for when selecting PLL2_N and PLL2_P value.

9.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK0482x family.

Using an external VCO prevents the use of CLKin1 for other purposes.

9.1.9 Clock Distribution

The LMK0482x family features a total of 14 PLL2 clock outputs, driven from the internal or external VCO.

All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL, LVDS, or HSDS,

or LCPECL.

If OSCout is included in the total number of clock outputs the LMK0482x family is able to distribute, then up to 15

differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF. Its output

format is programmable to LVDS, LVPECL, or LVCMOS. OSCout LVPECL mode only supports 240-Ω emitter

resistors.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

9.1.9.1 Device Clock Divider

Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32

(even and odd) with 50% output duty cycle, using duty cycle correction mode. The output of this divider may also

be directed to SDCLKoutY, where Y = X + 1.

9.1.9.2 SYSREF Clock Divider

The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191

(even and odd).

9.1.9.3 Device Clock Delay

The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.

The analog delay allows a nominal 25-ps step size, and range from 0 to 575 ps of total delay. Enabling the

analog delay adds a nominal 500 ps of delay, in addition to the programmed value.

The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles. The delay step can be as

small as half the period of the clock distribution path. For example, a 2-GHz VCO frequency results in 250 ps

coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

There are two ways to use the digital delay.

1. Fixed digital delay – Allows all the outputs to have a known phase relationship upon a SYNC event. Typically

performed at startup.

2. Dynamic digital delay – Allows the phase relationships of the clocks to change while the clocks continue to

operate.

9.1.9.4 SYSREF Delay

The global SYSREF divider includes a digital delay block, which allows a global phase shift with respect to the

other clocks.

Each local SYSREF clock output includes both an analog and additional local digital delay, for unique phase

adjustment of each SYSREF clock.

The local analog delay allows for 150-ps steps.

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Overview (continued)

The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from, 1.5 to

11 VCO cycles. The delay step can be as small as half the period of the clock distribution path, by using the

DCLKoutX_HS bit. For example, a 2-GHz VCO frequency results in 250 ps coarse tuning steps.

9.1.9.5 Glitchless Half Step and Glitchless Analog Delay

The device clocks include a feature to ensure glitchless operation of the half step and analog delay operations,

when enabled.

9.1.9.6 Programmable Output Formats

For increased flexibility all LMK0482x family device and SYSREF clock outputs, DCLKoutX and SDCLKoutY, can

be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. The OSCout can be programmed to an

LVDS, LVPECL, or LVCMOS output type. OSCout LVPECL mode only supports 240-Ω emitter resistors.

Any LVPECL output type can be programmed to 1600- or 2000-mVpp amplitude levels. The 2000-mVpp

LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential

swing for compatibility with many data converters, and is known as 2VPECL.

LCPECL allows for DC coupling SYSREF to low-voltage converters.

9.1.9.7 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge, as programmed by fixed digital

delay.

The SYNC event must occur for digital delay values to take effect.

9.1.10 Zero-Delay

The LMK0482x family supports two types of zero-delay.

1. Cascaded zero-delay

2. Nested zero-delay

Cascaded zero-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input

clock (OSCin) to the phase of a clock selected by the feedback mux. The zero-delay feedback may performed

with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin

port as selected by the FB_MUX. Because OSCin has a fixed deterministic phase relationship to the feedback

clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode, the

PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin); this

results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs.

Nested zero-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock

(CLKinX) to the phase of a clock selected by the feedback mux. The zero-delay feedback may performed with an

internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as

selected by the FB_MUX.

Without using zero-delay mode, there are numerous possible fixed phase relationships from clock input to clock

output, depending on the clock output divide value. Careful selection of the zero-delay feedback value can

reduce the number of fixed phase relationships from clock input to clock output, potentially to as few as one. As

a result, zero-delay simplifies input-to-output phase guarantees, especially across multiple devices. For more

information, see the application note Multi-Clock Synchronization.

Using an external zero-delay feedback prevents the use of CLKin1 for other purposes.

9.1.11 Status Pins

The LMK0482x provides status pins, which can be monitored for feedback, or in some cases used for input

depending upon device programming. For example:

•

The CLKin_SEL0 pin may be configured as an output, indicating the LOS (loss-of-signal) for CLKin0.

The CLKin_SEL1 pin may be configured as an input, for selecting the active clock input.

The Status_LD1 pin may indicate if the device is locked (PLL1 and PLL2 locked).

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Overview (continued)

•

The Status_LD2 pin may indicate if PLL2 is locked.

The status pins can be programmed to a variety of other outputs, including PLL divider outputs, combined PLL

lock detect signals, PLL1 Vtune railing, SPI readback, and so forth. Refer to the programming section of this data

sheet for more information.

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9.2 Functional Block Diagram

Figure 10 and Figure 11 illustrate the complete LMK0482x family block diagram.

Figure 10. Detailed LMK04821 Block Diagram

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Functional Block Diagram (continued)

Figure 11. Detailed LMK04826 and LMK04828 Block Diagram

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Functional Block Diagram (continued)

CLKoutX_Y_PD

DCLKout6/8 to FB_MUX

DCLKoutX_ADLY_PD

DCLKoutX_ADLYg_PD

DCLKoutX_DDLY_PD

DCLKoutX_HSg_PD

DCLKout0, 2, 4, 6, 8, 10, 12

VCO

DDLY Divider

(4 to 32) (1 to 32)

HS/

DCC

DCLKoutX

_MUX

DCLKoutX_

FMT

DCLKoutX

_ADLY

_MUX

Analog

DLY

DDDLYdX_EN

CLKoutX_Y_ODL

SYNC_

1SHOT_EN

CLKoutX_Y_IDL

SYSREF_GBL_PD

SDCLKoutY_DIS_MODE

One

Shot

SDCLKoutY

_POL

SYNC_

DISX

SDCLKoutY_PD

SDCLKoutY

_MUX

SDCLKoutY_

FMT

SDCLKoutY

_ADLY_EN

SYSREF/SYNC

Digital

DLY

Half

Step

Analog

DLY

SDCLKout1, 3, 5, 7, 9, 11, 13

Legend

SYSREF/SYNC Clock

SYSREF_CLR

SPI Register

VCO/Distribution Clock

Figure 12. Device and SYSREF Clock Output Block

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Functional Block Diagram (continued)

Figure 13. SYNC/SYSREF Clocking Paths

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9.3 Feature Description

9.3.1 SYNC/SYSREF

To properly use SYNC or SYSREF for JESD204B, it is important to understand the SYNC/SYSREF system. The

SYNC and SYSREF signals share the same clocking path, with SYNC_DISX bits used to enable the path from

SYSREF/SYNC to each divider reset port. Figure 12 illustrates the detailed diagram of a clock output block with

SYNC circuitry included.Figure 13 illustrates the interconnects and highlights some important registers used in

controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.

2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF

signal.

–

If SYSREF block is being used, the SYSREF_PD bit must be clear.

If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.

For each SDCLKoutY being used for SYSREF, respective SDCLKoutY_PD bits must be cleared.

3. SYSREF_DDLY_PD and DCLKoutX_DDLY_PD bits must be clear to power up the digital delay circuitry

during SYNC. After the SYNC event, these bits may be set to reduce power consumption.

4. The SYNC_DISX bit must be clear to allow the SYNC/SYSREF signal to reset the divider circuit. The

SYSREF_MUX register selects the SYNC source.

5. Other bits which impact the operation of SYNC, such as SYNC_1SHOT_EN, may be set as desired.

Table 1 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 1. Some Possible SYNC Configurations

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

SYNC disabled

0

CLKin0_OUT_MUX ≠ 0

No SYNC occurs.

Basic SYNC functionality, SYNC pin polarity is

selected by SYNC_POL.

To achieve SYNC through SPI, toggle the

SYNC_POL bit.

Pin or SPI SYNC

1

0

CLKin0_OUT_MUX ≠ 0

Differential input

SYNC

0 or 1

2

0 or 1

2

CLKin0_OUT_MUX = 0

Differential CLKin0 now operates as SYNC input.

Produce SYSREF_PULSE_CNT programmed

number of pulses on pin transition. SYNC_POL can

be used to cause SYNC through SPI.

JESD204B pulser

on pin transition.

SYSREF_PULSE_CNT

sets pulse count

JESD204B pulser

on SPI

programming.

SYSREF_PULSE_CNT

sets pulse count

Programming the SYSREF_PULSE_CNT register

starts sending the number of pulses.

3

1

2

1

SYSREF operational,

SYSREF divider as

required for training frame for non-JESD converters such as LM97600.

size.

Allows precise SYNC for n-bit frame training patterns

Re-clocked SYNC

When the SYNC pin is asserted, continuous SYSERF

External SYSREF

request

SYSREF_REQ_EN = 1

Pulser powered up

pulses occur. Turning on and off of the pulses is

synchronized, to prevent runt pulses from occurring

on SYSREF.

0

2

3

SYSREF_PD = 0

SYSREF_DDLY_PD = 0

Continuous SYSREF signal. Useful for validating

phase alignment of SYSREF clocks, but not

recommended for use in low-noise applications due to

crosstalk spurs.

Continuous

SYSREF

X

SYSREF_PLSR_PD = 1

(1)

(1) SDCLKoutY_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SDCLKoutY when

SDCLKoutY_MUX = 1 (SYSREF output)

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Feature Description (continued)

Table 1. Some Possible SYNC Configurations (continued)

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

CLKin0_OUT_MUX = 0

SDCLKoutY_DDLY = 0

(Local sysref DDLY

bypassed)

SYSREF_DDLY_PD = 1

SYSREF_PLSR_PD = 1

SYSREF_PD = 1.

Direct SYSREF

distribution

A direct fan-out of SYSREF with no re-clocking to

clock distribution path.

0

9.3.2 JEDEC JESD204B

9.3.2.1 How To Enable SYSREF

Table 2 summarizes the bits needed to make SYSREF functionality operational.

Table 2. SYSREF Bits

REGIS

TER

FIELD

VALUE

DESCRIPTION

Must be clear to power-up SYSREF circuitry.

0x140

SYSREF_PD

0

1

SYSREF_DDLY_

PD

0x140

0x143

Must be clear to power-up digital delay circuitry during initial SYNC, to ensure deterministic timing.

Must be set to enable SYNC.

SYNC_EN

Do not hold local SYSREF_DDLY block in reset except at start.

Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set

SYSREF_CLR for 15 clock distribution path cycles to clear the local SYSREF digital delay. After

clearing local delays, SYSREF_CLR must be cleared to allow SYSREF to operate.

0x143

SYSREF_CLR

1 → 0

Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divider, then

configuring the actual SYSREF functionality.

9.3.2.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system operating with a 3000-MHz VCO frequency.

Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz. Use DCLKout4 to drive an FPGA at 150 MHz.

Synchronize the converters and FPGA using two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x1fff as desired. Key to prepare for SYSREF operations (see Recommended

Programming Sequence):

a. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0

b. Setup output dividers as per example: DCLKout0_DIV and DCLKout2_DIV = 2 for frequency of 1500

MHz. DCLKout4_DIV = 20 for frequency of 150 MHz.

c. Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF

d. Setup SYSREF: SYSREF_PD

=

0, SYSREF_DDLY_PD

=

0, DCLKout0_DDLY_PD

=

0,

DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0,

SYSREF_PULSE_CNT = 1 (2 pulses). SDCLKout1_PD = 0, SDCLKout3_PD = 0

e. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and the device clock for JESD204B:

a. Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL,

DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL,

SYSREF_DDLY.

b. Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS.

c. Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY,

SDCLKout3_DDLY, SDCLKout5_DDLY.

d. To allow SYNC to effect dividers: SYNC_DIS0

SYNC_DISSYSREF = 0

= 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0,

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e. Perform SYNC by toggling SYNC_POL = 1, then SYNC_POL = 0.

3. When the dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for

SYSREF to reset it's own divider or the dividers of the output clocks.

a. Prevent SYSREF from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,

SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay.

a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path cycles after

SYSREF_PD = 0.

5. Set SYSREF operation.

a. Allow pin SYNC event to start pulser: SYNC_MODE = 2.

b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. After the procedure is complete, asserting the SYNC pin or toggling SYNC_POL results in a series of 2

SYSREF pulses.

9.3.2.1.2 SYSREF_CLR

The local digital delay of the SDCLKout is implemented as a shift buffer. To ensure no unwanted pulses occur at

this SYSREF output at startup when using SYSREF, clear the buffers by setting SYSREF_CLR = 1 for 15 VCO

clock cycles. This bit is set after a reset; thus, it must be cleared before the SYSREF output is used.

9.3.2.2 SYSREF Modes

9.3.2.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming.

This implements the gapped periodic functionality of the JEDEC JESD204B specification.

When in SYSREF pulser mode, programming the field SYSREF_PULSE_CNT in register 0x13E results in the

pulser sending the programmed number of pulses.

9.3.2.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

Continuous operation of SYSREF is not recommended, due to crosstalk from the SYSREF clock to device clock.

JESD204B is designed to operate with a single burst of pulses to initialize the system at startup, after which it is

theoretically not required to send another SYSREF, because the system continues to operate with deterministic

phases.

If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or

SYSREF from the OSCout pin, to minimize crosstalk.

9.3.2.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses,

using the SYNC/SYSREF_REQ pin.

Set up the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not

need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX is synchronously set to continuous mode, providing

continuous pulses at the SYSREF frequency, until the SYSREF_REQ pin is unasserted and the final SYSREF

pulse completes sending synchronously.

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9.3.3 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 4 to 32 VCO cycles. The delay step can be as

small as half the period of the VCO cycle, by using the DCLKoutX_HS bit. There are two ways to use the digital

delay:

1. Fixed digital delay

2. Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value. The substitute divide

value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum

_CNTH/_CNTL value is 2 and the maximum _CNTH/_CNTL value is 16. This results in a minimum alternative

divide value of 4 and a maximum of 32.

9.3.3.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs are LOW for

a while during the SYNC event. Applications that cannot accept clock interruption when adjusting digital delay

should use dynamic digital delay.

9.3.3.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations, and the application should delay DCLKout2

by one VCO cycle compared to DCLKout0:

•

VCO frequency = 2949.12 MHz

DCLKout0 = 368.64 MHz (DCLKout0_DIV = 8)

DCLKout2 = 368.64 MHz (DCLKout2_DIV = 8)

These steps should be followed:

1. Set DCLKout0_DDLY_CNTH = 4 and DCLKout2_DDLY_CNTH = 4. First part of delay for each clock.

2. Set DCLKout0_DDLY_CNTL = 4 and DCLKout2_DDLY_CNTL = 5. Second part of delay for each clock.

3. Set DCLKout0_DDLY_PD = 0 and DCLKout2_DDLY_PD = 0. Power up the digital delay circuit.

4. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the output to be synchronized.

5. Perform SYNC by asserting, then deasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.

6. When the SYNC is complete, power down DCLKout0_DDLY_PD = 1 and/or DCLKout2_DDLY_PD = 1 to

save power.

7. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1, to prevent the outputs from being synchronized by other

SYNC/SYSREF events.

No CLKout during SYNC

DCLKout0

368.64 MHz

DCLKout2

368.64 MHz

SYNC event

1 VCO cycle delay

Figure 14. Fixed Digital Delay Example

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9.3.3.2 Dynamic Digital Delay

Dynamic digital delay allows the phase of clocks to be changed with respect to each other, with little impact to

the clock signal. This is accomplished by substituting the regular clock divider with an alternate divide value for

one cycle. This substitution occurs

a number of times equal to the value programmed into the

DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.

•

By programming a larger alternate divider (delay) value, the phase of the adjusted outputs is delayed with

respect to the other clocks.

By programming a smaller alternate divider (delay) value, the phase of the adjusted output is advanced with

respect to the other clocks.

Table 3 shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting

for delay by one VCO cycle. The clock output is high during the DCLKoutX_DDLY_CNTH time to permit a

continuous output clock. The clock output is low during the DCLKoutX_DDLY_CNTL time.

Table 3. Recommended DCLKoutX_DDLY_CNTH/_CNTL Values for Delay by One VCO Cycle

CLOCK DIVIDER

_CNTH

_CNTL

CLOCK DIVIDER

_CNTH

9

_CNTL

9

2

3

2

3

2

3

4

5

6

7

8

3

4

3

4

5

6

7

8

9

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

9

10

4

10

11

12

13

14

15

0⁽¹⁾

10

5

11

6

11

7

12

8

12

9

13

10

11

12

13

14

15

16

13

14

15

0⁽¹⁾

(1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.

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9.3.3.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay

of 1 VCO cycle occurs between DCLKout2 and DCLKout0. In the second adjustment, two delays of 1 VCO cycle

occur between DCLKout2 and DCLKout0. At this point in the example, DCLKout2 is delayed 3 VCO cycles

behind DCLKout0.

Assuming the device already has the following initial configurations:

•

VCO frequency: 2949.12 MHz

DCLKout0 = 368.64 MHz, DCLKout0_DIV = 8

DCLKout2 = 368.64 MHz, DCLKout2_DIV = 8

The following steps illustrate the example above:

1. Set DCLKout2_DDLY_CNTH = 4. First part of delay for DCLKout2.

2. Set DCLKout2_DDLY_CNTL = 5. Second part of delay for DCLKout2.

3. Set DCLKout2_DDLY_PD = 0. Enable the digital delay for DCLKout2.

4. Set DDLYd2_EN = 1. Enable dynamic digital delay for DCLKout2.

5. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 0. Sync should be disabled to DCLKout0, but not DCLKout2.

6. Set SYNC_MODE = 3. Enable SYNC event from SPI write to the DDLYd_STEP_CNT register.

7. Set SYNC_MODE = 2, SYSREF_MUX = 2. Setup proper SYNC settings.

8. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 8 DCLKout2 clock edge is aligned with DCLKout0.

After step 8, DCLKout2 counts four VCO cycles high and then five VCO cycles low as programmed by

DCLKout2_DDLY_CNTH and DCLKout2_DDLY_CNTL fields, effectively delaying DCLKout2 by one VCO

cycle with respect to DCLKout0. This is the first adjustment.

9. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 9, DCLKout2 clock edge was delayed 1 VCO cycle from DCLKout0.

After step 9, DCLKout2 counts four VCO cycles high and then five VCO cycles low, as programmed by

DCLKout2_DDLY_CNTH and DCLKout2_DDLY_CNTL fields twice, delaying DCLKout2 by two VCO cycles

with respect to DCLKout0. This is the second adjustment.

VCO

2949.12 MHz

DCLKout0

368.64 MHz

DCLKout2

368.64 MHz

First

Adjustment

CNTH = 4 CNTL = 5

DCLKout2

368.64 MHz

Second

Adjustment

CNTH = 4 CNTL = 5

Figure 15. Single and Multiple Adjustment Dynamic Digital Delay Example

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9.3.4 SYSREF to Device Clock Alignment

To ensure proper JESD204B operation, the timing relationship between the SYSREF and the device clock must

be adjusted for optimum setup and hold time as shown in

Added timing alignment figure, alignment equations to SYSREF to Device Clock Alignment . The global SYSREF

digital delay (SYSREF_DDLY). local SYSREF digital delay (SDCLKoutY_DDLY), local SYSREF half step

(SDCLKoutY_HS), and local SYSREF analog delay (SDCLKoutY_ADLY, SDCLKoutY_ADLY_EN) can be

adjusted to provide the required setup and hold time between SYSREF and device clock. It is also possible to

adjust the device clock digital delay (DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL), device clock half step

(DCLKoutX_HS), device clock analog delay (DCLKoutX_ADLY, DCLKoutX_ADLY_EN), and device clock muxes

(DCLKoutX_MUX, DCLKoutX_ADLY_MUX) to adjust phase with respect to SYSREF.

Figure 16. SYSREF to Device Clock Timing Alignment

Depending on the settings for DCLKoutX and the SYSREF divider, some adjustment may be needed to correctly

align DCLKoutX to SDCLKoutY. Equation 1 and Equation 2 predict the relative DCLKoutX to SDCLKoutY delay:

DELAY_DCLK= DCLKoutX_DDLY_CNTH + DCLKoutX_DDLY_CNTL

(1)

DELAY_SDCLK= SYSREF_DDLY + SDCLKoutY_DDLY + SYSREF_DIV_ADJUST + DCLKout_MUX_ADJUST

where

•

SYSREF_DIV_ADJUST = 2 IF (SYSREF_DIV % 4 < 2) ELSE 3

DCLKoutX_MUX_ADJUST = 1 IF (Duty Cycle Correction enabled) ELSE 0

(2)

For the relative delay equations, the cycle delay rather than the register value should be used, since cycle delay

does not always equal register value (example: _CNTH/_CNTL=0, delay=16). Device clock duty cycle correction

can be enabled for both digital and analog paths, either by setting DCLKoutX_MUX=1 (digital only), or by setting

DCLKoutX_MUX=3 and DCLKoutX_ADLY_MUX=1. If half step is enabled on either path, delay can be included

by subtracting 0.5 from the enabled path. As an example, if DCLKoutX_DDLY_CNTH=7,

DCLKoutX_DDLY_CNTL=6,

SYSREF_DDLY=8,

SDCLKoutY_DDLY=2

cycles,

SYSREF_DIV=30,

DCLKoutX_MUX=1, DCLKoutX_HS=0, SDCLKoutX_HS=0:

•

DELAY_DCLK= 7 + 6 = 13

SYSREF_DIV_ADJUST = (30 % 4 < 2) ? 2 : 3 = 3

DCLKoutX_MUX_ADJUST = DCC ? 1 : 0 = 0

DELAY_SDCLK= 8 + 2 + 3 + 0 = 13

To calculate the expected time delay from the first edge of DCLKoutX to the first edge of SDCLKoutY, refer to

Equation 3. Substitute the analog delays with the appropriate time values (in seconds) according to

DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX and SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY.

ts_JESD204Bis provided in the Electrical Characteristics section for the conditions in the example above as -80 ps.

t_{DCLK-to-SDCLK}= (F_Distribution

)

^-1× (DELAY_SDCLK- DELAY_DCLK) + SDCLKoutY_ADLY - DCLKoutY_ADLY + ts_JESD204B

(3)

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9.3.5 Input Clock Switching

Manual, pin select, and automatic are three kinds clock input switching modes that can be set with the

CLKin_SEL_MODE register.

The following sections describe how the active input clock is selected and what causes a switching event in the

various clock input selection modes.

9.3.5.1 Input Clock Switching - Manual Mode

When CLKin_SEL_MODE is 0, 1, or 2, then CLKin0, CLKin1, or CLKin2 respectively is always selected as the

active input clock. Manual mode also overrides the EN_CLKinX bits, such that the CLKinX buffer operates even if

EN_CLKinX = 0.

If holdover is entered in this mode, the device re-locks to the selected CLKin upon holdover exit.

9.3.5.2 Input Clock Switching - Pin Select Mode

When CLKin_SEL_MODE is 3, the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active.

Configuring Pin Select Mode

The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input

for pin select mode.

The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input

for pin select mode.

If the CLKin_SELX_TYPE is set as output, the pin input value is considered low.

The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit.

Table 4 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state.

Table 4. Active Clock Input - Pin Select Mode, CLKin_SEL_INV = 0

PIN CLKin_SEL1

PIN CLKin_SEL0

ACTIVE CLOCK

CLKin0

Low

High

Low

High

Low

High

CLKin1

CLKin2

Holdover

The pin select mode ignores the EN_CLKinX bits, such that the CLKinX buffer operates even if EN_CLKinX = 0.

To switch as fast as possible, keep the switchable clock input buffers enabled (EN_CLKinX = 1).

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9.3.5.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_MODE is 4 and LOS_EN = 1, the active clock is selected in round-robin order of enabled

clock inputs, starting on an input clock switch event. The switching order of the clocks is CLKin0 → CLKin1 →

CLKin2 → CLKin0, and so forth.

For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX. The

LOS_TIMEOUT should also be set to a frequency below the input frequency.

To ensure LOS is valid for AC-coupled inputs, the MOS mode must be set for CLKinX and no termination is

allowed to be between the pins unless DC-blocked. For example, with an LVDS differential signal into CLKin0, no

100-Ω termination should be placed directly across CLKin0 and CLKin0* pins on the IC side of the AC coupling

capacitors. 100 Ω could instead be placed on the transmitter side of the AC coupling capacitors.

Starting Active Clock

When programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a

particular clock input is the active clock when starting this mode, program CLKin_SEL_MODE to the manual

mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select

this mode with CLKin_SEL_MODE = 4.

9.3.6 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference

path (R) and the feedback path (N) of the PLL at the phase detector. When the time error(phase error) between

the two signals is less than a specified window size (ε), a lock detect count increments. When the lock detect

count reaches a user-specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted (true). When

digital lock detect is true, a single phase comparison outside the specified window causes digital lock detect to

be deasserted (false). This is illustrated in Figure 17 .

NO

PLLX

Lock Detected = False

Lock Count = 0

YES

Increment

PLLX Lock Count

PLLX

Lock Detected = True

PLLX Lock Count =

PLLX_DLD_CNT

START

Phase Error < g

YES

NO

Figure 17. Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter, to ensure that lock detect is not asserted

when the phases of R and N are within the specified tolerance for a brief time during initial phase lock.

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to

achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be

programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting

Holdover for more info.

NOTE

In cases where the period of the phase detector frequency approaches the value of the

default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with

the default value of PLL1_WND_SIZE. For PLL1 phase detector frequencies at or above

25 MHz, TI recommends setting PLL1_WND_SIZE less than or equal to 0x02 (19 ns).

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9.3.7 Holdover

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock

reference to PLL1 becomes invalid, when PLL1 loses lock, or when the CPout1 voltage is outside of a user-

specified acceptable range. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning

voltage is set on CPout1 to operate PLL1 in open loop.

9.3.7.1 Enable Holdover

Program HOLDOVER_EN = 1 to enable holdover mode. Enabling holdover mode does not place the device in

holdover unless the relevant criteria have been met (example: PLL1 loss of lock). Program HOLDOVER_FORCE

= 1 to force the device into holdover.

Holdover mode can be configured to set the CPout1 voltage upon holdover entry, to a fixed user-defined voltage

or a tracked voltage.

9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode

By programming MAN_DAC_EN = 1, the MAN_DAC value is set on the CPout1 pin during holdover.

The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value,

then reprogram MAN_DAC value to a user-desired value based on information from previous DAC read backs.

This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.

9.3.7.1.2 Tracked CPout1 Holdover Mode

By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 is set on the CPout1

pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set,

which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX,

respectively.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector

frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR).

The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy.

The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024-

kHz PLL1 phase-detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the

device to look-back and set CPout1 at previous "good" CPout1 tuning voltage values before the event which

caused holdover to occur.

The current voltage of DAC value can be read back using RB_DAC_VALUE; see RB_DAC_VALUE.

9.3.7.2 Entering Holdover

There are several ways to enter holdover.

•

HOLDOVER_LOS_DET = 1 and a loss of active reference is detected.

HOLDOVER_PLL1_DET = 1 and PLL1 loss of lock is detected.

HOLDOVER_VTUNE_DET = 1 and the voltage monitored by the DAC on CPout1 is less than the value set

by DAC_TRIP_LOW, or greater than the value set by DAC_TRIP_HIGH.

•

HOLDOVER_FORCE = 1.

9.3.7.3 During Holdover

PLL1 is run in open-loop mode.

•

PLL1 charge pump is set to TRI-STATE.

PLL1 DLD is deasserted.

The HOLDOVER status is asserted.

During holdover, if PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.

CPout1 voltage is set to:

–

a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).

a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).

•

PLL1 attempts to lock with the active clock input.

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The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the

PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.

9.3.7.4 Exiting Holdover

Holdover mode can be exited in one of two ways.

•

Manually, by programming the device from the host.

Automatically, by a clock operating within a specified ppm of the current PLL1 frequency on the active clock

input.

9.3.7.5 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If fixed CPout1 mode is

used, then the output of the DAC is voltage-dependant upon the MAN_DAC register. If tracked CPout1 mode is

used, then the output of the DAC is the voltage at the CPout1 pin before holdover mode was entered. When

using tracked mode and MAN_DAC_EN = 1, during holdover the DAC value is loaded with the programmed

value in MAN_DAC, not the tracked value.

When in tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs when PLL1 tuning voltage is

acquired. The step size is approximately 3.2 mV, thus the VCXO frequency error during holdover mode caused

by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use. Thus, the

accuracy of the system when in holdover mode in ppm is:

6.4 mV × Kv × 1e6

Holdover accuracy (ppm) =

VCXO Frequency

(4)

Example: consider a system with a 19.2-MHz clock input, and a 153.6-MHz VCXO with a Kv of 17 kHz/V. The

accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

(5)

It is important to account for this frequency error when determining the allowable frequency error window to

cause holdover mode to exit.

9.3.7.6 Holdover Mode - Automatic Exit of Holdover

The LMK0482x device can be programmed to automatically exit holdover mode when the frequency on the

active clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and

HOLDOVER_DLD_CNT.

See Digital Lock Detect Frequency Accuracy to calculate the register values to cause holdover to automatically

exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.

The time to exit holdover may vary, because the condition for automatic holdover exit is for the reference and

feedback signals to have a time/phase error less than a programmable value. Because two clock signals may be

very close in frequency but not close in phase, it may take a long time for the phases of the clocks to align

themselves within the allowable time/phase error before holdover exits.

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9.4 Device Functional Modes

The following section describes the settings to enable various modes of operation for the LMK0482x family. See

Figure 12 and Figure 13 for visual diagrams of each mode.

The LMK0482x family is a flexible device that can be configured for many different use cases. The following

simplified block diagrams show the user the different use cases of the device.

9.4.1 Dual PLL

Figure 18 illustrates the typical use case of the LMK0482x family in dual-loop mode. In dual-loop mode, the

reference to PLL1 is from CLKin0, CLKin1, or CLKin2. An external VCXO or tunable crystal is used to provide

feedback for the first PLL, and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or

low-cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered

through the OSCout port. The VCXO or tunable crystal is used as the reference to PLL2, and may be doubled

using the frequency doubler. The internal VCO drives up to seven divide/delay blocks, which drive up to 14 clock

outputs.

Hitless switching and holdover functionality are optionally available when the input reference clock is lost.

Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal.

It is also possible to use an external VCO in place of the PLL2 internal VCO. In this case, one less CLKin is

available as a reference.

LMK04821 includes VCO1 divider on VCO1 output.

PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External VCXO

or Tunable

Crystal

OSCout*

CLKinX

CLKinX*

Up to 3

inputs

R

N

7 Device

Clocks

DCLKoutX

7 blocks

Phase

Detector

PLL1

CPout2

External

Loop Filter

R

Device Clock

Divider

Digital Delay

Analog Delay

Phase

Detector

PLL2

Partially

Integrated

Loop Filter

DCLKoutX*

Input

Buffer

N

Dual

Internal

VCOs

7 SYSREF

or Device

Clocks

SYSREF

Digital Delay

Analog Delay

SDCLKoutY

SDCLKoutY*

LMK0482x

1 Global SYSREF Divider

Figure 18. Simplified Functional Block Diagram for Dual-Loop Mode

Table 5. Dual-Loop Mode Register Configuration

REGISTER

ADDRESS

FIELD

FUNCTION

VALUE

SELECTED VALUE

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

FB_MUX

0x13F

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux

0

X

0

OSCin

PLL2_P

Disabled

0x13F

Selects the output of the feedback mux

Powers down the OSCin port

Don't care because FB_MUX is disabled

Powered up

OSCin_PD

0x140

Selects where the output of CLKin0 is

directed.

CLKin0_OUT_MUX

0x147

2

PLL1

Selects where the output of CLKin1 is

directed.

CLKin1_OUT_MUX

VCO_MUX

0x147

0x138

2

PLL1

Selects the VCO 0, 1 or an external VCO

0 or 1

VCO 0 or VCO 1

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9.4.2 Zero-Delay Dual PLL

Figure 19 illustrates the use case of cascaded zero-delay dual-loop mode. This configuration differs from dual-

loop mode Figure 18 in that the feedback for PLL2 is driven by a clock output instead of the VCO output.

Figure 20 illustrates the use case of nested zero-delay dual-loop mode. This configuration is similar to the dual

PLL in Dual PLL, except that the feedback to the first PLL is driven by a clock output. This causes the clock

outputs to have deterministic phase relationship with the clock input. Because all the clock outputs can be

synchronized together, all the clock outputs can share the same deterministic phase relationship with the clock

input signal. The feedback to PLL1 can be connected internally as shown using CLKout6, CLKout8, SYSREF, or

externally using FBCLKin (CLKin1).

It is also possible to use an external VCO in place of the PLL2 internal VCO; however, because CLKin1 must be

used as Fin for the external VCO, it is unavailable as a reference to PLL1 or as external zero-delay feedback.

LMK04821 includes VCO1 divider on VCO1 output.

PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External VCXO

or Tunable

Crystal

OSCout*

CLKinX

CLKinX*

R

N

Phase

Detector

PLL1

CPout2

External

Loop Filter

Up to 3

inputs

Divider

Digital Delay

Analog Delay

SDCLKoutY

R

Phase

Detector

PLL2

Partially

Integrated

Loop Filter

SDCLKoutY*

7 SYSREF

or Device

Clocks

Input

Buffer

N

Dual

Internal

VCOs

7 blocks

SYSREF

Analog Delay

Digital Delay

DCLKoutX

DCLKoutX*

7 Device

Clocks

Internal or external loopback, user programmable

1 Global SYSREF Divider

LMK0482x

Figure 19. Simplified Functional Block Diagram for Cascaded Zero-Delay Dual-Loop Mode

Table 6. Cascaded Zero-Delay Dual-Loop Mode Register Configuration

REGISTER

ADDRESS

FIELD

FUNCTION

VALUE

SELECTED VALUE

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

0x13F

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux.

0

1

OSCin

0x13F

Feedback mux

0x13F

Feedback mux enabled

Select between DCLKout6,

DCLKout8, SYSREF

FB_MUX

0x13F

Selects the output of the feedback mux.

0, 1, or 2

OSCin_PD

CLKin0_OUT_MUX

CLKin1_OUT_MUX

VCO_MUX

0x140

0x147

0x138

Powers down the OSCin port.

0

Powered up

PLL1

Selects where the output of CLKin0 is directed.

Selects where the output of CLKin1 is directed.

Selects the VCO 0, 1 or an external VCO

0

0 or 2

0 or 1

Fin or PLL1

VCO 0 or VCO 1

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PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External VCXO

or Tunable

Crystal

OSCout*

CLKinX

R

CLKinX*

Phase

CPout2

External

Loop Filter

Up to 3

inputs

Detector

PLL1

Divider

Digital Delay

Analog Delay

SDCLKoutY

R

Phase

Detector

PLL2

Partially

Integrated

Loop Filter

SDCLKoutY*

7 SYSREF

or Device

Clocks

N

Input

Buffer

N

Dual

Internal

VCOs

7 blocks

SYSREF

Analog Delay

Digital Delay

DCLKoutX

DCLKoutX*

7 Device

Clocks

Internal or external loopback, user programmable

1 Global SYSREF Divider

LMK0482x

Figure 20. Simplified Functional Block Diagram for Nested Zero-Delay Dual-Loop Mode

LMK04821 includes the VCO1 divider on the VCO1 output.

Table 7 illustrates nested zero-delay mode. This is the same as cascaded, except the clock out feedback is to

PLL1. The CLKin and CLKout have the same deterministic phase relationship, but the VCXO's phase is not

deterministic to the CLKin or CLKouts.

Table 7. Nested Zero-Delay Dual-Loop Mode Register Configuration

REGISTER

ADDRESS

FIELD

FUNCTION

VALUE

SELECTED VALUE

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

0x13F

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux.

1

0

1

Feedback mux

PLL2 P

0x13F

Enabled

Select between DCLKout6,

DCLKout8, SYSREF

FB_MUX

0x13F

Selects the output of the feedback mux.

0, 1, or 2

OSCin_PD

CLKin0_OUT_MUX

CLKin1_OUT_MUX

VCO_MUX

0x140

0x147

0x138

Powers down the OSCin port.

0

Powered up

PLL1

Selects where the output of CLKin0 is directed.

Selects where the output of CLKin1 is directed.

Selects the VCO 0, 1 or an external VCO

2

0 or 2

0 or 1

Fin or PLL1

VCO 0 or VCO 1

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9.4.3 Single-Loop Mode

Figure 21 illustrates the use case of PLL2 single loop mode. When used with a clean high frequency reference

on OSCin, performance can be comparable to (or even better than) dual-loop mode.

Figure 21. Simplified Functional Block Diagram for Single-Loop Mode

Table 8. Single-Loop Mode Register Configuration

REGISTER

ADDRESS

FIELD

FUNCTION

VALUE

SELECTED VALUE

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

0x13F

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux.

X

0

Don't care

PLL2 P

0x13F

Disabled

Select between DCLKout6, DCLKout8,

SYSREF

FB_MUX

0x13F

Selects the output of the feedback mux. 0, 1, or 2

OSCin_PD

PLL1_PD

0x140

Powers down the OSCin port.

Powers down PLL1.

0

1

Powered up

Powered down

Selects where the output of CLKin0 is

directed.

CLKin0_OUT_MUX

0x147

X

Don't care

Selects where the output of CLKin1 is

directed.

CLKin1_OUT_MUX

VCO_MUX

0x147

0x138

3

Off

Selects the VCO 0, 1 or an external VCO

0 or 1

VCO 0 or VCO 1

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9.4.4 Single-Loop Mode With External VCO

Adding an external VCO is possible using the CLKin1/Fin input port. The input may be single-ended or

differential. At high frequency the input impedance to Fin is low, so a resistive pad is recommended for matching.

Figure 22. Simplified Functional Block Diagram for Single-Loop Mode With External VCO

Table 9. Single-Loop Mode With External VCO Register Configuration

REGISTER

FIELD

FUNCTION

VALUE

SELECTED VALUE

ADDRESS

0x13F

0x140

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

FB_MUX

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux.

X

0

X

0

1

Don't care

PLL2_P

Disabled

Selects the output of the feedback mux.

Powers down the OSCin port.

Powers down the VCO LDO.

Powers down the VCO.

Don't care

OSCin_PD

Powered up

Powered down

VCO_LDO_PD

VCO_PD

PLL1_PD

Powers down PLL1.

Selects where the output of CLKin0 is

directed.

CLKin0_OUT_MUX

0x147

X

Don't care

Selects where the output of CLKin1 is

directed.

CLKin1_OUT_MUX

VCO_MUX

0x147

0x138

0

2

Fin

Selects the VCO 0, 1 or an external VCO

External VCO

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9.4.5 Distribution Mode

Figure 23 illustrates the use case of distribution mode. As in all other use cases, OSCin to OSCout can be used

as a buffer to OSCin or from clock distribution path via CLKout6, CLKout8, or the SYSREF divider. At high

frequency the input impedance to Fin is low, so a resistive pad is recommended for matching.

Figure 23. Simplified Functional Block Diagram for Distribution Mode

Table 10. Distribution Mode Register Configuration

REGISTER

FIELD

FUNCTION

VALUE

SELECTED VALUE

ADDRESS

0x13F

0x140

0x173

PLL1_NCLK_MUX

PLL2_NCLK_MUX

FB_MUX_EN

FB_MUX

Selects the input to the PLL1 N divider

Selects the input to the PLL2 N divider

Enables the feedback mux.

Selects the output of the feedback mux.

Powers down the OSCin port.

Powers down the VCO LDO.

Powers down the VCO.

X

0

X

1

Don't care

Disabled

Don't care

OSCin_PD

Powered down

VCO_LDO_PD

VCO_PD

PLL1_PD

Powers down PLL1.

PLL2_PRE_PD

PLL2_PD

Powers down PLL2 prescaler.

Powers down PLL2.

Selects where the output of CLKin0 is

directed.

CLKin0_OUT_MUX

0x147

X

Don't care

Selects where the output of CLKin1 is

directed.

CLKin1_OUT_MUX

VCO_MUX

0x147

0x138

0

2

Fin

Selects the VCO 0, 1 or an external VCO

External VCO

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9.5 Programming

LMK0482x family devices are programmed using 24-bit registers. Each register consists of a 1-bit command field

(R/W), a 2-bit multi-byte field (W1, W0), a 13-bit address field (A12 to A0), and an 8-bit data field (D7 to D0). The

contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS*

signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in,

the CS* signal goes high to latch the contents into the shift register. TI recommends programming registers in

numeric order – for example, 0x000 to 0x1FFF – to achieve proper device operation. Each register consists of

one or more fields which control the device functionality. See Electrical Characteristics and Figure 1 for timing

details.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 should be written as 0.

9.5.1 Recommended Programming Sequence

Registers are programmed in numeric order, with 0x000 being the first and 0x1FFF being the last register

programmed. The recommended programming sequence from POR involves:

1. Program register 0x000 with RESET = 1.

2. Program registers in numeric order from 0x000 to 0x165. Ensure the following register is programmed as

follows:

– 0x145 = 127 (0x7F)

3. Program register 0x171 to 0xAA and 0x172 to 0x02.

4. If using LMK04821, program register 0x174.

5. Program registers 0x17C and 0x17D as required by OPT_REG_1 and OPT_REG_2.

6. Program registers 0x166 to 0x1FFF.

When using LMK04821: Program register 0x174, bits 4:0 (VCO1_DIV) with the proper value before programming

the PLL2_N register in 0x166, 0x167, and 0x168 for proper total PLL2_N value.

Program register 0x171, 0x172, 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in

registers: 0x166, 0x167, and 0x168, to optimize PLL2_N and VCO1 phase-noise performance over temperature.

9.5.1.1 SPI LOCK

When writing to SPI_LOCK, registers 0x1FFD, 0x1FFE, and 0x1FFF should all always be written sequentially.

9.5.1.2 SYSREF_CLR

When using SYSREF output, SYSREF local digital delay block should be cleared using SYSREF_CLR bit. See

SYSREF_CLR for more info.

9.5.1.3 RESET Pin

If the RESET pin is not used during normal operation, TI recommends programming the RESET_TYPE register

to an output setting, to prevent noise from spontaneously resetting the device.

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9.6 Register Maps

9.6.1 Register Map for Device Programming

Table 11 provides the register map for device programming. Any register can be read from the same data

address it is written to.

Table 11. LMK0482x Register Map

ADDRESS

[11:0]

DATA

7

6

5

4

3

2

1

0

SPI_3WIRE

_DIS

0x000

0x002

RESET

0

POWER

DOWN

0

0x003

0x004

0x005

0x006

0x00C

0x00D

ID_DEVICE_TYPE

ID_PROD[15:8]

ID_PROD[7:0]

ID_MASKREV

ID_VNDR[15:8]

ID_VNDR[7:0]

CLKout0_1

_ODL

CLKout0_1

_IDL

0x100

0x101

0x103

0

DCLKout0_DIV

DCLKout0_DDLY_CNTH

DCLKout0_ADLY

SDCLKout1

DCLKout0_DDLY_CNTL

DCLKout0_

DCLKout0_MUX

ADLY_MUX

SDCLKout1_DDLY

SDCLKout1_ADLY

SDCLKout1_DIS_MODE

CLKout0_FMT

DCLKout0

_HS

SDCLKout1

_HS

0x104

0x105

0x106

0x107

0

_MUX

SDCLKout1_

ADLY_EN

0

CLKout0_1

_PD

SDCLKout1

_PD

DCLKout0

_ DDLY_PD

DCLKout0

_ HSg_PD

DCLKout0

_ ADLYg_PD

DCLKout0

_ADLY _PD

SDCLKout1

_POL

DCLKout0

_POL

CLKout1_FMT

CLKout2_3

_ODL

CLKout2_3

_IDL

0x108

0x109

0x10B

0

DCLKout2_DIV

DCLKout2_DDLY_CNTH

DCLKout2_ADLY

SDCLKout3

DCLKout2_DDLY_CNTL

DCLKout2_

DCLKout2_MUX

ADLY_MUX

SDCLKout3_DDLY

SDCLKout3_ADLY

SDCLKout3_DIS_MODE

CLKout2_FMT

DCLKout2

_HS

SDCLKout3

_HS

0x10C

0x10D

0x10E

0x10F

0

_MUX

SDCLKout3

_ ADLY_EN

0

DCLKout2

_ DDLY_PD

DCLKout2

_ HSg_PD

DCLKout2

_ ADLYg_PD

DCLKout2

_ADLY _PD

CLKout2_3

_PD

SDCLKout3

_PD

SDCLKout3

_POL

DCLKout2

_POL

CLKout3_FMT

CLKout4_5

_ODL

CLKout4_5

_IDL

0x110

0x111

0x113

0

DCLKout4_DIV

DCLKout4_DDLY_CNTH

DCLKout4_ADLY

SDCLKout5

DCLKout4_DDLY_CNTL

DCLKout4_

DCLKout4_MUX

ADLY_MUX

SDCLKout5_DDLY

SDCLKout5_ADLY

SDCLKout5_DIS_MODE

CLKout4_FMT

DCLKout4

_HS

SDCLKout5

_HS

0x114

0x115

0x116

0x117

0x118

0

_MUX

SDCLKout5

_ ADLY_EN

0

DCLKout4

_ DDLY_PD

DCLKout4

_ HSg_PD

DCLKout4

_ ADLYg_PD

DCLKout4

_ADLY _PD

CLKout4_5

_PD

SDCLKout5

_PD

SDCLKout5

_POL

DCLKout4

_POL

CLKout5_FMT

CLKout6_7

_ODL

CLKout6_8

_IDL

0

DCLKout6_DIV

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Register Maps (continued)

Table 11. LMK0482x Register Map (continued)

ADDRESS

[11:0]

DATA

7

6

5

4

3

2

1

0

0x119

DCLKout6_DDLY_CNTH

DCLKout6_ADLY

SDCLKout7

DCLKout6_DDLY_CNTL

DCLKout6_

0x11B

0x11C

0x11D

0x11E

0x11F

DCLKout6_MUX

ADLY_MUX

SDCLKout7_DDLY

SDCLKout7_ADLY

SDCLKout7_DIS_MODE

CLKout6_FMT

DCLKout6

_HS

SDCLKout7

_HS

0

_MUX

SDCLKout7

_ ADLY_EN

0

DCLKout6

_ DDLY_PD

DCLKout6

_ HSg_PD

DCLKout6

_ ADLYg_PD

DCLKout6

_ADLY _PD

CLKout6_7

_PD

SDCLKout7

_PD

SDCLKout7

_POL

CLKout7

_FMT

DCLKout6

_POL

CLKout8_9

_ODL

CLKout8_9

_IDL

0x120

0x121

0x123

0

DCLKout8_DIV

DCLKout8_DDLY_CNTH

DCLKout8_ADLY

SDCLKout9

DCLKout8_DDLY_CNTL

DCLKout8

DCLKout8_MUX

_ ADLY_MUX

SDCLKout9_DDLY

SDCLKout9_ADLY

SDCLKout9_DIS_MODE

CLKout8_FMT

DCLKout8

_HS

SDCLKout9

_HS

0x124

0x125

0x126

0x127

0

_MUX

SDCLKout9

_ ADLY_EN

0

DCLKout8

_ DDLY_PD

DCLKout8

_ HSg_PD

DCLKout8

_ ADLYg_PD

DCLKout8

_ADLY _PD

CLKout8_9

_PD

SDCLKout9

_PD

SDCLKout9

_POL

DCLKout8

_POL

CLKout9_FMT

CLKout10

_11 _ODL

CLKout10

_11_IDL

0x128

0x129

0x12B

0

DCLKout10_DIV

DCLKout10_DDLY_CNTH

DCLKout10_ADLY

SDCLKout11

DCLKout10_DDLY_CNTL

DCLKout10

DCLKout10_MUX

_ ADLY_MUX

SDCLKout11_DDLY

SDCLKout11_ADLY

SDCLKout11_DIS_MODE

CLKout10_FMT

DCLKout10

_HS

SDCLKout11

_HS

0x12C

0x12D

0x12E

0x12F

0

_MUX

SDCKLout11

_ ADLY_EN

0

DCLKout10

_ DDLY_PD

DCLKout10

_ HSg_PD

DLCLKout10

_ ADLYg_PD

DCLKout10

_ ADLY_PD

CLKout10

_11_PD

SDCLKout11

_PD

SDCLKout11

_POL

DCLKout10

_POL

CLKout11_FMT

CLKout12

_13 _ODL

CLKout12

_13_IDL

0x130

0x131

0x133

0

DCLKout12_DIV

DCLKout12_DDLY_CNTH

DCLKout12_ADLY

SDCLKout13

DCLKout12_DDLY_CNTL

DCLKout12_

DCLKout12_MUX

ADLY_MUX

SDCLKout13_DDLY

SDCLKout13_ADLY

SDCLKout13_DIS_MODE

CLKout12_FMT

OSCout_FMT

SYSREF_

DCLKout12

_HS

SDCLKout13

_HS

0x134

0x135

0x136

0x137

0x138

0x139

0

_MUX

SDCLKout13

_ ADLY_EN

0

DCLKout12

_ DDLY_PD

DCLKout12

_ HSg_PD

DCLKout12

_ ADLYg_PD

DCLKout12

_ ADLY_PD

CLKout12

_13_PD

SDCLKout13

_PD

SDCLKout13

_POL

DCLKout12

_POL

CLKout13_FMT

OSCout

_MUX

0

VCO_MUX

0

SYSREF_MUX

CLKin0_MUX

0x13A

0x13B

0x13C

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

0

SYSREF_DDLY[12:8]

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Register Maps (continued)

Table 11. LMK0482x Register Map (continued)

ADDRESS

DATA

[11:0]

0x13D

0x13E

7

6

5

4

3

2

1

0

SYSREF_DDLY[7:0]

0

SYSREF_PULSE_CNT

PLL2_NCLK

_MUX

PLL1_NCLK

_MUX

FB_MUX

_EN

0x13F

0x140

FB_MUX

SYSREF_GBL

_PD

SYSREF

_DDLY_PD

SYSREF

_PLSR_PD

PLL1_PD

VCO_LDO_PD

VCO_PD

OSCin_PD

SYSREF_PD

DDLYd_

SYSREF_EN

DDLYd12

_EN

DDLYd10

_EN

0x141

0x142

0x143

DDLYd7_EN

DDLYd6_EN

DDLYd4_EN

DDLYd2_EN

DDLYd0_EN

0

DDLYd_STEP_CNT

SYSREF_DDLY SYNC_1SHOT

SYNC_PLL2

_DLD

SYNC_PLL1

_DLD

SYNC_POL

SYNC_EN

SYNC_MODE

_CLR

_EN

SYNC

_DISSYSREF

0x144

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0x145

0x146

0

1

0

CLKin2_EN

CLKin1_EN

CLKin0_EN

CLKin2_TYPE

CLKin1_TYPE

CLKin0_TYPE

CLKin_SEL

_POL

0x147

0x148

0x149

0x14A

0x14B

CLKin_SEL_MODE

CLKin1_OUT_MUX

CLKin0_OUT_MUX

0

CLKin_SEL0_MUX

CLKin_SEL1_MUX

RESET_MUX

CLKin_SEL0_TYPE

CLKin_SEL1_TYPE

RESET_TYPE

SDIO_RDBK

_TYPE

0

HOLDOVER

_ FORCE

MAN_DAC

_EN

LOS_TIMEOUT

LOS_EN

TRACK_EN

MAN_DAC[9:8]

0x14C

0x14D

0x14E

0x14F

MAN_DAC[7:0]

0

DAC_TRIP_LOW

DAC_TRIP_HIGH

DAC_CLK_MULT

DAC_CLK_CNTR

HOLDOVER

_HITLESS

_SWITCH

CLKin

_OVERRIDE

HOLDOVER

_ PLL1_DET

HOLDOVER

_LOS _DET

HOLDOVER

_VTUNE_DET

HOLDOVER

_EN

0x150

0

0x151

0x152

0x153

0x154

0x155

0x156

0x157

0x158

0x159

0x15A

0

HOLDOVER_DLD_CNT[13:8]

HOLDOVER_DLD_CNT[7:0]

CLKin0_R[13:8]

0

CLKin0_R[7:0]

CLKin1_R[7:0]

CLKin2_R[7:0]

PLL1_N[7:0]

CLKin1_R[13:8]

CLKin2_R[13:8]

PLL1_N[13:8]

PLL1

_CP_TRI

PLL1

_CP_POL

0x15B

PLL1_WND_SIZE

PLL1_CP_GAIN

0x15C

0x15D

0x15E

0x15F

0x160

0x161

0

PLL1_DLD_CNT[13:8]

PLL1_DLD_CNT[7:0]

PLL1_R_DLY

PLL1_N_DLY

PLL1_LD_MUX

0

PLL1_LD_TYPE

0

PLL2_R[11:8]

PLL2_R[7:0]

OSCin_FREQ

PLL2

_XTAL_EN

PLL2

_REF_2X_EN

0x162

PLL2_P

0

0x163

0x164

0x165

0

PLL2_N_CAL[17:16]

PLL2_N_CAL[15:8]

PLL2_N_CAL[7:0]

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Register Maps (continued)

Table 11. LMK0482x Register Map (continued)

ADDRESS

[11:0]

DATA

7

6

5

4

3

2

1

0

1

PLL2_FCAL

_DIS

0x166

0

PLL2_N[17:16]

0x167

0x168

PLL2_N[15:8]

PLL2_N[7:0]

PLL2

_CP_POL

PLL

2_CP_TRI

0x169

0x16A

0

PLL2_WND_SIZE

PLL2_CP_GAIN

SYSREF_REQ_

EN

PLL2_DLD_CNT[15:8]

0x16B

0x16C

0x16D

0x16E

0x171

0x172

0x173

0x174

0x17C

0x17D

PLL2_DLD_CNT[7:0]

PLL2_LF_R4

0

PLL2_LF_R3

PLL2_LF_C4

PLL2_LF_C3

PLL2_LD_MUX

PLL2_LD_TYPE

1

0

1

0

1

0

1

0

PLL2_PD

0

PLL2_PRE_PD

0

VCO1_DIV

OPT_REG_1

OPT_REG_2

RB_PLL1_

LD_LOST

CLR_PLL1_

LD_LOST

0x182

0x183

0

RB_PLL1_LD

RB_PLL2_LD

RB_PLL2_

LD_LOST

CLR_PLL2_

LD_LOST

RB_CLKin2_

SEL

RB_CLKin1_

SEL

RB_CLKin0_

SEL

RB_CLKin1_

LOS

RB_CLKin0_

LOS

0x184

0x185

0x188

RB_DAC_VALUE[9:8]

X

RB_DAC_VALUE[7:0]

RB_

HOLDOVER

0

X

0x1FFD

0x1FFE

0x1FFF

SPI_LOCK[23:16]

SPI_LOCK[15:8]

SPI_LOCK[7:0]

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9.7 Device Register Descriptions

The following section details the fields of each register, the power-on reset defaults, and specific descriptions of

each bit.

In some cases, similar fields are located in multiple registers. In this case, specific outputs may be designated as

X or Y. In these cases, the X represents even numbers from 0 to 12, and the Y represents odd numbers from 1

to 13. In the case where X and Y are both used in a bit name, then Y = X + 1.

9.7.1 System Functions

9.7.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function, and a setting to disable 3-wire SPI mode.

Table 12. Register 0x000

BIT

NAME

POR

DEFAULT

DESCRIPTION

0: Normal operation

1: Reset (automatically cleared)

7

RESET

NA

0

6:5

Reserved

Disable 3-wire SPI mode. 4-wire SPI mode is enabled by selecting SPI Read back in one

of the output MUX settings. For example, CLKin0_SEL_MUX.

0: 3-wire mode enabled

4

SPI_3WIRE_DIS

NA

0

1: 3-wire mode disabled

3:0

NA

Reserved

9.7.1.2 POWERDOWN

This register contains the POWERDOWN function.

Table 13. Register 0x002

POR

DEFAULT

BIT

7:1

0

NAME

NA

DESCRIPTION

0

Reserved

0: Normal operation

1: Powerdown

POWERDOWN

0

9.7.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

Table 14. Register 0x003

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

ID_DEVICE_TYPE

6

PLL product device type

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9.7.1.4 ID_PROD[15:8], ID_PROD

These registers contain the product identifier. This is a read only register.

Table 15. ID_PROD Register Configuration, ID_PROD[15:0]

MSB

LSB

0x004[7:0]

0x005[7:0]

POR

DEFAULT

BIT REGISTERS

FIELD NAME

DESCRIPTION

7:0

0x004

0x005

ID_PROD[15:8]

ID_PROD

208

91

MSB of the product identifier

LSB of the product identifier

9.7.1.5 ID_MASKREV

This register contains the IC version identifier. This is a read only register.

Table 16. Register 0x006

POR

DEFAULT

BIT

NAME

DESCRIPTION

36

37

32

IC version identifier for LMK04821

IC version identifier for LMK04826

IC version identifier for LMK04828

7:0

ID_MASKREV

9.7.1.6 ID_VNDR[15:8], ID_VNDR

These registers contain the vendor identifier. This is a read only register.

Table 17. ID_VNDR Register Configuration, ID_VNDR[15:0]

MSB

LSB

0x00C[7:0]

0x00D[7:0]

Table 18. Registers 0x00C, 0x00D

BIT REGISTERS

NAME

POR

DEFAULT

DESCRIPTION

7:0

0x00C

0x00D

ID_VNDR[15:8]

ID_VNDR

81

MSB of the vendor identifier

LSB of the vendor identifier

4

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9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV

These registers control the input and output drive level, as well as the device clock out divider values.

Table 19. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

POR

DEFAULT

BIT

7

NAME

NA

DESCRIPTION

0

Reserved

Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers,

which can slightly improve noise floor.

6

CLKoutX_Y_ODL

0

Input drive level. Setting this bit increases the current to the clock distribution buffer

sourcing CLKoutX_Y, which can slightly improve noise floor.

5

CLKoutX_Y_IDL

DCLKoutX_DIV

DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd.

Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is

selected.

Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.

X = 0 → 2

X = 2 → 4

X = 4 → 8

X = 6 → 8

X = 8 → 8

X = 10 → 8

X = 12 → 2

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divider Value

32

4:0

(1)

1

2

...

30 (0x1E)

31 (0x1F)

30

31

(1) Not valid if DCLKoutX_MUX = 0, divider only. Not valid if DCLKoutX_MUX = 3 (analog delay + divider) and DCLKoutX_ADLY_MUX = 0

(without duty cycle correction/halfstep).

9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL

This register controls the digital delay high and low count values for the device clock outputs.

Table 20. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

POR

DEFAULT

BIT

NAME

DESCRIPTION

Number of clock cycles the output is high when digital delay is engaged.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Values

16

DCLKoutX

_DDLY_CNTH

7:4

5

Reserved

2

...

15 (0x0F)

15

Number of clock cycles the output is low when dynamic digital delay is engaged.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Values

16

DCLKoutX

_DDLY_CNTL

3:0

5

Reserved

2

...

15 (0x0F)

15

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9.7.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX

These registers control the analog delay properties for the device clocks.

Table 21. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

POR

DEFAULT

BIT

NAME

DESCRIPTION

Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0

(DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps

to 1075 ps.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Delay Value

0 ps

7:3

DCLKoutX_ALDY

0

25 ps

50 ps

...

23 (0x17)

575 ps

This register selects the input to the analog delay for the device clock. Used when

DCLKoutX_MUX = 3.

0: Divided without duty cycle correction or half step.

DCLKoutX_ADLY

_MUX

2

0

(1)

1: Divided with duty cycle correction and half step.

This selects the input to the device clock buffer.

Field Value

Mux Output

(1)

0 (0x0)

Divider only

1:0

DCLKoutX_MUX

Divider with duty cycle Correction

and half step

1 (0x1)

2 (0x2)

3 (0x3)

Bypass

Analog delay + divider

(1) DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3

and DCLKoutX_ADLY_MUX = 1.

9.7.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay,

and half step.

Table 22. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

BIT

7

NAME

NA

POR

DEFAULT

DESCRIPTION

0

Reserved

Sets the device clock half step value. Half step must be zero (0) for a divide of 1.

6

DCLKoutX_HS

0: 0 cycles

1: -0.5 cycles

Sets the input the the SDCLKoutX outputs.

0: Device clock output

1: SYSREF output

5

4:1

0

SDCLKoutY_MUX

SDCLKoutY_DDLY

SDCLKoutY_HS

0

Sets the number of VCO cycles to delay the SDCLKout by.

Field Value

0 (0x00)

Delay Cycles

Bypass

1 (0x01)

2

2 (0x02)

3

...

10 (0x0A)

11

11 to 15 (0x0B to 0x0F)

Reserved

Sets the SYSREF clock half-step value.

0: 0 cycles

1: -0.5 cycles

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9.7.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

Table 23. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

BIT

7:5

4

NAME

POR

DEFAULT

DESCRIPTION

NA

0

Reserved

Enables analog delay for the SYSREF output.

SDCLKoutY

_ADLY_EN

0

0: Disabled

1: Enabled

Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step

(600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed

700-ps delay. Effective range is 700 ps to 2950 ps.

Field Value

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

...

Delay Value

0 ps

SDCLKoutY

_ADLY

600 ps

3:0

0

750 ps (+150 ps from 0x1)

900 ps (+150 ps from 0x2)

...

14 (0xE)

15 (0xF)

2100 ps (+150 ps from 0xD)

2250 ps (+150 ps from 0xE)

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9.7.2.6 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD,

DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD

This register controls the power-down functions for the digital delay, glitchless half step, glitchless analog delay,

analog delay, outputs, and SYSREF disable modes.

Table 24. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT

NAME

POR DEFAULT

DESCRIPTION

Powerdown the device clock digital delay circuitry.

0: Enabled

1: Powerdown

DCLKoutX

_DDLY_PD

7

0

Powerdown the device clock glitchless half-step feature.

0: Enabled

1: Powerdown

DCLKoutX

_HSg_PD

6

5

4

1

Powerdown the device clock glitchless analog delay feature.

0: Enabled, analog delay step size of one code is glitchless between values 1 to 23.

1: Powerdown

DCLKoutX

_ADLYg_PD

Powerdown the device clock analog delay feature.

0: Enabled

1: Powerdown

DCLKoutX

_ADLY_PD

X_Y = 0_1 → 1

X_Y = 2_3 → 1

X_Y = 4_5 → 0

X_Y = 6_7 → 0

X_Y = 8_9 → 0

X_Y = 10_11 → 0

X_Y = 12_13 → 1

Powerdown the clock group defined by X and Y.

0: Enabled

1: Powerdown

3

CLKoutX_Y_PD

Configures the output state of the SYSREF

Field Value

0 (0x00)

Disable Mode

Active in normal operation

1 (0x01)

If SYSREF_GBL_PD = 1, the output is a

logic low, otherwise it is active.

SDCLKoutY

_DIS_MODE

2:1

0

1

2 (0x02)

3 (0x03)

If SYSREF_GBL_PD = 1, the output is a

nominal Vcm voltage⁽¹⁾, otherwise it is

active.

Output is a nominal Vcm voltage⁽¹⁾

0

SDCLKoutY_PD

Powerdown SDCLKoutY and set to the state defined by SDCLKoutY_DIS_MODE

(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V.

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9.7.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT

These registers configure the output polarity, and format.

Table 25. Registers 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137

BIT

POR

DEFAULT

NAME

DESCRIPTION

Sets the polarity of clock on SDCLKoutY when device clock output is selected with

SDCLKoutY_MUX.

0: Normal

7

SDCLKoutY_POL

0

1: Inverted

Sets the output format of the SYSREF clocks

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Output Format

Powerdown

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

6:4

SDCLKoutY_FMT

DCLKoutX_POL

DCLKoutX_FMT

0

Sets the polarity of the device clocks from the DCLKoutX outputs

3

0

0: Normal

1: Inverted

Sets the output format of the device clocks.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Output Format

LMK04821: 0

LMK04826/

LMK04828:

X = 0 → 0

X = 2 → 0

X = 4 → 1

X = 6 → 1

X = 8 → 1

X = 10 → 1

X = 12 → 0

Powerdown

LVDS

HSDS 6 mA

HSDS 8 mA

HSDS 10 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

2:0

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9.7.3 SYSREF, SYNC, and Device Config

9.7.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT

This register selects the clock distribution source, and OSCout parameters.

Table 26. Register 0x138

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

Selects clock distribution path source from VCO0, VCO1, or CLKin (external VCO)

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

VCO Selected

VCO 0

6:5

VCO_MUX

0

VCO 1

CLKin1 (external VCO)

Reserved

Select the source for OSCout:

0: Buffered OSCin

4

OSCout_MUX

1: Feedback mux

Selects the output format of OSCout. When powered down, these pins may be used as

CLKin2.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

OSCout Format

Powerdown (CLKin2)

LVDS

Reserved

LVPECL 1600 mVpp⁽¹⁾

LVPECL 2000 mVpp⁽¹⁾

LVCMOS (Norm / Inv)

LVCMOS (Inv / Norm)

LVCMOS (Norm / Norm)

LVCMOS (Inv / Inv)

LVCMOS (Off / Norm)

LVCMOS (Off / Inv)

LVCMOS (Norm / Off)

LVCMOS (Inv / Off)

LVCMOS (Off / Off)

3:0

OSCout_FMT

4

(1) When set to an LVPECL drive format, OSCout emitter resistors must be 240 Ω to GND.

68

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9.7.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX

This register sets the source for the SYSREF outputs. Refer to Figure 13 and SYNC/SYSREF.

Table 27. Register 0x139

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:3

NA

0

Reserved

Selects the SYSREF output from SYSREF_MUX or CLKin0 direct

Field Value

SYSREF Source

SYSREF_

CLKin0_MUX

2

0

SYSREF Mux

1

Selects the SYSREF source.

Field Value

CLKin0 direct (from CLKin0_OUT_MUX)

SYSREF Source

Normal SYNC

0 (0x00)

1:0

SYSREF_MUX

1 (0x01)

Re-clocked

2 (0x02)

SYSREF pulser

SYSREF continuous

3 (0x03)

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9.7.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]

These registers set the value of the SYSREF output divider.

Table 28. Registers 0x13A, 0x13B

MSB

LSB

0x13A[4:0]

0x13B[7:0]

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:5

0x13A

NA

0

Reserved

Divide value for the SYSREF outputs.

Field Value

0x00 to 0x07

8 (0x08)

Divide Value

4:0

0x13A

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

12

Reserved

8

9

9 (0x09)

...

7:0

0x13B

0

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

9.7.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]

These registers set the delay of the SYSREF digital delay value.

Table 29. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0]

MSB

LSB

0x13C[4:0]

0x13D[7:0]

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:5

0x13C

NA

0

Reserved

Sets the value of the SYSREF digital delay.

Field Value

0x00 to 0x07

8 (0x08)

Delay Value

4:0

0x13C

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

0

Reserved

8

9

9 (0x09)

...

7:0

0x13D

8

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

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9.7.3.5 SYSREF_PULSE_CNT

This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See

SYSREF_CLKin0_MUX, SYSREF_MUX for further description of SYSREF's outputs.

Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by

SYSREF_MUX and SYSREF functionality is powered up.

Table 30. Register 0x13E

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:2

NA

0

Reserved

Sets the number of SYSREF pulses generated when not in continuous mode.

See SYSREF_CLKin0_MUX, SYSREF_MUX for more information on SYSREF modes.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Number of Pulses

1 pulse

1:0

SYSREF_PULSE_CNT

3

2 pulses

4 pulses

8 pulses

9.7.3.6 PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN

This register controls the feedback feature.

Table 31. Register 0x13F

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:5

NA

0

Reserved

Selects the input to the PLL2 N divider

0: PLL prescaler

1: Feedback mux

4

3

PLL2_NCLK_MUX

PLL1_NCLK_MUX

0

Selects the input to the PLL1 N delay

0: OSCin

1: Feedback mux

When in zero-delay mode, the feedback mux selects the clock output to be fed back into

the PLL1 N divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Source

DCLKout6

2:1

FB_MUX

0

DCLKout8

SYSREF Divider

External

When using zero-delay, FB_MUX_EN must be set to 1 to power up the feedback mux.

0: Feedback mux powered down

0

FB_MUX_EN

1: Feedback mux enabled

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9.7.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD,

SYSREF_DDLY_PD, SYSREF_PLSR_PD

This register contains powerdown controls for OSCin and SYSREF functions.

Table 32. Register 0x140

POR

DEFAULT

BIT

NAME

DESCRIPTION

Powerdown PLL1

0: Normal operation

1: Powerdown

7

PLL1_PD

0

Powerdown VCO_LDO

0: Normal operation

1: Powerdown

6

5

4

VCO_LDO_PD

VCO_PD

0

Powerdown VCO

0: Normal operation

1: Powerdown

Powerdown the OSCin port.

0: Normal operation

1: Powerdown

OSCin_PD

Powerdown individual SYSREF outputs depending on the setting of

SDCLKoutY_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many

SYSREF outputs to be controlled through a single bit.

0: Normal operation

3

2

SYSREF_GBL_PD

SYSREF_PD

0

1

1: Activate powerdown mode

Powerdown the SYSREF circuitry and divider. If powered down, SYSREF output mode

cannot be used. SYNC cannot be provided either.

0: SYSREF can be used as programmed by individual SYSREF output registers.

1: Powerdown

Powerdown the SYSREF digital delay circuitry.

0: Normal operation, SYSREF digital delay may be used. Must be powered up during

SYNC for deterministic phase relationship with other clocks.

1: Powerdown

1

0

SYSREF_DDLY_PD

SYSREF_PLSR_PD

1

Powerdown the SYSREF pulse generator.

0: Normal operation

1: Powerdown

9.7.3.8 DDLYdSYSREF_EN, DDLYdX_EN

This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is

programmed.

Table 33. Register 0x141

BIT

7

NAME

DDLYd _SYSREF_EN

DDLYd12_EN

DDLYd10_EN

DDLYd8_EN

POR DEFAULT

DESCRIPTION

Enables dynamic digital delay on SYSREF outputs

Enables dynamic digital delay on DCLKout12

Enables dynamic digital delay on DCLKout10

Enables dynamic digital delay on DCLKout8

Enables dynamic digital delay on DCLKout6

Enables dynamic digital delay on DCLKout4

Enables dynamic digital delay on DCLKout2

Enables dynamic digital delay on DCLKout0

0

6

5

4

0: Disabled

1: Enabled

3

DDLYd6_EN

2

DDLYd4_EN

1

DDLYd2_EN

0

DDLYd0_EN

72

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9.7.3.9 DDLYd_STEP_CNT

This register sets the number of dynamic digital delay adjustments occur. Upon programming, the dynamic digital

delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic digital delay can only

be started by SPI.

Other registers must be set: SYNC_MODE = 3

Table 34. Register 0x142

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:4

NA

0

Reserved

Sets the number of dynamic digital delay adjustments that occur.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

SYNC Generation

No adjust

1 step

3:0

DDLYd_STEP_CNT

0

2 steps

3 steps

...

14 (0x0E)

15 (0x0F)

14 steps

15 steps

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9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD,

SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to Figure 13 for block

diagram. Refer to Table 1 for using SYNC_MODE for specific SYNC use cases.

Table 35. Register 0x143

POR

DEFAULT

BIT

NAME

DESCRIPTION

Resets and arms the SDCLKoutY_DDLY path, allowing local digital delays to take effect

after a SYNC event. Except during the SYSREF setup procedure (see SYNC/SYSREF), this

bit should always be programmed to 0. While this bit is set, extra current is used. Refer to

Table 87.

7

SYSREF_CLR

1

SYNC one shot enables edge-sensitive SYNC.

0: SYNC is level sensitive and outputs are held in SYNC while SYNC is asserted.

1: SYNC is edge sensitive, outputs are SYNCed on rising edge of SYNC. This results in the

clock being held in SYNC for a minimum amount of time.

6

SYNC_1SHOT_EN

0

Sets the polarity of the SYNC pin.

0: Normal

1: Inverted

5

4

SYNC_POL

SYNC_EN

0

1

Enables the SYNC functionality.

0: Disabled

1: Enabled

0: Off

3

2

SYNC_PLL2_DLD

SYNC_PLL1_DLD

0

1: Assert SYNC until PLL2 DLD = 1

0: Off

1: Assert SYNC until PLL1 DLD = 1

Sets the method of generating a SYNC event.

Field Value

SYNC Generation

Prevents SYNC pin, SYNC_PLL1_DLD flag, or

SYNC_PLL2_DLD flag from generating a SYNC event.

0 (0x00)

SYNC event generated from SYNC pin or, if enabled, the

SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag.

1 (0x01)

2 (0x02)

1:0

SYNC_MODE

1

For use with pulser – SYNC/SYSREF pulses are generated by

pulser block through the SYNC pin or, if enabled, the

SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag.

For use with pulser – SYNC/SYSREF pulses are generated by

pulser block when programming register 0x13E

3 (0x03)

(SYSREF_PULSE_CNT) is written to (see SYSREF Pulser).

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9.7.3.11 SYNC_DISSYSREF, SYNC_DISX

SYNC_DISX prevents a clock output from being synchronized or interrupted by a SYNC event, or when

outputting SYSREF.

Table 36. Register 0x144

POR

DEFAULT

BIT

NAME

DESCRIPTION

Prevents the SYSREF clocks from becoming synchronized during a SYNC event. If

SYNC_DISSYSREF is enabled, it continues to operate normally during a SYNC event.

7

SYNC_DISSYSREF

0

6

5

4

3

2

1

0

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0

Prevents the device clock output from becoming synchronized during a SYNC event or

SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to

operate normally during a SYNC event or SYSREF clock.

9.7.3.12 Fixed Registers (0x145, 0x171 - 0x172)

Always program this register to value 127.

Table 37. Register 0x145

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

Fixed Register

0

Always program to 127

Always program this register to value 170.

Table 38. Register 0x171

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

Fixed Register

10 (0x0A)

Always program to 170 (0xAA)

Always program this register to value 2.

Table 39. Register 0x172

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:0

Fixed Register

0

Always program to 2 (0x02)

9.7.4 (0x146 - 0x149) CLKin Control

9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE

This register has CLKin enable and type controls.

Table 40. Register 0x146

BIT

7:6

5

POR

DEFAULT

NAME

DESCRIPTION

NA

0

Reserved

Enable CLKin2 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

CLKin2_EN

CLKin1_EN

0

1: Enabled for auto mode

Enable CLKin1 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

4

1

1: Enabled for auto mode

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Table 40. Register 0x146 (continued)

BIT

POR

DEFAULT

NAME

DESCRIPTION

Enable CLKin0 to be used during auto-switching of CLKin_SEL_MODE.

0: Not enabled for auto mode

3

CLKin0_EN

1

1: Enabled for auto mode

2

1

CLKin2_TYPE

CLKin1_TYPE

0

There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS.

Bipolar is recommended for differential inputs such as LVDS or

LVPECL. CMOS is recommended for DC-coupled single-ended

inputs.

0: Bipolar

1: MOS

When using bipolar, CLKinX and CLKinX* must be AC coupled.

When using CMOS, CLKinX and CLKinX* may be AC or DC coupled

if the input signal is differential. If the input signal is single-ended, the

used input may be either AC or DC coupled, and the unused input

must AC grounded (see Driving CLKin and OSCin Pins With a Single-

Ended Source).

0

CLKin0_TYPE

0

9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX

Table 41. Register 0x147

POR

DEFAULT

BIT

NAME

DESCRIPTION

Inverts the CLKin polarity for use in pin select mode.

7

CLKin_SEL_POL

0

0: Active high

1: Active low

Sets the mode used in determining the reference for PLL1.

Field Value

CLKin Mode

CLKin0 manual

CLKin1 manual

CLKin2 manual

Pin select mode

Auto mode

0 (0x00)

1 (0x01)

2 (0x02)

6:4

CLKin_SEL_MODE

3

3 (0x03)

4 (0x04)

5 (0x05)

Reserved

6 (0x06)

Reserved

7 (0x07)

Reserved

Selects where the output of the CLKin1 buffer is directed.

Field Value

CLKin1 Destination

0 (0x00)

Fin

3:2

1:0

CLKin1_OUT_MUX

CLKin0_OUT_MUX

2

1 (0x01)

2 (0x02)

3 (0x03)

Feedback mux (zero-delay mode)

PLL1

Off

Selects where the output of the CLKin0 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin0 Destination

SYSREF mux

Reserved

PLL1

Off

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9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE

This register has CLKin_SEL0 controls.

Table 42. Register 0x148

BIT

NAME

POR

DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

This set the output value of the CLKin_SEL0 pin. This register only applies if

CLKin_SEL0_TYPE is set to an output mode

Field Value

Output Format

Logic low

0 (0x00)

1 (0x01)

CLKin0 LOS

CLKin0 selected

DAC locked

DAC low

2 (0x02)

5:3

CLKin_SEL0_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC high

6 (0x06)

SPI readback

Reserved

7 (0x07)

This sets the I/O type of the CLKin_SEL0 pin.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Configuration

Input

Function

Input mode, see Input

Clock Switching - Pin

Select Mode for

Input with pull-up resistor

Input with pull-down resistor

Output (push-pull)

2:0

CLKin_SEL0_TYPE

2

description of input mode.

Output modes; the

CLKin_SEL0_MUX

register for description of

outputs.

Output inverted (push-pull)

Reserved

Output (open drain)

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9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE

This register has CLKin_SEL1 controls and register readback SDIO pin type.

Table 43. Register 0x149

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

Sets the SDIO pin to open drain when during SPI readback in 3-wire mode.

6

SDIO_RDBK_TYPE

1

0: Output, push-pull

1: Output, open drain.

This set the output value of the CLKin_SEL1 pin. This register only applies if

CLKin_SEL1_TYPE is set to an output mode.

Field Value

Output Format

Logic low

0 (0x00)

1 (0x01)

CLKin1 LOS

CLKin1 selected

DAC locked

DAC low

2 (0x02)

5:3

CLKin_SEL1_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC high

6 (0x06)

SPI readback

Reserved

7 (0x07)

This sets the I/O type of the CLKin_SEL1 pin.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Configuration

Input

Function

Input mode, see Input Clock

Switching - Pin Select Mode for

description of input mode.

Input with pull-up resistor

Input with pull-down resistor

Output (push-pull)

Output inverted (push-pull)

Reserved

2:0

CLKin_SEL1_TYPE

2

Output modes; see the

CLKin_SEL1_MUX register for

description of outputs.

Output (open drain)

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9.7.5 RESET_MUX, RESET_TYPE

This register contains control of the RESET pin.

Table 44. Register 0x14A

POR

DEFAUL

T

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an

output mode.

Field Value

Output Format

Logic low

0 (0x00)

1 (0x01)

Reserved

5:3

RESET_MUX

0

2 (0x02)

CLKin2 selected

DAC locked

DAC low

3 (0x03)

4 (0x04)

5 (0x05)

DAC high

6 (0x06)

This sets the I/O type of the RESET pin.

Field Value

SPI readback

Configuration

Function

0 (0x00)

Input

Reset mode

Reset pin high = reset

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Input with pull-up resistor

Input with pull-down resistor

Output (push-pull)

2:0 RESET_TYPE

2

Output modes; see the

RESET_MUX register for

description of outputs.

Output inverted (push-pull)

Reserved

Output (open drain)

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9.7.6 (0x14B - 0x152) Holdover

9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]

This register contains the holdover functions.

Table 45. Register 0x14B

POR

DEFAULT

BIT

NAME

DESCRIPTION

This controls the amount of time in which no activity on a CLKin forces a clock switch

event.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Timeout

370 kHz (2.7 µs)

2.1 MHz (480 ns)

8.8 MHz (115 ns)

22 MHz (45 ns)

7:6

LOS_TIMEOUT

0

Enables the LOS (loss-of-signal) timeout control. Valid only for MOS clock inputs. To

ensure LOS is valid for AC-coupled inputs, no termination is allowed between CLKinX and

CLKinX* pins unless DC-blocked. For example, 100-Ω termination across CLKin0 and

CLKin0* pins on the IC side of AC coupling capacitors would invalidate the LOS detector. If

termination is required, it should be placed on the other side of the AC coupling capacitors,

away from the IC pins.

5

LOS_EN

0

0: Disabled

1: Enabled

Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After

device reset, tracking starts at DAC code = 512 (midrange).

Tracking can be used to monitor PLL1 voltage in any mode.

0: Disabled

4

3

TRACK_EN

1

0

1: Enabled, only tracks when PLL1 is locked.

This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then

the DAC sets the programmed MAN_DAC value. Otherwise the tracked DAC value sets the

DAC voltage.

0: Disabled

1: Enabled

HOLDOVER

_FORCE

This bit enables the manual DAC mode.

2

MAN_DAC_EN

MAN_DAC[9:8]

1

2

0: Automatic

1: Manual

1:0

See MAN_DAC[9:8], MAN_DAC[7:0] for more information on the MAN_DAC settings.

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9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]

These registers set the value of the DAC in holdover mode when used manually.

Table 46. MAN_DAC[9:0]

MSB

LSB

0x14B[1:0]

0x14C[7:0]

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

See LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE,

MAN_DAC_EN, MAN_DAC[9:8] for information on these bits.

7:2

0x14B

Sets the value of the manual DAC when in manual DAC mode.

Field Value

0 (0x00)

DAC Value

1:0

0x14B

MAN_DAC[9:8]

MAN_DAC[7:0]

2

0

1

1 (0x01)

2 (0x02)

2

...

7:0

0x14C

1022 (0x3FE)

1023 (0x3FF)

1022

1023

9.7.6.3 DAC_TRIP_LOW

This register contains the high value at which holdover mode is entered.

Table 47. Register 0x14D

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_LOW

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

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9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter, and the low value at which holdover mode is

entered.

Table 48. Register 0x14E

POR

DEFAULT

BIT

NAME

DESCRIPTION

This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is

tracked.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

DAC Multiplier Value

4

7:6

DAC_CLK_MULT

0

64

1024

16384

Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_HIGH

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

9.7.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

Table 49. Register 0x14F

POR

DEFAULT

BIT

NAME

DESCRIPTION

This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate (in

seconds) is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF (Hz)

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Value

0

1

2

7:0

DAC_CLK_CNTR

127

3

...

253 (0xFD)

254 (0xFE)

255 (0xFF)

253

254

255

82

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9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET,

HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN

This register has controls for enabling clock in switch events.

Table 50. Register 0x150

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1

forces that clock input. Used with clock distribution mode for best performance.

0: Normal, no override.

CLKin

_OVERRIDE

6

0

1: Force select of only CLKin0/1/2, as specified by CLKin_SEL_MODE in manual mode.

5

4

NA

0

Reserved

This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low.

0: PLL1 DLD does not cause a clock switch event

1: PLL1 DLD causes a clock switch event

HOLDOVER

_PLL1_DET

This enables HOLDOVER when PLL1 LOS signal is detected.

0: Disabled

1: Enabled

HOLDOVER

_LOS_DET

3

2

0

Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this

bit is enabled, the current clock input is considered invalid and an input clock switch event

is generated.

0: Disabled

1: Enabled

HOLDOVER

_VTUNE_DET

HOLDOVER

_HITLESS

_SWITCH

Determines whether a clock switch event will enter holdover use hitless switching.

0: Hard Switch

1: Hitless switching (has an undefined switch time)

1

0

1

Sets whether holdover mode can be entered when holdover conditions are met.

0: Disabled

1: Enabled

HOLDOVER_EN

9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]

Table 51. HOLDOVER_DLD_CNT[13:0]

MSB

LSB

0x151[5:0]

0x152[7:0]

This register has the number of valid clocks of PLL1 PDF before holdover is exited.

Table 52. Registers 0x151 and 0x152

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

0x151

NA

0

Reserved

The number of valid clocks of PLL1 PDF before holdover mode is exited.

Field Value

0 (0x00)

Count Value

HOLDOVER

_DLD_CNT[13:8]

5:0

0x151

2

0

1

1 (0x01)

2 (0x02)

2

...

HOLDOVER

_DLD_CNT[7:0]

7:0

0x152

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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9.7.7 (0x153 - 0x15F) PLL1 Configuration

9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]

Table 53. CLKin0_R[13:0]

MSB

LSB

0x153[5:0]

0x154[7:0]

These registers contain the value of the CLKin0 divider.

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

0x153

NA

0

Reserved

The value of PLL1 R divider when CLKin0 is selected.

Field Value

0 (0x00)

Divide Value

5:0

0x153

CLKin0_R[13:8]

CLKin0_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x154

120

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]

Table 54. CLKin1_R[13:0]

MSB

LSB

0x155[5:0]

0x156[7:0]

These registers contain the value of the CLKin1 R divider.

Table 55. Registers 0x155 and 0x156

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

5:0

0x155

NA

0

Reserved

The value of PLL1 R divider when CLKin1 is selected.

Field Value

0 (0x00)

Divide Value

CLKin1_R[13:8]

CLKin1_R[7:0]

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x156

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

84

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9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]

MSB

LSB

0x157[5:0]

0x158[7:0]

These registers contain the value of the CLKin2 R divider.

Table 56. Registers 0x157 and 0x158

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

0x157

NA

0

Reserved

The value of PLL1 R divider when CLKin2 is selected.

Field Value

0 (0x00)

Divide Value

5:0

0x157

CLKin2_R[13:8]

CLKin2_R[7:0]

Reserved

1 (0x01)

1

2

2 (0x02)

...

7:0

0x158

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

9.7.7.4 PLL1_N

Table 57. PLL1_N[13:8], PLL1_N[7:0]

PLL1_N[13:0]

MSB

LSB

0x159[5:0]

0x15A[7:0]

These registers contain the N divider value for PLL1.

Table 58. Registers 0x159 and 0x15A

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:6

5:0

0x159

NA

0

Reserved

The value of PLL1 N divider.

Field Value

0 (0x00)

Divide Value

PLL1_N[13:8]

PLL1_N[7:0]

Not valid

1 (0x01)

1

2

2 (0x02)

7:0

0x15A

120

...

16,383 (0x3FFF)

16,383

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9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN

This register controls the PLL1 phase detector.

Table 59. Register 0x15B

POR

DEFAULT

BIT

NAME

DESCRIPTION

PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase

error between the reference and feedback of PLL1 is less than specified time, the PLL1

lock counter increments.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

4 ns

7:6

PLL1_WND_SIZE

3

9 ns

19 ns

43 ns

This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE.

0: PLL1 CPout1 is active

1: PLL1 CPout1 is at TRI-STATE

5

4

PLL1_CP_TRI

PLL1_CP_POL

0

1

PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope.

A positive-slope VCXO increases output frequency with increasing voltage. A negative-

slope VCXO decreases output frequency with increasing voltage.

0: Negative-slope VCO/VCXO

1: Positive-slope VCO/VCXO

This bit programs the PLL1 charge pump output current level.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

...

Gain

50 µA

150 µA

250 µA

350 µA

450 µA

...

3:0

PLL1_CP_GAIN

4

14 (0x0E)

15 (0x0F)

1450 µA

1550 µA

86

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9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]

Table 60. PLL1_DLD_CNT[13:0]

MSB

LSB

0x15C[5:0]

0x15D[7:0]

This register contains the value of the PLL1 DLD counter.

Table 61. Registers 0x15C and 0x15D

BIT REGISTERS

NAME

POR DEFAULT

DESCRIPTION

7:6

0x15C

NA

0

Reserved

The reference and feedback of PLL1 must be within the window of phase

error, as specified by PLL1_WND_SIZE for this many phase detector

cycles, before PLL1 digital lock detect is asserted.

PLL1_DLD

_CNT[13:8]

5:0

0x15C

32

Field Value

0 (0x00)

Delay Value

Reserved

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL1_DLD

_CNT[7:0]

7:0

0x15D

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

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9.7.7.7 PLL1_R_DLY, PLL1_N_DLY

This register contains the delay value for PLL1 N and R delays.

Table 62. Register 0x15E

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Increasing delay of PLL1_R_DLY causes the outputs to lag from CLKinX. For use in zero-

delay mode.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Gain

0 ps

205 ps

410 ps

615 ps

820 ps

1025 ps

1230 ps

1435 ps

5:3

PLL1_R_DLY

0

Increasing delay of PLL1_N_DLY causes the outputs to lead from CLKinX. For use in zero-

delay mode.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Gain

0 ps

205 ps

410 ps

615 ps

820 ps

1025 ps

1230 ps

1435 ps

2:0

PLL1_N_DLY

0

88

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9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE

This register configures the PLL1 LD pin.

Table 63. Register 0x15F

POR

DEFAULT

BIT

NAME

DESCRIPTION

This sets the output value of the Status_LD1 pin.

Field Value

0 (0x00)

MUX Value

Logic low

1 (0x01)

PLL1 DLD

PLL2 DLD

PLL1 and PLL2 DLD

Holdover status

DAC locked

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI readback

DAC rail

7:3

PLL1_LD_MUX

1

8 (0x08)

9 (0x09)

DAC low

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

DAC high

PLL1_N

PLL1_N/2

PLL2_N

PLL2_N/2

PLL1_R

16 (0x10)

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the I/O type of the Status_LD1 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL1_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

Output inverted (push-pull)

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

Output (open drain)

(1) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 and PLL2 DLD).

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9.7.8 (0x160 - 0x16E) PLL2 Configuration

9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]

Table 64. PLL2_R[11:0]

MSB

LSB

0x160[3:0]

0x161[7:0]

This register contains the value of the PLL2 R divider.

Table 65. Registers 0x160 and 0x161

BIT REGISTERS

NAME

POR DEFAULT

DESCRIPTION

7:4

0x160

NA

0

Reserved

Valid values for the PLL2 R divider.

Field Value

0 (0x00)

Divide Value

3:0

0x160

PLL2_R[11:8]

PLL2_R[7:0]

0

2

Not valid

1 (0x01)

1

2

2 (0x02)

3 (0x03)

3

7:0

0x161

...

4,094 (0xFFE)

4,095 (0xFFF)

4,094

4,095

90

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9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN

This register sets other PLL2 functions.

Table 66. Register 0x162

POR

DEFAULT

BIT

NAME

DESCRIPTION

The PLL2 N prescaler divides the output of the VCO as selected by Mode_MUX1 and is

connected to the PLL2 N divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Value

8

2

3

4

5

6

7

7:5

PLL2_P

2

The frequency of the PLL2 reference input to the PLL2 phase detector (OSCin/OSCin* port)

must be programmed to support proper operation of the frequency calibration routine,

which locks the internal VCO to the target frequency.

Field Value

0 (0x00)

OSCin Frequency

0 to 63 MHz

4:2

OSCin_FREQ

7

1 (0x01)

>63 MHz to 127 MHz

>127 MHz to 255 MHz

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

>255 MHz to 500 MHz

Reserved

5 (0x05) to 7(0x07)

If an external crystal is being used to implement a discrete VCXO, the internal feedback

amplifier must be enabled with this bit to complete the oscillator circuit.

0: Oscillator amplifier disabled

1

0

PLL2_XTAL_EN

0

1

1: Oscillator amplifier enabled

Enabling the PLL2 reference frequency doubler allows for higher phase-detector

frequencies on PLL2 than would normally be allowed with the given VCXO or crystal

frequency.

PLL2_REF_2X_EN

Higher phase-detector frequencies reduce the PLL N values, which makes the design of

wider-loop bandwidth filters possible.

0: Doubler disabled

1: Doubler enabled

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9.7.8.3 PLL2_N_CAL

PLL2_N_CAL[17:0]

PLL2 never uses zero-delay during frequency calibration. These registers contain the value of the PLL2 N divider

used with the PLL2 prescaler during calibration for cascaded zero-delay mode. When calibration is complete,

PLL2 uses the PLL2_N value. Cascaded zero-delay mode occurs when PLL2_NCLK_MUX = 1.

Table 67. Register 0x162

MSB

—

LSB

0x163[1:0]

0x164[7:0]

0x165[7:0]

Table 68. Registers 0x163, 0x164, and 0x165

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:2

1:0

0x163

NA

0

Reserved

Field Value

0 (0x00)

Divide Value

PLL2_N

_CAL[17:16]

0

Not valid

1 (0x01)

1

7:0

0x164

0x165

PLL2_N_CAL[15:8]

2 (0x02)

2

...

PLL2_N_CAL[7:0]

12

262,143 (0x3FFFF)

262,143

9.7.8.4 PLL2_FCAL_DIS, PLL2_N

This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168

starts a VCO calibration routine if PLL2_FCAL_DIS = 0.

Table 69. PLL2_N[17:0]

MSB

—

LSB

0x166[1:0]

0x167[7:0]

0x168[7:0]

Table 70. Registers 0x166, 0x167, and 0x168

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7:3

2

0x166

NA

0

Reserved

This disables the PLL2 frequency calibration on programming register 0x168.

0: Frequency calibration enabled

PLL2_FCAL_DIS

0

1: Frequency calibration disabled

Field Value

0 (0x00)

Divide Value

1:0

7:0

0x166

0x167

0x168

PLL2_N[17:16]

PLL2_N[15:8]

PLL2_N[7:0]

0

Not valid

1 (0x01)

1

2 (0x02)

2

...

12

262,143 (0x3FFFF)

262,143

92

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9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

Table 71. Register 0x169

POR

DEFAULT

BIT

NAME

DESCRIPTION

7

NA

0

Reserved

PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase

error between the reference and feedback of PLL2 is less than the specified time, then the

PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns).

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Reserved

3.7 ns

6:5

PLL2_WND_SIZE

2

Reserved

This bit programs the PLL2 charge pump output current level. The table below also

illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

100 µA

4:3

PLL2_CP_GAIN

3

400 µA

1600 µA

3200 µA

PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the

negative charge pump polarity to be selected. Many VCOs use positive slope.

A positive-slope VCO increases output frequency with increasing voltage. A negative-slope

VCO decreases output frequency with increasing voltage.

2

PLL2_CP_POL

0

Field Value

Description

0

1

Negative-slope VCO/VCXO

Positive-slope VCO/VCXO

PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.

1

0

PLL2_CP_TRI

Fixed Value

0

1

0: Disabled

1: TRI-STATE

When programming register 0x169, this field must be set to 1.

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9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT

Table 72. PLL2_DLD_CNT[15:0]

MSB

LSB

0x16A[5:0]

0x16B[7:0]

This register has the value of the PLL2 DLD counter.

Table 73. Registers 0x16A and 0x16B

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

7

6

0x16A

NA

0

Reserved

Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for

continuous pulses. When using this feature, enable the pulser and set

SYSREF_MUX = 2 (pulser).

SYSREF_REQ_EN

0

The reference and feedback of PLL2 must be within the window of phase error,

as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles, before PLL2

digital lock detect is asserted.

PLL2_DLD

_CNT[13:8]

5:0

7:0

0x16A

0x16B

32

Field Value

0 (0x00)

Divide Value

Not valid

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL2_DLD_CNT

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

94

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9.7.8.7 PLL2_LF_R4, PLL2_LF_R3

This register controls the integrated loop filter resistors.

Table 74. Register 0x16C

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:6

NA

0

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop

filters without requiring external components.

Internal loop filter resistor R4 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Resistance

200 Ω

1 kΩ

5:3

PLL2_LF_R4

0

2 kΩ

4 kΩ

16 kΩ

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop

filters without requiring external components.

Internal loop filter resistor R3 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Resistance

200 Ω

1 kΩ

2:0

PLL2_LF_R3

0

2 kΩ

4 kΩ

16 kΩ

Reserved

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9.7.8.8 PLL2_LF_C4, PLL2_LF_C3

This register controls the integrated loop filter capacitors.

Table 75. Register 0x16D

POR

DEFAULT

BIT

NAME

DESCRIPTION

Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop

filters without requiring external components.

Internal loop filter capacitor C4 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Capacitance

10 pF

15 pF

29 pF

34 pF

47 pF

52 pF

7:4

PLL2_LF_C4

0

66 pF

71 pF

103 pF

108 pF

122 pF

126 pF

141 pF

146 pF

Reserved

Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop

filters without requiring external components.

Internal loop filter capacitor C3 can be set according to the following table.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Capacitance

10 pF

11 pF

15 pF

16 pF

19 pF

20 pF

3:0

PLL2_LF_C3

0

24 pF

25 pF

29 pF

30 pF

33 pF

34 pF

38 pF

39 pF

Reserved

96

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9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE

This register sets the output value of the Status_LD2 pin.

Table 76. Register 0x16E

POR

DEFAULT

BIT

NAME

DESCRIPTION

This sets the output value of the Status_LD2 pin.

Field Value

0 (0x00)

MUX Value

Logic low

1 (0x01)

PLL1 DLD

PLL2 DLD

PLL1 and PLL2 DLD

Holdover status

DAC locked

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI readback

DAC rail

7:3

PLL2_LD_MUX

2

8 (0x08)

9 (0x09)

DAC low

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

DAC high

PLL1_N

PLL1_N/2

PLL2_N

PLL2_N/2

PLL1_R

16 (0x10)

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the I/O type of the Status_LD2 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL2_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

Output inverted (push-pull)

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

Output (open drain)

(1) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 and PLL2 DLD).

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9.7.9 (0x16F - 0x1FFF) Misc Registers

9.7.9.1 PLL2_PRE_PD, PLL2_PD

Table 77. Register 0x173

BIT

NAME

DESCRIPTION

7

N/A

Reserved

Powerdown PLL2 prescaler

0: Normal operation

1: Powerdown

6

PLL2_PRE_PD

Powerdown PLL2

0: Normal operation

1: Powerdown

5

PLL2_PD

N/A

4:0

Reserved

9.7.9.2 VCO1_DIV

Sets the VCO1 VCO divider value. This divider cannot be bypassed, and has a minimum value of 2. This register

is reserved for LMK04826 and LMK04828, and should be left unprogrammed.

Table 78. Register 0x174

POR

DEFAULT

BIT

NAME

DESCRIPTION

7:5

N/A

0

Reserved

When VCO_MUX selects VCO1 for LMK04821, the clock distribution frequency is equal to

VCO1 frequency divided by this divide value. This divider is also on the PLL2 feedback

path, and impacts the PLL2 N divider value.

Unlisted field values are reserved.

Field Value

0 (0x00)

Divide Value

2

3

8

4

5

7

6

VCO1_DIV

(LMK04821 only)

4:0

0

5 (0x05)

10 (0x0A)

20 (0x14)

23 (0x17)

27 (0x1B)

30 (0x1E)

9.7.9.3 OPT_REG_1

This register must be written with the following value, depending on which LMK0482x family part is used to

optimize VCO1 phase-noise performance over temperature. This register must be written before writing register

0x168 when using VCO1.

Table 79. Register 0x17C

BIT

NAME

DESCRIPTION

21: LMK04821

24: LMK04826

21: LMK04828

7:0

OPT_REG_1

98

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9.7.9.4 OPT_REG_2

This register must be written with the following value, depending on which LMK0482x family part is used to

optimize VCO1 phase-noise performance over temperature. This register must be written before writing register

0x168 when using VCO1.

Table 80. Register 0x17D

BIT

NAME

DESCRIPTION

51: LMK04821

119: LMK04826

51: LMK04828

7:0

OPT_REG_2

9.7.9.5 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST

Table 81. Register 0x182

BIT

7:3

2

NAME

N/A

DESCRIPTION

Reserved

RB_PLL1_LD_LOST

This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low.

Read back 0: PLL1 DLD is low.

Read back 1: PLL1 DLD is high.

1

RB_PLL1_LD

To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.

0: RB_PLL1_LD_LOST is set on next falling PLL1 DLD edge.

1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to

become set again.

0

CLR_PLL1_LD_LOST

9.7.9.6 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST

Table 82. Register 0x0x183

BIT

7:3

2

NAME

N/A

DESCRIPTION

Reserved

RB_PLL2_LD_LOST

This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low.

PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid reading of this bit.

Read back 0: PLL2 DLD is low.

1

RB_PLL2_LD

Read back 1: PLL2 DLD is high.

To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.

0: RB_PLL2_LD_LOST is set on next falling PLL2 DLD edge.

1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to

become set again.

0

CLR_PLL2_LD_LOST

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9.7.9.7 RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS

This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs

are shared with the RB_DAC_VALUE. See RB_DAC_VALUE section.

Table 83. Register 0x184

BIT

NAME

DESCRIPTION

7:6

RB_DAC_VALUE[9:8] See RB_DAC_VALUE section.

Read back 0: CLKin2 is not selected for input to PLL1.

Read back 1: CLKin2 is selected for input to PLL1.

5

4

RB_CLKin2_SEL

RB_CLKin1_SEL

Read back 0: CLKin1 is not selected for input to PLL1.

Read back 1: CLKin1 is selected for input to PLL1.

Read back 0: CLKin0 is not selected for input to PLL1.

Read back 1: CLKin0 is selected for input to PLL1.

3

2

1

RB_CLKin0_SEL

N/A

Read back 1: CLKin1 LOS is active.

Read back 0: CLKin1 LOS is not active.

RB_CLKin1_LOS

Read back 1: CLKin0 LOS is active.

Read back 0: CLKin0 LOS is not active.

0

RB_CLKin0_LOS

9.7.9.8 RB_DAC_VALUE

Contains the value of the DAC for user readback.

FIELD NAME

MSB

LSB

RB_DAC_VALUE

0x184 [7:6]

0x185 [7:0]

Table 84. Registers 0x184 and 0x185

POR

DEFAULT

BIT REGISTERS

NAME

DESCRIPTION

RB_DAC_

VALUE[9:8]

DAC value is 512 on power-on reset; if PLL1 locks upon power-up, the DAC

value changes.

7:6

7:0

0x184

0x185

2

RB_DAC_

VALUE[7:0]

0

9.7.9.9 RB_HOLDOVER

Table 85. Register 0x188

BIT

NAME

DESCRIPTION

7:5

N/A

Reserved

Read back 0: Not in HOLDOVER

Read back 1: In HOLDOVER

4

RB_HOLDOVER

N/A

3:0

Reserved

100

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9.7.9.10 SPI_LOCK

Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, and 0x1FFF. These registers must be

written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF.

These registers cannot be read back.

MSB

—

LSB

0x1FFD [7:0]

0x1FFE [7:0]

0x1FFF [7:0]

Table 86. Registers 0x1FFD, 0x1FFE, and 0x1FFF

POR

BIT REGISTERS

NAME

DESCRIPTION

DEFAULT

0: Registers unlocked.

1 to 255: Registers locked

7:0

0x1FFD

0x1FFE

SPI_LOCK[23:16]

SPI_LOCK[15:8]

0

0: Registers unlocked.

1 to 255: Registers locked

0 to 82: Registers locked

83: Registers unlocked

84 to 256: Registers locked

7:0

0x1FFF

SPI_LOCK[7:0]

83

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10 Applications and Implementation

10.1 Application Information

To assist customers in frequency planning and designing loop filters, Texas Instruments provides PLLatinum Sim

(www.ti.com/tool/PLLATINUMSIM-SW) and TICS Pro (www.ti.com/tool/TICSPRO-SW).

10.2 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window

size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals

of the PLL, for each event to occur. When a PLL digital lock event occurs, the PLL digital lock detect is asserted

true. When the holdover exit event occurs, the device exits holdover mode.

EVENT

PLL

PLL1

PLL2

PLL1

WINDOW SIZE

PLL1_WND_SIZE

PLL2_WND_SIZE

PLL1_WND_SIZE

LOCK COUNT

PLL1_DLD_CNT

PLL1 locked

PLL2 locked

Holdover exit

PLL2_DLD_CNT

HOLDOVER_DLD_CNT

For a digital lock detect event to occur, there must be a “lock count” number of phase-detector cycles of PLLX,

during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the

user programmable "window size." Because there must be at least "lock count" phase-detector events before a

lock event occurs, a minimum digital lock event time can be calculated as "lock count" / f_PDX, where X = 1 for

PLL1 or 2 for PLL2.

By using Equation 6, values for a "lock count" and "window size" can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × f_PDX

ppm =

PLLX_DLD_CNT

(6)

The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size"

by "lock count".

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window

size", then the “lock count” value is reset to 0.

10.2.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase-detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000: the minimum lock time of PLL2 is 10,000 / 40 MHz = 250 µs.

102

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10.3 Driving CLKin and OSCin Inputs

10.3.1 Driving CLKin and OSCin Pins With a Differential Source

Both CLKin ports can be driven by differential signals. TI recommends that the CLKin input mode be set to

bipolar (CLKinX_TYPE = 0) when using differential reference clocks. The OSCin input mode is hard-wired to

bipolar-equivalent. The LMK0482x family internally biases the input pins, thus the differential interface should be

AC coupled. The recommended circuits for driving the CLKin/OSCin pins with either LVDS or LVPECL are

shown in Figure 24 and Figure 25.

Figure 24. CLKinX and OSCin Termination for an LVDS Reference Clock Source

Figure 25. CLKinX and OSCin Termination for an LVPECL Reference Clock Source

A reference clock source that produces a differential sine wave output can drive the CLKin/OSCin pins using the

following circuit. The signal level must conform to the requirements for the CLKin/OSCin pins listed in Electrical

Characteristics.

Figure 26. CLKinX and OSCin Termination for a Differential Sinewave Reference Clock Source

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Driving CLKin and OSCin Inputs (continued)

10.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source

The CLKin/OSCin pins of the LMK0482x family can be driven using a single-ended reference clock source; for

example, either a sine wave source or an LVCMOS/LVTTL source. For the CLKin pins, either AC coupling or DC

coupling may be used. For the OSCin pins, AC coupling is required. In the case of the sine wave source that is

expecting a 50-Ω load, TI recommends using AC coupling, as shown in the circuit below with a 50-Ω termination.

NOTE

The signal level must conform to the requirements for the CLKin/OSCin pins listed in

Electrical Characteristics. CLKinX_TYPE is recommended to be set to bipolar mode

(CLKinX_TYPE = 0). OSCin is hard-wired to bipolar mode.

Figure 27. CLKinX and OSCin Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC

coupling may be used. If DC coupling is used, the CLKinX_TYPE should be set to MOS buffer mode

(CLKinX_TYPE = 1), and the voltage swing of the source must meet the specifications for DC-coupled, MOS-

mode clock inputs given in Electrical Characteristics. If AC coupling is used, the CLKinX_TYPE should be set to

the bipolar buffer mode (CLKinX_TYPE = 0), and the voltage swing at the input pins must meet the specifications

for AC-coupled, bipolar-mode clock inputs given in Electrical Characteristics. In AC-coupled bipolar mode, some

attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling

capacitor is sufficient.

Figure 28. DC-Coupled LVCMOS/LVTTL Reference Clock

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10.4 Output Termination and Biasing

10.4.1 LVPECL

Figure 29 shows the recommended resistor biasing configuration for the LVPECL format for both CLKout and

OSCout pins. The LVPECL emitter resistors for DCLKoutX or SDCLKoutY can be selected such that 120 Ω ≤ Re

≤ 240 Ω. When OSCout (pins 40 and 41) are configured to provide a buffered oscillator output in LVPECL

format, TI recommends setting the value of the emitter resistors for OSCout to 240 Ω. To avoid bias mismatch or

excessive loading of the bias circuitry, TI recommends connecting LVPECL outputs to the load through AC-

coupling capacitors as shown.

Figure 29. LVPECL Biasing for CLKout and OSCout

10.4.2 LVDS/HSDS

Figure 30 shows the recommended resistor biasing configuration for the LVDS/HSDS format for both CLKout

and OSCout pins. When connecting an HSDS output to a load, it should be AC-coupled. In cases where the

common mode output voltage of the LMK0482x family LVDS matches the common mode input voltage of the

LVDS receiver, DC coupling can be used; however, frequently LVDS is also AC-coupled to avoid any

driver/receiver mismatch issues.

The LVDS/HSDS driver requires a DC path for current from CLKoutX to CLKoutX* and from OSCout to OSCout*

on initial startup. If a DC path for current is not present on startup, LVDS/HSDS outputs may start up with lower

amplitude than expected, and in some cases could generate runt pulses or fail to oscillate for some time after

startup. Whenever AC-coupled LVDS or HSDS is used with external termination, the 100-Ω termination should

be placed on the LMK0482x side of the AC-coupling capacitors as illustrated in Figure 30.

Figure 30. LVDS/HSDS Output Termination for OSCout and CLKout, External Receiver Termination

In cases where the termination is internal to the receiver, place 560 Ω close to the CLKoutX/X* or

OSCout/OSCout* pins, to provide a DC path for the output on startup as illustrated in Figure 31.

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Output Termination and Biasing (continued)

Figure 31. LVDS/HSDS Output Termination for OSCout and CLKout, Internal Receiver Termination

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10.5 Typical Applications

10.5.1 Design Example

This design example below highlights using the available tools to design loop filters and create a programming

map for the LMK0482x.

10.5.1.1 Design Requirements

Clocks outputs:

•

1x 245.76-MHz clock for JESD204B ADC, LVPECL.

This clock requires the best performance in this example.

–

•

2x 983.04-MHz clock for JESD204B DAC, LVPECL.

1x 122.88-MHz clock for JESD204B FPGA block, LVDS

4x 10.24-MHz SYSREF for ADC (LCPECL), DAC (LVPECL), FPGA (LVDS).

2x 122.88-MHz clock for FPGA, LVDS

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used.

10.5.1.2 Detailed Design Procedure

This information is current as of the date of the release of this data sheet. Design tools receive continuous

improvements to add features and improve model accuracy. Refer to the software instructions or training for the

latest features.

10.5.1.2.1 Device Configuration and Simulation - PLLatinum Sim

Select the LMK04828 and choose the PLL and VCO to simulate. Make adjustments for more accurate

simulations depending on the application. For example:

•

Enter the VCO gain of the external VCXO or possible external VCO-used device.

Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents

result in smaller components, but may increase impacts of leakage, and at the lowest values reduce PLL

phase-noise performance.

•

PLLatinum Sim allows loading a custom phase noise plot for any block. Typically, a custom phase-noise plot

is entered for CLKin to match the reference phase noise to device; a phase-noise plot for the VCXO can

additionally be provided to match the performance of VCXO used. For improved accuracy in simulation and

optimum loop filter design, load these custom noise profiles for use in the application.

The design tools return with high reference and phase-detector frequencies by default. If desired, experiment

with different reference divider settings, phase detector frequencies, and loop bandwidths. Due to the narrow

loop bandwidth used on PLL1, it is common to reduce the phase detector frequency on PLL1.

10.5.1.2.2 Device Programming

Using the PLLatinum Sim configuration, the TICS Pro software is manually updated with this information to meet

the required application. For the JESD204B outputs, place the device clocks on the DCLKoutX output, then turn

on the paired SDCLKoutY output for SYSREF output. For non-JESD204B outputs, both DCLKoutX and paired

SDCLKoutY may be driven by the device clock divider to maximize number of available outputs.

Frequency planning for assignment of outputs:

•

To minimize crosstalk, perform frequency planning / CLKout assignments to keep common frequencies on

outputs close together.

•

It is best to place common device clock output frequencies on outputs sharing the same Vcc group. For

example, these outputs share Vcc4_CG2. Refer to Pin Configuration and Functions to see the Vcc groupings

the clock outputs.

In this example, the 245.76-MHz ADC output requires the best performance. DCLKout2 on the LMK0482x

provides the best noise floor / performance. The 245.76 MHz is placed on DCLKout2 with 10.24-MHz SYSREF

on SDCLKout3.

•

For best performance, the input and output drive level bits may be set. Best noise floor performance is

achieved with CLKout2_IDL = 1 and CLKout2_ODL = 1.

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Typical Applications (continued)

In this example, the 983.04-MHz DAC output is placed on DCLKout4 and DCLKout6, with 10.24-MHz SYSREF

on paired SDCLKout5 and SDCLKout7 outputs.

•

These outputs share Vcc4_CG2.

In this example, the 122.88-MHz FPGA JESD204B output is placed on DCLKout10, with 10.24-MHz SYSREF on

paired SDCLKout11 output.

Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on DCLKout8 and SDCLKout9.

•

When frequency planning, consider PLL2 as a clock output at the phase-detector frequency. As such, these

122.88-MHz outputs have been placed on the outputs close to the PLL2 and charge pump power supplies.

The register programming can be validated live on the device, with a SPI header wired to a TI USB2ANY

programmer. When the device programming is completed as desired in the TICS Pro software, it is possible to

export the register settings by using the Export Hex Registers option in the file menu.

10.5.1.3 Application Curves

Figure 32. DCLKout0, 245.76-MHz

LVPECL20 With 240-Ω Emitter Resistors

CLKout0_1_IDL = 1, CLKout0_1_ODL = 1

Figure 33. DCLKout2, 245.76-MHz

LVPECL20 With 240-Ω Emitter Resistors

CLKout2_3_IDL = 1, CLKout2_3_ODL = 1

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Typical Applications (continued)

Figure 34. DCLKout4, 983.04-MHz

LVPECL16 With 240-Ω Emitter Resistors

CLKout4_5_IDL = 1, CLKout4_5_ODL = 0

Figure 35. DCLKout6, 983.04-MHz

LVPECL16 With 240-Ω Emitter Resistors

CLKout6_7_IDL = 1, CLKout6_7_ODL = 0

Figure 36. DCLKout10, 122.88 MHz, LVDS

CLKout10_11_IDL = 1, CLKout10_11_ODL = 0

Figure 37. SDCLKout11, 122.88 MHz, LVDS

CLKout10_11_IDL = 1, CLKout10_11_ODL = 0

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Typical Applications (continued)

Figure 38. OSCout, 122.88 MHz, LVCMOS (Norm/Inv)

Normal Output Measured, Inverse 50-Ω Termination

Figure 39. Direct VCXO Measurement

Open Loop, Holdover Mode Set

10.6 System Examples

10.6.1 System Level Diagram

Figure 40 and Figure 41 show an LMK0482x family device with external circuitry for clocking and for power

supply to serve as a guideline for good practices when designing with the LMK0482x family. Refer to Pin

Connection Recommendations for more details on the pin connections and bypassing recommendations. Also

refer to the evaluation board in LMK04826/28 User's Guide. PCB design will also play a role in device

performance.

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System Examples (continued)

Figure 40. Example Application - System Schematic Except for Power

Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving

CLKin1/1*. Both clocks are depicted as AC-coupled drivers. The VCXO attached to the OSCin/OSCin* port is

configured as an AC-coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, CLKin2/2*,

OSCin/OSCin*) may be configured as either differential or single-ended (see Driving CLKin and OSCin Inputs).

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System Examples (continued)

The loop filter for PLL1 is configured as a 2nd-order passive filter, while the loop filter for PLL2 is configured as a

4th order passive filter (using internal 3rd and 4th order components). Typically it is not necessary to increase the

filter beyond 2nd order for PLL1. PLL2 allows software programmability of the 3rd and 4th order components

(see PLL2 Integrated Loop Filter Poles). PLLatinum Sim can be used to compute the loop filter values for optimal

phase noise.

All the LVPECL clock outputs are AC-coupled with 0.1 µF capacitors. Some LVPECL outputs are depicted with

240-Ω emitter resistors, and some are depicted with 150-Ω emitter resistors. LVPECL clock outputs can use

emitter resistors between 120 Ω and 240 Ω. OSCout LVPECL format only supports 240-Ω emitter resistors is

depicted with 240-Ω emitter resistors. The LCPECL SYSREF output is DC-coupled, with termination values

matching the conditions specified for LCPECL in the Electrical Characteristics. The non-JESD204B LVDS

outputs are AC-coupled, and include 560 Ω between the pins of the differential pair to create a DC path for

current on startup (see LVDS/HSDS). The JESD204B LVDS outputs are DC-coupled. Unused outputs are left

floating.

PCB design will influence crosstalk performance. Tightly coupled clock traces will have less crosstalk than

loosely coupled clock traces. Proximity to other clock traces will influence crosstalk.

Figure 41. Example Application - Power System Schematic

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System Examples (continued)

Figure 41 shows an example decoupling and bypassing scheme for the LMK0482x, which could apply to the

configuration shown in Figure 40. Components drawn in dotted lines are optional (see Pin Connection

Recommendations). Two power planes are used in these example designs, one for the clock outputs and one for

the PLL circuits. It is possible to reduce the number of decoupling components by tying together clock output Vcc

pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between outputs

with different frequencies. In the two examples, Vcc2 and Vcc11 can be tied together since no outputs are

utilized from Clock Group 0. PCB design will influence impedance to the supply. Vias and traces will increase the

impedance to the power supply. Ensure good direct return current paths.

10.7 Do's and Don'ts

•

V_CCPins and Decoupling: all V_CCpins must always be connected.

Unused Clock Outputs: leave unused clock outputs floating and powered down.

Unused Clock Inputs: unused clock inputs can be left floating.

OSCout: When set to an LVPECL drive format, OSCout emitter resistors should be 240 Ω to GND.

Otherwise, OSCout may be treated like any other clock output.

•

LVDS/HSDS Outputs: Ensure that there is a DC path for current from CLKoutX to CLKoutX*, and from

OSCout to OSCout*, for all LVDS/HSDS outputs at startup. See LVDS/HSDS.

RESET Pin: If the RESET pin is used, place a capacitor on RESET pin to prevent external noise from

causing device reset. If reset functionality is not used, consider resetting GPIO as output to prevent external

noise from causing device reset.

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11 Power Supply Recommendations

11.1 Pin Connection Recommendations

11.1.1 VCC Pins and Decoupling

All Vcc pins must always be connected.

Integrated capacitance on the LMK0482x makes external high frequency decoupling capacitors (<1 nF)

unnecessary. The internal capacitance is more effective at filtering high frequency noise than off-device bypass

capacitance because there is no bond wire inductance between the LMK0482x circuit and the bypass capacitor.

For lower-frequency decoupling and voltage stabilization, decoupling capacitors are still beneficial.

11.1.1.1 Clock Output Supplies

These supplies include Vcc2_CG1, Vcc3_SYSREF, Vcc4_CG2, Vcc11_CG3, and Vcc12_CG0. If OSCout is

used, Vcc7_OSCout can also be considered a clock output supply.

Ferrite beads may be used to reduce crosstalk between different clock groups on the same LMK0482x device.

Ferrite beads placed between the power supply and a clock group Vcc pin should reduce noise between the Vcc

pin and the power supply modestly above 30 MHz. Below 30 MHz, integrated LDOs provide additional noise

mitigation. When two clock groups share the same frequency, or if a clock group is not used, a single ferrite bead

can be used between the power supply and each same-frequency clock group Vcc pin.

When using ferrite beads on clock group Vcc pins, consider the following guidelines to ensure the power supply

will source the needed switching current:

•

In cases with an output frequency > 30 MHz, a ferrite bead may be placed and the internal capacitance is

sufficient

•

If a ferrite bead is used with a low frequency output (< 30 MHz), and the output format is set to a high current

switching format such as LVPECL or LCPECL, then:

–

The ferrite bead can be removed to lower the impedance to the main power supply and bypass capacitors,

or

–

Localized capacitance can be placed between the ferrite bead and Vcc pin to support the switching

current.

–

Note: the decoupling capacitors used between the ferrite bead and a clock group Vcc pin can permit

high frequency switching noise to couple through the capacitors into the ground plane and onto other

clock VCC pins through their decoupling capacitors. Placing unnecessary decoupling capacitances, or

placing ferrite beads with excessive impedance at high frequency (> 200 Ω) can degrade crosstalk

performance.

–

If the OSCout buffer format is LVCMOS, TI recommends using a complementary output format such as

LVCMOS (Norm/Inv) to reduce switching noise and crosstalk. If only a single LVCMOS output is required,

the complementary LVCMOS output format can still be used by leaving the unused LVCMOS output

floating.

•

Vcc3_SYSREF powers both the SYSREF divider and the SYNC circuitry. If SYNC is used but the SYSREF

divider is not, Vcc3_SYSREF can be connected to any other clock output supply without impacting noise

performance.

11.1.1.2 Low-Crosstalk Supplies

These supplies include Vcc1_VCO, Vcc5_DIG, and Vcc6_PLL1.

Each of these pins has internal bypass capacitance. Ferrite beads should not be needed between these pins and

the power supply. A ferrite bead can optionally before the common point connecting these supplies, in which

case a large decoupling capacitance (1 µF or more) should be used for voltage stability after the ferrite bead.

The typical application diagram in Figure 41 shows all these supply pins connected together to the power supply

with an optional ferrite bead and decoupling capacitance.

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Pin Connection Recommendations (continued)

These supplies are considered low-crosstalk supplies because they do not generate much noise. Vcc1_VCO

noise is effectively captured by the on-chip bypass capacitance, since noise from this pin is typically very high

frequency. This pin also uses a high-quality integrated LDO to minimize noise below 30 MHz. Vcc5_DIG is only

active at startup and during GPIO events, so after startup there is no continuous noise contribution from this pin.

Vcc6_PLL1 is usually low-noise as well, due to the low frequency of the PLL1 phase detector. An on-chip LDO

regulates this supply and prevents most PLL1 charge pump noise from escaping. If the PLL1 phase detector is

set to a high frequency, a ferrite bead may optionally be used on this supply. If a ferrite bead is used with this

supply, the DC resistance of this ferrite bead should be minimized to avoid voltage fluctuation at the PLL1

supply/PLL1 charge pump, and a 0.1-µF decoupling capacitor should be placed after the ferrite bead close to the

supply pin.

11.1.1.3 PLL2 Supplies

These supplies include Vcc9_CP2 and Vcc10_PLL2.

Each of these pins has an internal bypass capacitor. A ferrite bead should be placed between the power supply

and Vcc9. The DC resistance of this ferrite bead should be minimized to avoid voltage fluctuations at the PLL2

charge pump. Typically the frequency of the PLL2 phase detector is >50 MHz and an external decoupling

capacitor is not necessary. For lower PLL2 phase detector frequencies, a 0.1-µF decoupling capacitor should be

placed after the ferrite bead close to the supply pin. Use of a ferrite bead between the power supply and

Vcc10_PLL2 is optional. Normally the frequency of the dividers used by PLL2 is high enough that all noise is

well-constrained by the on-chip bypass capacitance. If a ferrite bead is used, a 0.1-µF decoupling capacitor

should be placed after the ferrite bead close to the supply pin.

11.1.1.4 Clock Input Supplies

These supplies include Vcc6_PLL1 and Vcc9_OSCin. If CLKin2 is used, Vcc7_OSCout is also included.

For Vcc6_PLL1, follow guidance in Low-Crosstalk Supplies. For Vcc9_OSCin, a ferrite bead is recommended for

VCXO frequencies above 30 MHz. Typically above 100 MHz no bypass capacitance is necessary on this pin, but

if the OSCin frequency is < 100 MHz, a 0.1-µF decoupling capacitor should be placed after the ferrite bead close

to the supply pin. Vcc7_OSCout should follow similar guidance to Vcc9 for CLKin2 above 30 MHz, and

Vcc6_PLL1 for CLKin2 below 30 MHz.

When CLKin1 is used as Fin or FBCLKin, TI recommends using CLKin2 as the source to PLL1 whenever

possible. CLKin0 and CLKin1 share Vcc6_PLL1 supply, and in cases where Fin or FBCLKin is high frequency,

CLKin0 can crosstalk to Fin/FBCLKin through Vcc6_PLL1. CLKin2 is powered from Vcc7_OSCout, and the

crosstalk between Fin/FBCLKin and CLKin2 is significantly reduced as a result.

11.1.1.5 Unused Clock Inputs/Outputs

Leave unused clock inputs and outputs floating. Set unused clock outputs to powerdown format, and disable

unused channel pairs. If the SYSREF is not used in a channel pair, SDCLKoutY_PD can be set. For maximum

power savings and noise immunity, set DCLKoutX_PD, SDCLKoutY_PD, and CLKoutX_Y_PD on all unused

channel pairs.

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11.2 Current Consumption / Power Dissipation Calculations

From Table 87, the current consumption can be calculated for any configuration. The data below is typical and

not assured.

The TICS Pro device profiles for LMK0482x family devices also include a current calculator, which performs real-

time analysis of the register settings and estimates the current consumption based on which blocks are enabled.

TI strongly recommends using TICS Pro to compute the current for any device profile, as it is faster and more

flexible than manual computation using the table below. TICS Pro does not require a connection to the

LMK0482x to generate a current consumption estimate or a register file.

Table 87. Typical Current Consumption for Selected Functional Blocks

(T_A= 25 °C, V_CC= 3.3 V)

POWER

TYPICAL I_CC

(mA)

DISSIPATED

in DEVICE

(mW)

BLOCK

CONDITION

CORE and FUNCTIONAL BLOCKS

Core

Dual loop, internal VCO0

VCO1 is selected

PLL1 and PLL2 locked

131.5

13.5

22

433.95

44.55

72.6

LMK04826/LMK04828

LMK04821

VCO (with VCO divider for

LMK04821)

OSCin Doubler

CLKin

Doubler is enabled

EN_PLL2_REF_2X = 1

3

9.9

Any one of the CLKinX is enabled

4.9

1.3

16.17

4.29

Holdover is enabled

Hitless switch is enabled

Track mode

HOLDOVER_EN = 1

HOLDOVER_HITLESS_SWI

TCH = 1

Holdover

0.9

2.97

TRACK_EN = 1

2.5

7.6

8.25

25.08

89.76

SYNC_EN = 1

Required for SYNC and SYSREF functionality

Enabled

SYSREF_PD = 0

27.2

Dynamic digital delay

enabled

SYSREF_DDLY_PD = 0

5

16.5

SYSREF

Pulser is enabled

SYSREF_PLSR_PD = 0

SYSREF_MUX = 2

SYSREF_MUX = 3

4.1

3

13.53

9.9

SYSREF pulses mode

SYSREF continuous mode

3

9.9

CLOCK GROUP

Enabled

IDL

Any one of the CLKoutX_Y_PD = 0

Any one of the CLKoutX_Y_IDL = 1

Andy one of the CLKoutX_Y_ODL = 1

20.1

2.2

66.33

7.26

ODL

3.2

10.56

44.88

58.41

44.88

Divider only

DCLKoutX_MUX = 0

13.6

17.7

13.6

Clock Divider

Divider + DCC + HS

Analog delay + divider

DCLKoutX_MUX = 1

DCLKoutX_MUX = 3

CLOCK OUTPUT BUFFERS

LVDS

100-Ω differential termination

6

19.8

29.04

38.28

64.02

HSDS 6 mA, 100-Ω differential termination

HSDS 8 mA, 100-Ω differential termination

HSDS 10 mA, 100-Ω differential termination

8.8

HSDS

11.6

19.4

OSCout BUFFERS

LVDS

100-Ω differential termination

18.5

42.6

27

61.05

140.58

89.1

LVCMOS pair

150 MHz

LVCMOS

LVCMOS single

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12 Layout

12.1 Layout Guidelines

12.1.1 Thermal Management

Power consumption of the LMK0482x family of devices can be high enough to require attention to thermal

management. For reliability and performance reasons, the die temperature should be limited to a maximum of

125°C. That is, as an estimate, T_A(ambient temperature) plus device power consumption multiplied by R_θJA

should not exceed 125°C.

The package of the device has an exposed pad that provides the primary heat removal path, as well as excellent

electrical grounding to a printed circuit board. To maximize the removal of heat from the package, a thermal land

pattern, including multiple vias to a ground plane, must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

7.2 mm

0.2 mm

1.46 mm

1.15 mm

Figure 42. Recommended Land and Via Pattern

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12.2 Layout Example

Figure 43. LMK0482x Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

13.1.1.1 PLLatinum Sim

Loop filter design and simulation.

For PLLatinum Sim, go to www.ti.com/tool/PLLATINUMSIM-SW.

13.1.1.2 TICS Pro

EVM programming software. Can also be used to generate register map for programming for a specific

application.

For TICS Pro, go to www.ti.com/tool/TICSPRO-SW

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 88. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LMK04821

LMK04826

LMK04828

Click here

13.3 Trademarks

PLLatinum is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

NKD 64

9 x 9, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4229637/A

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PACKAGE OUTLINE

NKD0064A

WQFN - 0.8 mm max height

S

C

A

L

E

1

.

6

0

WQFN

9.1

8.9

A

B

PIN 1 INDEX AREA

0.5

0.3

9.1

8.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

C

SEATING PLANE

(0.1)

TYP

7.2 0.1

SEE TERMINAL

DETAIL

17

32

60X 0.5

33

16

4X

7.5

1

48

0.3

64X

PIN 1 ID

64

49

0.2

(OPTIONAL)

0.1

C A

C

B

0.5

0.3

64X

0.05

4214996/A 08/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

NKD0064A

WQFN - 0.8 mm max height

WQFN

(

7.2)

SYMM

64X (0.6)

64X (0.25)

SEE DETAILS

49

64

1

48

60X (0.5)

SYMM

(8.8)

(1.36)

TYP

8X (1.31)

33

(

0.2) VIA

TYP

16

17

32

(1.36) TYP

8X (1.31)

(8.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214996/A 08/2013

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

NKD0064A

WQFN - 0.8 mm max height

WQFN

SYMM

(1.36) TYP

49

64X (0.6)

64X (0.25)

64

1

48

(1.36)

TYP

60X (0.5)

SYMM

(8.8)

METAL

TYP

16

33

17

32

25X (1.16)

(8.8)

SOLDERPASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

EXPOSED PAD

65% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4214996/A 08/2013

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMK04821NKDT
厂家：	TEXAS INSTRUMENTS
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