LMK1D1208P [TI]
带引脚控制的 8 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器;型号: | LMK1D1208P |
厂家: | TEXAS INSTRUMENTS |
描述: | 带引脚控制的 8 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器 |
文件: | 总31页 (文件大小:2260K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
LMK1D1208P 引脚控制型OE 低附加抖动LVDS 缓冲器
1 特性
3 说明
• 具有2 路输入和8 路输出(2:8) 的高性能LVDS 时
钟缓冲器系列
• 输出频率最高可达2GHz
• 通过硬件引脚实现启用/禁用独立输出
• 电源电压:1.8V/2.5V/3.3V ± 5%
• 低附加抖动:156.25MHz 下小于12kHz 至20MHz
范围内的60fs rms 最大值
LMK1D1208P 时钟缓冲器将两个中的任何一个可选时
钟输入(IN0 和IN1)分配给 8 对差分 LVDS 时钟输出
(OUT0 至OUT7),通过超小延迟实现时钟分配。输
入可以为 LVDS、LVPECL、LVCMOS、HCSL 或
CML。
LMK1D1208P 专为驱动 50Ω 传输线路而设计。在单端
模式下驱动输入时,对未使用的负输入引脚施加适当的
偏置电压(请参阅图 9-6)。IN_SEL 引脚用于选择要
发送到输出的输入。该器件支持失效防护输入功能。该
器件还整合了输入迟滞,可防止在没有输入信号的情况
下输出随机振荡。
– 超低相位本底噪声:-164dBc/Hz(典型值)
• 超低传播延迟:< 575ps(最大值)
• 输出偏斜:20ps(最大值)
• 失效防护输入
• 通用输入接受LVDS、LVPECL、LVCMOS、HCSL
和CML
• LVDS 基准电压(VAC_REF) 适用于容性耦合输入
• 工业温度范围:–40°C 至105°C
• 可用封装:
各个 LVDS 差分输出均可通过将对应的 OEx 引脚设置
为逻辑高电平“1”来实现。如果此引脚设置为逻辑低
电平“0”,输出将被禁用,呈现高阻态,从而降低功
耗。
– 6mm × 6mm 40 引脚VQFN (RHA)
该器件可在 1.8V、2.5V 或 3.3V 电源环境下工作,额
定温度范围是–40°C 至105°C(环境温度)。
2 应用
封装信息
• 电信及网络
• 医疗成像
封装尺寸(标称值)
封装(1)
器件型号
(2)
• 测试和测量
• 无线基础设施
• 专业音频、视频和标牌
LMK1D1208P
VQFN (40)
6.00mm × 6.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸(长× 宽)为标称值,并包括引脚(如适用)。
ADC CLOCK
500 MHz
156.25 MHz
Oscillator
LMK1D1208P
LVDS Buffer
IN_SEL
FPGA CLOCK
OEx
应用示例
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
9.2 Functional Block Diagram.........................................13
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................14
10 Application and Implementation................................17
10.1 Application Information........................................... 17
10.2 Typical Application.................................................. 17
10.3 Power Supply Recommendations...........................20
10.4 Layout..................................................................... 21
11 Device and Documentation Support..........................22
11.1 Documentation Support.......................................... 22
11.2 支持资源..................................................................22
11.3 Trademarks............................................................. 22
11.4 静电放电警告...........................................................22
11.5 术语表..................................................................... 22
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics..............................................10
8 Parameter Measurement Information.......................... 11
9 Detailed Description......................................................13
9.1 Overview...................................................................13
Information.................................................................... 22
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2021) to Revision A (June 2023)
Page
• 将表标题从“器件信息”更改为“封装信息”....................................................................................................1
• Added the Device Comparison table for LMK1Dxxxx buffer family of devices................................................... 3
• Moved the Power Supply Recommendations and Layout section to the Application and Implementation
section.............................................................................................................................................................. 20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
2
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
5 Device Comparison
表5-1. Device Comparison
OUTPUT
DEVICE
DEVICE TYPE
FEATURES
SWING
PACKAGE
BODY SIZE
Global output enable and
swing control through pin
control
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
LMK1D2108
Dual 1:8
Dual 1:6
Dual 1:4
Dual 1:2
VQFN (48)
7.00 mm × 7.00 mm
Global output enable and
swing control through pin
control
LMK1D2106
LMK1D2104
LMK1D2102
VQFN (40)
VQFN (28)
VQFN (16)
6.00 mm × 6.00 mm
5.00 mm × 5.00 mm
3.00 mm × 3.00 mm
Global output enable and
swing control through pin
control
Global output enable and
swing control through pin
control
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
Global output enable control
through pin control
LMK1D1216
LMK1D1212
LMK1D1208P
LMK1D1208I
2:16
2:12
2:8
VQFN (48)
VQFN (40)
VQGN (40)
VQFN (40)
7.00 mm × 7.00 mm
6.00 mm × 6.00 mm
6.00 mm × 6.00 mm
6.00 mm × 6.00 mm
Global output enable control
through pin control
Individual output enable
control through pin control
Individual output enable
control through I2C
2:8
Global output enable control
through pin control
LMK1D1208
LMK1D1204P
LMK1D1204
2:8
2:4
2:4
350 mV
350 mV
350 mV
VQFN (28)
VQGN (28)
VQFN (16)
5.00 mm × 5.00 mm
5.00 mm × 5.00 mm
3.00 mm × 3.00 mm
Individual output enable
control through pin control
Global output enable control
through pin control
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
6 Pin Configuration and Functions
V
ꢀ
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
V
ꢀ
DD
DD
NC
NC
OE4
OE5
OE3
OE2
OE1
OE6
DAP
OUT6_P
OUT6_N
OUT7_P
OUT7_N
OUT1_N
OUT1_P
OUT0_N
OUT0_P
V
ꢀ
V
ꢀ
DD
DD
Not to scale
图6-1. LMK1D1208P: RHA Package 40-Pin VQFN Top View
表6-1. Pin Functions
NAME
NO.
TYPE(1)
DESCRIPTION
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P
8
9
2
3
I
I
Primary: Differential input pair or single-ended input
Secondary: Differential input pair or single-ended input.
IN0_N
IN1_P
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
IN1_N
INPUT SELECT
Input selection with an internal 500-kΩpullup and 320-kΩpulldown,
selects input port. See 表9-2.
IN_SEL
1
I
I
AMPLITUDE SELECT
AMP_SEL
Output amplitude swing select with an internal 500-kΩpullup and 320-kΩ
pulldown. See 表9-4.
10
OUTPUT ENABLE
Output Enable for channel 0
OE0
OE1
OE2
OE3
OE4
6
I
I
I
I
I
HIGH (default): Enable output channel 0
LOW: Disable output channel 0 in Hi-Z state
Output Enable for channel 1
HIGH (default): Enable output channel 1
LOW: Disable output channel 1 in Hi-Z state
16
17
18
33
Output Enable for channel 2
HIGH (default): Enable output channel 2
LOW: Disable output channel 2 in Hi-Z state
Output Enable for channel 3
HIGH (default): Enable output channel 3
LOW: Disable output channel 3 in Hi-Z state
Output Enable for channel 4
HIGH (default): Enable output channel 4
LOW: Disable output channel 4 in Hi-Z state
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Functions (continued)
TYPE(1)
NAME
NO.
DESCRIPTION
Output Enable for channel 5
OE5
OE6
OE7
34
I
I
I
HIGH (default): Enable output channel 5
LOW: Disable output channel 5 in Hi-Z state
Output Enable for channel 6
HIGH (default): Enable output channel 6
LOW: Disable output channel 6 in Hi-Z state
35
5
Output Enable for channel 7
HIGH (default): Enable output channel 7
LOW: Disable output channel 7 in Hi-Z state
BIAS VOLTAGE OUTPUT
VAC_REF0
4
7
Bias voltage output for capacitive-coupled inputs. If used, TI recommends
using a 0.1-µF capacitor to GND on this pin.
O
VAC_REF1
DIFFERENTIAL CLOCK OUTPUT
OUT0_P
12
13
14
15
22
23
24
25
26
27
28
29
36
37
38
39
O
O
O
O
O
O
O
O
Differential LVDS output pair number 0
Differential LVDS output pair number 1
Differential LVDS output pair number 2
Differential LVDS output pair number 3
Differential LVDS output pair number 4
Differential LVDS output pair number 5
Differential LVDS output pair number 6
Differential LVDS output pair number 7
OUT0_N
OUT1_P
OUT1_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
OUT5_P
OUT5_N
OUT6_P
OUT6_N
OUT7_P
OUT7_N
SUPPLY VOLTAGE
VDD
11, 20, 31, 40
21, 30
P
Device power supply (1.8 V, 2.5 V, or 3.3 V)
Ground
GROUND
GND
G
MISC
DAP
G
Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for
heat dissipation.
DAP
NC
19, 32
No Connection. Leave floating.
—
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–20
–50
MAX
3.6
UNIT
V
VDD
VIN
VO
IIN
Supply voltage
Input voltage
3.6
V
Output voltage
VDD + 0.3
20
V
Input current
mA
mA
°C
°C
IO
Continuous output current
Junction temperature
Storage temperature (2)
50
TJ
135
Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Device unpowered
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
2.375
1.71
NOM
3.3
MAX
3.465
2.625
1.89
UNIT
3.3-V supply
2.5-V supply
1.8-V supply
VDD
Core supply voltage
Supply voltage ramp
2.5
V
1.8
Supply
Ramp
Requires monotonic ramp (10-90 % of
VDD)
0.1
20
ms
TA
TJ
Operating free-air temperature
Operating junction temperature
105
135
°C
°C
–40
–40
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
6
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
7.4 Thermal Information
LMK1D1208P
THERMAL METRIC(1)
RHA (VQFN)
40 PINS
30.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.6
13.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJT
13
ΨJB
RθJC(bot)
4.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
Core supply current, static
(LMK1D1208P)
All outputs enabled and
unterminated, f = 0 Hz
IDDSTAT
75
87
mA
mA
All outputs enabled, RL = 100 Ω, f
=100 MHz
IDD100M
Core supply current (LMK1D1208P)
110
IN_SEL/AMP_SEL CONTROL INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VdI3
VIH
Tri-state input
Open
0.4 × VCC
V
V
Minimum input voltage for a
logical "1" state in table 1
Input high voltage
0.7 × VCC
VCC + 0.3
0.3 × VCC
30
Maximum input voltage for a
logical "0" state in table 1
VIL
IIH
IIL
Input low voltage
Input high current
Input low current
V
–0.3
VDD can be 1.8V, 2.5V, or 3.3V
with VIH = VDD
µA
µA
VDD can be 1.8V, 2.5V, or 3.3V
with VIH = VDD
–30
Rpull-up
Input pullup resistor
500
320
kΩ
kΩ
Rpull-down
Input pulldown resistor
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
DC
0.4
250
MHz
V
Assumes a square wave input
with two levels
VIN_S-E
Single-ended Input Voltage Swing
3.465
Input Slew Rate (20% to 80% of the
amplitude)
dVIN/dt
0.05
V/ns
IIH
Input high current
Input low current
Input capacitance
VDD = 3.465 V, VIH = 3.465 V
VDD = 3.465 V, VIL = 0 V
at 25°C
60
µA
µA
pF
IIL
–30
CIN_SE
3.5
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
2
2.4
2.4
GHz
VPP
VICM = 1 V (VDD = 1.8 V)
VICM = 1.25 V (VDD = 2.5 V/3.3 V)
0.3
0.3
Differential input voltage peak-to-peak {2
× (VINP –VINN)}
VIN,DIFF(p-p)
VIN,DIFF(P-P) > 0.4 V (VDD = 1.8
V/2.5 V/3.3 V)
VICM
Input common-mode voltage
0.25
2.3
V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.465 V, VINP = 2.4 V, VINN
= 1.2 V
IIH
Input high current
30
µA
VDD = 3.465 V, VINP = 0 V, VINN
1.2 V
=
IIL
Input low current
µA
pF
–30
CIN_SE
Input capacitance (Single-ended)
at 25°C
3.5
LVDS DC OUTPUT CHARACTERISTICS
Differential output voltage magnitude |
VOUTP - VOUTN
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
|VOD|
|VOD|
ΔVOD
ΔVOD
250
400
–15
–20
1
350
500
450
650
15
mV
mV
mV
mV
|
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Differential output voltage magnitude |
VOUTP - VOUTN
|
Change in differential output voltage
magnitude
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Change in differential output voltage
magnitude
20
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 1.8 V)
1.2
Steady-state, common-mode output
voltage
VOC(SS)
V
V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 2.5 V/3.3 V)
1.1
1.375
1.05
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 1.8 V), AMP_SEL = 1
0.8
Steady-state, common-mode output
voltage
VOC(SS)
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 2.5 V/3.3 V), AMP_SEL
= 1
0.9
1.15
Change in steady-state, common-mode
output voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
15
20
mV
mV
ΔVOC(SS)
ΔVOC(SS)
–15
–20
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Change in steady-state, common-mode
output voltage
LVDS AC OUTPUT CHARACTERISTICS
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, fOUT = 491.52 MHz
Vring
VOS
Output overshoot and undershoot
Output AC common-mode voltage
0.1
VOD
–0.1
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
50
75
100
mVpp
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
VOS
Output AC common-mode voltage
150
12
mVpp
mA
IOS
Short-circuit output current (differential)
VOUTP = VOUTN
–12
–24
Short-circuit output current (common-
mode)
IOS(cm)
VOUTP = VOUTN = 0
24
mA
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
tPD
Propagation delay
Output skew
0.3
0.575
20
ns
ps
Ω(1)
Skew between outputs with the
same load conditions (12 and 16
channels) (2)
tSK, O
Skew between outputs on
different parts subjected to the
same operating conditions with
the same input and output
loading.
tSK, PP
Part-to-part skew
Pulse skew
200
20
ps
ps
50% duty cycle input, crossing
tSK, P
point-to-crossing-point distortion
–20
(4)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
8
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 156.25 MHz with 50% duty-
cycle, Input slew rate = 1.5V/ns,
Integration range = 12 kHz to 20
tRJIT(ADD)
Random additive Jitter (rms)
45
60 fs, RMS
MHz, with output load RLOAD
=
100 Ω
PN1kHz
PN10kHz
PN100kHz
PN1MHz
PNfloor
–143
–150
–157
–160
–164
Phase Noise for a carrier frequency of
156.25 MHz with 50% duty-cycle, Input
slew rate = 1.5V/ns with output load
RLOAD = 100 Ω
Phase noise
dBc/Hz
fIN = 156.25 MHz. The difference
in power level at fIN when the
selected clock is active and the
unselected clock is static versus
when the selected clock is inactive
and the unselected clock is active.
MUXISO
Mux Isolation
80
dB
ODC
tR/tF
Output duty cycle
With 50% duty cycle input
45
55
%
Output rise and fall time
300
ps
20% to 80% with RLOAD = 100 Ω
20% to 80% with RLOAD = 100 Ω
(AMP_SEL= 1)
tR/tF
Output rise and fall time
300
1
ps
µs
Time taken for outputs to go from
disable state to enable state and
vice versa. (3)
ten/disable
Output Enable and Disable Time
Outputs are held in high Z mode
with OUTP = OUTN (max applied
external voltage is the lesser of
VDD or 1.89V and minimum
IleakZ
Output leakage current in High Z
Reference output voltage
50
µA
V
applied external voltage is 0V)
VAC_REF
0.9
1.25
1.375
VDD = 2.5 V, ILOAD = 100 μA
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
10 kHz, 100 mVpp ripple injected
–70
–50
on VDD
Power Supply Noise Rejection (fcarrier
156.25 MHz)
=
PSNR
dBc
1 MHz, 100 mVpp ripple injected
on VDD
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Applies to the dual bank family.
(4) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
7.6 Typical Characteristics
图7-1 captures the variation of the LMK1D1208P current consumption with input frequency and supply voltage. 图7-2 shows
the variation of the differential output voltage (VOD) swept across frequency. It is important to note that 图7-1 and 图7-2
serve as a guidance to the users on what to expect for the range of operating frequency supported by LMK1D1208P. These
graphs were plotted for a limited number of frequencies and load conditions, which may not represent the customer system.
145
140
135
130
125
120
115
110
105
100
95
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
90
85
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
图7-1. LMK1D1208P Current Consumption vs Frequency
380
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V, Ta = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V, TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V, TA = 105
370
360
350
340
330
320
310
300
290
280
270
260
250
240
100
200
300
400
500
600 700 800 9001000
2000
Frequency (MHz)
图7-2. LMK1D1208P VOD vs Frequency
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
10
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
8 Parameter Measurement Information
Oscilloscope
100 W
LVDS
图8-1. LVDS Output DC Configuration During Device Test
Phase Noise/
Spectrum Analyzer
LMK1D1208P
Balun
100 Ω
图8-2. LVDS Output AC Configuration During Device Test
V
IH
V
th
IN
V
IL
IN
V
th
图8-3. DC-Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
V
OD
V
OL
80%
V
(= 2 x V
)
OD
20%
0 V
OUT,DIFF,PP
t
r
t
f
图8-4. Output Voltage and Rise/Fall Time
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
INNx
INPx
t
t
t
PLH0
PHL0
PHL1
OUTN0
OUTP0
t
PLH1
OUTN1
OUTP1
t
t
PLH2
PHL2
OUTN2
OUTP2
t
t
PHL7
PLH7
OUTN7
OUTP7
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
图8-5. Output Skew and Part-to-Part Skew
V
ring
OUTNx
V
OD
0 V Differential
OUTPx
图8-6. Output Overshoot and Undershoot
V
OS
GND
图8-7. Output AC Common Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
12
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
9 Detailed Description
9.1 Overview
The LMK1D1208P LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing
and termination are required to ensure correct operation of the device and to maximize signal integrity.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the LMK1D1208P, AC coupling must be used. If the LVDS
receiver has internal 100-Ωtermination, external termination must be omitted.
9.2 Functional Block Diagram
VDD
1.8 to 3.3 V
OE0
OUT0
LVDS
OE1
Reference
Generator
VAC_REF
OE1
IN0
IN1
LVDS
OUT1
IN_MUX
OE2
VDD
Rpull-up
LVDS
OUT2
IN_SEL
OE2
Rpull-down
OE7
VDD
Rpull-up
OUT7
LVDS
Output
Swing
AMP_SEL
Control
Rpull-down
GND
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
9.3 Feature Description
The LMK1D1208P is a low additive jitter LVDS fan-out buffer that can generate up to four copies of two
selectable LVPECL, LVDS, HCSL, CML, or LVCMOS inputs. The LMK1D1208P can accept reference clock
frequencies up to 2 GHz while providing low output skew.
表9-1 lists the LMK1D1208P outputs divided into two banks.
表9-1. Output Bank Mapping
BANK
CLOCK OUTPUTS
0
1
OUT0, OUT1, OUT2, OUT3
OUT4, OUT5, OUT6, OUT7
Apart from providing a very low additive jitter and low output skew, the LMK1D1208P has an input select pin
(IN_SEL) and an output amplitude control pin (AMP_SEL).
9.3.1 Fail-Safe Input
The LMK1D120x family of devices is designed to support fail-safe input operation feature. This feature allows the
user to drive the device inputs before VDD is applied without damaging the device. Refer to Specifications for
more information on the maximum input supported by the device. The user should note that incorporating the
fail-safe inputs also results in a slight increase in clock input pin capacitance. The device also incorporates an
input hysteresis which prevents random oscillation in absence of an input signal. Furthermore, this feature allows
the input pins to be left open.
9.4 Device Functional Modes
The two inputs of the LMK1D1208P are internally muxed together and can be selected through the control pin
(see 表 9-2). Unused inputs can be left floating to reduce overall component cost. Both AC- and DC-coupling
schemes can be used with the LMK1D1208P to provide greater system flexibility.
表9-2. Input Selection Table
IN_SEL
ACTIVE CLOCK INPUT
IN0_P, IN0_N
IN1_P, IN1_N
None (1)
0
1
Open
(1) The input buffers are disabled and the state of the outputs are
dependent on the state of OEx (see 表9-3). If OEx = 0, the
corresponding output will be disabled in Hi-Z state, whereas if
OEx = 1 (default), the corresponding output will be logic low.
The outputs of the LMK1D1208P can be individually enabled or disabled using the OEx hardware pins (see 表
9-3). The disabled state of the outputs is Hi-Z (high impedance) as this reduces the power consumption and also
prevents back-biasing of the devices connected to these outputs.
Unused outputs should be disabled to eliminate the need for a termination resistor. In the case of enabled
unused outputs, TI recommends a 100-Ωtermination for optimal performance.
表9-3. Output Control
OEx
0
CLOCK OUTPUTS
OUTPx, OUTNx disabled in Hi-Z
state
1 (default)
OUTPx, OUTNx enabled
The output amplitude of the banks of the LMK1D1208P can be selected through the amplitude selection pin (see
表 9-4). The higher output amplitude mode (boosted LVDS swing mode) can be used in applications which
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
14
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
require higher amplitude either for better noise performance (higher slew rate) or if the receiver has swing
requirements which the standard LVDS swing cannot meet.
表9-4. Amplitude Selection
AMP_SEL
OUTPUT AMPLITUDE (mV)
Bank 0: boosted LVDS swing (500 mV)
Bank 1: standard LVDS swing (350 mV)
0
Bank 0: standard LVDS swing (350 mV)
Bank 1: standard LVDS swing (350 mV)
OPEN
1
Bank 0: boosted LVDS swing (500 mV)
Bank 1: boosted LVDS swing (500 mV)
9.4.1 LVDS Output Termination
TI recommends that unused outputs are terminated differentially with a 100-Ωresistor for optimum performance,
although unterminated outputs are also okay but will result in slight degradation in performance (Output AC
common-mode VOS) in the outputs being used.
The LMK1D1208P can be connected to LVDS receiver inputs with DC and AC coupling as shown in 图 9-1 and
图9-2, respectively.
100 W
LVDS
LMK1D120xP
Z = 50 W
图9-1. Output DC Termination
100 nF
100 W
LVDS
LMK1D120xP
Z = 50 W
100 nF
图9-2. Output AC Termination (With the Receiver Internally Biased)
9.4.2 Input Termination
The LMK1D1208P inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.
LVDS drivers can be connected to LMK1D1208P inputs with DC and AC coupling as shown 图 9-3 and 图 9-4,
respectively.
100 W
LVDS
LMK1D120xP
Z = 50 W
图9-3. LVDS Clock Driver Connected to LMK1D1208P Input (DC-Coupled)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
100 nF
LVDS
LMK1D120xP
Z = 50 W
100 nF
50 W
50 W
V
AC_REF
图9-4. LVDS Clock Driver Connected to LMK1D1208P Input (AC-Coupled)
图 9-5 shows how to connect LVPECL inputs to the LMK1D1208P. The series resistors are required to reduce
the LVPECL signal swing if the signal swing is >1.6 VPP
.
75 W
100 nF
LMK1D120xP
LVPECL
Z = 50 W
100 nF
50 W
75 W
150 W
150 W
50 W
V
AC_REF
图9-5. LVPECL Clock Driver Connected to LMK1D1208P Input
图9-6 shows how to couple a LVCMOS clock input to the LMK1D1208P directly.
R
S
LVCMOS
(1.8/2.5/3.3 V)
LMK1D120XP
V
V
+
2
V
=
IH
IL
th
图9-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1208P Input
For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩresistors.
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LMK1D1208P is a low additive jitter universal to LVDS fan-out buffer with two selectable inputs, output
amplitude selection, and pin-controlled output enables. The small package size, low output skew, low
propagation delay and low additive jitter of this device is designed for applications that require high-performance
clock distribution as well as for low-power and space-constraint applications.
10.2 Typical Application
1.8 V / 2.5 V / 3.3 V
PHY
PRIREF_P
156.25 MHz LVDS
From Backplane
100
PRIREF_N
50
50
VAC_REF
ASIC
100
156.25 MHz LVCMOS
Oscillator
SECREF_P
FPGA
100
2.5 V
1k
SECREF_N
CPU
1k
100
图10-1. Fan-Out Buffer for Line Card Application
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
10.2.1 Design Requirements
The LMK1D1208P shown in 图 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the
backplane, or a secondary 156.25-MHz, LVCMOS, 2.5-V oscillator. The LVDS clock is AC-coupled and biased
using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly
for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both VAC_REF and SECREF_N. Either
input signal can be then fanned out to desired devices, as shown. The configuration example is driving 4 LVDS
receivers in a line card application with the following properties:
• The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1208P. This PHY device
features internal termination so no additional components are required for proper operation.
• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as
the LMK1D1208P. Again, no additional components are required.
• The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to
provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling
capacitors.
• The unused outputs of the LMK1D1208P can be disabled using the corresponding OEx pin. This results in a
lower power consumption.
10.2.2 Detailed Design Procedure
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
Unused outputs can be disabled using the corresponding OEx pin setting according to 表 9-3. Disabling the
outputs also eliminates requirement of termination resistors.
In this example, the PHY, ASIC, FPGA and CPU require different schemes. Power supply filtering and bypassing
is critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide (SCAU043).
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
18
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
10.2.3 Application Curves
This section shows the low additive noise for the LMK1D1208P. The low noise 156.25-MHz source with 24-fs
RMS jitter shown in 图 10-2 drives the LMK1D1208P, resulting in 46.4-fs RMS when integrated from 12 kHz to
20 MHz (see 图10-3). The resultant additive jitter is 39.7-fs RMS for this configuration.
Note: Reference signal is a low-noise Rhode and Schwarz SMA100B
图10-2. LMK1D1208P Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
图10-3. LMK1D1208P Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)
10.3 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver. These ferrite beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC
resistance because it is imperative to provide adequate isolation between the board supply and the chip supply,
as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper
operation.
图10-4 shows this recommended power-supply decoupling method.
Board
Supply
Chip
Supply
Ferrite Bead
1 μF
0.1 μF (x4)
10 μF
GND
GND
GND
图10-4. Power Supply Decoupling
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
20
Submit Document Feedback
Product Folder Links: LMK1D1208P
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
10.4 Layout
10.4.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.
The device package has an exposed pad that provides the primary heat removal path to the PCB. To maximize
the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must
be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to
ensure adequate heat conduction to of the package. 图 10-5 and 图 10-6 show the recommended land and via
patterns for the 40-pin LMK1D1208P device.
10.4.2 Layout Examples
图10-5. Recommended PCB Layout, Top Layer
图10-6. Recommended PCB Layout, GND Layer
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: LMK1D1208P
English Data Sheet: SNAS832
LMK1D1208P
ZHCSOB1A –OCTOBER 2021 –REVISED JUNE 2023
www.ti.com.cn
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide
• Texas Instruments, Power Consumption of LVPECL and LVDS Analog design journal
• Texas Instruments, Using Thermal Calculation Tools for Analog Components application report
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS832
22
Submit Document Feedback
Product Folder Links: LMK1D1208P
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK1D1208PRHAR
LMK1D1208PRHAT
ACTIVE
VQFN
VQFN
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
LMK1D
1208P
Samples
Samples
ACTIVE
RHA
NIPDAU
LMK1D
1208P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1D1208PRHAR
LMK1D1208PRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK1D1208PRHAR
LMK1D1208PRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040B
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
2X 4.5
4.15 0.1
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
4.5
SYMM
41
30
0.27
40X
1
0.17
PIN 1 ID
(OPTIONAL)
0.1
C A B
40
31
SYMM
0.05
0.5
0.3
40X
4219052/A 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.15)
SYMM
40X (0.6)
40X (0.22)
40
31
1
30
(0.25) TYP
36X (0.5)
SYMM
41
(5.8)
(0.685)
TYP
(1.14)
TYP
(
0.2) TYP
VIA
10
21
(R0.05) TYP
20
11
(0.685)
TYP
(1.14)
TYP
(5.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MIN
ALL SIDES
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219052/A 06/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.17)
(1.37) TYP
40X (0.6)
40X (0.22)
31
40
1
30
41
(1.37)
TYP
(0.25) TYP
SYMM
(5.8)
36X (0.5)
(R0.05) TYP
10
21
11
20
METAL
TYP
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4219052/A 06/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明