LMK60A0-148M35SIAR [TI]
148.352MHz、LVDS、高性能、低抖动差动振荡器 | SIA | 6 | -40 to 85;型号: | LMK60A0-148M35SIAR |
厂家: | TEXAS INSTRUMENTS |
描述: | 148.352MHz、LVDS、高性能、低抖动差动振荡器 | SIA | 6 | -40 to 85 机械 输出元件 振荡器 |
文件: | 总19页 (文件大小:587K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
LMK60XX 高性能低抖动振荡器
1 特性
3 说明
1
•
低噪声、高性能
LMK60XX 器件是一款低抖动振荡器,可生成常用参考
时钟。该器件在工厂预编程,可支持任何参考时钟频
率;支持的输出格式包括 LVPECL、LVDS(最高
800MHz)和 HCSL(最高 400MHz)。内部电源调节
功能提供出色的电源纹波抑制 (PSRR),降低了供电网
络的成本和复杂性。该器件由单个 3.3V ± 5% 电源供
电。
–
抖动:Fout > 100MHz 时的典型值为 150fs
(RMS)
–
电源抑制比 (PSRR):-60dBc,出色的电源抗扰
度
•
•
支持的输出格式
–
低压正发射极耦合逻辑 (LVPECL) 和低压差
分信令 (LVDS) 高达 800MHz
器件信息(1)
–
HCSL 高达 400MHz
输出频率 (MHz)
及格式
总频率稳定性
(ppm)
总频率容差为 ±50ppm (LMK60X2) 和 ±25ppm
(LMK60X0)
器件型号
封装/尺寸
LMK60E2-
150M
150 LVPECL
±50
±25
±25
±25
•
•
•
3.3V 工作电压
工业温度范围(-40ºC 至 +85ºC)
LMK60E0-
156257
156.257
LVPECL
6 引脚四方扁
平无引线模块
(QFM) 封装,
7mm × 5mm
7mm × 5mm 6 引脚封装,与行业标准 7050 XO 封
装引脚兼容
LMK60A0-
148351
148 + 32/91
LVDS
LMK60A0-
148M
2 应用
148.5 LVDS
•
晶体振荡器、表面声波 (SAW) 振荡器或芯片振荡
器的高性能替换产品
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
•
开关、路由器、网卡、基带装置 (BBU)、服务器、
存储/SAN
•
•
•
测试和测量
医疗成像
FPGA,处理器连接
引脚分配
6
5
OE
NC
1
2
3
6
5
4
VDD
4
OUTN
OUTP
GND
1
2
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS687
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
目录
6.12 PSRR Characteristics ............................................. 6
6.13 PLL Clock Output Jitter Characteristics .................. 6
6.14 Additional Reliability and Qualification.................... 6
6.15 Typical Characteristics............................................ 7
Parameter Measurement Information .................. 8
7.1 Device Output Configurations ................................... 8
Power Supply Recommendations...................... 10
Layout ................................................................... 10
9.1 Layout Guidelines ................................................... 10
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings ............................................................ 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics - Power Supply ................. 4
6.6 LVPECL Output Characteristics................................ 4
6.7 LVDS Output Characteristics .................................... 5
6.8 HCSL Output Characteristics.................................... 5
6.9 OE Input Characteristics........................................... 5
6.10 Frequency Tolerance Characteristics ..................... 5
6.11 Power-On/Reset Characteristics (VDD).................. 6
7
8
9
10 器件和文档支持 ..................................................... 12
10.1 相关链接................................................................ 12
10.2 接收文档更新通知 ................................................. 12
10.3 社区资源................................................................ 12
10.4 商标....................................................................... 12
10.5 静电放电警告......................................................... 12
10.6 Glossary................................................................ 12
11 机械、封装和可订购信息....................................... 13
4 修订历史记录
Changes from Revision B (December 2016) to Revision C
Page
•
•
LMK60A0-148351 新品发布 ................................................................................................................................................... 1
LMK60A0-148M 新品发布 ...................................................................................................................................................... 1
Changes from Revision A (August 2016) to Revision B
Page
•
•
将 LMK60E2-150M00 更改为 LMK60E2-150M ..................................................................................................................... 1
删除了 LMK60E2-156M 并将其移动到其他产品说明书 .......................................................................................................... 1
Changes from Original (June 2016) to Revision A
Page
•
LMK60E0-156257 新品发布 ................................................................................................................................................... 1
2
Copyright © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
5 Pin Configuration and Functions
SIA Package
6-pin QFM
Top View
OE
NC
1
6
5
4
VDD
2
3
OUTN
OUTP
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
POWER
GND
NO.
3
6
Ground
Analog
Device ground
VDD
3.3-V power supply
OUTPUT BLOCK
OUTP,
OUTN
4, 5
Universal
Differential output pair (LVPECL, LVDS or HCSL).
No connect
DIGITAL CONTROL / INTERFACES
NC
2
N/A
Output enable (internal pullup). When set to low, output pair is disabled and set at high
impedance.
OE
1
LVCMOS
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
3.6
UNIT
V
VDD
VIN
Device supply voltage
Output voltage for logic inputs
Output voltage for clock outputs
Junction temperature
VDD + 0.3
VDD + 0.3
150
V
VOUT
TJ
V
°C
°C
TSTG
Storage temperature
–40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2017, Texas Instruments Incorporated
3
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
–40
NOM
3.3
MAX
3.465
85
UNIT
V
VDD
TA
Device supply voltage
Ambient temperature
Junction temperature
VDD power-up ramp time
25
°C
TJ
120
°C
tRAMP
0.1
100
ms
6.4 Thermal Information
(2) (3) (4)
LMK60XX
SIA (QFM)
THERMAL METRIC(1)
UNIT
6 PINS
Airflow (LFM) 0
Airflow (LFM) 200
Airflow (LFM) 400
RθJA
Junction-to-ambient thermal resistance
55.2
34.6
37.7
11.3
37.7
n/a
46.4
n/a
43.7
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
n/a
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.6
41.5
n/a
22.5
40.1
n/a
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal resistance is calculated on a 4 layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. See the Layout Guidelines section for
more information on ensuring good system reliability and quality.
6.5 Electrical Characteristics - Power Supply(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
162
152
155
MAX
208
196
196
UNIT
LVPECL(2)
LVDS
IDD
Device current consumption
mA
HCSL
Device current consumption
when output is disabled
IDD-PD
OE = GND
136
mA
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 Ω termination resistors, from total power dissipation.
6.6 LVPECL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
Output frequency(2)
TEST CONDITIONS
MIN
10
TYP
MAX
800
UNIT
MHz
mV
V
fOUT
VOD
(2)
Output voltage swing (VOH – VOL
)
700
800
1200
VOUT, DIFF, PP Differential output peak-to-peak swing
2 × |VOD|
VOS
Output common-mode voltage
Output rise/fall time (20% to 80%)(3)
Output duty cycle(3)
VDD – 1.55
150
V
tR / tF
ODC
250
ps
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.
4
Copyright © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
6.7 LVDS Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
Output frequency(1)
TEST CONDITIONS
MIN
10
TYP
MAX
800
UNIT
MHz
mV
fOUT
VOD
Output voltage swing
300
390
480
(1)
(VOH - VOL
)
VOUT, DIFF, PP Differential output peak-to-peak swing
2 × |VOD
|
V
V
VOS
Output common-mode voltage
Output rise/fall time (20% to 80%)(2)
Output duty cycle(2)
1.2
tR / tF
ODC
ROUT
150
250
ps
45%
55%
Differential output impedance
125
Ω
(1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(2) Ensured by characterization.
6.8 HCSL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
Output frequency
Output high voltage
Output low voltage
TEST CONDITIONS
MIN
10
TYP
MAX
400
850
100
475
140
2
UNIT
MHz
mV
fOUT
VOH
600
–100
250
0
VOL
mV
VCROSS
Absolute crossing voltage(2)(3)
mV
(2)(3)
VCROSS-DELTA Variation of VCROSS
mV
dV/dt
ODC
Slew rate(4)
Output duty cycle(4)
0.8
V/ns
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
(3) Ensured by design.
(4) Ensured by characterization.
6.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
Input high voltage
Input low voltage
Input high current
Input low current
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIH
1.4
0.6
40
40
V
VIH = VDD
VIL = GND
–40
–40
µA
µA
pF
IIL
CIN
2
6.10 Frequency Tolerance Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LMK60X2: All output formats, frequency
bands and device junction temperature up to
125°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (10 years)
–50
50
25
ppm
fT
Total frequency tolerance
LMK60X0: All output formats, frequency
bands and device junction temperature up to
115°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (5 years at 40°C)
–25
ppm
(1) Ensured by characterization.
Copyright © 2016–2017, Texas Instruments Incorporated
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LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6.11 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.95
0.1
UNIT
V
VTHRESH
VDROOP
Threshold voltage(1)
Allowable voltage droop(2)
2.72
V
Time elapsed from VDD at 3.135 V to output
enabled
(1)
tSTARTUP
Start-up time
10
ms
tOE-EN
tOE-DIS
Output enable time(2)
Output disable time(2)
Time elapsed from OE at VIH to output enabled
Time elapsed from OE at VIL to output disabled
50
50
µs
µs
(1) Ensured by characterization.
(2) Ensured by design.
6.12 PSRR Characteristics(1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER
TEST CONDITIONS
Sine wave at 50 kHz
MIN
TYP
–60
–60
–60
–60
MAX
UNIT
Spurs induced by 50-mV
power supply ripple(2)(3) at
PSRR
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
dBc
156.25-MHz output, all
output types
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
(3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.13 PLL Clock Output Jitter Characteristics(1)(2)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
RMS phase jitter(3)
(12 kHz – 20 MHz)
TEST CONDITIONS
MIN
TYP
150
MAX
250
UNIT
RJ
f
OUT ≥ 100 MHz, All output types
fs RMS
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
(3) Ensured by characterization.
6.14 Additional Reliability and Qualification
PARAMETER
CONDITION / TEST METHOD
MIL-STD-202, Method 213
MIL-STD-202, Method 204
J-STD-020, MSL3
Mechanical Shock
Mechanical Vibration
Moisture Sensitivity Level
6
Copyright © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
6.15 Typical Characteristics
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0.9
0.8
0.7
0.6
0.5
0
200
400
600
800
1000
0
200
400
600
800
1000
Output Frequency (MHz)
Output Frequency (MHz)
D013
D014
Figure 1. LVPECL Differential Output Swing vs Frequency
Figure 2. LVDS Differential Output Swing vs Frequency
1.5
1.48
1.46
1.44
1.42
1.4
0
100
200
300
400
500
Output Frequency (MHz)
D015
Figure 3. HCSL Differential Output Swing vs Frequency
Copyright © 2016–2017, Texas Instruments Incorporated
7
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
7 Parameter Measurement Information
7.1 Device Output Configurations
High impedance differential probe
LVPECL
LMK60XX
Oscilloscope
150 ꢀ
150 ꢀ
Figure 4. LVPECL Output DC Configuration During Device Test
High impedance differential probe
LMK60XX
LVDS
Oscilloscope
Figure 5. LVDS Output DC Configuration During Device Test
High impedance differential probe
HCSL
LMK60XX
Oscilloscope
50 ꢀ
50 ꢀ
Figure 6. HCSL Output DC Configuration During Device Test
Phase Noise/
Balun/
Buffer
Spectrum
Analyzer
LMK60XX
LVPECL
150 ꢀ
150 ꢀ
Figure 7. LVPECL Output AC Configuration During Device Test
Phase Noise/
Spectrum
Analyzer
Balun/
Buffer
LMK60XX
LVDS
Figure 8. LVDS Output AC Configuration During Device Test
8
Copyright © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
Device Output Configurations (continued)
Phase Noise/
Spectrum
Analyzer
Balun/
Buffer
LMK60XX
HCSL
50 ꢀ
50 ꢀ
Figure 9. HCSL Output AC Configuration During Device Test
Sine wave
Modulator
Power Supply
Phase Noise/
LMK60XX
Spectrum
Analyzer
Balun
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
Figure 10. PSRR Test Setup
OUT_P
OUT_N
VOD
80%
VOUT,DIFF,PP = 2 x VOD
0 V
20%
tR
tF
Figure 11. Differential Output Voltage and Rise/Fall Time
Copyright © 2016–2017, Texas Instruments Incorporated
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LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
8 Power Supply Recommendations
For best electrical performance of LMK60XX, TI recommends using a combination of 10 µF, 1 µF and 0.1 µF on
its power supply bypass network. TI also recommends using component side mounting of the power supply
bypass capacitors, and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the
connections between the bypass capacitors and the power supply on the device as short as possible. Ground the
other side of the capacitor using a low impedance connection to the ground plane. Figure 12 shows the layout
recommendation for power supply decoupling of LMK60XX.
9 Layout
9.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK60XX to ensure good thermal / electrical performance and overall signal integrity of
entire system.
9.1.1 Ensuring Thermal Reliability
The LMK60XX is a high performance device. Therefore pay careful attention to device configuration and printed-
circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the
ground plane of the PCB through three vias or more, as shown in Figure 12, to maximize thermal dissipation out
of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK60XX and its junction
temperature.
TB = TJ – ΨJB * P
where
•
•
•
•
TB: PCB temperature around the LMK60XX
TJ: Junction temperature of LMK60XX
ΨJB: Junction-to-board thermal resistance parameter of LMK60XX (37.7°C/W without airflow)
P: On-chip power dissipation of LMK60XX
(1)
To ensure that the maximum junction temperature of LMK60XX is below 120°C, it can be calculated that the
maximum PCB temperature without airflow should be at 90°C or below when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.68 W.
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK60XX, TI recommends routing vias
into decoupling capacitors and then into the LMK60XX. TI also recommends increasing the via count and width
of the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency
current flow. Figure 12 shows the layout recommendation for LMK60XX.
10
版权 © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
Layout Guidelines (接下页)
Figure 12. LMK60XX Layout Recommendation for Power Supply and Ground
9.1.3 Recommended Solder Reflow Profile
TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the LMK60XX to be
processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
版权 © 2016–2017, Texas Instruments Incorporated
11
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ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
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10 器件和文档支持
10.1 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的
快速链接。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
LMK60E2-150M
LMK60E0-156257
10.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
10.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12
版权 © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
13
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
PACKAGE OUTLINE
SIA0006A
QFM - 1.15 mm max height
S
C
A
L
E
2
.
2
0
0
QUAD FLAT MODULE
5.1
4.9
B
A
PIN 1 INDEX
AREA
7.1
6.9
C
1.15 MAX
0.1 C
3X 3.7
6X (0.15)
3
4
4X (0.26)
SYMM
6X
2X
5.08
1.43
1.37
4X
2.54
0.1
0.05
C A
C
B
6
1
1.03
0.97
SYMM
6X
4222361/B 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
14
版权 © 2016–2017, Texas Instruments Incorporated
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com.cn
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
EXAMPLE BOARD LAYOUT
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
6X (1)
1
6
6X (1.4)
SYMM
4X (2.54)
4
3
(R0.05) TYP
(3.7)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222361/B 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
版权 © 2016–2017, Texas Instruments Incorporated
15
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
ZHCSFA1C –JUNE 2016–REVISED NOVEMBER 2017
www.ti.com.cn
EXAMPLE STENCIL DESIGN
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
12X (1)
1
6
12X (0.6)
(R0.05)
METAL TYP
SYMM
4X (2.54)
4
3
(0.4) TYP
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
ALL PADS: 86%
SCALE:10X
4222361/B 10/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
16
版权 © 2016–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK60A0-148M35SIAR
LMK60A0-148M35SIAT
LMK60A0-148M50SIAR
LMK60A0-148M50SIAT
LMK60E0-156257SIAR
LMK60E0-156257SIAT
LMK60E2-150M00SIAR
LMK60E2-150M00SIAT
ACTIVE
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
SIA
6
6
6
6
6
6
6
6
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LMK60A0
148M35
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SIA
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
LMK60A0
148M35
SIA
LMK60A0
148M50
SIA
LMK60A0
148M50
SIA
LMK60E0
156257
SIA
LMK60E0
156257
SIA
LMK60E2
150M00
SIA
LMK60E2
150M00
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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