LMK61PD0A2-SIAT [TI]
±50ppm、超低抖动、引脚可选、差动振荡器 | SIA | 8 | -40 to 85;
| 型号： | LMK61PD0A2-SIAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ±50ppm、超低抖动、引脚可选、差动振荡器 | SIA | 8 | -40 to 85 振荡器 |
| 文件： | 总27页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMK61PD0A2
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
LMK61PD0A2 超低抖动引脚可选振荡器
1 特性
2 应用
1
•
超低噪声、高性能
•
晶体振荡器、表面声波 (SAW) 振荡器或芯片振荡
器的高性能替换产品
–
抖动：fOUT > 100MHz 时的典型值为 90fs
•
开关、路由器、网卡、基带装置 (BBU)、服务器、
存储/SAN
(RMS)
–
高电源抑制比 (PSRR)：-70dBc，出色的电源抗
扰度
•
•
•
测试和测量
医疗成像
•
灵活的输出频率和格式；用户可选择
现场可编程门阵列 (FPGA)，处理器连接
–
频率：62.5MHz、100MHz、106.25MHz、
125MHz、156.25MHz、212.5MHz、312.5MHz
3 说明
–
格式：低电压正射极耦合逻辑 (LVPECL)、低压
差分信令 (LVDS) 或高速收发器逻辑 (HSTL)
LMK61PD0A2 是一款超低抖动的 PLLatinumTM 引脚
可选振荡器。该振荡器可生成通用基准时钟。 该器件
在出厂前进行了预编程，可支持七种不同基准时钟频
率。相应频率可通过将每个 FS[1:0] 配置为 VDD、
GND 或 NC（无连接）进行选择。 输出格式可通过将
操作系统 (OS) 的引脚配置为 VDD、GND 或 NC 进行
选择，三种配置方式分别对应格式 LVPECL、LVDS
以及 HCSL。 内部电源调节功能提供出色的电源纹波
抑制 (PSRR)，降低了供电网络的成本和复杂性。 该
器件由单个 3.3V ± 5% 电源供电。
•
•
总频率容差：±50ppm
内部存储器存储了多个启动配置，可通过引脚控制
进行选择
•
•
•
3.3V 工作电压
工业温度范围（-40ºC 至 +85ºC）
7mm x 5mm 8 引脚封装
器件信息(1)
部件号
封装
封装尺寸（标称值）
LMK61PD0A2
8 引脚 QFM (SIA)
7.0mm x 5.0mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
引脚分布和简化框图
FS1
7
Power Conditioning
OE
OS
1
2
3
6
5
4
VDD
Output
Divider
Output
Buffer
Integrated
Oscillator
PLL
OUTN
OUTP
GND
Interface
ROM (Pin Control)
8
FS0
LMK61PD0A2
Ultra-high performance oscillator
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS675
LMK61PD0A2
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
目录
7.15 Additional Reliability and Qualification.................... 9
7.16 Typical Performance Characteristics .................... 10
Parameter Measurement Information ................ 11
8.1 Device Output Configurations ................................. 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Control........................................................ 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics - Power Supply ................. 6
7.6 LVPECL Output Characteristics................................ 6
7.7 LVDS Output Characteristics .................................... 6
7.8 HCSL Output Characteristics.................................... 7
7.9 OE Input Characteristics........................................... 7
7.10 OS, FS[1:0] Input Characteristics ........................... 7
7.11 Frequency Tolerance Characteristics ..................... 7
7.12 Power-On/Reset Characteristics (VDD).................. 8
7.13 PSRR Characteristics ............................................. 8
7.14 PLL Clock Output Jitter Characteristics .................. 9
8
9
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 14
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
13 器件和文档支持 ..................................................... 19
13.1 社区资源................................................................ 19
13.2 商标....................................................................... 19
13.3 静电放电警告......................................................... 19
13.4 Glossary................................................................ 19
14 机械、封装和可订购信息....................................... 19
4 修订历史记录
Changes from Original (October 2015) to Revision A
Page
•
“产品预览”至“量产数据”........................................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
LMK61PD0A2
www.ti.com.cn
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
5 Device Control
Table 1. Output Frequency Mapping for FS[1:0] Selection
FS1
0
FS0
0
OUT FREQUENCY (MHz)
RELEVANT STANDARDS
PCI Express
100
0
NC
1
312.5
10 Gbps Ethernet
1 Gbps Ethernet
Fiber Channel
10 Gbps Ethernet
Fiber Channel
1 Gbps Ethernet
n/a
0
125
NC
NC
NC
1
0
106.25
156.25
212.5
NC
1
0
62.5
1
NC
1
Reserved
Reserved
1
n/a
Table 2. Output Type Mapping for OS, OE Selection
OS
X
OE
0
OUTPUT TYPE
Disabled (PLL functional)
0
1
LVPECL
LVDS
NC
1
1
1
HCSL
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LMK61PD0A2
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
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6 Pin Configuration and Functions
SIA Package
8 pin QFM
FS1
7
OE
OS
1
6
5
4
VDD
2
3
OUTN
OUTP
GND
8
FS0
Table 3. Pin Functions
PIN
I/O
DESCRIPTION
NAME
POWER
GND
NO.
3
6
Ground
Analog
Device Ground.
3.3 V Power Supply.
VDD
OUTPUT BLOCK
OUTP,
OUTN
4, 5
Universal
Differential Output Pair (LVPECL, LVDS or HCSL).
DIGITAL CONTROL / INTERFACES
FS[1:0]
OE
7, 8
1
LVCMOS
LVCMOS
LVCMOS
Output Frequency Select. Refer toTable 1.
Output Enable (internal pullup). Refer toTable 2.
Output Type Select. Refer toTable 2.
OS
3
4
Copyright © 2015, Texas Instruments Incorporated
LMK61PD0A2
www.ti.com.cn
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
MAX
3.6
UNIT
V
VDD
VIN
Device Supply Voltage
Output Voltage Range for Logic Inputs
Output Voltage Range for Clock Outputs
Junction Temperature
VDD + 0.3
VDD + 0.3
150
V
VOUT
TJ
V
°C
°C
TSTG
Storage Temperature
-40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
-40
NOM
3.3
MAX
3.465
85
UNIT
V
VDD
TA
Device Supply Voltage
Ambient Temperature
Junction Temperature
VDD Power-Up Ramp Time
25
°C
TJ
125
°C
tRAMP
0.1
100
ms
7.4 Thermal Information
(2) (3) (4)
LMK61PD0A2
QFM (SIA)
8 PINS
THERMAL METRIC(1)
UNIT
Airflow (LFM) 0
Airflow (LFM) 200
Airflow (LFM) 400
RθJA
Junction-to-ambient thermal resistance
54
34
44
n/a
41.2
n/a
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
36.7
11.2
36.7
n/a
n/a
n/a
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.9
37.8
n/a
21.9
38.9
n/a
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The package thermal resistance is calculated on a 4 layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations
section for more information on ensuring good system reliability and quality.
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7.5 Electrical Characteristics - Power Supply(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
Device Current Consumption LVPECL(2)
TEST CONDITIONS
MIN
TYP
162
152
155
136
MAX
208
196
196
UNIT
IDD
mA
LVDS
HCSL
IDD-PD
Device Current Consumption OE = GND
when output is disabled
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.
7.6 LVPECL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
Output Frequency(2)
TEST CONDITIONS
MIN
62.5
700
TYP
MAX
312.5
1200
UNIT
MHz
mV
fOUT
VOD
Output Voltage Swing
800
2 x
(2)
(VOH - VOL
)
VOUT, DIFF, PP Differential Output Peak-to-
Peak Swing
V
V
|VOD
|
VOS
Output Common Mode
Voltage
VDD –
1.55
tR / tF
PN-Floor
ODC
Output Rise/Fall Time (20% to
80%)(3)
120
200
ps
Output Phase Noise Floor
(fOFFSET > 10 MHz)
Output Duty Cycle(3)
156.25 MHz
-165
dBc/Hz
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.
7.7 LVDS Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
Output Frequency(1)
TEST CONDITIONS
MIN
62.5
300
TYP
MAX
312.5
480
UNIT
MHz
mV
fOUT
VOD
Output Voltage Swing
390
2 x
(1)
(VOH - VOL
)
VOUT, DIFF, PP Differential Output Peak-to-
Peak Swing
V
V
|VOD
|
VOS
Output Common Mode
Voltage
1.2
tR / tF
Output Rise/Fall Time (20% to
80%)(2)
150
250
ps
PN-Floor
Output Phase Noise Floor
(fOFFSET > 10 MHz)
Output Duty Cycle(2)
156.25 MHz
-162
125
dBc/Hz
ODC
ROUT
45%
55%
Differential Output Impedance
Ohm
(1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(2) Ensured by characterization.
6
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ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
7.8 HCSL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
62.5
600
TYP
MAX
312.5
850
UNIT
MHz
mV
fOUT
Output Frequency
Output High Voltage
Output Low Voltage
VOH
VOL
-100
250
100
mV
VCROSS
Absolute Crossing
Voltage(2)(3)
475
mV
(2)(3)
VCROSS-DELTA Variation of VCROSS
0
140
2
mV
V/ns
dV/dt
Slew Rate(4)
0.8
PN-Floor
Output Phase Noise Floor
(fOFFSET > 10 MHz)
100 MHz
-164
dBc/Hz
ODC
Output Duty Cycle(4)
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
(3) Ensured by design.
(4) Ensured by characterization.
7.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
1.4
0.6
40
40
V
VIH = VDD
VIL = GND
-40
-40
uA
uA
pF
IIL
CIN
2
7.10 OS, FS[1:0] Input Characteristics
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
1.4
0.4
40
40
V
VIH = VDD
VIL = GND
-40
-40
uA
uA
pF
IIL
CIN
2
7.11 Frequency Tolerance Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fT
Total Frequency Tolerance
All output formats, frequency bands and
device junction temperature up to 125°C;
includes initial freq tolerance, temperature &
supply voltage variation, solder reflow and
aging (10 years)
-50
50
ppm
(1) Ensured by characterization.
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7.12 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.95
0.1
UNIT
V
VTHRESH
VDROOP
tSTARTUP
Threshold Voltage(1)
Allowable Voltage Droop(2)
2.72
V
(1)
Startup Time
Time elapsed from VDD at 3.135 V to output
enabled
10
ms
tOE-EN
tOE-DIS
Output enable time(2)
Output disable time(2)
Time elapsed from OE at VIH to output enabled
Time elapsed from OE at VIL to output disabled
50
50
us
us
(1) Ensured by characterization.
(2) Ensured by design.
7.13 PSRR Characteristics(1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER
TEST CONDITIONS
Sine wave at 50 kHz
MIN
TYP
-70
-70
-70
-70
MAX
UNIT
PSRR
Spurs Induced by 50 mV
Power Supply Ripple(2)(3) at
156.25 MHz output, all
output types
dBc
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
(3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
8
Copyright © 2015, Texas Instruments Incorporated
LMK61PD0A2
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ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
7.14 PLL Clock Output Jitter Characteristics(1)(2)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
OUT ≥ 100 MHz, All output frequencies and
output types
MIN
TYP
MAX
UNIT
RJ
RJ
RMS Phase Jitter(3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
f
100
200
fs RMS
RMS Phase Jitter(3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
fOUT = 62.5 MHz, All output frequencies and
output types
200
400
fs RMS
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
(3) Ensured by characterization.
7.15 Additional Reliability and Qualification
PARAMETER
CONDITION / TEST METHOD
MIL-STD-202, Method 213
MIL-STD-202, Method 204
J-STD-020, MSL3
Mechanical Shock
Mechanical Vibration
Moisture Sensitivity Level
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7.16 Typical Performance Characteristics
Figure 1. Phase Noise of LVPECL Differential Output at
156.25 MHz with FS[1:0] = NC, NC, OS = GND
Figure 2. Phase Noise of LVDS Differential Output at 156.25
MHz with FS[1:0] = NC, NC, OS = NC
1.8
1.75
1.7
1.65
1.6
1.55
1.5
0
50
100
150
200
250
300
350
Output Frequency (MHz)
D016
Figure 4. LVPECL Differential Output Swing vs Frequency
Figure 3. Phase Noise of HCSL Differential Output at 156.25
MHz with FS[1:0] = NC, NC, OS = VDD
0.95
1.48
1.47
1.46
1.45
1.44
1.43
1.42
0.9
0.85
0.8
0.75
0.7
0
50
100
150
200
250
300
350
0
50
100
150
200
250
300
350
Output Frequency (MHz)
Output Frequency (MHz)
D017
D018
Figure 5. LVDS Differential Output Swing vs Frequency
Figure 6. HCSL Differential Output Swing vs Frequency
10
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ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
8 Parameter Measurement Information
8.1 Device Output Configurations
High impedance differential probe
LVPECL
LMK61PD0A2
Oscilloscope
150 ꢀ
150 ꢀ
Figure 7. LVPECL Output DC Configuration during Device Test
High impedance differential probe
LMK61PD0A2
LVDS
Oscilloscope
Figure 8. LVDS Output DC Configuration during Device Test
High impedance differential probe
HCSL
LMK61PD0A2
Oscilloscope
50 ꢀ
50 ꢀ
Figure 9. HCSL Output DC Configuration during Device Test
Phase Noise/
Balun/
Buffer
Spectrum
Analyzer
LMK61PD0A2
LVPECL
150 ꢀ
150 ꢀ
Figure 10. LVPECL Output AC Configuration during Device Test
Phase Noise/
Balun/
Buffer
LMK61PD0A2
Spectrum
Analyzer
LVDS
Figure 11. LVDS Output AC Configuration during Device Test
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Device Output Configurations (continued)
Phase Noise/
Spectrum
Analyzer
Balun/
Buffer
LMK61PD0A2
HCSL
50 ꢀ
50 ꢀ
Figure 12. HCSL Output AC Configuration during Device Test
Sine wave
Modulator
Power Supply
Phase Noise/
LMK61PD0A2
Spectrum
Analyzer
Balun
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
Figure 13. PSRR Test Setup
OUT_P
OUT_N
VOD
80%
VOUT,DIFF,PP = 2 x VOD
0 V
20%
tR
tF
Figure 14. Differential Output Voltage and Rise/Fall Time
12
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ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
9 Detailed Description
9.1 Overview
The LMK61PD0A2 is a pin selectable oscillator that generates commonly used reference clocks, greater than
100 MHz, with less than 200 fs, rms max random jitter.
9.2 Functional Block Diagram
VDD
Power Conditioning
PLL
Integrated
Oscillator
Output
XO
LVPECL
or LVDS
or HCSL
Integer Div
¥
Control
N Div
FS1
FS0
OS
3
3
3
∑û fractional
ROM
(Pin Control)
OE
GND
3
= tri-state
NOTE
Control blocks are compatible with 1.8/2.5/3.3 V I/O voltage levels.
9.3 Feature Description
9.3.1 Device Block-Level Description
The LMK61PD0A2 comprises of an integrated oscillator that includes a 50 MHz crystal, a fractional PLL with
integrated VCO. Completing the device is the combination of an integer output divider and a universal differential
output buffer. The on-chip ROM contains seven pre-programmed output frequency plans that selects the
appropriate settings for the integrated oscillator, PLL blocks and output divider. Table 1 lists the supported output
frequency plans that can be selected by pin-strapping FS[1:0] as required. Table 2 lists the supported output
types that can be selected by pin-strapping OS and OE as required. The device is powered by on-chip low
dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive
analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs
provide isolation from any noise in the external power supply rail with a PSRR of better than -70 dBc at 50 kHz to
1 MHz ripple frequencies at 3.3 V device supply.
9.3.2 Device Configuration Control
The LMK61PD0A2 selects an output frequency plan and output type using control pins FS[1:0].
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The LMK61PD0A2 is an ultra-low jitter pin selectable oscillator that can be used to provide reference clocks for
high-speed serial links resulting in improved system performance.
10.2 Typical Application
10.2.1 Jitter Considerations in Serdes Systems
Jitter-sensitive applications such as 10 Gbps or 100 Gbps Ethernet, deploy a serial link utilizing a Serializer in the
transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically
embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of
the TX PLL bandwidth and the RX CDR bandwidth.
As can be seen in Figure 15, the pass band region between the TX low pass cutoff and RX high pass cutoff
frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of
the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec
or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR
bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC
or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification
that needs to be met, as related to the RX CDR bandwidth.
The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example,
IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10 Gbps Ethernet should be no more than
0.28 * UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.
The jitter contributing elements are made up of the reference clock, generated potentially from a device like
LMK61PD0A2, the transmit medium, transmit driver etc. Only a portion of the overall allowable transmit jitter is
allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a 20%
clock jitter budget, is 5.43 ps, p-p.
Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or
mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other
uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout
buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern
fanout buffers have low additive random jitter (less than 100 fs, rms) with no substantial contribution to the
deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the
primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is
to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This
amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For
serial link systems that need to meet a bit error rate (BER) of 10-12, the allowable random jitter in root-mean-
square is 0.29 ps, rms. This is calculated by dividing the p-p jitter by 14 for a BER of 10-12. Accounting for
random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps, rms. This is
calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100
fs, rms of additive jitter from the fanout buffer.
With careful frequency planning techniques, like spur optimization (covered in the Spur Mitigation Techniques
section) and on-chip LDOs to suppress supply noise, the LMK61PD0A2 is able to generate clock outputs with
deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps, rms. This gives the serial link
system with additional margin on the allowable transmit jitter resulting in a BER better than 10-12
.
14
Copyright © 2015, Texas Instruments Incorporated
LMK61PD0A2
www.ti.com.cn
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
Typical Application (continued)
TX
RX
Parallel
Serializer
Data
Parallel
Sampler
Data
Serialized clock/data
Recovered
Clock
TX PLL
Ref Clk
CDR
Deserializer
Jitter Transfer (on clock)
Jitter Tolerance (on data)
Jitter Transfer (on clock)
F1 = TX_PLL_BWmax
F2 = RX_CDR_BWmin
F2 = RX_CDR_BWmin
Jitter Tolerance (on data)
F2
SoC trend:
Increase stop band
Less % of jitter budget
Jitter Transfer (on clock)
F2
F1
SoC trend:
Decrease stop band
Improved LO design
Figure 15. Dependence of Clock Jitter in Serial Links
Copyright © 2015, Texas Instruments Incorporated
15
LMK61PD0A2
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
11 Power Supply Recommendations
For best electrical performance of LMK61PD0A2, it is preferred to utilize a combination of 10 uF, 1 uF and 0.1 uF
on its power supply bypass network. It is also recommended to utilize component side mounting of the power
supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep
the connections between the bypass capacitors and the power supply on the device as short as possible. Ground
the other side of the capacitor using a low impedance connection to the ground plane. Figure 16 shows the
layout recommendation for power supply decoupling of LMK61PD0A2.
16
Copyright © 2015, Texas Instruments Incorporated
LMK61PD0A2
www.ti.com.cn
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
12 Layout
12.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK61PD0A2 to ensure good thermal / electrical performance and overall signal integrity
of entire system.
12.1.1 Ensuring Thermal Reliability
The LMK61PD0A2 is a high performance device. Therefore careful attention must be paid to device configuration
and printed circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected
to the ground plane of the PCB through three vias or more, as shown in Figure 16, to maximize thermal
dissipation out of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK61PD0A2 and its junction
temperature.
TB = TJ – ΨJB * P
where
•
•
•
•
TB: PCB temperature around the LMK61PD0A2
TJ: Junction temperature of LMK61PD0A2
ΨJB: Junction-to-board thermal resistance parameter of LMK61PD0A2 (36.7°C/W without airflow)
P: On-chip power dissipation of LMK61PD0A2
(1)
In order to ensure that the maximum junction temperature of LMK61PD0A2 is below 125°C, it can be calculated
that the maximum PCB temperature without airflow should be at 100°C or below when the device is optimized for
best performance resulting in maximum on-chip power dissipation of 0.68 W.
12.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61PD0A2, it is recommended to
route vias into decoupling capacitors and then into the LMK61PD0A2. It is also recommended to increase the via
count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for
high frequency current flow. Figure 16 shows the layout recommendation for LMK61PD0A2.
Figure 16. LMK61PD0A2 Layout Recommendation for Power Supply and Ground
版权 © 2015, Texas Instruments Incorporated
17
LMK61PD0A2
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
Layout Guidelines (接下页)
12.1.3 Recommended Solder Reflow Profile
It is recommended to follow the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61PD0A2
to be processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
18
版权 © 2015, Texas Instruments Incorporated
LMK61PD0A2
www.ti.com.cn
ZHCSEB9A –OCTOBER 2015–REVISED NOVEMBER 2015
13 器件和文档支持
13.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 商标
E2E is a trademark of Texas Instruments.
13.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK61PD0A2-SIAR
LMK61PD0A2-SIAT
ACTIVE
QFM
QFM
SIA
8
8
2500 RoHS & Green
250 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LMK61
PD0A2
ACTIVE
SIA
NIAU
LMK61
PD0A2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK61PD0A2-SIAR
LMK61PD0A2-SIAT
QFM
QFM
SIA
SIA
8
8
2500
250
330.0
178.0
16.4
16.4
5.5
5.5
7.5
7.5
1.5
1.5
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK61PD0A2-SIAR
LMK61PD0A2-SIAT
QFM
QFM
SIA
SIA
8
8
2500
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
SIA0008B
QFM - 1.15 mm max height
S
C
A
L
E
1
.
9
0
0
QUAD FLAT MODULE
B
A
5±0.1
PIN 1 INDEX
AREA
7±0.1
4X
0.15 C
0.1 C
C
1.15 MAX
0.1 C
6X (0.15)
0.83
0.77
2X
2X (0.24)
8
4
4X (0.26)
3
2X
2.865
SYMM
6X
2X
5.08
4X
1.43
1.37
2.54
0.1
0.05
C A
C
B
6
1
7
1.03
0.97
6X
6X 1.85
SYMM
4221443/B 09/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
SIA0008B
QFM - 1.15 mm max height
QUAD FLAT MODULE
2X ( 0.8)
6X (1)
7
1
6
6X (1.4)
(2.865)
SYMM
4X (2.54)
4
3
8
(R0.05) TYP
SYMM
(3.7)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221443/B 09/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
SIA0008B
QFM - 1.15 mm max height
QUAD FLAT MODULE
2X ( 0.8)
12X (1)
7
6
1
12X (0.6)
2X
(2.865)
(R0.05) TYP
SYMM
4X (2.54)
4
3
(0.4) TYP
EXPOSED METAL
TYP
8
SYMM
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
PADS 1-3 & 4-6: 86%
SCALE:10X
4221443/B 09/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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