LMP2012MDR [TI]
Operational Amplifier;
| 型号： | LMP2012MDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Operational Amplifier 放大器 |
| 文件： | 总33页 (文件大小：1734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMP2011, LMP2012
SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier
1 Features
3 Description
The LMP201x series are the first members of TI's
new LMP™ precision amplifier family. The LMP201x
series offers unprecedented accuracy and stability in
space-saving miniature packaging, offered at an
affordable price. This device utilizes patented auto-
zero techniques to measure and continually correct
the input offset error voltage. The result is an
amplifier which is ultra-stable over time and
temperature. It has excellent CMRR and PSRR
ratings, and does not exhibit the familiar 1/f voltage
and current noise increase that plagues traditional
amplifiers. The combination of the LMP201x
characteristics makes it a good choice for transducer
amplifiers, high gain configurations, ADC buffer
amplifiers, DAC I-V conversion, and any other 2.7-V
to 5-V application requiring precision and long term
stability.
1
(For VS = 5 V, Typical Unless Otherwise Noted)
•
•
•
•
•
•
•
•
•
•
Low Ensured VOS Over Temperature 60 µV
Low Noise with No 1/f 35nV/√Hz
High CMRR 130 dB
High PSRR 120 dB
High AVOL 130 dB
Wide Gain-Bandwidth Product 3 MHz
High Slew Rate 4 V/µs
Low Supply Current 930 µA
Rail-to-Rail Output 30 mV
No External Capacitors Required
2 Applications
•
•
•
Precision Instrumentation Amplifiers
Thermocouple Amplifiers
Other useful benefits of the LMP201x are rail-to-rail
output, a low supply current of 930 µA, and wide
gain-bandwidth product of 3 MHz. These versatile
features found in the LMP201x provide high
performance and ease of use.
Strain Gauge Bridge Amplifier
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
2.90 mm × 1.60 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SOIC (8)
LMP2011
SOT-23 (5)
SOIC (8)
LMP2012
VSSOP (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Bridge Amplifier
Offset Voltage vs Common Mode Voltage
5V
+
-
V
OUT
+
-
R1
R2
R2
R1
10k, 0.1%
2k, 1%
2k, 1%
10k, 0.1%
R3
20W
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP2011, LMP2012
SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
Power Supply Recommendations...................... 20
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: LMP2011 ................................ 4
6.5 Thermal Information: LMP2012 ................................ 5
6.6 2.7-V DC Electrical Characteristics........................... 5
6.7 2.7-V AC Electrical Characteristics........................... 6
6.8 5-V DC Electrical Characteristics.............................. 7
6.9 5-V AC Electrical Characteristics.............................. 8
6.10 Typical Characteristics............................................ 9
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1 Device Support .................................................... 22
11.2 Documentation Support ........................................ 22
11.3 Related Links ........................................................ 22
11.4 Community Resources.......................................... 22
11.5 Trademarks........................................................... 22
11.6 Electrostatic Discharge Caution............................ 22
11.7 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (March 2013) to Revision L
Page
•
Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
Changes from Revision J (March 2013) to Revision K
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
2
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LMP2011, LMP2012
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23 Single
Top View
D Package
8-Pin Single SOIC
Top View
1
8
b/ꢀ
N/C
2
3
4
-
7
6
5
+
-
V
V
IN
+
V
IN
V
OUT
+
-
b/ꢀ
V
Pin Functions: LMP2011
PIN
NO.
I/O
DESCRIPTION
NAME
DBV
D
3
2
1
5
8
6
4
7
-IN
4
3
-
O
I
Inverting input
+IN
N/C
N/C
N/C
OUT
V-
Non-Inverting input
-
No Internal Connection
No Internal Connection
No Internal Connection
Output
-
-
-
-
1
2
5
I
P
P
Negative (lowest) power supply
Positive (highest) power supply
V+
D or DGK Package
8-Pin Dual SOIC and VSSOP
Top View
Pin Functions: LMP2012
PIN
NO.
I/O
DESCRIPTION
NAME
D, DGK
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
2
3
6
5
1
7
4
8
I
I
Inverting input, channel A
Non-Inverting input, channel A
Inverting input, channel B
Non-Inverting input, channel B
Output, channel A
I
I
O
O
P
P
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
See
MIN
MAX
5.8
UNIT
V
Supply Voltage
Common-Mode Input Voltage
Lead Temperature (soldering 10 sec.)
Differential Input Voltage
Current at Input Pin
(V-) - 0.3
(V+) + 0.3
V
300
°C
±Supply Voltage
30
30
30
30
mA
mA
mA
°C
Current at Output Pin
Current at Power Supply Pin
Storage Temperature
50
30
−65
150
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical
Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.25
125
UNIT
V
Supply Voltage
2.7
Operating Temperature Range
−40
°C
6.4 Thermal Information: LMP2011
LMP2011
THERMAL METRIC(1)
D (SOIC)
8 PINS
119
DBV (SOT-23)
UNIT
5 PINS
164
116
28
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
66
60
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17
13
ψJB
59
27
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
6.5 Thermal Information: LMP2012
LMP2012
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
110
50
8 PINS
157
51
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
52
77
Junction-to-top characterization parameter
Junction-to-board characterization parameter
8
5
ψJB
51
75
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 2.7-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
TJ = 25°C
0.8
25
Input Offset Voltage
(LMP2011 only)
The temperature extremes
TJ = 25°C
60
μV
0.8
0.5
36
Input Offset Voltage
(LMP2012 only)
VOS
The temperature extremes
TJ = 25°C
60
10
Offset Calibration Time
ms
The temperature extremes
12
Input Offset Voltage
Long-Term Offset Drift
Lifetime VOS Drift
Input Current
0.015
0.006
2.5
-3
μV/°C
μV/month
μV
TCVOS
IIN
pA
IOS
Input Offset Current
6
pA
Input Differential
Resistance
9
RIND
MΩ
TJ = 25°C
95
90
130
Common Mode Rejection −0.3 ≤ VCM ≤ 0.9 V,
CMRR
dB
The temperature
extremes
Ratio
0 ≤ VCM ≤ 0.9 V
TJ = 25°C
95
90
95
90
120
130
Power Supply Rejection
Ratio
PSRR
dB
dB
The temperature extremes
TJ = 25°C
RL = 10 kΩ
The temperature
extremes
AVOL
Open Loop Voltage Gain
TJ = 25°C
90
85
124
RL = 2 kΩ
The temperature
extremes
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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2.7-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
MIN(1)
2.665
2.655
TYP(2)
MAX(1)
UNIT
TJ = 25°C
2.68
The temperature
extremes
RL = 10 kΩ to 1.35 V,
VIN(diff) = ±0.5 V
V
TJ = 25°C
0.033
2.65
0.061
2.68
0.033
2.65
0.061
12
0.060
0.075
The temperature
extremes
Output Swing
(LMP2011 only)
TJ = 25°C
2.630
2.615
The temperature
extremes
RL = 2 kΩ to 1.35 V,
VIN(diff) = ±0.5 V
V
V
V
TJ = 25°C
0.085
0.105
The temperature
extremes
VO
TJ = 25°C
2.64
2.63
The temperature
extremes
RL = 10 kΩ to 1.35 V,
VIN(diff) = ±0.5 V
TJ = 25°C
0.060
0.075
The temperature
extremes
Output Swing
(LMP2012 only)
TJ = 25°C
2.615
2.6
The temperature
extremes
RL = 2 kΩ to 1.35 V,
VIN(diff) = ±0.5 V
TJ = 25°C
0.085
0.105
The temperature
extremes
TJ = 25°C
5
3
Sourcing, VO = 0 V,
VIN(diff) = ±0.5 V
The temperature
extremes
IO
Output Current
mA
mA
TJ = 25°C
5
3
18
VIN(diff) = ±0.5 V,
Sinking, VO = 5 V
The temperature
extremes
TJ = 25°C
0.919
1.20
1.50
Supply Current per
Channel
IS
The temperature extremes
6.7 2.7-V AC Electrical Characteristics
TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
GBW
SR
Gain-Bandwidth Product
Slew Rate
3
4
MHz
V/μs
Deg
θ m
Gm
Phase Margin
60
Gain Margin
−14
35
dB
en
Input-Referred Voltage Noise
Input-Referred Voltage Noise
Input Overload Recovery Time
nV/√Hz
nVpp
ms
enp-p
trec
RS = 100 Ω, DC to 10 Hz
850
50
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
6
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
6.8 5-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V, V CM = 2.5 V, VO = 2.5 V, and RL > 1MΩ.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
TJ = 25°C
0.12
25
Input Offset Voltage
(LMP2011 only)
The temperature extremes
TJ = 25°C
60
μV
0.12
0.5
36
Input Offset Voltage
(LMP2012 only)
VOS
The temperature extremes
TJ = 25°C
60
10
Offset Calibration Time
ms
The temperature extremes
12
Input Offset Voltage
Long-Term Offset Drift
Lifetime VOS Drift
Input Current
0.015
0.006
2.5
-3
μV/°C
μV/month
μV
TCVOS
IIN
pA
IOS
Input Offset Current
6
pA
Input Differential
Resistance
9
RIND
MΩ
TJ = 25°C
The temperature extremes
100
90
130
120
Common Mode
Rejection Ratio
−0.3 ≤ VCM ≤ 3.2,
0 ≤ VCM ≤ 3.2
CMRR
dB
TJ = 25°C
95
Power Supply Rejection
Ratio
PSRR
AVOL
dB
dB
The temperature extremes
90
TJ = 25°C
105
100
95
130
RL = 10 kΩ
RL = 2 kΩ
The temperature extremes
TJ = 25°C
Open Loop Voltage
Gain
132
The temperature extremes
TJ = 25°C
90
4.96
4.95
4.978
0.040
4.919
0.091
4.978
0.040
4.919
0.0.91
15
The temperature extremes
TJ = 25°C
RL = 10 kΩ to 2.5 V,
VIN(diff) = ±0.5 V
V
V
V
V
0.070
0.085
The temperature extremes
TJ = 25°C
Output Swing
(LMP2011 only)
4.895
4.875
The temperature extremes
TJ = 25°C
RL = 2 kΩ to 2.5 V,
VIN(diff) = ±0.5 V
0.115
0.140
The temperature extremes
TJ = 25°C
VO
4.92
4.91
The temperature extremes
TJ = 25°C
RL = 10 kΩ to 2.5 V,
VIN(diff) = ±0.5 V
0.080
0.095
The temperature extremes
TJ = 25°C
Output Swing
(LMP2012 only)
4.875
4.855
The temperature extremes
TJ = 25°C
RL = 2 kΩ to 2.5 V,
VIN(diff) = ±0.5 V
0.125
0.150
The temperature extremes
TJ = 25°C
8
6
8
6
Sourcing, VO = 0 V,
VIN(diff) = ±0.5 V
The temperature extremes
TJ = 25°C
IO
Output Current
mA
mA
17
Sinking, VO = 5 V,
VIN(diff) = ±0.5 V
The temperature extremes
TJ = 25°C
0.930
1.20
1.50
Supply Current per
Channel
IS
The temperature extremes
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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6.9 5-V AC Electrical Characteristics
TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2.5 V, VO = 2.5 V, and RL > 1MΩ.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
3
MAX(1)
UNIT
MHz
V/μs
deg
GBW
SR
Gain-Bandwidth Product
Slew Rate
4
θ m
Gm
Phase Margin
60
Gain Margin
−15
35
dB
en
Input-Referred Voltage Noise
Input-Referred Voltage Noise
Input Overload Recovery Time
nV/√Hz
nVpp
ms
enp-p
trec
RS = 100 Ω, DC to 10 Hz
850
50
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
8
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
6.10 Typical Characteristics
TA=25C, VS= 5 V unless otherwise specified.
Figure 1. Supply Current vs Supply Voltage
Figure 2. Offset Voltage vs Supply Voltage
Figure 3. Offset Voltage vs Common Mode
Figure 4. Offset Voltage vs Common Mode
500
10000
V
= 5V
V = 5V
S
S
400
300
200
100
0
1000
100
10
-100
-200
-300
-400
-500
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
0.1
1M
1k
10k 100k
1
10
100
V
CM
FREQUENCY (Hz)
Figure 5. Voltage Noise vs Frequency
Figure 6. Input Bias Current vs Common Mode
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
120
120
100
80
V
V
= 2.7V
V
= 5V
S
S
= 1V
V = 2.5V
CM
CM
100
80
b9D!ÇLë9
b9D!ÇLë9
60
60
40
40
th{LÇLë9
th{LÇLë9
20
0
20
0
10
100
1k
FREQUENCY (Hz)
Figure 7. PSRR vs Frequency
10k 100k
1M
10M
10
100
1k
FREQUENCY (Hz)
Figure 8. PSRR vs Frequency
10k 100k
1M
10M
Figure 9. Output Sourcing at 2.7 V
Figure 10. Output Sourcing at 5 V
Figure 11. Output Sinking at 2.7 V
Figure 12. Output Sinking at 5 V
10
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
Figure 13. Maximum Output Swing vs Supply Voltage
Figure 14. Maximum Output Swing vs Supply Voltage
Figure 15. Minimum Output Swing vs Supply Voltage
Figure 16. Minimum Output Swing vs Supply Voltage
100
150.0
140
V
S
= 5V
V
= 5V
S
120
100
80
120.0
tI!{9
V
= 5V
S
60
40
20
0
90.0
60.0
80
60
40
20
0
D!Lb
30.0
0.0
R
C
= 1M
L
L
V
= 2.7V
S
= < 20pF
= 2.7V OR 5V
V
S
-30.0
10M
-20
100k
FREQUENCY (Hz)
Figure 18. Open Loop Gain and Phase vs Supply Voltage
1M
100
1k
10k
10
100
FREQUENCY (Hz)
Figure 17. CMRR vs Frequency
1k
100k
100k
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
100
100
80
150.0
120.0
150.0
R
= >1M
L
80
120.0
tI!{9
tI!{9
R
L
= 2k
60
40
20
0
60
40
20
0
90.0
60.0
90.0
60.0
R
= >1M
L
D!Lb
R
= >1M
L
R
= >1M
L
D!Lb
30.0
0.0
30.0
0.0
V
= 5V
V
= 2.7V
S
S
R
= 2k
L
C
= < 20 pF
= >1M & 2k
C
= < 20 pF
L
L
L
L
R
L
= 2k
R
R
= >1M & 2k
-30.0
-30.0
-20
-20
100k
100k
FREQUENCY (Hz)
Figure 20. Open Loop Gain and Phase vs RL at 5 V
100
1k
10k
1M
10M
100
1k
10k
1M
10M
FREQUENCY (Hz)
Figure 19. Open Loop Gain and Phase vs RL at 2.7 V
100
150.0
100
150.0
10pF
10pC
80
120.0
80
60
40
20
0
120.0
90.0
60.0
tI!{9
tI!{9
10pC
60
40
20
0
90.0
60.0
10pF
500pF
500pC
D!Lb
D!Lb
30.0
0.0
30.0
0.0
V
= 2.7V, R = >1M
L
S
V
= 5V, R = >1M
L
S
500pC
C
L
= 10,50,200 & 500pF
500pF
C
= 10,50,200 & 500pF
L
-30.0
-20
-20
-30.0
100
10M
100k
FREQUENCY (Hz)
Figure 21. Open Loop Gain and Phase vs CL at 2.7 V
1k
10k
FREQUENCY (Hz)
1M
100
1k
10k
1M
10M
100k
Figure 22. Open Loop Gain and Phase vs CL at 5 V
113
90
68
45
23
0
113
90
68
45
23
0
100
80
60
40
20
0
100
80
60
40
20
0
tI!{9
tI!{9
-40°/
-40°/
-40°/
-40°/
D!Lb
D!Lb
25°/
25°/
85°/
85°/
85°/
85°/
V
V
= 2.7V
V
= 5V
S
S
= 200 mV
PP
V
= 200 mV
PP
OUT
OUT
R
= >1M
R
= >1M
L
L
L
L
C
= < 20 pF
C
= < 20pF
-23
-23
-20
-20
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Open Loop Gain and Phase vs Temperature
at 2.7 V
Figure 24. Open Loop Gain and Phase vs Temperature
at 5 V
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
10
10
MEAS FREQ = 1 KHz
V
= 2 V
PP
OUT
MEAS BW = 500 kHz
MEAS BW = 22 KHz
R
= 10k
= +10
L
R
= 10k
= +10
L
A
V
A
V
1
0.1
V = 2.7V
S
1
V
S
= 2.7V
V
= 5V
S
0.1
0.01
V
S
= 5V
V
S
= 5V
V
= 2.7V
100
S
0.01
0.1
1
10
10
1k
10k
100k
OUTPUT VOLTAGE (V
)
PP
FREQUENCY (Hz)
Figure 26. THD+N vs Frequency
Figure 25. THD+N vs AMPL
1 sec/DIV
Figure 27. 0.1 Hz − 10 Hz Noise vs Time
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7 Detailed Description
7.1 Overview
The LMP201x series offers unprecedented accuracy and stability in space-saving miniature packaging while also
being offered at an affordable price. This device utilizes patented techniques to measure and continually correct
the input offset error voltage. The result is an amplifier which is ultra stable over time and temperature.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 How the LMP201x Works
The LMP201x uses new, patented auto-zero techniques to achieve the high DC accuracy traditionally associated
with chopper-stabilized amplifiers without the major drawbacks produced by chopping. The LMP201x
continuously monitors the input offset and corrects this error.
The conventional low-frequency chopping process produces many mixing products, both sums and differences,
between the chopping frequency and the incoming signal frequency. This mixing causes large amounts of
distortion, particularly when the signal frequency approaches the chopping frequency. Even without an incoming
signal, the chopper harmonics mix with each other to produce even more trash. If this sounds unlikely or difficult
to understand, look at the plot (Figure 28), of the output of a typical (MAX432) chopper-stabilized op amp. This is
the output when there is no incoming signal, just the amplifier in a gain of -10 with the input grounded. The
chopper is operating at about 150 Hz; the rest is mixing products. Add an input signal and the noise gets much
worse.
Compare this plot with Figure 29 of the LMP201x. This data was taken under the exact same conditions. The
auto-zero action is visible at about 30 kHz but note the absence of mixing products at other frequencies. As a
result, the LMP201x has very low distortion of 0.02% and very low mixing products.
10000
V
= 5V
S
1000
100
10
0.1
1M
1k
10k 100k
1
10
100
FREQUENCY (Hz)
Figure 28. The Output of a Chopper Stabilized Op Amp
(MAX432)
Figure 29. The Output of the LMP2011/LMP2012
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Feature Description (continued)
7.3.2 The Benefits of LMP201x: No 1/F Noise
Using patented methods, the LMP201x eliminates the 1/f noise present in other amplifiers. This noise, which
increases as frequency decreases, is a major source of measurement error in all DC-coupled measurements.
Low-frequency noise appears as a constantly-changing signal in series with any measurement being made. As a
result, even when the measurement is made rapidly, this constantly-changing noise signal will corrupt the result.
The value of this noise signal can be surprisingly large. For example: If a conventional amplifier has a flat-band
noise level of 10 nV/√Hz and a noise corner of 10 Hz, the RMS noise at 0.001 Hz is 1 µV/√Hz. This is equivalent
to a 0.50-µV peak-to-peak error, in the frequency range 0.001 Hz to 1.0 Hz. In a circuit with a gain of 1000, this
produces a 0.50-mV peak-to-peak output error. This number of 0.001 Hz might appear unreasonably low, but
when a data acquisition system is operating for 17 minutes, it has been on long enough to include this error. In
this same time, the LMP201x will only have a 0.21-mV output error. This is smaller by 2.4×. This 1/f error gets
even larger at lower frequencies. At the extreme, many people try to reduce this error by integrating or taking
several samples of the same signal. This is also doomed to failure because the 1/f nature of this noise means
that taking longer samples just moves the measurement into lower frequencies where the noise level is even
higher.
The LMP201x eliminates this source of error. The noise level is constant with frequency so that reducing the
bandwidth reduces the errors caused by noise.
7.3.3 No External Capacitors Required
The LMP201x does not need external capacitors. This eliminates the problems caused by capacitor leakage and
dielectric absorption, which can cause delays of several seconds from turn-on until the amplifier's error has
settled.
7.3.4 Copper Leadframe
Another source of error that is rarely mentioned is the error voltage caused by the inadvertent thermocouples
created when the common Kovar type IC package lead materials are soldered to a copper printed circuit board.
These steel-based leadframe materials can produce over 35 μV/°C when soldered onto a copper trace. This can
result in thermocouple noise that is equal to the LMP201x noise when there is a temperature difference of only
0.0014°C between the lead and the board!
For this reason, the lead-frame of the LMP201x is made of copper. This results in equal and opposite junctions
which cancel this effect. The extremely small size of the SOT-23 package results in the leads being very close
together. This further reduces the probability of temperature differences and hence decreases thermal noise.
7.3.5 More Benefits
The LMP201x offers the benefits mentioned above and more. It has a rail-to-rail output and consumes only 950
µA of supply current while providing excellent DC and AC electrical performance. In DC performance, the
LMP201x achieves 130 dB of CMRR, 120 dB of PSRR, and 130 dB of open loop gain. In AC performance, the
LMP201x provides 3 MHz of gain-bandwidth product and 4 V/µs of slew rate.
7.4 Device Functional Modes
7.4.1 Input Currents
The LMP201x input currents are different than standard bipolar or CMOS input currents. Due to the auto-zero
action of the input stage, the input current appears as a pulsating current at the chopping frequency (35 kHz)
flowing in one input and out the other. Under most operating conditions, these currents are in the picoamp level
and will have little or no effect in most circuits.
These currents tend to increase slightly when the common-mode voltage is near the minus supply. (See the
Typical Characteristics.) At high temperatures such as 85°C, the input currents become larger, 0.5 nA typical,
and are both positive except when the VCM is near V−. If operation is expected at low common-mode voltages
and high temperature, do not add resistance in series with the inputs to balance the impedances. Doing this can
cause an increase in offset voltage. A small resistance such as 1 kΩ can provide some protection against very
large transients or overloads, and will not increase the offset significantly.
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Device Functional Modes (continued)
Because of these issues, the LMV201x is not recommended for source impedances over 1MΩ.
7.4.2 Overload Recovery
The LMP201x recovers from input overload much faster than most chopper-stabilized op amps. Recovery from
driving the amplifier to 2X the full scale output, only requires about 40 ms. Many chopper-stabilized amplifiers will
take from 250 ms to several seconds to recover from this same overload. This is because large capacitors are
used to store the unadjusted offset voltage.
Figure 30. Overload Recovery Test Circuit
The wide bandwidth of the LMP201x enhances performance when it is used as an amplifier to drive loads that
inject transients back into the output. ADCs (Analog-to-Digital Converters) and multiplexers are examples of this
type of load. To simulate this type of load, a pulse generator producing a 1-V peak square wave was connected
to the output through a 10-pF capacitor. (Figure 30) The typical time for the output to recover to 1% of the
applied pulse is 80 ns. To recover to 0.1% requires 860 ns. This rapid recovery is due to the wide bandwidth of
the output stage and large total GBW.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV201x family offers excellent dc precision and ac performance. These devices offer true rail-to-rail output,
ultralow offset voltage and offset voltage drift over the entire –40 to 125°C temperature range, as well as 3-MHz
bandwidth and no 1/f noise. These features make the LMV201x a robust, high performance operational amplifier
ideal for industrial applications.
8.2 Typical Applications
8.2.1 Extending Supply Voltages and Output Swing with a Composite Amplifier
C2
R2
R7, 3.9k
+15V
1N4731A
(4.3V)
D1
C4
0.01
mF
R1
2
3
7
-
3
7
LMP201X
U1
+
Output
6
6
LM6171
U2
+
4
-15V
Input
2
-
4
R6
(-0.7V)
10k
+15V
(+2.5V)
R5, 1M
R3
C5
0.01 mF
20k
C3
0.01 mF
D2
1N4148
R4
3.9k
Figure 31. Inverting Composite Amplifier
Figure 32. Non-Inverting Composite Amplifier
8.2.1.1 Design Requirements
In cases where substantially higher output swing is required with higher supply voltages, arrangements like the
ones shown in Figure 31 and Figure 32 could be used. These configurations utilize the excellent DC performance
of the LMP201x while at the same time allow the superior voltage and frequency capabilities of the LM6171 to
set the dynamic performance of the overall amplifier.
For example, it is possible to achieve ±12-V output swing with 300 MHz of overall GBW (AV = 100) while keeping
the worst case output shift due to VOS less than 4 mV.
8.2.1.2 Detailed Design Procedure
The LMP201x output voltage is kept at about mid-point of its overall supply voltage, and its input common mode
voltage range allows the V- terminal to be grounded in one case (Figure 31, inverting operation) and tied to a
small non-critical negative bias in another (Figure 32, non-inverting operation). Higher closed-loop gains are also
possible with a corresponding reduction in realizable bandwidth. Table 1 shows some other closed loop gain
possibilities along with the measured performance in each case.
In terms of the measured output peak-to-peak noise, the following relationship holds between output noise
voltage, en p-p, for different closed-loop gain, AV, settings, where −3 dB Bandwidth is BW:
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Typical Applications (continued)
enpp1
AV 1
·
BW1
=
enpp2
BW2 AV 2
(1)
It should be kept in mind that in order to minimize the output noise voltage for a given closed-loop gain setting,
one could minimize the overall bandwidth. As can be seen from Equation 1 above, the output noise has a
square-root relationship to the Bandwidth.
In the case of the inverting configuration, it is also possible to increase the input impedance of the overall
amplifier, by raising the value of R1, without having to increase the feed-back resistor, R2, to impractical values,
by utilizing a "Tee" network as feedback. See the LMC6442 data sheet (Application Notes section) for more
details on this.
8.2.1.3 Application Results
Table 1 shows the results using various gains and compensation values.
Table 1. Composite Amplifier Measured Performance
R1
(Ω)
R2
(Ω)
C2
(pF)
BW
(MHz)
SR
(V/μs)
en p-p
AV
(mVPP
)
50
100
100
500
1000
200
100
1k
10k
10k
8
3.3
2.5
178
174
170
96
37
10
70
100k
100k
100k
0.67
1.75
2.2
3.1
70
200
100
1.4
250
400
0.98
64
8.2.2 Precision Strain-gauge Amplifier
5V
+
-
V
OUT
+
-
R1
10k, 0.1%
R2
2k, 1%
R2
R1
10k, 0.1%
2k, 1%
R3
20W
Figure 33. Precision Strain Gauge Amplifier
This Strain-Gauge amplifier (Figure 33) provides high gain (1006 or ~60 dB) with very low offset and drift. Using
the resistors' tolerances as shown, the worst case CMRR will be greater than 108 dB. The CMRR is directly
related to the resistor mismatch. The rejection of common-mode error, at the output, is independent of the
differential gain, which is set by R3. The CMRR is further improved, if the resistor ratio matching is improved, by
specifying tighter-tolerance resistors, or by trimming.
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8.2.3 ADC Input Amplifier
Figure 34. DC Coupled ADC Driver
The LMP201x is a great choice for an amplifier stage immediately before the input of an ADC (Analog-to-Digital
Converter). See Figure 34.
This is because of the following important characteristics:
•
Very low offset voltage and offset voltage drift over time and temperature allow a high closed-loop gain setting
without introducing any short-term or long-term errors. For example, when set to a closed-loop gain of 100 as
the analog input amplifier for a 12-bit A/D converter, the overall conversion error over full operation
temperature and 30 years life of the part (operating at 50°C) would be less than 5 LSBs.
•
•
Fast large-signal settling time to 0.01% of final value (1.4 μs) allows 12 bit accuracy at 100 KHZ or more
sampling rate
No flicker (1/f) noise means unsurpassed data accuracy over any measurement period of time, no matter how
long. Consider the following op amp performance, based on a typical low-noise, high-performance
commercially-available device, for comparison:
–
–
–
–
–
Op amp flatband noise = 8 nV/√Hz
1/f corner frequency = 100 Hz
AV = 2000
Measurement time = 100 sec
Bandwidth = 2 Hz
•
This example will result in about 2.2 mVPP (1.9 LSB) of output noise contribution due to the op amp alone,
compared to about 594 μVPP (less than 0.5 LSB) when that op amp is replaced with the LMP201x which has
no 1/f contribution. If the measurement time is increased from 100 seconds to 1 hour, the improvement
realized by using the LMP201x would be a factor of about 4.8 times (2.86 mVPP compared to 596 μV when
LMP201x is used) mainly because the LMP201x accuracy is not compromised by increasing the observation
time.
•
•
Copper leadframe construction minimizes any thermocouple effects which would degrade low level/high gain
data conversion application accuracy (see discussion under The Benefits of the LMP201X section above).
Rail-to-Rail output swing maximizes the ADC dynamic range in 5-Volt single-supply converter applications.
Below is a typical block diagram showing the LMP201x used as an ADC amplifier (Figure 34).
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9 Power Supply Recommendations
The LMP201x is specified for operation from 2.7 V to 5.25 V (±1.35 V to ±2.625 V) over a –40°C to +125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single
supply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor between V+
and ground, and one capacitor between V- and ground.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply
applications.
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
SLOA089, Circuit Board Layout Techniques.
•
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
•
•
Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
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10.2 Layout Example
Figure 35. Single Non-Inverting Amplifier Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMP2011/12 PSPICE Model, SNOM113
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance
SLOA089, Circuit Board Layout Techniques
SLOD006, Op Amps for Everyone
TIPD128, Capacitive Load Drive Solution using an Isolation Resistor
SBOA092, Handbook of Operational Amplifier Applications
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LMP2011
LMP2012
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
LMP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2016
PACKAGING INFORMATION
Orderable Device
5962L0620602V9A
LMP2011MA/NOPB
LMP2011MAX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
DIESALE
SOIC
Y
0
8
8
32
Green (RoHS
& no Sb/Br)
Call TI
CU SN
CU SN
Level-1-NA-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ACTIVE
ACTIVE
D
D
95
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
LMP20
11MA
SOIC
2500
Green (RoHS
& no Sb/Br)
LMP20
11MA
LMP2011MF
NRND
SOT-23
SOT-23
DBV
DBV
5
5
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
AN1A
AN1A
LMP2011MF/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LMP2011MFX/NOPB
LMP2012 MDE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
DIESALE
DIESALE
SOIC
DBV
Y
5
0
0
8
8
8
8
3000
32
Green (RoHS
& no Sb/Br)
CU SN
Call TI
Call TI
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
AN1A
Green (RoHS
& no Sb/Br)
LMP2012 MDR
Y
32
Green (RoHS
& no Sb/Br)
LMP2012MA/NOPB
LMP2012MAX/NOPB
LMP2012MM/NOPB
LMP2012MMX/NOPB
D
95
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LMP20
12MA
SOIC
D
2500
1000
3500
Green (RoHS
& no Sb/Br)
LMP20
12MA
VSSOP
VSSOP
DGK
DGK
Green (RoHS
& no Sb/Br)
AP1A
Green (RoHS
& no Sb/Br)
AP1A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2016
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP2011MAX/NOPB
LMP2011MF
SOIC
SOT-23
SOT-23
SOT-23
SOIC
D
8
5
5
5
8
8
8
2500
1000
1000
3000
2500
1000
3500
330.0
178.0
178.0
178.0
330.0
178.0
330.0
12.4
8.4
6.5
3.2
3.2
3.2
6.5
5.3
5.3
5.4
3.2
3.2
3.2
5.4
3.4
3.4
2.0
1.4
1.4
1.4
2.0
1.4
1.4
8.0
4.0
4.0
4.0
8.0
8.0
8.0
12.0
8.0
Q1
Q3
Q3
Q3
Q1
Q1
Q1
DBV
DBV
DBV
D
LMP2011MF/NOPB
LMP2011MFX/NOPB
LMP2012MAX/NOPB
LMP2012MM/NOPB
LMP2012MMX/NOPB
8.4
8.0
8.4
8.0
12.4
12.4
12.4
12.0
12.0
12.0
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP2011MAX/NOPB
LMP2011MF
SOIC
SOT-23
SOT-23
SOT-23
SOIC
D
8
5
5
5
8
8
8
2500
1000
1000
3000
2500
1000
3500
367.0
210.0
210.0
210.0
367.0
210.0
367.0
367.0
185.0
185.0
185.0
367.0
185.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DBV
DBV
DBV
D
LMP2011MF/NOPB
LMP2011MFX/NOPB
LMP2012MAX/NOPB
LMP2012MM/NOPB
LMP2012MMX/NOPB
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 2
IMPORTANT NOTICE
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