LMP7707MAX/NOPB [TI]
精密 CMOS 输入 RRIO 宽电源电压范围解补偿单通道放大器 | D | 8;
| 型号： | LMP7707MAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精密 CMOS 输入 RRIO 宽电源电压范围解补偿单通道放大器 | D | 8 放大器 光电二极管 |
| 文件： | 总47页 (文件大小：2019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
LMP7707/LMP7708/LMP7709 Precision, CMOS Input, RRIO, Wide Supply Range
Decompensated Amplifiers
Check for Samples: LMP7707, LMP7708, LMP7709
1
FEATURES
DESCRIPTION
The LMP7707/LMP7708/LMP7709 devices are
single, dual, and quad low offset voltage, rail-to-rail
input and output precision amplifiers which each have
a CMOS input stage and a wide supply voltage
range. The LMP7707/LMP7708/LMP7709 are part of
the LMP™ precision amplifier family and are ideal for
23
•
Unless Otherwise Noted, Typical Values at
VS = 5V.
•
•
Input Offset Voltage (LMP7707) ±200 µV (Max)
Input Offset Voltage (LMP7708/LMP7709)
±220 µV (Max)
sensor
interface
and
other
instrumentation
•
•
•
•
•
•
•
•
•
•
•
•
Input Bias Current ±200 fA
applications. These decompensated amplifiers are
stable at a gain of 6 and higher.
Input Voltage Noise 9 nV/√Hz
CMRR 130 dB
The ensured low offset voltage of less than ±200 µV
along with the ensured low input bias current of less
than ±1 pA make the LMP7707/LMP7708/LMP7709
Open Loop Gain 130 dB
Temperature Range −40°C to 125°C
Gain Bandwidth Product (AV =10) 14 MHz
Stable at a Gain of 10 or Higher
Supply Current (LMP7707) 715 µA
Supply Current (LMP7708) 1.5 mA
Supply Current (LMP7709) 2.9 mA
Supply Voltage Range 2.7V to 12V
Rail-to-Rail Input and Output
ideal
for
precision
applications.
The
LMP7707/LMP7708/LMP7709 are built utilizing VIP50
technology, which allows the combination of a CMOS
input stage and a supply voltage range of 12V with
rail-to-rail common mode voltage capability. The
LMP7707/LMP7708/LMP7709 are the perfect choice
in many applications where conventional CMOS parts
cannot operate due to the voltage conditions.
The unique design of the rail-to-rail input stage of
each
of
the
LMP7707/LMP7708/LMP7709
APPLICATIONS
significantly reduces the CMRR glitch commonly
associated with rail-to-rail input amplifiers. Both sides
of the complimentary input stage have been trimmed,
thereby reducing the difference between the NMOS
and PMOS offsets. The output swings within 40 mV
of either rail to maximize the signal dynamic range in
applications requiring low supply voltage.
•
•
•
•
•
•
High Impedance Sensor Interface
Battery Powered Instrumentation
High Gain Amplifiers
DAC Buffer
Instrumentation Amplifier
Active Filters
The LMP7707 is offered in the space-saving 5-pin
SOT-23 and 8-pin SOIC packages, the LMP7708 is
offered in the 8-pin VSSOP and 8-pin SOIC
packages, and the quad LMP7709 is offered in the
14-pin TSSOP and 14-pin SOIC packages. These
small packages are ideal solutions for area
constrained PC boards and portable electronics.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Open Loop Frequency Response
DECOMPENSATED OP AMP
UNITY-GAIN STABLE OP AMP
A
OL
G
min
f
GBWP
fu
f
1
f
f
d
2
'
f
u
Figure 1. Increased Bandwidth for Same Supply Current at AV> 10
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model
Machine Model
2000V
200V
ESD Tolerance(3)
Charge Device Model
1000V
VIN Differential
±300 mV
Supply Voltage (VS = V+ – V−)
Voltage at Input/Output Pins
Input Current
13.2V
V++ 0.3V to V− − 0.3V
10 mA
Storage Temperature Range
Junction Temperature(4)
−65°C to +150°C
+150°C
Infrared or Convection (20 sec)
235°C
Soldering Information
Wave Soldering Lead Temp. (10 sec)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Temperature Range(2)
Supply Voltage (VS = V+ – V−)
−40°C to +125°C
2.7V to 12V
265°C/W
5-Pin SOT-23
8-Pin SOIC
190°C/W
(2)
Package Thermal Resistance (θJA
)
8-Pin VSSOP
14-Pin TSSOP
14-Pin SOIC
235°C/W
122°C/W
145°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
2
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
3V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
VOS
±37
±200
±500
LMP7707
Input Offset Voltage
μV
±56
±220
±520
LMP7708/LMP7709
TCVOS
IB
Input Offset Voltage Drift(4)
Input Bias Current(4)(5)
Input Offset Current
±1
±5
±1
μV/°C
pA
±0.2
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
±50
±400
IOS
40
fA
CMRR
0V ≤ VCM ≤ 3V
86
130
LMP7707
80
Common Mode Rejection Ratio
dB
0V ≤ VCM ≤ 3V
LMP7708/LMP7709
84
78
130
98
PSRR
CMVR
86
82
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 12V, VO = V+/2
dB
V
CMRR ≥ 80 dB
CMRR ≥ 77 dB
−0.2
−0.2
3.2
Input Common-Mode Voltage Range
3.2
AVOL
RL = 2 kΩ (LMP7707)
VO = 0.3V to 2.7V
100
96
114
114
124
40
RL = 2 kΩ (LMP7708/LMP7709)
VO = 0.3V to 2.7V
100
94
Open Loop Voltage Gain
dB
RL = 10 kΩ
VO = 0.2V to 2.8V
RL = 2 kΩ to V+/2
100
96
VO
80
LMP7707
120
RL = 2 kΩ to V+/2
40
80
LMP7708/LMP7709
RL = 10 kΩ to V+/2
150
mV
Output Swing High
from V+
30
40
LMP7707
60
RL = 10 kΩ to V+/2
35
50
LMP7708/LMP7709
100
RL = 2 kΩ to V+/2
40
60
LMP7707
80
RL = 2 kΩ to V+/2
45
100
LMP7708/LMP7709
RL = 10 kΩ to V+/2
170
Output Swing Low
mV
20
40
LMP7707
50
RL = 10 kΩ to V+/2
20
50
LMP7708/LMP7709
90
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
IO
Parameter
Conditions
Sourcing VO = V+/2
Min(2)
Typ(3)
Max(2)
Units
25
42
VIN = 100 mV
15
Sinking VO = V+/2
VIN = −100 mV (LMP7707)
Sinking VO = V+/2
VIN = −100 mV
25
20
42
42
Output Short Circuit Current(6)(7)
mA
25
15
(LMP7708/LMP7709)
IS
0.670
1.4
1.0
1.2
LMP7707
LMP7708
LMP7709
1.8
2.1
Supply Current
mA
2.9
3.5
4.5
SR
Slew Rate(8)
VO = 2 VPP,10% to 90%
AV = 10
5.1
13
V/μs
GBWP
THD+N
Gain Bandwidth Product
MHz
f = 1 kHz, AV = 10, VO = 2.5V,
RL = 10 kΩ
Total Harmonic Distortion + Noise
0.024
%
en
in
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 1 kHz
9
1
nV/√Hz
fA/√Hz
f = 100 kHz
(6) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
VOS
±37
±200
±500
LMP7707
Input Offset Voltage
μV
±32
±220
±520
LMP7708/LMP7709
TCVOS
IB
Input Offset Voltage Drift(4)
Input Bias Current(4)(5)
Input Offset Current
±1
±5
±1
μV/°C
pA
±0.2
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
±50
±400
IOS
40
fA
CMRR
0V ≤ VCM ≤ 5V
88
130
LMP7707
83
Common Mode Rejection Ratio
Power Supply Rejection Ratio
dB
dB
0V ≤ VCM ≤ 5V
LMP7708/LMP7709
2.7V ≤ V+ ≤ 12V, VO = V+/2
86
81
130
100
PSRR
86
82
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
4
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
CMRR ≥ 80 dB
Min(2)
Typ(3)
Max(2)
Units
CMVR
−0.2
5.2
Input Common-Mode Voltage Range
V
CMRR ≥ 78 dB
−0.2
5.2
AVOL
RL = 2 kΩ (LMP7707)
VO = 0.3V to 4.7V
100
96
119
119
130
60
RL = 2 kΩ (LMP7708/LMP7709)
VO = 0.3V to 4.7V
100
94
Open Loop Voltage Gain
dB
RL = 10 kΩ
VO = 0.2V to 4.8V
RL = 2 kΩ to V+/2
100
96
VO
110
LMP7707
130
RL = 2 kΩ to V+/2
60
120
LMP7708/LMP7709
RL = 10 kΩ to V+/2
200
mV
Output Swing High
from V+
40
50
LMP7707
70
RL = 10 kΩ to V+/2
40
60
LMP7708/LMP7709
120
RL = 2 kΩ to V+/2
50
80
LMP7707
90
RL = 2 kΩ to V+/2
50
120
LMP7708/LMP7709
RL = 10 kΩ to V+/2
190
Output Swing Low
mV
30
40
LMP7707
50
RL = 10 kΩ to V+/2
30
50
LMP7708/LMP7709
100
IO
Sourcing VO = V+/2
40
66
VIN = 100 mV (LMP7707)
28
Sourcing VO = V+/2
38
66
VIN = 100 mV (LMP7708/LMP7709)
Sinking VO = V+/2
VIN = −100 mV (LMP7707)
Sinking VO = V+/2
25
Output Short Circuit Current(6)(7)
mA
mA
40
28
76
40
23
76
VIN = −100 mV (LMP7708/LMP7709)
IS
0.715
1.5
2.9
1.0
1.2
LMP7707
LMP7708
LMP7709
1.9
2.2
Supply Current
3.7
4.6
SR
Slew Rate(8)
VO = 4 VPP, 10% to 90%
AV = 10
5.6
14
V/μs
GBWP
THD+N
Gain Bandwidth Product
MHz
f = 1 kHz, AV = 10, VO = 4.5V,
RL = 10 kΩ
Total Harmonic Distortion + Noise
0.024
%
en
in
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 1 kHz
9
1
nV/√Hz
fA/√Hz
f = 100 kHz
(6) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
±5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
VOS
±37
±200
±500
LMP7707
Input Offset Voltage
μV
±37
±220
±520
LMP7708/LMP7709
TCVOS
IB
Input Offset Voltage Drift(4)
Input Bias Current(4)(5)
Input Offset Current
±1
±5
1
μV/°C
pA
±0.2
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
±50
±400
IOS
40
fA
CMRR
−5V ≤ VCM ≤ 5V
92
138
LMP7707
88
Common Mode Rejection Ratio
dB
−5V ≤ VCM ≤ 5V
LMP7708/LMP7709
2.7V ≤ V+ ≤ 12V, V− = 0V, VO = V+/2
90
86
138
98
PSRR
CMVR
86
82
Power Supply Rejection Ratio
dB
V
CMRR ≥ 80 dB
CMRR ≥ 78 dB
−5.2
−5.2
5.2
Input Common-Mode Voltage Range
5.2
AVOL
RL = 2 kΩ (LMP7707)
VO = −4.7V to 4.7V
100
98
121
121
134
134
90
RL = 2 kΩ (LMP7708/LMP7709)
VO = −4.7V to 4.7V
100
94
Open Loop Voltage Gain
Output Swing High
Output Swing Low
dB
RL = 10 kΩ (LMP7707)
VO = −4.8V to 4.8V
100
98
RL = 10 kΩ (LMP7708/LMP7709)
VO = −4.8V to 4.8V
100
97
VO
RL = 2 kΩ to 0V
LMP7707
150
170
RL = 2 kΩ to 0V
LMP7708/LMP7709
90
180
290
mV
from V+
RL = 10 kΩ to 0V
LMP7707
40
80
100
RL = 10 kΩ to 0V
LMP7708/LMP7709
40
80
150
RL = 2 kΩ to 0V
LMP7707
90
130
150
RL = 2 kΩ to 0V
LMP7708/LMP7709
90
180
290
mV
from V–
RL = 10 kΩ to 0V
40
50
LMP7707
60
RL = 10 kΩ to 0V
40
60
LMP7708/LMP7709
110
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
6
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
±5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V.
Boldface limits apply at the temperature extremes.
Symbol
IO
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Sourcing VO = 0V
50
86
VIN = 100 mV (LMP7707)
35
Sourcing VO = 0V
VIN = 100 mV (LMP7708/LMP7709)
48
33
86
84
Output Short Circuit Current(6)(7)
mA
Sinking VO = 0V
50
VIN = −100 mV
35
IS
0.790
1.7
1.1
1.3
LMP7707
LMP7708
LMP7709
2.1
2.5
Supply Current
mA
3.2
4.2
5.0
SR
Slew Rate(8)
VO = 9 VPP, 10% to 90%
AV = 10
5.9
15
V/μs
GBWP
THD+N
Gain Bandwidth Product
MHz
f = 1 kHz, AV = 10, VO = 9V,
RL = 10 kΩ
Total Harmonic Distortion + Noise
0.024
%
en
in
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 1 kHz
9
1
nV/√Hz
fA/√Hz
f = 100 kHz
(6) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Connection Diagrams
Top View
Top View
+
8
1
2
5
1
V
NC
OUT
NC
IN-
7
+
V
-
2
3
-
V
6
5
3
4
+
IN+
OUT
NC
-
+
4
-
IN-
IN+
V
Figure 2. LMP7707 5-Pin SOT-23
See DBV Package
Figure 3. LMP7707 8-Pin SOIC
See D Package
Top View
Top View
Figure 4. LMP7708 8-Pin VSSOP (See DGK
Package)
Figure 5. LMP7709 14-Pin TSSOP (See PW
Package)
LMP7709 14-Pin SOIC (See D Package)
LMP7708 8-Pin SOIC (See D Package)
8
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Offset Voltage Distribution
TCVOS Distribution
= 3V
20
16
25
20
V
V
T
= 3V
S
S
-40°C Ç T Ç 125°C
= 25°C
A
A
12
8
15
10
5
4
0
0
-200
-100
0
100
200
-3
-3
-3
-2
-2
-2
-1
0
1
2
3
3
3
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
Figure 6.
Figure 7.
TCVOS Distribution
= 5V
Offset Voltage Distribution
20
16
25
20
15
10
5
V
T
= 5V
V
S
S
= 25°C
-40°C Ç T Ç 125°C
A
A
12
8
4
0
0
-200
-100
0
100
200
-1
0
1
2
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
Figure 8.
Figure 9.
TCVOS Distribution
= 10V
Offset Voltage Distribution
20
16
25
20
15
10
5
V
S
V
= 10V
= 25°C
S
-40°C Ç T Ç 125°C
T
A
A
12
8
4
0
0
-200
-100
0
100
200
-1
0
1
2
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
Figure 10.
Figure 11.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Offset Voltage vs. Temperature
CMRR vs. Frequency
-20
200
-40
150
100
50
-60
V
= 3V
S
-80
0
-100
-50
V
S
= 5V
-120
-100
-150
-200
-140
V
= 10V
S
-160
10
100
1k
10k
100k
1M
-40 -20
0
20 40 60 80 100 120125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 12.
Figure 13.
Offset Voltage vs. Supply Voltage
Offset Voltage vs. VCM
200
150
100
200
150
100
50
V
= 3V
S
-40°C
25°C
-40°C
25°C
50
0
0
-50
-50
125°C
-100
-100
-150
-200
125°C
-150
-200
2
4
6
8
10
12
-0.5
0
0.5
1.5
(V)
2
2.5
3
3.5
1
V
CM
SUPPLY VOLTAGE (V)
Figure 14.
Figure 15.
Offset Voltage vs. VCM
Offset Voltage vs. VCM
200
150
200
V
S
= 10V
V
= 5V
S
150
100
100
-40°C
25°C
-40°C
25°C
50
0
50
0
-50
-50
-100
-150
-200
-100
-150
125°C
125°C
3
-200
-1
0
1
2
3
4
5
6
5
-1
0
1
2
4
6
7
8
9 10 11
V
CM
(V)
V
CM
(V)
Figure 16.
Figure 17.
10
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Input Bias Current vs. VCM
Input Bias Current vs. VCM
300
200
100
200
100
0
V
S
= 3V
V
S
= 3V
85°C
-40°C
0
-100
-100
-200
-200
-300
125°C
25°C
1.5
0
0
0
0.5
1
1.5
(V)
2
2.5
3
0
0.5
1
2
2.5
3
V
V
(V)
CM
CM
Figure 18.
Input Bias Current vs. VCM
V
Figure 19.
Input Bias Current vs. VCM
300
200
100
300
200
V
S
= 5V
= 5V
S
100
0
85°C
-40°C
25°C
0
-100
-100
-200
-300
-200
-300
125°C
1
2
3
4
5
0
1
2
3
4
5
V
(V)
V
CM
(V)
CM
Figure 20.
Figure 21.
Input Bias Current vs. VCM
= 10V
Input Bias Current vs. VCM
500
300
200
V
S
V
= 10V
S
250
0
100
0
85°C
-40°C
25°C
-100
-250
-200
-300
125°C
-500
2
4
6
8
10
0
2
4
6
8
10
V
CM
(V)
V
CM
(V)
Figure 22.
Figure 23.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Supply Current vs.
PSRR vs. Frequency
Supply Voltage (Per Channel)
1.2
1
120
100
80
125°C
25°C
0.8
0.6
0.4
-40°C
60
40
0.2
0
20
A
= +10
V
10
100
1k
10k
100k
1M
2
4
6
8
10
12
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 24.
Figure 25.
Sinking Current vs. Supply Voltage
Sourcing Current vs. Supply Voltage
120
120
100
-40°C
25°C
-40°C
100
25°C
80
60
40
80
60
40
125°C
125°C
20
0
20
0
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 26.
Figure 27.
Output Voltage vs. Output Current
Slew Rate vs. Supply Voltage
8.0
7.5
+
A
V
= +10
V
V
T
A
= -40°C, 25°C, 125C
= 200 mV
= 10 kW
= 10 pF
IN
+
(V ) -1
7.0
R
C
L
L
6.5
+
(V ) -2
6.0
5.5
3V
ö
ö
5.0
2
1
0
4.5
4.0
3.5
3.0
V
S
= 3V, 5V, 10V
2
4
6
8
10
12
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 28.
Figure 29.
12
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Open Loop Frequency Response
Open Loop Frequency Response
100
225
80
180
GAIN
100
80
60
40
20
0
225
180
135
90
PHASE
135
60
V
= 10V
40
90
S
C
= 22 pF
L
-40°C
20
0
45
0
45
PHASE
0
-20
-40
-60
-45
-90
-135
A
V
= -10
V
= 3V
V
S
S
-45
-20
= 5V
C
= 100 pF
L
A
V
= -10
V
S
25°C
R
C
= 10 kW
L
L
= 3V, 5V, 10V
= 22 pF, 47 pF, 100 pF
-90
-40
-60
= 22 pF
125°C
C
L
-135
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30.
Figure 31.
Small Signal Step Response, AV = 10
Large Signal Step Response, AV = 10
V
= 5V
V
= 5V
S
S
f = 10 kHz
f = 10 kHz
A
V
= +10
A
V
= +10
V
V
= 200 mV
= 10 kW
= 10 pF
= 10 mV
= 10 kW
= 10 pF
IN
PP
IN
PP
R
R
L
L
L
L
C
C
10 Ûs/DIV
10 Ûs/DIV
Figure 32.
Figure 33.
Large Signal Step Response, AV = 100
Small Signal Step Response, AV = 100
V
S
= 5V
V
= 5V
S
f = 10 kHz
f = 10 kHz
A
V
= +100
= 20 mV
= 10 kW
= 10 pF
A
V
= +100
= 1 mV
= 10 kW
= 10 pF
V
V
IN
PP
IN
PP
R
C
R
L
L
L
L
C
10 Ûs/DIV
10 Ûs/DIV
Figure 34.
Figure 35.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Open Loop Gain vs.
Output Voltage Swing
Input Voltage Noise vs. Frequency
120
100
80
60
40
20
0
150
140
130
120
V
= 10V
S
V
= 5V
S
R
L
= 10 kW
110
100
90
V
= 3V
S
V
= 3V
S
V
= 5V
S
80
R
L
= 2 kW
70
V
= 10V
S
60
500
1k
100
10k
100k
1
10
400
300
200
100
0
FREQUENCY (Hz)
OUTPUT SWING FROM RAIL (mV)
Figure 36.
Figure 37.
Output Swing High vs.
Supply Voltage
Output Swing Low vs.
Supply Voltage
50
40
30
20
10
0
50
40
30
20
10
0
R
L
= 10 kW
R
L
= 10 kW
25°C
125°C
-40°C
-40°C
25°C
125°C
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 38.
Figure 39.
Output Swing High vs.
Supply Voltage
Output Swing Low vs.
Supply Voltage
100
80
60
40
20
0
100
80
60
40
20
0
R
= 2 kW
R
L
= 2 kW
L
25°C
25°C
125°C
125°C
-40°C
-40°C
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 40.
Figure 41.
14
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
THD+N vs. Frequency
THD+N vs. Output Voltage
100
1
V
= 5V
S
V
= 4.5V
OUT
PP
R
= 100 kW
L
Noise band = 500 kHz
10
1
0.1
0.1
0.01
V
= 5V
S
f = 1 kHz
R
Noise band = 500 kHz
= 100 kW
L
0.01
0.01
0.1
1
10
10
100
1k
10k
100k
V
(V )
OUT PP
FREQUENCY (Hz)
Figure 42.
Figure 43.
Crosstalk Rejection Ratio vs.
Frequency(LMP7708/LMP7709)
140
V
S
= 12V
120
100
80
V
= 5V
S
V
S
= 3V
60
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 44.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
LMP7707/LMP7708/LMP7709
The LMP7707/LMP7708/LMP7709 devices are single, dual and quad low offset voltage, rail-to-rail input and
output precision amplifiers each with a CMOS input stage and the wide supply voltage range of 2.7V to 12V. The
LMP7707/LMP7708/LMP7709 have a very low input bias current of only ±200 fA at room temperature.
The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes
either the LMP7707, LMP7708 or LMP7709 an excellent choice for low voltage precision applications with
extensive temperature requirements.
The LMP7707/LMP7708/LMP7709 have only ±37 µV of typical input referred offset voltage and this offset is
ensured to be less than ±500 µV for the single and ±520 µV for the dual and quad over temperature. This
minimal offset voltage allows more accurate signal detection and amplification in precision applications.
The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz give the
LMP7707/LMP7708/LMP7709 superior qualities for use in sensor applications. Lower levels of noise introduced
by the amplifier mean better signal fidelity and a higher signal-to-noise ratio.
The LMP7707/LMP7708/LMP7709 are stable for a gain of 6 or higher. With proper compensation though, the
LMP7707, LMP7708 or LMP7709 can be operational at a gain of ±1 and still maintain much faster slew rates
than comparable fully compensated amplifiers. The increase in bandwidth and slew rate is obtained without any
additional power consumption.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7707 is offered in the space-saving 5-pin SOT-23 and 8-pin SOIC packages, the LMP7708 comes in the
8-pin VSSOP and 8-pin SOIC packages, and the LMP7709 is offered in the 14-pin TSSOP and 14-pin SOIC
packages. These small packages are ideal solutions for area constrained PC boards and portable electronics.
CAPACITIVE LOAD
The LMP7707/LMP7708/LMP7709 devices can each be connected as a non-inverting voltage follower. This
configuration is the most sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier’s output
impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response will be either underdamped or it will oscillate.
In order to drive heavier capacitive loads, an isolation resistor, RISO, as shown in the circuit in Figure 45 should
be used. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the
pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output
voltage will be. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value
of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.
R
ISO
V
+
-
IN
V
OUT
R
R
1
2
C
L
Figure 45. Isolating Capacitive Load
16
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The
LMP7707/LMP7708/LMP7709 enhances this performance by having the low input bias current of only ±200 fA,
as well as a very low input referred voltage noise of 9 nV/√Hz. In order to achieve this a large input stage has
been used. This large input stage increases the input capacitance of the LMP7707/LMP7708/LMP7709. The
typical value of this input capacitance, CIN, for the LMP7707/LMP7708/LMP7709 is 25 pF. The input capacitance
will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the
amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and
DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this
pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input
capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking
values for the feedback resistor, a capacitor can be added to the feedback path to increase stability.
C
F
R
2
R
1
-
+
C
IN
V
+
-
IN
+
V
OUT
-
Figure 46. Compensating for Input Capacitance
Using this compensation method will have an impact on the high frequency gain of the op amp, due to the
frequency dependent feedback of this amplifier. Low gain settings can, again, introduce instability issues.
DIODES BETWEEN THE INPUTS
The LMP7707/LMP7708/LMP7709 have a set of anti-parallel diodes between the input pins, as shown in
Figure 47. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode
voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV
or the input current needs to be limited to ±10 mA. Exceeding these limits will damage the part.
+
+
V
V
D
1
ESD
IN
ESD
ESD
R
1
R
2
-
+
IN
ESD
D
2
-
-
V
R
1
= R = 130Ö
2
V
Figure 47. Input of the LMP7707
TOTAL NOISE CONTRIBUTION
The LMP7707/LMP7708/LMP7709 have very low input bias current, very low input current noise and very low
input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor
applications.
Figure 48 shows the typical input noise of the LMP7707/LMP7708/LMP7709 as a function of source resistance.
The total noise at the input can be calculated using Equation 1.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
eni = en2+ e2i + et2
where
•
•
•
•
eni is the total noise on the input
en denotes the input referred voltage noise
ei is the voltage drop across source resistance due to input referred current noise or ei = RS * in
et is the thermal noise of the source resistance
(1)
The input current noise of the LMP7707/LMP7708/LMP7709 is so low that it will not become the dominant factor
in the total noise unless source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in Figure 48, at lower RS values, the total noise is dominated by the amplifier’s input voltage noise.
Once RS is larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As
mentioned before, the current noise will not be the dominant noise factor for any practical application.
1000
100
e
ni
e
n
10
e
t
e
i
1
0.1
10k
(W)
1M
10
1k
100k
10M
100
R
S
Figure 48. Total Input Noise
HIGH IMPEDANCE SENSOR INTERFACE
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often
needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier
can load the sensor’s output and cause a voltage drop across the source resistance as shown in Figure 49,
where VIN + = VS – IBIAS*RS
The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this
voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep
the error contribution by IBIAS*RS less than the input voltage noise of the amplifier, so that it will not become the
dominant noise factor. The LMP7707/LMP7708/LMP7709 have very low input bias current, typically 200 fA.
18
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
SENSOR
+
V
I
B
R
S
V
+
IN
+
-
+
-
V
S
R
R
1
2
-
V
Figure 49. Noise Due to IBIAS
USAGE OF DECOMPENSATED AMPLIFIERS
This section discusses the differences between compensated and decompensated op amps and presents the
advantages of decompensated amplifiers. In high gain applications decompensated amplifiers can be used
without any changes compared to standard amplifiers. However, for low gain applications special frequency
compensation measures have to be taken to ensure stability.
Feedback circuit theory is discussed in detail, in particular as it applies to decompensated amplifiers. Bode plots
are presented for a graphical explanation of stability analysis. Two solutions are given for creating a feedback
network for decompensated amplifiers when relatively low gains are required: A simple resistive feedback
network and a more advanced frequency dependent feedback network with improved noise performance. Finally,
a design example is presented resulting in a practical application. The results are compared to fully compensated
amplifiers (Texas Instruments LMP7701/LMP7702/LMP7704).
COMPENSATED AMPLIFIERS
A (fully) compensated op amp is designed to operate with good stability down to gains of ±1. For this reason, the
compensated op amp is also called a unity gain stable op amp.
Figure 50 shows the Open Loop Response of a compensated amplifier.
80
100
80
100
120
140
160
60
40
20
0
180
200
-20
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 50. Open Loop Frequency Response Compensated Amplifier (LMP7701)
This amplifier is unity gain stable, because the phase shift is still < 180°, when the gain crosses 0 dB (unity gain).
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Stability can be expressed in two different ways:
Phase MarginThis is the phase difference between the actual phase shift and 180°, at the point where the gain
is 0 dB.
Gain MarginThis is the gain difference relative to 0 dB, at the frequency where the phase shift crosses the 180°.
The amplifier is supposed to be used with negative feedback but a phase shift of 180° will turn the negative
feedback into positive feedback, resulting in oscillations. A phase shift of 180° is not a problem when the gain is
smaller than 0 dB, so the critical point for stability is 180° phase shift at 0 dB gain. The gain margin and phase
margin express the margin enhancing overall stability between the amplifiers response and this critical point.
DECOMPENSATED AMPLIFIERS
Decompensated amplifiers, such as the LMP7707/LMP7708/LMP7709, are designed to maximize the bandwidth
and slew rate without any additional power consumption over the unity gain stable op amp. That is, a
decompensated op amp has a higher bandwidth to power ratio than an equivalent compensated op amp.
Compared with the unity gain stable amplifier, the decompensated version has the following advantages:
1. A wider closed loop bandwidth
2. Better slew rate due to reduced compensation capacitance within the op amp
3. Better Full Power Bandwidth, given with Equation 2
SR
FPBW =
í
2
VP
(2)
Figure 51 shows the frequency response of the decompensated amplifier.
80
100
80
100
120
140
160
60
40
20
0
180
200
-20
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 51. Open Loop Frequency Response Decompensated Amplifier (LMP7707)
As shown in Figure 51, the reduced internal compensation moves the first pole to higher frequencies. The
second open loop pole for the LMP7707/LMP7708/LMP7709 occurs at 4 MHz. The extrapolated unity gain (see
dashed line in Figure 51) occurs at 14 MHz. An ideal two pole system would give a phase margin of > 45° at the
location of the second pole. Unfortunately, the LMP7707/LMP7708/LMP7709 have parasitic poles close to the
second pole, giving a phase margin closer to 0°. The LMP7707/LMP7708/LMP7709 can be used at frequencies
where the phase margin is > 45°. The frequency where the phase margin is 45° is at 2.4 MHz. The
corresponding value of the open loop gain (also called GMIN) is 6 times.
Stability has only to do with the loop gain and not with the forward gain (G) of the op amp. For high gains, the
feedback network is attenuating and this reduces the loop gain; therefore the op amp will be stable for G > GMIN
and no special measures are required. For low gains the feedback network attenuation may not be sufficient to
ensure loop stability for a decompensated amplifier. However, with an external compensation network
decompensated amplifiers can still be made stable while maintaining their advantages over unity gain stable
amplifiers.
20
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
EXTERNAL COMPENSATION FOR GAINS LOWER THAN GMIN.
This section explains how decompensated amplifiers can be used in configurations requiring a gain lower than
GMIN. In the next sections the concept of the feedback factor is introduced. Subsequently, an explanation is given
how stability can be determined using the frequency response curve of the op amp together with the feedback
factor. Using the circuit theory, it will be explained how decompensated amplifiers can be stabilized at lower
gains.
FEEDBACK THEORY
Stability issues can be analyzed by verifying the loop gain function GF, where G is the open loop gain of the
amplifier and F is the feedback factor of the feedback circuit.
The feedback function (F) of arbitrary electronic circuits, as shown in Figure 52, is defined as the ratio of the
input and output signal of the same circuit.
R
R
F
F
R
1
R
1
V
V
V
V
A
B
A
-
-
V
V
OUT
OUT
B
V
IN
+
+
V
IN
Figure 52. Op Amp with Resistive Feedback. (a) Non-inverting (b) Inverting
The feedback function for a three-terminal op amp as shown in Figure 52 is the feedback voltage VA – VB across
the op amp input terminals relative to the op amp output voltage, VOUT. That is
VA - VB
F =
VOUT
(3)
GRAPHICAL EXPLANATION OF STABILITY ANALYSIS
Stability issues can be observed by verifying the closed loop gain function GF. In the frequencies of interest, the
open loop gain (G) of the amplifier is a number larger than 1 and therefore positive in dB. The feedback factor (F)
of the feedback circuit is an attenuation and therefore negative in dB. For calculating the closed loop gain GF in
dB we can add the values of G and F (both in dB).
One practical approach to stabilizing the system, is to assign a value to the feedback factor F such that the
remaining loop gain GF equals one (unity gain) at the frequency of GMIN. This realizes a phase margin of 45° or
greater. This results in the following requirement for stability: 1/F > GMIN. The inverse feedback factor 1/F is
constant over frequency and should intercept the open loop gain at a value in dB that is greater than or equal to
GMIN
The inverse feedback factor for both configurations shown in Figure 52, is given by:
RF
.
1
= 1 +
F
R1
(4)
(5)
(6)
The closed loop gain for the non-inverting configuration (a) is:
RF
R1
1
F
ACL = 1 +
=
The closed loop gain for the inverting configuration (b) is:
RF
1
ACL = -
= 1 -
R1
F
For stable operation the phase margin must be equal to or greater than 45°. The corresponding closed loop gain
GMIN, for a non-inverting configuration, is
|ACL|(min) = Gmin
(7)
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
For an inverting configuration:
|ACL|(min) = Gmin - 1
(8)
If R1 and RF and are chosen so that the closed loop gain is lower than the minimum gain required for stability,
then 1/F intersects the open loop gain curve for a value that is lower than GMIN. For example, assume the GMIN is
equal to 10 V/V (20 dB). This is shown as the dashed line in Figure 53. The resistor choice of RF = R1 = 2 kΩ
makes the inverse feedback equal 2 V/V (6 dB), shown in Figure 53 as the solid line. The intercept of G and 1/F
represents the frequency for which the loop gain is identical to 1 (0 dB). Consequently, the total phase shift at the
frequency of this intercept determines the phase margin and the overall system stability. In this system example
1/F crosses the open loop gain at a frequency which is larger than the frequency where GMIN occurs, therefore
this system has less than 45° phase margin and is most likely instable.
A
OL
G
= 20 dB
= 6 dB
R
min
F
1
F
= 1 +
1
F
R
1
f
1
f
2
Figure 53. 1/F for RF = R1 and Open Loop Gain Plot
RESISTIVE COMPENSATION
A straightforward way to achieve a stable amplifier configuration is to add a resistor RC between the inverting and
the non-inverting inputs as shown in Figure 54.
R
F
R
1
-
V
OUT
R
C
+
Figure 54. Op Amp with Compensation Resistor between Inputs
This additional resistor RC will not affect the closed loop gain of the amplifier but it will have positive impact on
the feedback network.
The inverse feedback function of this circuit is:
1
RF
RF
RF
= 1 +
= 1 +
+
Rc
F
R1//Rc
R1
(9)
22
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Proper selection of the value of RC results in the shifting of the 1/F function to GMIN or greater, thus fulfilling the
condition for circuit stability. The compensation technique of reducing the loop gain may be used to stabilize the
circuit for the values given in the previous example, that is GMIN = 20 dB and RF = R1 = 2 kΩ. A resistor value of
250 Ω applied between the amplifier inputs shifts the 1/F curve to the value GMIN (20 dB) as shown by the
dashed line in Figure 55. This results in overall stability for the circuit. This figure shows a combination of the
open and closed loop gain and the inverse feedback function.
This example, represented by Figure 52 and Figure 53, is generic in the sense that the GMIN as specified did not
distinguish between inverting and non-inverting configurations.
A
OL
G
= 20 dB
= 6 dB
min
R
R
F
F
1 +
f
1
f
2
Figure 55. Compensation with Reduced Loop Gain
The technique of reducing loop gain to stabilize a decompensated op amp circuit will be illustrated using the non-
inverting input configuration shown in Figure 56.
R
F
R
1
V
X
-
V
OUT
R
C
+
V
IN
Figure 56. Closed Loop Gain Analysis with RC
The effect of the choice of resistor RC in Figure 56 on the closed loop gain can be analyzed in the following
manner:
Assume the voltage at the inverting input of the op amp is VX. Then,
(VIN œ VX) G = VOUT
where
•
G is the open loop gain of the op amp
(10)
(11)
VX
R1
VX - VIN VOUT - VX
=
+
RC
RF
Combining Equation 10, Equation 11, and Equation 9 produces the following equation for closed loop gain,
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
RF
1 +
VOUT
VIN
R1
=
1
GF
1 +
(12)
By inspection of Equation 12, RC does not affect the ideal closed loop gain. In this example where RF = R1, the
closed loop gain remains at 6 dB as long as GF >> 1. The closed loop gain curve is shown as the solid line in
Figure 55.
The addition of RC affects the circuit in the following ways:
1.
1/F is moved to a higher gain, resulting in overall system stability.
However, adding RC results in reduced loop gain and increased noise gain. The noise gain is defined as the
inverse of the feedback factor, F. The noise gain is the gain from the amplifier input referred noise to the output.
In effect, loop gain is traded for stability.
2.
The ideal closed loop gain retains the same value as the circuit without the compensation resistor RC.
LEAD-LAG COMPENSATION
This section presents a more advanced compensation technique that can be used to stabilize amplifiers. The
increased noise gain of the prior circuit is prevented by reducing the low frequency attenuation of the feedback
circuit. This compensation method is called Lead-Lag compensation. Lead-lag compensation components will be
analyzed and a design example using this procedure will be discussed.
The feedback function in a lead-lag compensation circuit is shaped using a resistor and a capacitor. They are
chosen in a way that ensures sufficient phase margin.
Figure 57 shows a Bode plot containing: the open loop gain of the decompensated amplifier, a feedback function
without compensation and a feedback function with lead-lag compensation.
100
80
-20 dB/dec
60
40
20 dB/dec
1/F with compensation
20
0
1/F without compensation
1M
FREQUENCY (Hz)
Figure 57. Bode Plot of Open Loop gain G and 1/F with and without Lead-Lag Compensation
The shaped feedback function presented in Figure 57 can be realized using the amplifier configuration in
Figure 58. Note that resistor RP is only used for compensation of the input voltage caused by the IBIAS current. RP
can be used to introduce more freedom for calculating the lead-lag components. This will be discussed later in
this section.
24
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
R
F
R
1
-
R
C
C
+
R
P
Figure 58. LMP7707 with Lead-Lag Compensation for Inverting Configuration
The inverse feedback factor of the circuit in Figure 58 is:
1 + s(RC + R1//RF + RP)C
1 + sRCC
RF
R1
1
F
= (1 +
)(
)
(13)
(14)
(15)
The pole of the inverse feedback function is located at:
1
fP =
2íRCC
The zero of the inverse feedback function is located at:
1
fZ =
2í(RC + R1//RF + RP) C
The low frequency inverse feedback factor is given by:
RF
1
F
= 1 +
f = 0
R1
(16)
(17)
The high frequency inverse feedback factor is given by:
RF
R1
RP + R1//RF
RC
1
F
= (1 +
)(1 +
)
f = ñ
From these formulas, we can tell that
1. The 1/F's zero is located at a lower frequency compared to 1/F's pole.
2. The intersection point of 1/F and the open loop gain G is determined by the choice of resistor values for RP
and RC if the values of R1 and RF are set before compensation.
3. This procedure results in the creation of a pole-zero pair, the positions of which are interdependent.
4. This pole-zero pair is used to:
–
Raise the 1/F value to a greater value in the region immediately to the left of its intercept with the A
function in order to meet the Gmin requirement.
–
Achieve the preceding with no additional loop phase delay.
5. The location of the 1/F zero is determined by the following conditions:
–
–
–
The value of 1/F at low frequency.
The value of 1/F at the intersection point.
The location of 1/F pole.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Note that the constraint 1/F ≥ Gmin needs to be satisfied only in the vicinity of the intersection of G and 1/F; 1/F
can be shaped elsewhere as needed. Two rules must be satisfied in order to maintain adequate phase margin.
Rule 1The plot of 1/F should intersect with the plot of the open loop gain at a value larger than GMIN. At that
point, the open loop gain G has a phase margin of 45°.
The location f2 in Figure 59 illustrates the proper intersection point for the LMP7707/LMP7708/LMP7709
using the circuit of Figure 58. The intersection of G and 1/F at the op amp's second pole location is the
45° phase margin reference point.
Rule 2The 1/F pole (see Figure 59) should be positioned at the frequency that is at least one decade below the
intersection point f2 of 1/F and G. This positioning takes full advantage of the 90° of phase lead brought
about by the 1/F pole. This additional phase lead accompanies the increase in magnitude of 1/F observed
at frequencies greater than the 1/F pole.
The resulting system has approximately 45° of phase margin, based upon the fact that the open loop gain's
dominant pole and the second pole are more than one decade apart and that the open loop gain has no other
pole within one decade of its intersection point with 1/F. If there is a third pole in the open loop gain G at a
frequency greater than f2 and if it occurs less than a decade above that frequency, then there will be an effect on
phase margin.
DESIGN EXAMPLE
The input lead-lag compensation method can be applied to an application using the LMP7707, LMP7708 or
LMP7709 in an inverting configuration, as shown in Figure 58.
100
80
60
40
1/F
20
0
G
MIN
-20
1k
10k
100k
f /10
1M
10M
100M
f
2
2
FREQUENCY (Hz)
Figure 59. LMP7707 Open Loop Gain and 1/F Lead-Lag Feedback Network.
Figure 59 shows that GMIN = 16 dB and f2 (intersection point) = 2.4 MHz.
A gain of 6 dB (or a magnitude of –1) is well below the LMP7707’s GMIN. Without external lead-lag compensation,
the inverse feedback factor is found using Equation 4 which applies to both inverting and non-inverting
configurations. Unity gain implementation for the inverting configuration means RF = R1, and 1/F = 2 (6 dB).
Procedure:
The compensation circuit shown in Figure 58 is implemented. The inverse feedback function is shaped by the
solid line in Figure 59. The 1/F plot is 6 dB at low frequencies. At higher frequencies, it is made to intersect the
loop gain G at frequency f2 with gain amplitude of 16 dB (GMIN), which equals a magnitude of six times. This
follows the recommendations in Rule 1. The 1/F pole fp is set one decade below the intersection point (f2 = 2.4
MHz) as given in Rule 2, and results in a frequency fp = 240 kHz. The next steps should be taken to calculate the
values of the compensation components:
Step 1)Set 1/F equal to GMIN using Equation 17. This gives a value for resistor RC.
Step 2)Set the 1/F pole one decade below the intersection point using Equation 14. This gives a value for
capacitor C.
26
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
This method uses bode plot approximation. Some fine-tuning may be needed to get the best results.
Calculations:
As described in Step 1, use Equation 17:
RF
R1
RP + R1//RF
RC
1
F
= (1 +
)(1 +
)
= 6 V/V
f = ñ
(18)
(19)
Now substitute RF/R1 = 1 into the equation above since this is a unity gain, inverting amplifier, then
RP + R1//RF = 2 RC
According to Step 2 use Equation 14:
1
fP =
= 240 kHz
2pRCC
(20)
(21)
which leads to:
1
C =
2pfRC
Choose a value of RF that is below 2 kΩ, in order to minimize the possibility of shunt capacitance across high
value resistors producing a negative effect on high frequency operation. If RF = R1 = 1 kΩ, then RF // R1 = 500 Ω.
For simplicity, choose RP = 0 Ω . The value of RC is derived from Equation 19 and has a value of RC = 250 Ω.
This is not a standard value. A value of RC = 330 Ω is a first choice (using 10% tolerance components).
The value of capacitor C is 2.2 nF. This value is significantly higher than the parasitic capacitances associated
with passive components and board layout, and is therefore a good solution.
Bench results:
For bench evaluation the LMP7707 in an inverting configuration has been verified under three different
conditions:
•
•
•
Uncompensated
Lead-lag compensation resulting in a phase margin of 45°
Lead lag overcompensation resulting in a phase margin larger than 45°
The calculated components for these three conditions are
Condition
RC
C
Uncompensated
Compensated
NA
NA
330 Ω
240 Ω
2.2 nF
3.3 nF
Overcompensated
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Figure 60 shows the results of the compensation of the LMP7707.
uncompensated
0
0
compensated
0
overcompensated
TIME (1 ms/DIV)
Figure 60. Bench Results for Lead- Lag Compensation
The top waveform shows the output response of a uncompensated LMP7707 using no external compensation
components. This trace shows ringing and is unstable (as expected). The middle waveform is the response of a
compensated LMP7707 using the compensation components calculated with the described procedure. The
response is reasonably well behaved. The bottom waveform shows the response of an overcompensated
LMP7707.
Finally, Figure 61 compares the step response of the compensated LMP7707 to that of the unity gain stable
LMP7701. The increase in dynamic performance is clear.
0.8
0.4
0.0
LMP7701
-0.4
-0.8
LMP7707 compensated
TIME (1 ms/DIV)
Figure 61. Bench Results for Comparison of LMP7701 and LMP7707
The application of input lead-lag compensation to a decompensated op amp enables the realization of circuit
gains of less than the minimum specified by the manufacturer. This is accomplished while retaining the
advantageous speed versus power characteristic of decompensated op amps.
28
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 28
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: LMP7707 LMP7708 LMP7709
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMP7707MA/NOPB
LMP7707MAX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LMP77
07MA
ACTIVE
2500 RoHS & Green
SN
LMP77
07MA
LMP7707MF/NOPB
LMP7707MFX/NOPB
LMP7708MA/NOPB
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
1000 RoHS & Green
3000 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AH4A
AH4A
95
RoHS & Green
LMP77
08MA
LMP7708MAX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP77
08MA
LMP7708MM/NOPB
LMP7708MME/NOPB
LMP7708MMX/NOPB
LMP7709MA/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
SN
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AJ4A
AJ4A
AJ4A
250
3500 RoHS & Green
55 RoHS & Green
2500 RoHS & Green
94 RoHS & Green
2500 RoHS & Green
RoHS & Green
8
14
LMP7709
MA
LMP7709MAX/NOPB
LMP7709MT/NOPB
LMP7709MTX/NOPB
ACTIVE
ACTIVE
ACTIVE
SOIC
D
14
14
14
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LMP7709
MA
TSSOP
TSSOP
PW
PW
-40 to 125
-40 to 125
LMP77
09MT
LMP77
09MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP7707MAX/NOPB
LMP7707MF/NOPB
LMP7707MFX/NOPB
LMP7708MAX/NOPB
LMP7708MM/NOPB
LMP7708MME/NOPB
LMP7708MMX/NOPB
LMP7709MAX/NOPB
LMP7709MTX/NOPB
SOIC
SOT-23
SOT-23
SOIC
D
8
5
2500
1000
3000
2500
1000
250
330.0
178.0
178.0
330.0
178.0
178.0
330.0
330.0
330.0
12.4
8.4
6.5
3.2
3.2
6.5
5.3
5.3
5.3
6.5
6.95
5.4
3.2
3.2
5.4
3.4
3.4
3.4
9.35
5.6
2.0
1.4
1.4
2.0
1.4
1.4
1.4
2.3
1.6
8.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
8.0
Q1
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
DBV
DBV
D
5
8.4
8.0
8
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
16.0
12.0
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
3500
2500
2500
14
14
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP7707MAX/NOPB
LMP7707MF/NOPB
LMP7707MFX/NOPB
LMP7708MAX/NOPB
LMP7708MM/NOPB
LMP7708MME/NOPB
LMP7708MMX/NOPB
LMP7709MAX/NOPB
LMP7709MTX/NOPB
SOIC
SOT-23
SOT-23
SOIC
D
8
5
2500
1000
3000
2500
1000
250
356.0
208.0
208.0
356.0
208.0
208.0
356.0
356.0
356.0
356.0
191.0
191.0
356.0
191.0
191.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DBV
DBV
D
5
8
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
3500
2500
2500
14
14
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMP7707MA/NOPB
LMP7708MA/NOPB
LMP7709MA/NOPB
LMP7709MT/NOPB
D
D
SOIC
SOIC
8
8
95
95
55
94
495
495
495
495
8
8
8
8
4064
4064
3.05
3.05
3.05
4.06
D
SOIC
14
14
4064
PW
TSSOP
2514.6
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明