LMP8480MME-S/NOPB [TI]
Precision 76V High-Side Current Sense Amplifiers with Voltage Output; 精密76V高边电流检测放大器，带有电压输出
| 型号： | LMP8480MME-S/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision 76V High-Side Current Sense Amplifiers with Voltage Output |
| 文件： | 总24页 (文件大小：992K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP8480, LMP8481
www.ti.com
SNVS829A –JUNE 2012–REVISED AUGUST 2012
LMP8480 / LMP8481 Precision 76V High-Side Current Sense Amplifiers with Voltage
Output
Check for Samples: LMP8480, LMP8481
1
FEATURES
•
•
Temperature Range -40 to +125°C
MSOP-8 or LLP-8 Packages
2
•
Typical values, TA = 25°C
Bi-Directional or Uni-Directional Sensing
Common Mode Voltage Range 4.0V to 76V
Supply Voltage Range 4.5V to 76V
Fixed Gains 20, 50, 60 and 100 V/V
Gain Accuracy ±0.1%
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
•
•
High-side current sense
Vehicle current measurement
Telecommunications
Motor controls
Offset ±80µV
Laser or LED Drivers
Energy Management
Solar Panel Monitoring
Bandwidth (-3dB) 270KHz
Quiescent Current <100µA
Buffered High-Current Output >5mA
Input Bias Current 7µA
PSRR (DC) 122dB
CMRR (DC) 124dB
DESCRIPTION
The LMP8480 and LMP8481 are precision high-side current sense amplifiers that amplify a small differential
voltage developed across a current sense resistor in the presence of high input common-mode voltages.
These amplifiers are designed for bidirectional (LMP8481) or unidirectional (LMP8480) current applications and
will accept input signals with common-mode voltage range from 4V to 76V with a bandwidth of 270 kHz.
Since the operating power supply range overlaps the input common mode voltage range, the LMP848x can be
powered by the same voltage that is being monitored. This benefit eliminates the need for an intermediate supply
voltage to be routed to the point of load where the current is being monitored, resulting in reduced component
count and board space.
The LMP848x family consists of fixed gains of 20, 50, 60 and 100 for applications that demand high accuracy
over temperature. The low input offset voltage allows the use of smaller sense resistors without sacrificing
system error.
The wide operating temperature range of -40C to 125C makes the LMP848x an ideal choice for automotive,
telecommunications, industrial, and consumer applications.
The LMP8480 and LMP8481 are pin for pin replacements for the MAX4080 and MAX4081, offering improved
offset voltage, wider reference adjust range and higher output drive capabilities.
The LMP8480 and LMP8481 are available in a 8-pin MSOP package and the LMP8481 is also available in a
8–pad LLP.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
LMP8480, LMP8481
SNVS829A –JUNE 2012–REVISED AUGUST 2012
www.ti.com
Typical Application
I
SENSE
V
CC
= +4.5V to +76V
To Load
C1
0.1 mF
R
SENSE
RSN
GND
V
LMP8481
OUT
VSENSE
V
V
+
REFA
REFB
RSP
IN
ADC
-
V
IN
REF
LM4140ACM-1.2
C2
0.1 mF
Block Diagram
Figure 1. LMP8480 Block Diagram
R
SENSE
I
L
4.0V < V < 76V
IN
+IN
-IN
L
o
a
d
LMP8480
V
SENSE
Difference
Amplifier
(x5)
V
CM
SENSE
R
GP
R
GN
2 MW
Internal
14V LDO
V
CC
V
Regulator
OUT
-
+
-
+
4.5V < V
CC
< 76V
100 kW
100 kW
V to I
Converter
1.95 MW
400 kW
400 kW
V
REF‘
GND
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Figure 2. LMP8481 Block Diagram
R
4.0V < V < 76V
IN
SENSE
I
L
+IN
-IN
L
o
a
LMP8481
V
SENSE
d
Difference
Amplifier
(x5)
V
CM
SENSE
R
GP
R
GN
2 MW
Internal
14V LDO
Regulator
V
CC
V
OUT
-
+
-
+
4.5V < V
CC
< 76V
100 kW
100 kW
V
REFA
V to I
Converter
1.95 MW
V
REFB
400 kW
400 kW
V
REF‘
GND
Connection Diagram
LMP8480 8-Pin MSOP
1
2
3
4
8
7
6
5
R
R
SN
SP
NC
NC
V
CC
LMP8480
NC
GND
V
OUT
Figure 3. Top View
LMP8480 8-Pad LLP
1
2
3
4
8
7
6
5
R
V
R
SN
SP
NC
NC
CC
LMP
8480
NC
GND
V
OUT
Figure 4. Top View
LMP8481 8-Pin MSOP
RSP
1
2
3
4
8
7
6
5
RSN
REFA
REFB
V
CC
LMP8481
NC
GND
V
OUT
Figure 5. Top View
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LMP8481 8-Pad LLP
1
2
3
4
8
7
6
5
R
V
R
V
SP
SN
CC
LMP
8481
REFA
REFB
NC
V
GND
V
OUT
Figure 6. Top View
Table 1. Pin Descriptions
Pin
1
Name
RSP
Description
Positive current sense input
Positive supply voltage
No Connection – Not internally Connected.
Ground
2
VCC
3
NC
4
GND
5
VOUT
Output
6
NC or REFA
NC or REFB
RSN
LMP8480: No Connection
LMP8480: No Connection
Negative current sense input
LMP8481: Reference Voltage “B” Input
LMP8481: Reference Voltage “A” Input
7
8
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
LMP8480, LMP8481
UNIT
V
Supply Voltage (VCC to GND)
RSP or RSN to GND
VOUT to GND
-0.3 to +85
-0.3 to +85
V
-0.3 to the lesser of (VCC + 0.3) or +20
V
Other VREF pin tied to ground
-0.3 to +12
-0.3 to +6
±85
V
VREF Pins
(LMP8481 Only)
Applied to both VREF Pins tied together
V
Differential Input Voltage
Current into output pin
V
(2)
±20
mA
mA
°C
°C
°C
°C/W
°C/W
V
(2)
Current into any other pins
Operating Temperature
Storage Temperature
Junction Temperature
±5
–40 to +125
-65° to +150
+150
MSOP-8
185
Package Thermal
Resistance (θJA
)
LLP-8
70
Human Body Model (HBM)
Charged Device Model (CDM)
2000
ESD Ratings
750
V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VS ), the current at that pin must not exceed
5mA, and the voltage (VIN) has to be within the Absolute Maximum Rating for that pin. The 20mA package input current rating limits the
number of pins that can safely exceed the power supplies with current flow to four pins.
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Recommended Operating Ratings
Expected normal operating conditions over free-air temperature range (unless otherwise noted).
LMP8480, LMP8481
UNIT
V
Supply Voltage (VCC
)
+4.5V to +76
+4.0V to +76
±667
Common Mode Voltage
V
Differential Input Voltage (VSENSE
)
mV
V
VREFA and VREFB tied together
-0.3 to the lesser of (VCC - 1.5) or +6
Reference Input
(LMP8481 Only)
-0.3 to +12, or where the average of the two VREF
pins is less than the lesser of (VCC - 1.5) or +6
Single VREF pin with other VREF pin grounded
V
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(1)
Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TA = 25°C, VCC= +4.5V to +76V, +4.5V < VCM < +76V, RL= 100k,
VSENSE = (VRSP - VRSN) = 0V. Boldface limits apply at the temperature extremes, TMIN ≦ TA ≦ TMAX
.
Min
Typ
Max
(2)
(3)
(2)
Parameter
Input Offset Voltage (RTI)
Condition
Units
Ta= +25°C
±80
6
±265
VCC = VRSP = 48V,
VOS
µV
ΔVSENSE = 100mV
Ta= –40°C to +125°C
±900
Input Offset Voltage Drift
TCVOS
μV/°C
(4)
(5)
Input Bias Current
IB VCC = VRSP = 76V, Per Input
ILEAK VCC = 0, VRSP = 76V, Both Inputs Together
-T Version
6.3
12
2
μA
μA
Input Leakage Current
0.01
667
267
222
133
20.2
50.4
60.5
100.8
±0.6
±0.8
-F Version
-S Version
-H Version
Differential Input Voltage Across Sense
VSENSE(
VCC = 16
mV
V/V
(6)
Resistor
MAX)
-T Version
-F Version
-S Version
-H Version
19.8
49.6
59.5
99.2
20
50
Gain
AV
60
100
Ta= +25°C
%
%
Gain Error
VCC = VRSP = 48V
Ta= –40°C to +125°C
DC
PSRR
DC Power Supply Rejection Ratio
DC Common Mode Rejection Ratio
VRSP = 48V, VCC = 4.5 to 76V
100
100
122
dB
VCC = 48V, VRSP = 4.5 to 76V
VCC = 48V, VRSP = 4 to 76V
124
124
dB
dB
V
DC
CMRR
Input Common Mode Voltage Range
Output Resistance / Load Regulation
CMVR CMRR > 100dB
ROUT VSENSE = 100mV
4
76
0.1
Maximum Output Voltage
(Headroom)
VCC = 4.5V, VRSP = 48V, VSENSE = +1V
IOUT (sourcing) = 500μA
VOMAX
230
500
mV
mV
(VOMAX = VCC – VOUT
)
VCC = VRSP = 48V, VSENSE = -1V,
IOUT (sinking) = 10µA
3
3
15
VCC = VRSP = 4.5V, VSENSE = -1V,
IOUT (sinking) = 10µA
Minimum Output Voltage
VOMIN
VCC = VRSP = 48V, VSENSE = -1V,
IOUT (sinking) = 100µA
18
55
VCC = VRSP = 4.5V, VSENSE = -1V,
IOUT (sinking) = 100µA
18
VCC=28V, VRSP=28V, VSENSE=600mV, IOUT
(sourcing)=500uA
Output voltage with load
Output Load Regulation
VOLOAD
12
V
VCC = 20, VRSP = 16, VOUT =12, ΔIL= 200na
to 8mA
VOLREG
0.001
%
Supply Current
ICC VOUT=2V, RL = 10M, VCC= VRSP = 76V
BW RL= 10M, CL = 20pF
88
155
uA
−3 dB Bandwidth
270
kHz
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) All limits are guaranteed by testing, design, or statistical analysis.
(3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production
material.
(4) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
(5) Positive Bias Current corresponds to current flowing into the device.
(6) This parameter is guaranteed by design and/or characterization and is not tested in production.
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Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits guaranteed for at TA = 25°C, VCC= +4.5V to +76V, +4.5V < VCM < +76V, RL= 100k,
VSENSE = (VRSP - VRSN) = 0V. Boldface limits apply at the temperature extremes, TMIN ≦ TA ≦ TMAX
.
Min
Typ
Max
(2)
(3)
(2)
Parameter
Condition
Units
VSENSE from 10mV to 80mV, RL=10M,
CL=20pF
V/µs
(7)
Slew Rate
SR
1
Input Referred Voltage Noise
eni f = 1 kHz
95
20
nV/
µs
VSENSE = 10mV to 100mV and 100mV to
Output Settling Time to 1% of Final Value
tSETTLE
10mV,
VCC = VRSP = 48V, VSENSE = 100mV, output
to 1% of final value
Power-up Time
tPU
50
µs
Output settles to 1% of final value, the device
will not experience phase reversal when
overdriven.
tRECOVE
Saturation Recovery Time
50
µs
pF
RY
Max Output Capacitance Load
CLOAD No sustained oscillations
500
(7) The number specified is the average of rising and falling slew rates and measured at 90% to 10%.
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Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, VCC= 4.5V to 76V, 4.5V < VCM < 76V, RL= 100k, VSENSE = (VR – VRSN) = 0V, for all
SP
gain options.
Typical Offset Voltage
vs.
Offset Voltage Histogram
Temperature
60
50
40
30
20
10
0
50
40
V
= V = 48V
RSP
CC
30
20
10
0
-10
-20
-30
-40
-50
-50 -40 -30 -20 -10
0
10 20 30 40 50
-50 -25
0
25 50 75 100 125
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (ꢀV)
Typical Gain Accuracy
vs.
Temperature
Typical Gain Accuracy vs. Supply Voltage
0.5
0.4
0.5
V
= 48V
0.4
0.3
V
= V
RSP
= 48V
RSP
CC
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-50 -25
0
25 50 75 100 125
0
10 20 30 40 50 60 70 80
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Typical Offset Voltage
vs.
AC Common-Mode Rejection Ratio
vs.
Frequency
-40
Supply Voltage
100
80
V
= 48V
ûVCM = 2Vpp
RSP
-50
60
-60
-70
40
20
0
-80
-20
-40
-60
-80
-100
-90
-100
-110
-120
0
10 20 30 40 50 60 70 80
SUPPLY VOLTAGE (V)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCC= 4.5V to 76V, 4.5V < VCM < 76V, RL= 100k, VSENSE = (VR – VRSN) = 0V, for all
SP
gain options.
AC Power Supply Rejection Ratio
Small Signal Gain
vs.
vs.
Frequency
Frequency
-40
50
45
40
35
30
25
20
15
10
5
V
= 100mVpp
OUT
-50
-60
LMP8480-S
-70
-80
-90
-100
-110
-120
-130
-140
0
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Large Signal Pulse Response
Small Signal Pulse Response
4
3
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
2
1
0
-1
-2
-3
-4
0
20 40 60 80 100 120 140 160 180 200
0 20 40 60 80 100120140160180200
TIME (ꢀs)
TIME (ꢀs)
Supply Current
vs.
Supply Current
vs.
Supply Voltage
Temperature
100
95
90
85
80
75
115
110
105
100
95
V
= V = 48V
RSP
V
= 48V
CC
RSP
90
85
80
0
10 20 30 40 50 60 70 80
SUPPLY VOLTAGE (V)
-50 -25
0
25 50 75 100 125
TEMPERATURE (°C)
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCC= 4.5V to 76V, 4.5V < VCM < 76V, RL= 100k, VSENSE = (VR – VRSN) = 0V, for all
SP
gain options.
Saturated Output Sourcing Current at 4.5V
Saturated Output Sinking Current at 4.5V
10
10
V
= 5V
V
= 5V
CC
CC
1
.1
1
.1
.01
.001
.01
.001
-40°C
-40°C
+25°C
+85°C
+125°C
+25°C
+85°C
+125°C
.01
.1
1
10
.01
.1
1
10
SOURCING CURRENT (mA)
SINKING CURRENT (mA)
Saturated Output Sourcing Current at 12V
Saturated Output Current Sinking at 12V
10
10
V
= 12V
V
= 12V
CC
CC
1
.1
1
.1
.01
.001
.01
.001
-40°C
-40°C
+25°C
+85°C
+125°C
+25°C
+85°C
+125°C
.01
.1
1
10
.01
.1
1
10
SOURCING CURRENT (mA)
SINKING CURRENT (mA)
Application Information
LMP8480 AND LMP8481 INTRODUCTION
The LMP8480 and LMP8481 are single supply, high side current sense amplifiers with available fixed gains of
x20, x50, x60 and x100. The power supply range is 4.5V to 76V, while the common mode input voltage range is
capable of 4.0V to 76V operation. The supply voltage and common mode range are completely independent of
each other. This makes the LMP848x supply voltage extremely flexible, as the LMP848x's supply voltage can be
greater than, equal to, or less than the load source voltage, and allowing the device to be powered from the
system supply or the load supply voltage.
The amplifier supply voltage does not have to be larger than the load source voltage. A 76V load source voltage
with a 5V LMP8481 supply voltage is perfectly acceptable.
THEORY OF OPERATION
The LMP8480 and LMP8481 are comprised of two main stages. The first stage is a differential input current to
voltage converter, followed by a differential voltage amplifier and level-shifting output stage. Also present is an
internal 14 Volt Low Dropout Regulator (LDO) to power the amplifiers and output stage, as well as a reference
divider resistor string to allow the setting of the reference level.
As seen in Figure 7, the current flowing through RSENSE develops a voltage drop called VSENSE. The voltage
across the sense resistor, VSENSE, is then applied to the input RSP and RSN pins of the amplifier.
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R
4.0V < V < 76V
IN
SENSE
I
L
+IN
-IN
L
o
a
LMP8481
V
SENSE
d
Difference
Amplifier
(x5)
V
CM
SENSE
R
GP
R
GN
2 MW
Internal
14V LDO
Regulator
V
CC
V
OUT
-
+
-
+
4.5V < V
CC
< 76V
100 kW
100 kW
V
REFA
V to I
Converter
1.95 MW
V
REFB
400 kW
400 kW
V
REF‘
GND
Figure 7. LMP8481 Functional Diagram
Internally, the voltage on each input pin is converted to a current by the internal precision thin-film input resistors
RGP and RGN . A second set of much higher value VCM sense resistors between the inputs provide a sample of
the input common mode voltage for internal use by the differential amplifier.
VSENSE is applied to the differential amplifier through RGP and RGN. These resistors change the input voltage to a
differential current. The differential amplifier then servos the resistor currents through the MOSFETs to maintain
a zero balance across the differential amplifier inputs.
With no input signal present, the currents in RGP and RGN are equal. When a signal is applied to VSENSE, the
current through RGP and RGN are imbalanced and are no longer equal. The amplifier then servos the MOSFETS
to correct this current imbalance, and the extra current required to balance the input currents is then reflected
down into the two lower 400kΩ “tail” resistors. The difference in the currents into the tail resistors is therefore
proportional to the amplitude and polarity of VSENSE. The tail resistors, being larger than the input resistors for the
same current, then provide voltage gain by changing the current into a proportionally larger voltage. The gain of
the first stage is then set by the tail resistor value divided by RG value.
The differential amplifier stage then samples the voltage difference across the two 400K tail resistors and also
applies a further gain-of-five and output level-shifting according to the applied reference voltage (VREF).
The resulting output of the amplifier will be equal to the differential input voltage times the gain of the device, plus
any voltage value applied to the two VREF pins.
The resistor values in the schematic are ideal values for clarity and understanding. The table below shows the
actual values used that account for parallel combinations and loading. This table can be used for calculating the
effects of any additional external resistance.
Table 2. Actual Internal Resistor Values
RGP and RGN
(each)
RVCMSENSE
(each)
RTAIL
(each)
Differential Amp FB
(each)
VREFx Resistors
(each)
Gain Option
20x
98.38k
39.352k
32.793k
19.676k
491.9k
196.76k
172.165k
98.38k
393.52k
393.52k
393.52k
393.52k
1967.6k
1967.6k
1967.6k
1967.6k
98.38k
98.38k
98.38k
98.38k
50x
60x
100x
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UNI-DIRECTIONAL VS. BI-DIRECTIONAL OPERATION
Uni-directional operation is where the load current only flows in one direction (VSENSE is always positive).
Application examples would be PA monitoring, non-inductive load monitoring and laser or LED drivers. This
allows the output zero reference to be true zero volts on the output. The LMP8480 is designed for unidirectional
applications where the setting of VREF is not required. See the UNI-DIRECTIONAL OPERATION for more
details.
Bi-directional operation is where the load current can flow in both directions (VSENSE can be positive or
negative). Application examples would be battery charging or regenerative motor monitoring. The LMP8481 is
designed for bidirectional applications and has a pair of VREF pins to allow the setting of the output zero
reference level (VREF). See the BI-DIRECTIONAL OPERATION (LMP8481 ONLY) section for more details.
UNI-DIRECTIONAL OPERATION
The LMP8480 is designed for unidirectional current sense applications. The output of the amplifier will be equal
to the differential input voltage times the fixed device gain.
I
SENSE
To Load
V
= +4.5V to +76V
+4.0V
to
+76V
CC
C1
0.1 mF
R
SENSE
V
CC
RSN
V
OUT
V
LMP8480
SENSE
V
IN
+
ADC
RSP
GND
V
IN
- V
REF
Figure 8. Uni-Directional Application with LMP8480
14
V
> 14V
CC
12
10
8
6
4
2
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VSENSE (V)
Figure 9. Uni-Directional Transfer Function for Gain-of-20 option
The output voltage can be calculated from:
VOUT = ( (VRSP – VRSN) * Av )
(1)
It should be noted that the minimum “zero” reading will be limited by the lower output swing and input offset.
The LMP8480 is functionally identical to the LMP8481, but with the VREFA and VREFB nodes grounded internally.
The LMP8481 can replace the LMP8480 if both the VREF inputs (pins 6 & 7) are grounded.
BI-DIRECTIONAL OPERATION (LMP8481 ONLY)
Bi-directional operation is required where the measured load current can be positive or negative. Because VSENSE
can be positive or negative, and the output cannot swing negative, the “zero” output level must be level-shifted
above ground to a known zero reference point. The LMP8481 allows for the setting this reference point.
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I
SENSE
V
CC
= +4.5V to +76V
To Load
C1
0.1 mF
R
SENSE
RSN
GND
V
LMP8481
OUT
VSENSE
V
V
+
REFA
REFB
RSP
IN
ADC
-
V
IN
REF
LM4140ACM-1.2
C2
0.1 mF
Figure 10. Bi-Directional current sensing using LMP8481
The VREFA and VREFB pins set the zero reference point. The output “zero” reference point is set by applying a
voltage to the REFA and/or REFB pins. See the BI-DIRECTIONAL OPERATION (LMP8481 ONLY) section
below. REFA AND REFB PINS (LMP8481 Only) below shows the output transfer function with a 1.2V reference
applied to the Gain-of-20 option
14
V
> 14V
CC
12
10
8
6
4
V
= 1.2V
REF
2
0
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VSENSE (V)
Figure 11. Bi-Directional Transfer Function using 1.2V Reference Voltage
REFA AND REFB PINS (LMP8481 Only)
The voltage applied to the VREFA and VREFB pins controls the output zero reference level.
The reference inputs consist of a pair of divider resistors with equal values to a common summing point, VREF’,
as shown in Figure 16 below.
100 kW
V
REFA
V
‘
REF
(6V Max)
100 kW
V
REFB
Figure 12. VREF Input Resistor Network
VREF’ is the voltage at the resistor tap point that will be directly applied to the output as an offset.
VOUT = ( (VRSP – VRSN) * Av ) + VREF
’
(2)
Where:
VREF’ = VREFA = VREFB (Equal Inputs)
OR
(3)
(4)
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VREF’ = ( VREFA + VREFB ) / 2 (Separate inputs)
(5)
100 kW
100 kW
V
V
REFA
V
‘
V
REF
REF
2.5V
2.5V
REFB
Figure 13. Applying 1:1 Direct Reference Voltage
For mid-range operation VREFB should be tied to ground and VREFA can be tied to VS or an external A/D
reference voltage. The output will be set to one-half the reference voltage. For example, a 5V reference would
result in a 2.5V output “zero” reference.
100 kW
V
REFA
5V
V
‘
REF
2.5V
100 kW
V
REFB
Figure 14. Applying A Divided Reference Voltage.
VREF’ = (VREFA – VREFB) / 2
(6)
When the reference pins are biased at different voltages, the output will be referenced to the average of the two
applied voltages.
The reference pins should always be driven from clean, stable sources, such as A/D reference lines or clean
supply lines. Any noise or drifts on the reference inputs are directly reflected in the output. Care should be taken
if the power supply is used as the reference source so as to not introduce supply noise, drift or sags into the
measurement.
It is possible to set different resistor divider ratios by adding external resistors in series with the internal 100K
resistors, though the temperature coefficient (tempco) of the external resistors may not tightly track the internal
resistors and there will be slight errors over temperature.
REFERENCE INPUT VOLTAGE LIMITS
The maximum voltage on either reference input pin is limited to VCC or 12V, whichever is less.
The average voltage on the two VREF pins, and thus the actual output reference voltage level, is limited to a
maximum of 1.5V below VCC, or 6V, whichever is less. Beware that supply voltages of less than 7.5V will have a
diminishing VREF maximum.
Both VREFA and VREFB may both be grounded to provide a ground referenced output (thus functionally duplicating
the LMP8480).
It should be noted that there can be a dynamic error in the VREF to output level matching of up to 100µV/V.
Normally this is not an issue for fixed references, but if the reference voltage is dynamically adjusted during
operation, this error needs to be taken into account during calibration routines. This error will vary in both
amplitude and polarity part-to-part, but the slope will generally be linear.
SELECTION OF THE SENSE RESISTOR
The accuracy of the current measurement depends heavily on the accuracy of the shunt resistor RSENSE. Its
value depends on the application and is a compromise between small-signal accuracy, maximum permissible
voltage drop and allowable power dissipation in the current measurement circuit.
The use of a “4-terminal” or “Kelvin” sense resistor is highly recommended. See the ERROR SOURCES AND
LAYOUT CONSIDERATIONS below.
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For best results, the value of the resistor is calculated from the maximum expected load current ILMAX and the
expected maximum output swing VOUTMAX, plus a few percent of headroom. See the MAXIMUM OUTPUT
VOLTAGE section for details about the maximum output voltage limits.
High values of RSENSE provide better accuracy at lower currents by minimizing the effects of amplifier offset. Low
values of RSENSE minimize load voltage loss, but at the expense of accuracy at low currents. A compromise
between low current accuracy and load circuit losses must generally be made.
The maximum VSENSE voltage that must be generated across the RSENSE resistor will be:
VSENSE = VOUTMAX / AV.
(7)
Note: The maximum VSENSE voltage should be no more than 667mV.
From this maximum VSENSE voltage, the RSENSE value can be calculated from:
RSENSE = VSENSE / ILMAX
(8)
Care must be taken to not exceed the maximum power dissipation of the resistor. The maximum sense resistor
power dissipation will be:
PR
= VSENSE * ILMAX
(9)
SENSE
It is recommended that a 2-3x minimum safety margin be used in selecting the power rating of the resistor.
USING PCB TRACES AS SENSE RESISTORS
While it may be tempting to use a known length of PCB trace resistance as a sense resistor, it is not
recommended.
The tempco of copper is typically 3300-4000ppm/°K, which can vary over PCB process variations and require
measurement correction (possibly requiring ambient temperature measurements).
A typical surface mount sense resistor tempco is in the 50ppm to 500ppm/°C range offering more measurement
consistency and accuracy over the copper trace. Special low tempco resistors are available in the 0.1 to 50ppm
range, but at a higher cost.
INPUT COMMON MODE AND DIFFERENTIAL VOLTAGE RANGE
The input common mode range, where “common mode range” is defined as the voltage from ground to the
voltage on RSP input, should be in the range of +4.0V to +76V. Operation below 4.0V on either input pin will
introduce severe gain error and nonlinearities.
The maximum differential voltage (defined as the voltage difference between RSP and RSN) should be 667mV or
less. The theoretical maximum input is 700mV (14V / 20).
Taking the inputs below 4V will not damage the device, but the output conditions during this time are not
predictable and are not guaranteed.
If the load voltage (Vcm) is expected to fall below 4V as part of normal operation, preparations must be made for
invalid output levels during this time.
LOW SIDE CURRENT SENSING
The LMP8480 and LMP8481 are not recommended for low-side current sensing at ground level. The voltage on
either input pin must be a minimum of 4.0V above the ground pin for proper operation.
INPUT SERIES RESISTANCE
Because the input stage uses precision resistors to convert the voltage on the input pin to a current, any
resistance added in series with the input pins will change the gain. If a resistance is added in series with an
input, the gain of that input will not track that of the other input, causing a constant gain error.
It is not recommended to use external resistances to alter the gain, as external resistors will not have the same
thermal matching as the internal thin film resistors.
If resistors are purposely added for filtering, resistance should be added equally to both inputs and the user
should be aware that the gain will change slightly. See end of the THEORY OF OPERATION section for the
internal resistor values.
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MINIMUM OUTPUT VOLTAGE
The amplifier output cannot swing to exactly zero volts. There will always be a minimum output voltage set by the
output transistor saturation and input offset errors. This will create a minimum output swing around the zero
current reading due to the output saturation. The user should be aware of this when designing any servo loops or
data acquisition systems that may assume 0V = 0A. If a true zero is required, the LMP8481 should be used with
a VREF set slightly above ground (>50mV). See the SWINGING OUTPUT BELOW GROUND section below for a
possible solution to this issue.
SWINGING OUTPUT BELOW GROUND
If a negative supply is available, a pull-down resistor can be added from the output to the negative voltage to
allow the output to swing a few millivolts below ground. This will now allow the ADC to resolve true zero and
recover codes that would normally be lost to the negative output saturation limit.
V
= +4.5V to +76V
CC
C1
0.1 mF
V
CC
R
SN
V
OUT
LMP848x
V
+
IN
ADC
- V
R
SP
50 µA
GND
R
PD
V
IN
REF
-V
S
R
= -V / 50 µA
S
PD
Figure 15. Output “Pull-Down” Resistor Example
A minimum of 50µA should be sourced (“pulled”) from the output to a negative voltage. The pulldown resistor can
be calculated from:
RPD = –VS/50µA
(10)
For example, if a -5V supply is available, a pull-down resistor of 5V/50uA = 100K should be used. This will allow
the output to swing to about 10mV below ground.
This technique may also reduce the maximum positive swing voltage. Do not forget to include the parallel loading
effects of the pulldown any output load. It is recommended not to exceed -100mV on the output. Source currents
greater than 100uA should be avoided to prevent self-heating at high supply voltages. Pulldown resistor values
should not be so low as to heavily load the output during positive output excursions. This mode of operation is
not directly specified and is not guaranteed.
MAXIMUM OUTPUT VOLTAGE
The LMP8481 has an internal precision 14V low dropout regulator which limits the maximum amplifier output
swing to about 250mV below VCC or 13.7V (whichever is less). This effectively clamps the maximum output to
slightly less than 13.7V even with a VCC greater than 14V.
Care should be taken if the output is driving an A/D input with a maximum A/D maximum input voltage lower than
the amplifier supply voltage, as the output can swing higher than the planned load maximum due to input
transients or shorts on the load and overload or possibly damage the A/D input.
A resistive attenuator, as shown in Figure 16 below, can be used to match the maximum swing to the input range
of the A/D.
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SNVS829A –JUNE 2012–REVISED AUGUST 2012
I
SENSE
To Load
V
= +4.5V to +76V
+4.5V
to
+76V
CC
C1
0.1 mF
R
SENSE
V
CC
RSN
R1
V
OUT
V
LMP8480
SENSE
V
V
+
IN
ADC
RSP
GND
- V
R2
IN
REF
Figure 16. Typical Application with Resistive Divider
ERROR SOURCES AND LAYOUT CONSIDERATIONS
The traces leading to and from the sense resistor can be significant error sources. With small value sense
resistors (<100m), any trace resistance shared with the load current can cause significant errors.
Load Current Path
PCB
Source
Trace
PCB
Load
Trace
Kelvin Sense
Traces to
Amplifer
Sense Resistor
V
SENSE
Figure 17. “Kelvin” or “4–wire” Connection to the Sense Resistor
The amplifier inputs should be directly connected to the sense resistor pads using “Kelvin” or “4-wire” connection
techniques. The traces should be one continuous piece of copper from the sense resistor pad to the amplifier
input pin pad, and ideally on the same copper layer with minimal vias or connectors. This can be important
around the sense resistor if it is generating any significant heat gradients.
To minimize noise pickup and thermal errors, the input traces should be treated as a differential signal pair and
routed tightly together with a direct path to the input pins. The input traces should be run away from noise
sources, such as digital lines, switching supplies or motor drive lines. Remember that these traces can contain
high voltage, and should have the appropriate trace routing clearances.
Since the sense traces only carry the amplifier bias current (about 7µA at room temp), the connecting input
traces can be thinner, signal level traces. Excessive Resistance in the trace should also be avoided.
The paths of the traces should be identical, including connectors and vias, so that these errors will be equal and
cancel.
The sense resistor will heat up as the load increases. As the resistor heats up, the resistance generally goes up,
which will cause a change in the readings The sense resistor should have as much heatsinking as possible to
remove this heat through the use of heatsinks or large copper areas coupled to the resistor pads. A reading
drifting over time after turn-on can usually be traced back to sense resistor heating.
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POWER SUPPLY DECOUPLING
In order to decouple the LMP8480/81 from AC noise on the power supply, it is recommended to use a 0.1 μF
bypass capacitor between the VCC and GND pins. This capacitor should be placed as close as possible to the
supply pins. In some cases an additional 10 μF bypass capacitor may further reduce the supply noise.
Do not forget that these bypass capacitors must be rated for the full supply and/or load source voltage! It is
recommended that the working voltage of the capacitor (WVDC) should be at least two times the maximum
expected circuit voltage.
LLP DIE ATTACH PAD
The bottom thermal pad of the LLP package should be tied to the same ground as the ground pin. Be aware that
noise on this pad can couple into the bottom of the die, so the ground should be as clean as possible.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2013
PACKAGING INFORMATION
Orderable Device
LMP8480MM-T/NOPB
LMP8480MME-S/NOPB
LMP8480MME-T/NOPB
LMP8480MMX-S/NOPB
LMP8480MMX-T/NOPB
LMP8481MM-S/NOPB
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
8
8
8
8
8
8
1000
250
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
AV8A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
DGK
DGK
DGK
DGK
DGK
Green (RoHS
& no Sb/Br)
AY8A
AV8A
AY8A
AV8A
250
Green (RoHS
& no Sb/Br)
3500
3500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP8480MM-T/NOPB
VSSOP
DGK
DGK
DGK
DGK
DGK
8
8
8
8
8
1000
250
178.0
178.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
LMP8480MME-S/NOPB VSSOP
LMP8480MME-T/NOPB VSSOP
LMP8480MMX-S/NOPB VSSOP
LMP8480MMX-T/NOPB VSSOP
250
3500
3500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP8480MM-T/NOPB
LMP8480MME-S/NOPB
LMP8480MME-T/NOPB
LMP8480MMX-S/NOPB
LMP8480MMX-T/NOPB
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
DGK
8
8
8
8
8
1000
250
203.0
203.0
203.0
349.0
349.0
190.0
190.0
190.0
337.0
337.0
41.0
41.0
41.0
45.0
45.0
250
3500
3500
Pack Materials-Page 2
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